Calculation device, calculation system, calculation method, and program

Abstract

To easily find out a switching pattern that is to be applied to a gate terminal of a power device and enables suppression of surge voltage and power loss of a power device.SOLUTION: A calculation device calculates a switching pattern including a change for each time in a value of voltage applied to a gate of a non-contact switch or a value of current flowing in the non-contact switch, the switching pattern including a slot for each time and a voltage value or a current value corresponding to the slot. The calculation device comprises: a request information acquisition unit for acquiring request information including information on at least any one of a request value for power loss at the time of switching of the non-contact switch and a request value for overshoot voltage at the time of switching of the non-contact switch; a calculation unit for calculating the switching pattern on the basis of the acquired request information; and an output unit for outputting the calculated switching pattern.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present invention relates to an arithmetic device, an arithmetic system, an arithmetic method, and a program.

Background Art

[0002] Conventionally, in a switching control circuit for controlling the current flowing through a transistor used in a power device, there has been a technique for suppressing a surge voltage by controlling the voltage applied to the gate (see, for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] When controlling the voltage applied to the gate using the technology as described above, it has been necessary to determine circuit constants and control parameters at the design stage in consideration of the electrical characteristics of the power device and the load fluctuations connected to the power device. However, since the electrical characteristics of the power device vary greatly and the fluctuations of the connected load are also large, it has not been easy to set suitable circuit constants and control parameters at the design stage. On the other hand, even when the fluctuations of the load connected to the power device are not constant, there is a demand to suppress surge voltage and power loss.

[0005] To meet such requirements, an active gate driver that can control the voltage value applied to the gate terminal or the current value flowing through the gate terminal according to time is known. According to the active gate driver, since the voltage value applied to the gate terminal or the current value flowing through the gate terminal can be controlled according to time, by applying a suitable switching pattern to the gate terminal, surge voltage and power loss can be suppressed. However, the combinations of switching patterns become an enormous number according to the controllable voltage levels and controllable times. Therefore, there has been a problem that it is difficult to find a suitable switching pattern from among the enormous combinations.

[0006] The present invention has been made in view of such a situation, and an object thereof is to provide a control technique that can easily find a switching pattern applied to the gate terminal of a power device and that can suppress the surge voltage and power loss of the power device.

Means for Solving the Problems

[0007] An arithmetic device according to an aspect of the present invention is a switching pattern including a change over time of a voltage value applied to a gate of a non-contact switch or a current value flowing into the non-contact switch, the switching pattern including time slots for each time and a voltage value or a current value corresponding to the slot. In the arithmetic device that calculates the switching pattern, at the time of switching of the non-contact switch Base a required information acquisition unit that acquires required information including at least one of a required value of power loss or a required value of overshoot voltage at the time of switching of the non-contact switch, an arithmetic unit that calculates the switching pattern based on the acquired required information, and an output unit that outputs the calculated switching pattern. Generated in the contactless switch a required value of power loss, or at the time of switching of the non-contact switch , which is the maximum value of the voltage between both ends of the main current path in the contactless switch an output unit that outputs the calculated switching pattern.

[0008] Also, in the arithmetic unit according to one aspect of the present invention, the arithmetic unit is a neural network learned to calculate a switching pattern such that the power loss or the overshoot voltage becomes at least one of the required value of the power loss included in the required information or the required value of the overshoot voltage.

[0009] Further, the arithmetic unit according to one aspect of the present invention further includes a specifying unit that specifies an effective slot that is the slot contributing to the change in the power loss or the overshoot voltage among the calculated switching patterns, and the output unit outputs the specified effective slot Switching pattern for controlling thereof.

[0010] Further, the arithmetic unit according to one aspect of the present invention further includes a measured information acquisition unit that acquires measured information including at least one of the power loss or the overshoot voltage when the switching pattern is applied to the gate of the non-contact switch, and the specifying unit specifies the slot in which the difference between the power loss or the overshoot voltage predicted by the switching pattern and the power loss or the overshoot voltage included in the measured information is within a predetermined threshold value as the effective slot.

[0011] Also, the arithmetic system according to one aspect of the present invention includes any one of the above-described arithmetic units and a storage unit that stores teacher data for training the arithmetic unit, the teacher data being the teacher data in which the switching pattern is associated with the required value of the power loss or the required value of the overshoot voltage, and the arithmetic unit is trained by the teacher data stored in the storage unit.

[0012] Also, the arithmetic system according to one aspect of the present invention further includes a teacher data generation unit that generates the teacher data by simulation.

[0013] Also, in the arithmetic system according to one aspect of the present invention, the teacher data generation unit generates the teacher data by calculating the power loss or the overshoot voltage according to the randomly given switching pattern.

[0014] Also, an arithmetic method according to one aspect of the present invention is when a non-contact switch is switched Generated in the contactless switch a required information acquisition step of acquiring required information including at least one of a required value of power loss or When the contactless switch is switched, it is the maximum value of the voltage between both ends of the main current path in the contactless switch a required value of overshoot voltage, and an arithmetic step of calculating a switching pattern including a change over time of a voltage value applied to the gate of the non-contact switch or a current value flowing into the non-contact switch Base wherein the arithmetic step calculates the switching pattern based on the acquired required information, and an output step of outputting the calculated switching pattern.

[0015] Also, a program according to one aspect of the present invention causes a computer to, when a non-contact switch is switched Generated in the contactless switch a required information acquisition step of acquiring required information including at least one of a required value of power loss or When the contactless switch is switched, it is the maximum value of the voltage between both ends of the main current path in the contactless switch a required value of overshoot voltage, and an arithmetic step of calculating a switching pattern including a change over time of a voltage value applied to the gate of the non-contact switch or a current value flowing into the non-contact switch Base wherein the arithmetic step calculates the switching pattern based on the acquired required information, and an output step of outputting the calculated switching pattern.

Advantages of the Invention

[0016] According to the present invention, it is possible to provide a control technique capable of easily finding a switching pattern that suppresses the surge voltage and power loss of a power device among the switching patterns applied to the gate terminal of the power device.

Brief Description of the Drawings

[0017]

Figure 1

Figure 2

Figure 3

Figure 4

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Figure 11

Figure 12

Figure 13

Figure 14

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Figure 16

Figure 17

Figure 18

Figure 19

Figure 20

Embodiments for Carrying Out the Invention

[0018] [Prior Art] First, the prior art will be described with reference to FIGS. 19 and 20. Conventionally, there has been a technique for controlling the voltage applied to the gate terminal of a switching element (hereinafter simply referred to as a switching element), which is a power device, using a gate driver. The gate driver includes a gate driver that controls the current flowing through the switching element by controlling the duty ratio of the pulse applied by a binary voltage level, and an active gate driver that varies the voltage value applied to the gate terminal or the current value applied to the gate terminal according to time.

[0019] 19 is an example of a circuit configuration diagram of a gate drive circuit according to the prior art. With reference to the figure, an example of the circuit configuration of a gate drive circuit 90 will be described. The gate drive circuit 90 includes a gate drive circuit 91, a switching element 92, and a load 94. The switching element 92 and the load 94 are connected in series between a DC power supply terminal 96 and a ground point 95 .

[0020] The switching element 92 may be a voltage-controlled element or a current-controlled element. In the following description, an example in which the switching element 92 is a voltage-controlled element will be described. The switching element 92 has a gate terminal G, a drain terminal D, and a source terminal S. The switching element 92 controls a drain current i flowing between the drain terminal D and the source terminal S by controlling the voltage applied to the gate terminal G. D Here, the voltage generated between the drain terminal D and the source terminal S is called the drain-source voltage v DS It is written as follows.

[0021] The gate drive circuit 91 includes a rectangular wave voltage source (not shown) and a limiting resistor (not shown), and applies a voltage to the gate terminal of the switching element 92. The gate drive circuit 91 outputs a pulse signal with a predetermined duty ratio. A drain current i D Here, depending on the control of the gate drive circuit 91, the drain-source voltage v DS In some cases, a surge voltage may occur as a result of the switching control of the gate drive circuit 91. The surge voltage may adversely affect adjacent electronic devices as electromagnetic noise. DS and the drain current i D In order to suppress such surge voltage and power consumption, it is conceivable to use an active gate driver instead of the gate drive circuit 91.

[0022] FIG. 20 is a diagram showing an example of switching control according to the prior art and an example of switching control when an active gate driver is used. With reference to FIG. 20(A), an example of switching control according to the prior art will be described, and with reference to FIG. 20(B), an example of switching control by an active gate driver will be described. In the figure, the vertical axis represents the voltage level applied to the gate terminal G of the switching element 92, and the horizontal axis represents time.

[0023] FIG. 20(A) is a diagram showing an example of switching control according to the prior art. According to the switching control according to the prior art, the voltage applied to the gate terminal G of the switching element 92 is either a low level or a high level. In the example shown in the figure, a low level is applied during the period from 0 [ns (nanoseconds)] to 20 [ns], and a high level is applied after 20 [ns].

[0024] FIG. 20(B) is a diagram showing an example of switching control when an active gate driver is used. When an active gate driver is used, it is possible to control the value of the voltage according to time. In the example shown in the figure, assuming one slot is 20 [ns], 64 voltage levels from 0 to 63 can be set respectively during the period of 60 slots. According to the control using an active gate driver, flexible and fine control is possible, so that the surge voltage and power consumption generated in the switching element 92 can be effectively suppressed. However, in the case of the example shown in the figure, since there are a number of switching patterns equal to the product of 64 steps for 60 slots, it has been difficult to find a suitable switching pattern from among all the combinations of switching patterns.

[0025] [This Embodiment] Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a diagram for explaining the outline of the arithmetic system according to this embodiment. With reference to this figure, the outline of the arithmetic system 1 will be described. In the following description, an example will be described where the switching element to be processed by the arithmetic system 1 is a contactless switch such as a transistor or an FET (Field Effect Transistor). Further, in the following description, an example will be described in which the arithmetic system 1 calculates the switching pattern of the voltage value applied to the gate terminal or the base terminal of a contactless switch such as a transistor or an FET. However, the present embodiment is not limited to this example. For example, when the switching element is an element that requires current control, the arithmetic system 1 may calculate the switching pattern of the current value flowing into the switching element instead of the voltage value applied to the switching element. The description of "voltage value switching pattern" or "current value switching pattern" means that the voltage value or the current value is determined according to the switching pattern, and does not mean that the switching pattern itself includes the absolute value of the voltage value or the current value.

[0026] A required waveform, which is a waveform required during the switching of the switching element, is input to the neural network NN. Here, the required waveform is one of the waveforms of the power loss or the overshoot voltage during the switching of the switching element. The required waveform may or may not include information about the temporal change. That is, the required waveform may be information about a predetermined value specified by a maximum value, an average value, or the like. In the figure, as an example of the required waveform, a waveform W1 including information about the temporal change is shown. The waveform W1 shows the temporal change of the voltage value generated in the switching element. The voltage value generated in the switching element is, for example, the voltage between the collector and the emitter when the switching element is an IGBT (Insulated Gate Bipolar Transistor), and the voltage between the drain and the source when the switching element is a MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor).

[0027] Here, the neural network NN is a pre-trained learned model. The neural network NN predicts a suitable pattern for gate control of the switching element based on the input waveform. In the figure, waveform W2 is shown as an example of a suitable pattern. Waveform W2 shows an example of the time variation of the gate voltage. Specifically, waveform W2 is a waveform representing the voltage value applied to the gate in 64 steps from 0 to 63 according to 60 slots every 20 [ns].

[0028] FIG. 2 is a diagram showing an example of the functional configuration of the arithmetic system according to the present embodiment. With reference to this figure, the functional configuration of the arithmetic system 1 will be described. The arithmetic system 1 includes an arithmetic device 10, an active gate driver 30, an input device 40, a teacher data generation unit 50, and a switching element 60.

[0029] The arithmetic device 10 acquires request information IR from the input device 40. The request information IR includes information regarding the requested waveform. Based on the acquired request information IR, the arithmetic device 10 calculates a voltage pattern applied to the gate terminal or a current pattern flowing into the gate terminal. Hereinafter, when the voltage pattern and the current pattern are not distinguished, it is also referred to as a switching pattern. The arithmetic device 10 outputs pattern information IP including the calculated switching pattern to the active gate driver 30. Here, the switching pattern calculated by the arithmetic device 10 includes the change over time of the voltage value applied to the gate of the switching element 60. The switching pattern also includes the time slots and the voltage values corresponding to the slots. The arithmetic device 10 acquires teacher data TD from the teacher data generation unit 50. The arithmetic device 10 learns based on the acquired teacher data TD.

[0030] The active gate driver 30 acquires pattern information IP including the switching pattern from the arithmetic device 10. The active gate driver 30 generates the switching pattern included in the acquired pattern information IP and applies it to the gate terminal of the switching element 60.

[0031] Based on the user's operation, the input device 40 inputs the required waveform as the request information IR to the arithmetic unit 10. The input device 40 may be, for example, an information storage device that stores information about the required waveform. Also, when the required waveform is a predetermined value specified by a maximum value, an average value, etc., the user may input the request information IR to the arithmetic unit 10 via the input device 40. In this case, the input device 40 may be an information input device such as a keyboard, a mouse, a touch panel, a microphone, etc.

[0032] The teacher data generation unit 50 generates teacher data TD. For example, the teacher data generation unit 50 generates the teacher data TD by simulation based on a circuit simulation model of the switching element 60 or the like. The teacher data generation unit 50 outputs the generated teacher data TD to the arithmetic unit 10. Also, the teacher data generation unit 50 includes a storage unit (not shown) and stores the generated teacher data TD. The arithmetic unit 10 learns based on the teacher data TD stored in the storage unit.

[0033] The switching element 60 is a non-contact switch such as a transistor or an FET. In particular, the switching element 60 may be a power device capable of controlling a large current.

[0034] FIG. 3 is a diagram showing an example of the functional configuration of the arithmetic unit according to the present embodiment. The functional configuration of the arithmetic unit 10 will be described with reference to this figure. The arithmetic unit 10 includes a request information acquisition unit 110, an arithmetic unit 120, and an output unit 130. The arithmetic unit 10 includes a storage device such as a CPU (Central Processing Unit), a ROM (Read only memory), or a RAM (Random access memory) (not shown) connected by a bus, and functions as a device including the request information acquisition unit 110, the arithmetic unit 120, and the output unit 130 by executing an arithmetic program.

[0035] Note that all or part of each function of the arithmetic unit 10 may be implemented using hardware such as an ASIC (Application Specific Integrated Circuit), a PLD (Programmable Logic Device), or an FPGA (Field-Programmable Gate Array). The arithmetic program may be recorded on a computer-readable recording medium. A computer-readable recording medium is, for example, a portable medium such as a flexible disk, a magneto-optical disk, a ROM, a CD-ROM, or a storage device such as a hard disk incorporated in a computer system. The arithmetic program may be transmitted via a telecommunication line.

[0036] The request information acquisition unit 110 acquires request information IR from the input device 40. The request information IR includes information on at least one of a required value of power loss at the time of switching of the switching element 60 or a required value of overshoot voltage at the time of switching of the switching element 60.

[0037] The arithmetic unit 120 calculates a switching pattern based on the acquired request information IR. Specifically, the arithmetic unit 120 calculates a switching pattern such that the power loss or overshoot voltage at the time of switching of the switching element 60 becomes at least one of the required value of power loss or the required value of overshoot voltage included in the request information IR. More specifically, the arithmetic unit 120 may be a learned neural network.

[0038] The output unit 130 outputs pattern information IP including the switching pattern calculated by the arithmetic unit 120. The pattern information IP is also described as voltage information or current information.

[0039] [Learning stage] Referring to FIGS. 4 to 10, the learning stage in the arithmetic system 1 will be described. In the learning stage, the arithmetic system 1 may learn using the measured values of power loss and overshoot voltage when actually applying a switching pattern to the switching element 60, or may create a combination of a switching pattern, power loss, and overshoot by simulation. Hereinafter, an example of creating a combination of a switching pattern, power loss, and overshoot by the teacher data generation unit 50 will be described.

[0040] FIG. 4 is a diagram showing an example of a switching pattern obtained by the simulation according to the present embodiment. In the figure, an example of a switching pattern is shown with the horizontal axis being slots and the vertical axis being the voltage level for each slot. A slot is a section obtained by dividing a predetermined control time during which the active gate driver 30 controls the voltage applied to the gate terminal of the switching element 60 into a plurality of sections. The larger the number of divisions (i.e., the larger the number of slots), the more precisely the control can be performed, but the processing becomes more complicated. The figure shows an example when divided into 12 slots. The voltage level is a section obtained by dividing the voltage value of the voltage applied by the active gate driver 30 to the gate terminal of the switching element 60 into a predetermined voltage value. The larger the number of divisions (i.e., the larger the number of voltage levels), the more precisely the control can be performed, but the processing becomes more complicated. The figure shows an example when divided into 10 levels. That is, in the example of the figure, there is a switching pattern of a combination of 12 slots × 10 levels.

[0041] The teacher data generation unit 50 first generates a plurality of switching patterns as shown in FIG. 4. Specifically, in the switching pattern shown in the figure, the voltage level when the slot is "1" is "5", the voltage level when the slot is "2" is "0", the voltage level when the slot is "3" is "10",..., and the voltage level when the slot is "12" is "8".

[0042] Note that when it is impossible to perform simulations for all patterns that can be used as switching patterns due to time constraints or performance constraints of the processing device, the teacher data generation unit 50 may specify a switching pattern using a random function and perform a simulation only for the specified switching pattern. That is, the teacher data generation unit 50 generates teacher data by calculating power loss or overshoot voltage according to a randomly given switching pattern.

[0043] Next, the teacher data generation unit 50 calculates, by simulation, the power loss and overshoot corresponding to each of the generated plurality of switching patterns. FIG. 5 is a diagram showing an example of the drain-source voltage obtained by the simulation according to the present embodiment. In the example shown in the figure, an example of the calculation of the overshoot is shown for the case where the teacher data generation unit 50 calculates the drain-source voltage V DS Here, the vertical axis represents the change of the drain-source voltage V DS with time. The drain-source voltage v DS shown in the figure specifically rises steeply 0.5 [ms (milliseconds)] after the voltage starts to be applied to the gate terminal of the switching element 60, and an overshoot voltage close to 900 [V (volts)] occurs. Then, after ringing for a predetermined time, it converges to 500 [V].

[0044] The teacher data generation unit 50 performs an operation for simulating a waveform as shown in the figure for a plurality of switching patterns. The teacher data generation unit 50 associates the switching pattern with the operation result and stores it as teacher data TD.

[0045] FIG. 6 is a diagram showing the correlation between the power loss and the overshoot voltage obtained by the simulation according to the present embodiment. With reference to this figure, the correlation between the power loss and the overshoot voltage of the teacher data TD generated by the teacher data generation unit 50 will be described. In this figure, the horizontal axis represents the overshoot voltage and the vertical axis represents the power loss, showing their correlation with each other. Since it is preferable that both the power loss and the overshoot voltage are small, the closer to the lower left in the figure, the more ideal the switching pattern can be said to be.

[0046] Next, the arithmetic unit 10 performs learning based on the teacher data TD generated by the teacher data generation unit 50. FIG. 7 is a diagram for explaining the learning stage of the neural network according to the present embodiment. The learning of the arithmetic unit 10 will be described with reference to this figure. Specifically, the arithmetic unit 10 is a neural network. A switching pattern is input to the input layer of the neural network. When the number of slots is 12, the number of nodes in the input layer is 12. A switching pattern corresponding to each node is input to each node. The power loss E loss and the overshoot voltage V OV are output from the output layer of the neural network.

[0047] FIG. 8 is a diagram for explaining an example of evaluation using the coefficient of determination obtained by the simulation according to the present embodiment. The evaluation of the learning result will be described with reference to this figure. FIG. 8(A) shows the result of learning the power loss, and FIG. 8(B) shows the result of learning the overshoot voltage. Both FIG. 8(A) and FIG. 8(B) show the predicted value on the vertical axis and the measured value on the horizontal axis.

[0048] Here, in order to measure the prediction accuracy, an evaluation using the coefficient of determination R 2 is performed. The coefficient of determination R 2 is represented by the following formula (1). The coefficient of determination R 2 is an index representing the explanatory power of the predicted value with respect to the true value of the target variable. The coefficient of determination R 2is a number between 0 and 1.0, indicating that the closer it is to 1.0, the higher the accuracy.

[0049]

Number

[0050] As a result of the learning, the coefficient of determination R of the power loss E loss was 0.995. Also, the coefficient of determination R of the overshoot voltage V 2 was 0.997. Therefore, it was found that both the power loss and the overshoot voltage were sufficiently close to 1.0, and the arithmetic unit 10 could predict them with high accuracy. OV of the overshoot voltage V 2 was 0.997. Therefore, it was found that both the power loss and the overshoot voltage were sufficiently close to 1.0, and the arithmetic unit 10 could predict them with high accuracy.

[0051] With reference to FIGS. 9 and 10, the relative error rates of the power loss and the overshoot voltage will be described. By calculating the relative error rate e, the accuracy of the simulation can be evaluated. The relative error rate e is represented by the following formula (2). In formula (2), y represents the measured value and t represents the predicted value.

[0052]

Number

[0053] FIG. 9 is a diagram for explaining the relative error rate obtained by the simulation according to the present embodiment. FIG. 9(A) shows the histogram of the power loss, and FIG. 9(B) shows the histogram of the overshoot voltage. It can be seen that for both the power loss and the overshoot voltage, the relative error rate e is extremely close to 0.

[0054] FIG. 10 is a diagram for explaining the average value and the standard deviation of the relative error rate obtained by the simulation according to the present embodiment. The figure shows the average value and the standard deviation of the relative error rate e for each of the power loss and the overshoot voltage. As shown in the figure, the average value of the relative error rate e of the power loss is 0.439, and the standard deviation is 0.772. The average value of the relative error rate e of the overshoot voltage is -0.002, and the standard deviation is 0.316. Therefore, it was found that both the power loss and the overshoot voltage can be predicted accurately. Therefore, it was found that the arithmetic unit 10 can predict with high accuracy.

[0055] [Prediction stage] Next, with reference to FIG. 11, the prediction stage will be described. In the prediction stage, the arithmetic unit 10 predicts the switching pattern based on the request information IR. Specifically, the arithmetic unit 10 is a neural network. FIG. 11 is a diagram for explaining the neural network according to the present embodiment. In the prediction stage, either the waveform of the power loss or the overshoot voltage at the time of switching of the switching element is input to the input layer of the neural network. The waveform of the power loss or the overshoot voltage is included in the request information IR. In an example shown in the figure, the overshoot voltage is input to the input layer. Specifically, the drain-source voltage V DS is input to the input layer. More specifically, after a predetermined voltage is applied to the gate terminal, the drain-source voltage V DS during 50 [ns] is input at a sampling interval of 0.1 [ns]. Therefore, the number of nodes in the input layer is 500. The drain-source voltage V DS corresponding to each node is input to each node. The switching pattern is output to the output layer of the neural network. Specifically, the voltage levels every 4 [ns] obtained by dividing the 48 [ns] period during which a voltage is applied to the gate terminal into 12 slots are output to the output layer.

[0056] [Findings obtained by prediction of the arithmetic unit] Next, with reference to FIGS. 12 to 17, the findings obtained by the prediction of the arithmetic unit 10 will be described. FIG. 12 is a diagram for explaining the correct answer rate for each slot regarding the calculation result of the calculation system according to the present embodiment. In this figure, an example of the case where a neural network (NN) is used as the calculation device 10 and an example of the case where a convolutional neural network (CNN) is used as the calculation device 10 are shown, and the correct answer rates are shown respectively. The correct answer rate is the ratio of whether the measured value is included within a predetermined threshold based on the predicted value.

[0057] When using the neural network NN and when using the convolutional neural network CNN, the correct answer rate was higher when using the convolutional neural network CNN. Also, in any case, the highest correct answer rate was obtained in slot 4, and the lowest correct answer rate was obtained in slot 12. Also, from slot 1 to slot 5, the correct answer rate was high, and generally, the result was a high correct answer rate. From slot 6 to slot 8, the correct answer rate was low, but it was considered that it was predicted to some extent. However, it was found that the correct answer rate after slot 9 was clearly low and hardly predictable.

[0058] FIG. 13 is a diagram showing the distribution of the number of correct answers for each level of each slot regarding the calculation result of the calculation system according to the present embodiment. FIGS. 13(A) to 13(L) show the distribution of the number of correct answers for slots 1 to 12 respectively. Each distribution of the number of correct answers has the predicted value on the x-axis, the measured value on the y-axis, and the number of data on the z-axis. When the predicted value and the measured value are the same, that is, when located on the diagonal line, it indicates high prediction accuracy. As shown in FIGS. 13(A) to 13(E), for slots 1 to 5, since the number of data located on the diagonal line is large, it can be seen that the prediction accuracy is high. Also, after FIG. 13(F), that is, after slot 6, the number of data located on the diagonal line gradually decreases, and after FIG. 13(I), that is, after slot 9, it can be seen that the prediction accuracy is low and hardly predictable.

[0059] Next, with reference to FIGS. 14 and 15, an example of a case where the predicted pattern and the actual pattern are substantially the same will be described. FIG. 14 is a diagram showing an example of a switching pattern in a case where the predicted pattern and the actual pattern of the arithmetic system according to the present embodiment are substantially the same. In the figure, the voltage level for each slot is shown with the slot on the horizontal axis and the voltage level on the vertical axis. The switching pattern indicated by the solid line in the figure shows the switching pattern predicted by the arithmetic unit 10. The switching pattern indicated by the broken line in the figure shows the actually measured result. From slot 1 to slot 6, the predicted pattern and the actual pattern completely match. On the other hand, from slot 7 to slot 12, the predicted pattern and the actual pattern do not match.

[0060] FIG. 15 is a diagram showing an example of a waveform in a case where the predicted pattern and the actual pattern of the arithmetic system according to the present embodiment are substantially the same. In the figure, the drain-source voltage V DS is shown with time on the horizontal axis and voltage on the vertical axis. Note that the figure shows the normalized value of the drain-source voltage V DS . The switching pattern indicated by the solid line in the figure shows the switching pattern predicted by the arithmetic unit 10. Also, the switching pattern indicated by the broken line in the figure shows the actually measured result. The example shown in the figure is an example of the voltage measured when the predicted pattern and the actual pattern shown in FIG. 14 are respectively input.

[0061] As is clear from the example shown in FIG. 15, although the predicted pattern and the actual pattern are different from each other, the drain-source voltage V DS is substantially the same.

[0062] Next, with reference to FIGS. 16 and 17, a case where the predicted pattern and the actual pattern do not match will be described. FIG. 16 is a diagram showing an example of a switching pattern when the predicted pattern and the actual pattern of the arithmetic system according to the present embodiment do not match. In this figure, the voltage level for each slot is shown with the slot on the horizontal axis and the voltage level on the vertical axis. The switching pattern indicated by the solid line in the figure shows the switching pattern predicted by the arithmetic unit 10. The switching pattern indicated by the broken line in the figure shows the measured result. In the example shown in this figure, in almost all slots from slot 1 to slot 12, the predicted pattern and the actual pattern do not match.

[0063] FIG. 17 is a diagram showing an example of a waveform when the predicted pattern and the actual pattern of the arithmetic system according to the present embodiment do not substantially match. In this figure, the drain-source voltage V DS is shown with time on the horizontal axis and voltage on the vertical axis. Note that the figure shows the normalized value of the drain-source voltage V DS . The switching pattern indicated by the solid line in the figure shows the switching pattern predicted by the arithmetic unit 10. Also, the switching pattern indicated by the broken line in the figure shows the measured result. The example shown in this figure is an example of the voltage measured when the predicted pattern and the actual pattern shown in FIG. 16 are respectively input.

[0064] As is clear from the example shown in FIG. 17, since the predicted pattern and the actual pattern are different from each other, the drain-source voltage V DS is also different. In the examples shown in FIGS. 16 and 17, compared with the examples shown in FIGS. 14 and 15, there are differences in that the predicted pattern and the actual pattern are different from each other in the slots in the first half. That is, among all 12 slots, it can be said that the slots in the first half (for example, slots 1 to 6) are the slots that affect the drain-source voltage V DS . Hereinafter, the slots that affect the drain-source voltage V DS will be referred to as effective slots.

[0065] Here, the number of effective slots, that is, the time among the times for controlling the gate terminal during which the drain-source voltage V DS changes depends on the device specification of the switching element 60. The number of effective slots varies depending on the type or individual differences of the switching element 60. Identifying effective slots or slots that are not effective slots and performing control only on the effective slots is effective for shortening the time required for the control of the active gate driver 30.

[0066] Note that in FIGS. 14 to 17, the drain-source voltage V DS has been described, but this embodiment is not limited to this example, and the power loss has a similar tendency.

[0067] [Modification Example of Arithmetic Unit] FIG. 18 is a diagram showing an example of the functional configuration of a modification example of the arithmetic unit according to this embodiment. With reference to this figure, the arithmetic unit 10A, which is a modification example of the arithmetic unit 10, will be described. The arithmetic unit 10A is different from the arithmetic unit 10 in that it further includes an actually measured information acquisition unit 140 and a specifying unit 150. In the description of the arithmetic unit 10A, the same components as those of the arithmetic unit 10 may be denoted by the same reference numerals and the description may be omitted.

[0068] The actually measured information acquisition unit 140 acquires actually measured information IM from the measuring device 70. The actually measured information IM is information including at least one of power loss or overshoot voltage when a switching pattern is applied to the gate of the switching element 60. That is, the actually measured information acquisition unit 140 acquires the actually measured information IM including at least one of power loss or overshoot voltage when a switching pattern is applied to the gate of the switching element 60 from the measuring device 70. The measuring device 70 acquires at least one of power loss or overshoot voltage during the switching of the switching element 60. The measuring device 70 may be, for example, a voltmeter or a wattmeter.

[0069] The specific part 150 identifies valid slots among the controllable slots, where a valid slot is a slot effective for at least one of power loss or overshoot voltage change. In other words, a valid slot is a slot that contributes to the change in power loss or overshoot voltage among the switching patterns calculated by the arithmetic unit 10. That is, the specific part 150 identifies valid slots that are slots contributing to the change in power loss or overshoot voltage among the calculated switching patterns.

[0070] Also, the specific part 150 may identify valid slots based on whether at least one of power loss or overshoot voltage is within a predetermined threshold. That is, the specific part 150 identifies as valid slots those slots where the difference between the power loss or overshoot voltage predicted by the switching pattern and the power loss or overshoot voltage included in the measured information is within the predetermined threshold. The output part 130 outputs a switching pattern for controlling the identified valid slots.

[0071] Note that, as a result of learning based on the first teacher data, valid slots are identified, and second teacher data limited to the valid slots is generated, so that learning may be configured to be more effective. By adopting such a configuration, the arithmetic system 1 can omit the time for learning about slots that are not valid slots and can learn more efficiently.

[0072] [Summary of the Embodiment] According to the embodiments described above, by including the request information acquisition unit 110, the arithmetic unit 10 acquires request information IR including at least one of the power loss or the required value of the overshoot voltage during the switching of the switching element 60, and calculates a suitable switching pattern based on the acquired request information IR. The switching element 60 is, for example, a non-contact switch such as a FET or a transistor which is a power device. Further, the request information IR may be a waveform including at least one of the required value of the power loss or the overshoot voltage. Therefore, since the arithmetic unit 10 calculates a suitable switching pattern based on the request information IR, according to the arithmetic unit 10, it is possible to easily find a switching pattern capable of suppressing the surge voltage and power loss of the power device.

[0073] Also, according to the embodiments described above, the arithmetic unit 120 is a neural network. Further, the arithmetic unit 120 is trained to calculate a switching pattern such that the power loss or the overshoot voltage becomes the same as the required value. Therefore, according to the present embodiment, since the switching pattern is calculated using machine learning, processing can be performed at high speed compared to the case of calculating the switching pattern by the conventional technique. Also, according to the present embodiment, since the switching pattern is calculated using machine learning, calculations based on a large number of simulation results can be performed. Therefore, according to the present embodiment, the switching pattern can be found accurately.

[0074] Also, according to the embodiments described above, by including the specifying unit 150, the arithmetic unit 10A specifies the effective slots. The effective slots are the slots that contribute to the change in the power loss or the overshoot voltage. Therefore, according to the present embodiment, it is possible to easily know the number of slots to be used for control, and by not controlling the slots that do not contribute to the change in the power loss or the overshoot voltage, the processing time can be shortened.

[0075] Also, according to the above-described embodiment, the arithmetic unit 10A includes the measured information acquisition unit 140, and acquires measured information IM including at least one measured value of the power loss or the overshoot voltage value when a voltage is applied to the gate terminal of the switching element 60. The specifying unit 150 specifies the effective slot based on the predicted result and the measured value included in the acquired IM. Therefore, according to the present embodiment, the effective slot can be specified with high accuracy.

[0076] Also, according to the above-described embodiment, the arithmetic system 1 includes the arithmetic unit 10 as described above and a storage unit in which teacher data is stored, and learns based on the stored teacher data. The teacher data is data in which a switching pattern is associated with a required value of power loss or a required value of overshoot voltage. Therefore, according to the present embodiment, the arithmetic unit 10 can be easily learned without taking time for learning.

[0077] Also, according to the above-described embodiment, the arithmetic unit 10 includes the teacher data generation unit 50, and generates teacher data in which a switching pattern is associated with a required value of power loss or a required value of overshoot voltage by simulation. Therefore, according to the present embodiment, a large amount of teacher data can be generated without measurement, and thus the arithmetic unit 10 can be easily learned in a short time.

[0078] Also, according to the above-described embodiment, the arithmetic unit 10 generates a large amount of teacher data according to a randomly given switching pattern. Therefore, according to the present embodiment, even when simulations are not performed for all combinations of switching patterns, teacher data can be generated without bias. Therefore, according to the present embodiment, the arithmetic unit 10 can be accurately learned.

[0079] Note that all or part of the functions provided by the above-described arithmetic unit 10 and arithmetic unit 10A may be recorded as a program on a computer-readable recording medium, and this program may be executed by a computer system. The computer system shall include hardware such as an OS and peripheral devices. Further, the computer-readable recording medium is, for example, a portable medium such as a flexible disk, a magneto-optical disk, a ROM (Read Only Memory), a CD-ROM, a storage device such as a hard disk built into the computer system, or a volatile memory (Random Access Memory: RAM) provided in a server on a network such as the Internet. Note that the volatile memory is an example of a recording medium that holds a program for a certain period of time.

[0080] Also, the above-described program may be transmitted to another computer system via a transmission medium, for example, a network such as the Internet or a communication line such as a telephone line.

[0081] Also, the above program may be a program that realizes all or part of the above-described functions. Note that the program that realizes part of the above-described functions may be a program that can be realized in combination with a program pre-recorded in the computer system for the above-described functions, that is, a so-called differential program.

[0082] As described above, the embodiments of the present invention have been described with reference to the drawings, but the specific configuration is not limited to the above-described embodiments, and also includes design changes and the like without departing from the gist of the present invention.

Explanation of Reference Numerals

[0083] 1…Computation system, 10…Computation device, 110…Required information acquisition unit, 120…Computation unit, 130…Output unit, 140…Measured information acquisition unit, 150…Specification unit, 20…Memory device, 30…Active gate driver, 40…Input device, 50…Teacher data generation unit, 60…Switching element, 70…Measuring device, NN…Neural network, IR…Required information, IP…Pattern information, ID…Drive information, TD…Teacher data, 90…Gate drive circuit, 91…Gate drive circuit, 92…Switching element, 94…Load, 941…Diode, 942…Inductance, 95…Ground point, 96…DC power supply terminal

Claims

1. A switching pattern including a change over time in a voltage value applied to a gate of a non-contact switch or a current value flowing into a base of the non-contact switch, the switching pattern including time slots for each time and a voltage value or a current value corresponding to the slot, in an arithmetic unit that calculates the switching pattern, A required information acquisition unit that acquires required information including at least one of information on a required value of power loss generated in the non-contact switch when the non-contact switch is switched or a required value of overshoot voltage that is a maximum value of voltage between both ends of a main current path in the non-contact switch when the non-contact switch is switched; An arithmetic unit that calculates the switching pattern based on the acquired required information; And an output unit that outputs the calculated switching pattern An arithmetic unit comprising the same.

2. The arithmetic unit is a neural network learned to calculate the switching pattern such that the power loss or the overshoot voltage becomes at least one of the required value of the power loss included in the required information or the required value of the overshoot voltage. The arithmetic unit according to claim 1.

3. Further comprising a specifying unit that specifies an effective slot that is the slot contributing to the change in the power loss or the overshoot voltage among the calculated switching patterns, The output unit outputs a switching pattern that controls the specified effective slot. The arithmetic unit according to claim 1 or claim 2.

4. Further comprising an actual measurement information acquisition unit that acquires actual measurement information including at least one of the power loss or the overshoot voltage when the switching pattern is applied to the gate of the non-contact switch. The specific part specifies the slot within a predetermined threshold as the effective slot, where the difference between the power loss or the overshoot voltage predicted by the switching pattern and the power loss or the overshoot voltage included in the measured information is within a predetermined threshold. The arithmetic unit according to claim 3.

5. An arithmetic unit according to any one of claims 1 to 4, and a storage unit that stores teacher data for training the arithmetic unit, the teacher data being such that the switching pattern is associated with a required value of the power loss or a required value of the overshoot voltage, The arithmetic unit is trained by the teacher data stored in the storage unit. An arithmetic system.

6. Further comprising a teacher data generation unit that generates the teacher data by simulation. The arithmetic system according to claim 5.

7. The teacher data generation unit generates the teacher data by calculating the power loss or the overshoot voltage corresponding to the randomly given switching pattern. The arithmetic system according to claim 6.

8. A required information acquisition step of acquiring required information including at least one of a required value of power loss generated in the non-contact switch during switching of the non-contact switch or a required value of overshoot voltage which is the maximum value of the voltage between both ends of the main current path in the non-contact switch during switching of the non-contact switch, An arithmetic step of calculating a switching pattern including the change over time of the voltage value applied to the gate of the non-contact switch or the current value flowing into the base of the non-contact switch, the arithmetic step of calculating the switching pattern based on the acquired required information, An output step of outputting the calculated switching pattern and having an arithmetic method.

9. causing a computer to a required information acquisition step of acquiring required information including at least one of information on a required value of power loss generated in the non-contact switch during switching of the non-contact switch or information on a required value of overshoot voltage which is a maximum value of voltage between both ends of a main current path in the non-contact switch during switching of the non-contact switch; a calculation step of calculating a switching pattern including a change over time of a voltage value applied to a gate of the non-contact switch or a current value flowing into a base of the non-contact switch, the calculation step of calculating the switching pattern based on the acquired required information; an output step of outputting the calculated switching pattern; and a program for executing the above.

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