Method for manufacturing an electronic device precursor

Abstract

A method 100 for manufacturing an electronic device precursor 200 is provided, comprising: (i) providing 105 a plasma-etchable layer structure 210 on a plasma-resistant substrate 205, the layer structure 210 having an exposed top surface; (ii) patterning 110 a plasma-resistant dielectric 215 on the exposed top surface to form an intermediate body having at least one covered region and at least one uncovered region of the layer structure 210; (iii) subjecting the intermediate body to plasma etching 115, thereby etching away the at least one uncovered region of the layer structure 210 to form at least one covered region of the layer structure 210 having an exposed edge surface; and (iv) forming 120 ohmic contacts 220 a, 220 b in direct contact with a portion of the exposed edge surface, the plasma-etchable layer structure 210 including one or more graphene layers extending across the covered region of the layer structure 210 to the exposed edge surface.

Description

Technical Field

[0001] The present invention provides a method for manufacturing an electronic device precursor. In particular, a method including plasma etching to expose an edge surface of a graphene layer for direct contact with an ohmic contact and forming the ohmic contact. Further, the present invention provides an electronic device precursor, in particular an electronic device precursor including a graphene layer that makes direct contact with an ohmic contact at an edge. Further, the electronic device precursor includes a continuous air-resistant coating layer for protecting the edge of the graphene layer. Most preferably, the electronic device precursor is for a Hall effect sensor.

Background Art

[0002] Two-dimensional (2D) materials, particularly graphene, are currently the focus of intense research and development worldwide. 2D materials have been shown to have very excellent properties both theoretically and practically, and as a result, products incorporating such materials, including coatings, batteries, and sensors, are being mass-produced, but the number of 2D materials is small. Graphene is the most prominent and has been studied for various potential applications. The most notable is the use of graphene in electronic devices and their components, including transistors, LEDs, photovoltaic cells, Hall effect sensors, diodes, and the like.

[0003] Accordingly, a wide range of electronic devices known in the prior art incorporating graphene layer structures (single-layer or multi-layer graphene) and / or other 2D materials exist as important materials for bringing about improvements in such devices over previous devices and electronic products. These include structural improvements through the use of thinner and lighter materials (which can lead to flexible electronic devices), as well as performance improvements such as increased electrical and thermal conductances that result in higher operating efficiencies.

[0004] However, due to the air interactions and sensitivity to contamination of the exposed 2D materials, it is necessary to encapsulate the 2D materials and / or devices comprising such materials with one or more protective layers. The inventors have found that the metals present in ohmic contacts necessary to form electrical connections to 2D materials can introduce unwanted doping. Doping of 2D materials results in the modification of electronic properties. In the case of devices such as Hall effect sensors (also known as Hall sensors), device operation is highly sensitive to changes in the electronic structure as it relies on maintaining charge neutrality within the 2D material as close as possible. Nevertheless, contamination from oxygen or water vapor in the air can lead to a degradation of device performance over time, which is undesirable for customers / consumers who expect electronic devices to maintain a certain level of performance for years after manufacture. Furthermore, it may not be possible, or at least very difficult, to retroactively replace electronic components, particularly microelectronic components, and thus even a slight improvement in lifespan and performance stability is highly important.

[0005] During the manufacture of electronic devices, the inventors have found that standard lithography processes, such as those used to etch the desired configuration of underlying 2D materials using a polymer coating such as PMMA, have several drawbacks. PMMA coatings can dope 2D materials and may not be suitable for variable temperature applications or particularly high or low temperature applications. Standard processes for removing such polymer coatings by dissolution in organic solvents can introduce further impurities and contamination, which can prevent the manufacture of reliable devices with consistent properties essential for electronic devices such as microelectronics. Nevertheless, it is also known that polymer residues can remain and interfere with subsequent processing steps.

[0006] Alternatively, it is known that in order to avoid contamination, 2D materials can be simply laser-etched from a substrate without using such photolithography materials. Such a method involves using a laser beam to ablate the substrate and the 2D material outside the active region, leaving a patterned 2D material layer. One such disclosure can be found in UK Patent No. 2570124, which discloses using a laser having a wavelength greater than 600 nm and an output of less than 50 watts to selectively ablate graphene from a substrate having a higher thermal resistance than sapphire. This process has been found to function well in patterning without damaging the graphene layer structure or the underlying substrate, but this process can generate large particles of debris that can land on the 2D material surface. The debris can act as a contaminant or at least prevent the formation of an effective and / or hermetic coating on the 2D material.

[0007] Accordingly, it is desirable to manufacture an electronic device comprising a 2D material (or, indeed, manufacture a precursor for an electronic device for use as an electronic device when providing the necessary electrical connections) via a method involving fewer processing steps, thereby avoiding unnecessary and harmful contamination and / or doping. As a result, there is also a desire for electronic devices and their precursors that offer improved long-term stability and / or temperature stability over the prior art. Improvements are needed to enable the use of 2D material-based devices under extreme conditions in order to benefit from the unique electronic properties of 2D materials.

[0008] The inventors have also found that contact deposition after device encapsulation hinders the electrical contact between the 2D material and the metal, which is essential for the final electronic device to function. However, contact deposition before the encapsulation or coating layer can cause problems due to the height difference between the 2D material and the contact thereon, resulting in a non-conformal coating that is more susceptible to damage.

[0009] Chinese Patent No. 103985762 discloses an ultra-low ohmic contact resistance graphene transistor. The method disclosed therein includes patterning a dielectric layer with a photoresist and etching the dielectric layer using a wet chemical technique (e.g., buffered oxide etching (BOE) or a mixture of nitric acid and hydrogen peroxide (HNO3 + H2O2)).

[0010] 「The Dependence of the High-Frequency Performance of Graphene Field-Effect Transistors on Channel Transport Properties」, Asad et al., Journal of the Electron Devices Society, 8, 2020, pages 457 - 464 discloses a graphene field-effect transistor including an Al2O3 dielectric layer patterned using lithography technology and etching for removing the dielectric in the contact region on graphene.

Summary of the Invention

Problems to be Solved by the Invention

[0011] There is still a need for a method that enables the manufacture of an electronic device precursor including a 2D material layer and avoids surface contamination and doping by ohmic contact deposition. There is also still a need for a method that can encapsulate a 2D material while enabling the provision of at least one ohmic contact. The object of the present invention is to provide a method and several specific embodiments that each overcome, or substantially reduce, or at least provide a commercially useful alternative to various problems associated with the prior art, together with an electronic device precursor obtained by such a method.

Means for Solving the Problems

[0012] Therefore, the present inventors have devised a method of protecting a graphene layer on a substrate using a plasma-resistant dielectric, defining an etching pattern of the graphene layer, and functioning as a protective coating in a final device precursor (and ultimately the device). The present inventors have found that by using a plasma-resistant dielectric to define an etching pattern of a plasma-etchable layer structure containing graphene, an intermediate is obtained in which only the edges of the graphene layer are left exposed, and an ohmic contact can be formed in direct contact with a part of the exposed edges.

[0013] Accordingly, according to a first aspect of the present invention, there is provided a method of manufacturing an electronic device precursor, comprising: (i) providing a plasma-etchable layer structure on a plasma-resistant substrate, the layer structure having an exposed upper surface; (ii) patterning a plasma-resistant dielectric on the exposed upper surface to form an intermediate having at least one coated region and at least one uncoated region of the layer structure; (iii) subjecting the intermediate to plasma etching, thereby etching away at least one uncoated region of the layer structure to form at least one coated region of the layer structure having an exposed edge surface; (iv) forming an ohmic contact in direct contact with a part of the exposed edge surface, wherein the plasma-etchable layer structure includes one or more graphene layers extending to the exposed edge surface across the coated region of the layer structure.

[0014] Next, the present disclosure will be further described. In the following sections, different aspects / embodiments of the present disclosure are defined in more detail. Each aspect / embodiment so defined can be combined with any other aspect / embodiment or aspects / embodiments unless clearly indicated otherwise. In particular, any feature shown to be preferred or advantageous can be combined with any other feature shown to be preferred or advantageous.

[0015] Thus, the method disclosed herein uses a plasma-resistant dielectric to define an etching pattern and protect the surface of the 2D material from being doped by ohmic contacts. This solution is particularly sophisticated because the inventors have found that charge injection is significantly greater at the edges of the 2D material layer than at the surface, thereby avoiding doping and simultaneously improving the flow of current.

[0016] As described above, the present invention provides a method for manufacturing an electronic device precursor. The precursor is typically intended to refer to a component that can be installed in an electrical or electronic circuit by wire bonding to a further circuit or by other methods known in the art such as soldering using the "flip chip" style solder bumps described herein. Thus, an electronic device is a functional device that supplies current to the precursor during installation and operation.

[0017] This method includes a first step of providing a plasma-etchable layer structure on a plasma-resistant substrate, the layer structure having an exposed upper surface, and the plasma-etchable layer structure including one or more graphene layers.

[0018] The plasma-etchable layer structure can be etched during the plasma etching step as is typical in electronic device manufacturing to ablate the layer structure rather than the underlying substrate. Plasma etching will be described in more detail herein. In the present invention, the plasma-etchable layer structure includes, preferably consists of, one or more graphene layers. Preferably, at least the uppermost layer of the plasma-etchable layer structure is a graphene layer, thereby ensuring that at least the uppermost graphene layer is etched during plasma etching to form an exposed edge surface.

[0019] Preferably, the plasma-etchable layer structure consists of one or more 2D material layers. 2D materials are well-known in the art and are sometimes referred to as monolayer materials consisting of a single layer of atoms, but materials generally known as transition metal dichalcogenides are also well-known 2D materials that include a layer of metal atoms sandwiched between layers of chalcogen atoms (i.e., compounds of the type MX2 composed of three atomic planes). Similarly, graphen (CH) n and graphene oxide are 2D materials, which are graphene with terminal hydrogen atoms and graphene oxide with cross-linked oxygen atoms and terminal hydroxyl groups. Silicene is not completely flat and has wrinkles. In all situations, 2D materials can be regarded as two-dimensional quasi-infinite-sized sheets or layers, including, for example, graphene, graphyne, silicene, germanene, borophene, phosphorene, antimonene, hexagonal boron nitride (h-BN), borocarbonitride, and TMDCs (e.g., MoS2, WS2, MoSe2, WSe2, and MoTe2). Thus, in some embodiments, the plasma-etchable layer structure consists of one or more layers of graphene and one or more layers of silicene, germanene, h-BN, borophene, and / or TMDC. In such embodiments, the plasma-etchable layer structure may be referred to as a heterostructure. Even more preferably, the plasma-etchable layer structure consists of one or more layers of graphene, which may be referred to as a graphene layer structure.

[0020] The present invention provides at least one ohmic contact that directly contacts the exposed edge surface of at least one graphene layer of the plasma-etchable layer structure. The plasma-etchable layer structure includes graphene and optionally silicene, germanene, borophene, h-BN, and / or TMDC. Thus, any reference to graphene herein applies equally to other 2D materials unless the context clearly indicates otherwise.

[0021] The layer structure may include 1 to 10 individual 2D material layers, at least one of which is a graphene layer. For example, a plasma-etchable layer structure consists of a single layer of graphene. When the layer structure includes multiple 2D material layers, 2 to 5 layers are preferred, and 2 or 3 layers are even more preferred. Nevertheless, a single layer is also preferred because some of the inherent properties due to the 2D material are most prominent when provided as a single layer. For example, single-layer graphene is a zero-bandgap semiconductor (i.e., a semimetal), the density of states at the Fermi level is 0, and the top of the valence band meets the bottom of the conduction band (forming a Dirac cone). Due to the low density of states near the Dirac point, the shift of the Fermi level is particularly sensitive to charge transfer to graphene in such an initial state. The electronic structure also gives rise to, for example, the quantum Hall effect. Thus, in certain embodiments, particularly the hall sensor configurations described herein, a single layer of graphene is particularly preferred and provides the greatest benefit from the present invention. Nevertheless, bilayer or multilayer graphene (so-called graphene layer structures) can be used.

[0022] In the first step of the method, providing graphene with a plasma-etchable layer structure can be achieved by any method known in the art. However, the plasma-etchable layer structure containing graphene is synthesized directly on the surface of the substrate and thus does not include any physical transfer steps. Preferably, the graphene and any other two-dimensional material layer are formed by CVD or MOCVD growth. It is particularly preferred that graphene is formed by VPE or MOCVD. MOCVD is a term used to describe a system used for a specific method of depositing a layer on a substrate. This acronym represents metal-organic chemical vapor deposition, but MOCVD is a term in the art and is understood to be related to general processes and the apparatus used therein, and is not necessarily considered to be limited to the use of metal-organic reactants or the production of metal-organic materials, but simply requires the use of carbon-containing precursors when forming graphene. Instead, the use of this term indicates to those skilled in the art a general set of process and apparatus characteristics. MOCVD is further different from CVD technology due to the complexity and precision of the system. CVD technology enables reactions to be carried out with simple stoichiometry and structure, while MOCVD enables the generation of difficult stoichiometry and structure. The MOCVD system differs from the CVD system by at least a gas distribution system, a heating and temperature control system, and a chemical control system. The MOCVD system typically costs at least 10 times more than a typical CVD system. MOCVD is particularly preferred for achieving high-quality graphene layer structures.

[0023] MOCVD can also be readily distinguished from atomic layer deposition (ALD) technology. ALD relies on the stepwise reaction of reagents with intervening flushing steps, which are used to remove unwanted products and / or excess reagents. It does not rely on the decomposition or dissociation of reagents in the gas phase. It is not particularly suitable for the use of low-vapor-pressure reagents such as silane that require excessive time for removal from the reaction chamber. The MOCVD growth of graphene is discussed in WO 2017 / 029470 pamphlet, which is incorporated by reference and provides a preferred method.

[0024] The method of WO 2017 / 029470 pamphlet provides a chamber having a plurality of cooled inlets arranged such that, in use, the inlets are distributed across the substrate and have a defined separation from the substrate. The flow containing the precursor compound may be provided as a horizontal laminar flow or may be provided substantially vertically. Inlets suitable for such reactors are well known and include Planetary and Showerhead® reactors available from Aixtron®. Other suitable growth chambers include Turbodisc K series or Propel® MOCVD systems available from Veeco® Instruments Inc.

[0025] Thus, in one particularly preferred embodiment, the step of providing a plasma-etchable layer structure on a plasma-resistant substrate is the step of forming a graphene layer structure, the step of providing the plasma-resistant substrate on a heated susceptor within a reaction chamber, the chamber having a plurality of cooled inlets arranged such that, in use, the inlets are distributed across the substrate and have a defined separation from the substrate, and the step of supplying a flow containing a precursor compound into the reaction chamber through the inlets, thereby decomposing the precursor compound and forming graphene on the substrate. The step is that the inlet is cooled to less than 100°C, preferably 50°C to 60°C, and the susceptor is heated to a temperature of at least 50°C above the decomposition temperature of the precursor.

[0026] Such methods enable the production of very high-quality pristine graphene that can be scaled up to large-area substrates and the production of arrays of electronic device precursors. As described herein, such pristine graphene is advantageous for use in hall sensor applications due to the quantum hall effect that results from the unique electronic structure of pristine graphene.

[0027] As described herein, sapphire and silicon are preferred substrates, particularly in the case of graphene prepared by the method of International Publication No. WO 2017 / 029470. As will be appreciated, a silicon substrate can include a CMOS substrate that is a silicon-based substrate, whereby graphene is deposited on the silicon surface, and the CMOS substrate can include various additional layers or circuits embedded therein. Sapphire is a particularly preferred substrate. R-plane sapphire is most preferred. As is known in the art, the r-plane refers to the crystallographic orientation of the surface of the substrate (i.e., the surface on which graphene is deposited). Such substrates are particularly suitable for providing high-quality graphene, particularly sensors such as the hall effect sensors described herein. In part, this is due to the effect of the substrate on the charge carrier density resulting from the graphene deposited thereon. The inventors have found that r-plane sapphire provides graphene having a particularly low charge carrier density. Preferably, the charge carrier density of one or more graphene layers is 10 12 cm -2 less than, preferably 8×10 11 cm -2 less than. For example, when using r-plane sapphire, a charge carrier density of less than 6×10 11 cm -2 less than, preferably 5×10 11 cm -2 less than can be obtained.

[0028] The 2D material with a plasma-etchable layer structure may be a doped 2D material. As a mere example, when the 2D material is graphene and is doped, the graphene is preferably doped with one or more elements selected from the group consisting of silicon, magnesium, zinc, arsenic, oxygen, boron, bromine, and nitrogen. Similarly, the method may then preferably include the step of introducing a doping element into the reaction chamber and selecting the temperature of the substrate, the pressure of the reaction chamber, and the gas flow rate to produce the doped graphene. Preferably, the precursor for the growth of the doped graphene contains a doping element. Alternatively, a precursor containing a seed (e.g., carbon for graphene growth and silicon for silicon carbide growth) and one or more additional precursors containing a doping element are introduced onto the substrate in the reaction chamber, and the second precursor is in gaseous form or suspended in a gas to produce the doped graphene. The deposition of the plasma-resistant dielectric itself can result in the doping of the 2D material. Thus, the use of the provided doped 2D material can compensate for any doping effects from the patterning of the dielectric thereon.

[0029] The plasma-etchable layer structure is provided on a plasma-resistant substrate. In other words, the layer structure is directly on the substrate without an intervening layer. The layer structure composed of the 2D material layer provides a layer structure having two opposing surfaces, and the first surface or the bottom surface is the surface in direct contact with the substrate. Thus, the second surface or the top surface is exposed, and preferably, at least this layer is a graphene layer.

[0030] Plasma-resistant substrates are well-known in the art. Ceramic materials such as silicon carbide, silicon nitride, and silicon oxide are particularly plasma-resistant. Standard crystalline silicon wafers can be considered ceramics and are plasma-resistant. Crystalline group III-V semiconductors are also plasma-resistant and may be preferred as substrates for certain applications such as LEDs. In a preferred embodiment, the plasma-resistant substrate is sapphire, silicon, silicon dioxide, silicon nitride, silicon carbide, germanium, or a group III-V semiconductor, more preferably sapphire or silicon.

[0031] In a preferred embodiment, the rate of etching the layer structure and the substrate is at least 10 times, preferably 10 2 times, more preferably 10 3 times different. Thus, regardless of the resistivity of the substrate to a given plasma treatment, the layer structure is etched significantly more rapidly than the substrate, resulting in complete etching of the exposed layer structure and negligible loss of the substrate surface over the time required for the plasma etch.

[0032] Preferably, the plasma-etchable layer structure has an etching rate of greater than 0.345 nm per minute. The plasma etching rate can be measured using oxygen plasma etching with an output of 40 W and an O2 flow of 6 sccm. Thus, under these conditions, in one minute, a monolayer of graphene (ideal thickness 0.345 nm) would be etched. Preferably, the etching rate is greater than 0.5 nm per minute. Thus, the plasma-resistant substrate can preferably have an etching rate of less than 0.1 nm per minute, preferably less than 0.01 nm per minute.

[0033] The method further includes patterning a plasma-resistant dielectric on the exposed top surface to form an intermediate having at least one coated region and at least one uncoated region of a layer structure. As described herein with respect to plasma-resistant substrates, the plasma-resistant dielectric may be any known in the art, and its plasma resistivity is measured by the same parameters (i.e., with respect to layer structure and / or etching rate). Typically, this is an inorganic dielectric such as a ceramic (i.e., one that does not contain carbon-hydrogen bonds). The ceramic may be considered to be an inorganic oxide, nitride, carbide, fluoride, or sulfide, and often has a crystalline structure. In a preferred embodiment, the plasma-resistant dielectric is an inorganic oxide, nitride, carbide, fluoride, or sulfide, preferably one of alumina (aluminum oxide), silica (silicon dioxide), or silicon nitride.

[0034] Inorganic dielectrics, particularly ceramic dielectrics, are particularly preferred because they provide significantly improved barrier properties over organic dielectric materials such as PMMA. Thus, the dielectric layer can be retained in the final electronic device precursor to protect the layer structure from contamination by airborne contaminants, particularly oxygen and water vapor. This air and moisture-resistant coating provides a barrier against unintentional doping over a significantly longer period, improving the device lifetime. Further, inorganic materials such as ceramics can withstand large temperature variations as well as operation at very high temperatures, enabling the use of electronic devices under more extreme conditions without risk of damage to the layer structure and eventual contamination, which would otherwise eventually lead to drift in device performance (requiring recalibration or simply causing device failure).

[0035] A plasma-resistant dielectric is patterned on the exposed top surface of the plasma-etchable layer structure. That is, the plasma-resistant dielectric is patterned simultaneously with being deposited on the exposed top surface of the plasma-etchable layer structure. As described herein, this is particularly preferably achieved by physical vapor deposition (PVD). PVD is a well-known technique. The patterning results in the formation of a dielectric across a portion of the surface, thereby forming one or more coated regions and one or more uncoated regions of the layer structure (providing an intermediate in the manufacture of the device precursor). In a preferred embodiment, the method includes the step of forming an array of coated regions, each corresponding to an electronic device precursor. Such patterning to form an array of coated regions can include using a mask (i.e., a shadow mask), thereby forming a dielectric in a plurality of regions. The formation of at least one coated region results in the uncoated region being the remaining portion of the layer structure. Thus, when an array of coated regions is patterned on the layer structure, this typically provides at least one continuous uncoated region separating the coated regions. In a preferred embodiment, the plasma etching step described herein results in the formation of a continuous outer edge surface of the layer structure of each electronic device precursor (i.e., the formation of a "filled" "2D shape" having an outer edge), so that only one uncoated region is formed during the patterning step. However, in some embodiments, the 2D shape and the patterned dielectric may have therein an uncoated portion that provides inner and outer edges to the graphene layer after etching.

[0036] Thus, in a preferred embodiment, the patterning step includes forming one or more rectangular-shaped regions of the plasma-resistant dielectric. Such patterning of the dielectric and then the 2D material means that it is particularly preferred for the electronic device precursor to form a transistor. The electronic device precursor may then preferably further comprise a gate contact which is a third contact. The gate contact may be provided, for example, on top of the plasma-resistant dielectric or coating (if present) as a so-called “front gate” or under the substrate as a so-called “back gate”. When provided under the substrate, the 2D material is provided on an insulating region of the substrate surface. Silicon substrates having SiO2, SiO2 / Si, and “embedded” SiO2 regions (as well as silicon nitride equivalents) are exemplary substrates that can be used to fabricate the transistors of the present invention. Alternatively, in a preferred embodiment, the patterning step includes forming one or more regions having a “Hall bar” and / or “van der Pauw” shape (such geometries or shapes are well known in the art and include, for example, circles, “clover leaves”, squares, rectangles, and crosses) of the plasma-resistant dielectric, preferably regions having a cross-shaped region. These geometries are well known in the art for Hall sensors (which require at least four contacts), and the cross is the most preferred geometry, and thus the electronic device precursor is preferably for forming a Hall sensor.

[0037] In embodiments including forming an array of coated regions, the method preferably further includes a step of dicing the substrate to separate the electronic device precursors from the array. Thus, multiple electronic device precursors can be fabricated simultaneously on a single substrate and then diced for individual use. This dicing step is preferably performed towards the end of the process.

[0038] In a preferred embodiment of the present invention, the patterning step includes patterning the plasma-resistant dielectric by physical vapor deposition such as electron beam evaporation or thermal evaporation. Preferably, electron beam evaporation is used to pattern the plasma-resistant dielectric and is preferably performed using a mask (i.e., a shadow mask). Such a method is particularly suitable for depositing an alumina or silica plasma-resistant dielectric layer on a 2D material layer.

[0039] Preferably, the thickness of the patterned dielectric is less than 200 nm, preferably less than 100 nm, more preferably less than 50 nm and / or more than 1 nm, preferably more than 3 nm, more preferably more than 5 nm. Thus, the dielectric layer can have a thickness of 1 nm to 200 nm, preferably 3 nm to 100 nm, even more preferably 5 nm to 50 nm.

[0040] The method further includes subjecting the intermediate to plasma etching, whereby at least one uncoated region of the layer structure is etched away to form at least one coated region of the layer structure having an exposed edge surface. The plasma etching step etches all uncoated regions of the plasma-etchable layer structure, thereby exposing the underlying substrate within these regions. The plasma-resistant dielectric prevents etching of the layer structure within the coated region, and thus plasma etching results in the formation of exposed edges of the layer structure whose shape and boundaries match those of the patterned dielectric thereon. Thus, as described herein, the 2D material layer extends across (and down to) the exposed edge surface of the coated region of the layer structure. Thus, the shape or pattern of the dielectric defines the shape of the etched 2D material layer.

[0041] Plasma etching is a typical process used in the manufacture of electronic devices and integrated circuits. Plasma etching involves a flow of plasma of a suitable gas mixture across a substrate, and the plasma is typically formed by applying RF between two electrodes under low pressure. In oxygen plasma etching, RF radiation ionizes the gas to form oxygen radicals, which etch the layer structure. By-products, also known as "ash" in the art, are removed by a pump, which are mainly carbon monoxide and carbon dioxide when the graphene layer structure is etched by oxygen plasma etching. In a preferred embodiment, plasma etching includes oxygen plasma etching. In a preferred embodiment, oxygen plasma etching involves using an RF output of at least 5 W, preferably at least 10 W, more preferably at least 20 W, and preferably less than 200 W, preferably less than 100 W. The flow rate of O2 can be at least 1 sccm, preferably at least 3 sccm and / or less than 50 sccm, preferably less than 30 sccm. Preferably, the chamber pressure is at least 0.1 mbar and / or a maximum of 100 mbar, preferably at least 0.2 mbar and / or a maximum of 10 mbar. Thus, the time required for plasma etching can be as little as 1 second and / or a maximum of 5 minutes. Preferably, the required time is at least 10 seconds and / or less than 2 minutes.

[0042] Finally, the method of the present invention further includes the step of forming an ohmic contact (i.e., at least one ohmic contact) that directly contacts a portion of the exposed edge surface. Additional contacts may also be formed and may be formed simultaneously. In that case, additional contacts that directly contact the exposed edge surface but are separate from the other contacts (i.e., the contacts do not contact each other) are also provided. Preferably, one or more ohmic contacts are metal contacts preferably including one or more of titanium, aluminum, chromium, and gold. Preferably, the contacts are metal contacts of titanium and / or gold. The contacts can preferably be formed by any standard technique such as electron beam deposition using a mask.

[0043] The inventors have found that the dielectric layer not only protects the underlying 2D material from air pollution but also prevents contacts from being formed on the surface of the 2D material. Thus, the 2D material is substantially protected from metal doping and avoids wet lithography techniques, including avoiding etchants such as BOE, as contact occurs only at the exposed edges, enabling improved contact between ohmic contacts and graphene. Furthermore, the inventors have found that as a result, charge injection is significantly more efficient at the edges of the 2D material.

[0044] The protective dielectric layer helps limit contamination of the graphene surface; nevertheless, while being very effective especially over long periods, the inventors have found that the exposed edges can provide a path for contamination and doping of the 2D material over time. This process is significantly slower than surface doping and can occur only to a limited extent, but the inventors have found that stability and lifetime can be further improved by providing an additional protective or coating layer that is resistant to air (and moisture). As described herein for devices such as Hall sensors, the functionality of devices based on 2D materials can be very sensitive to any change in charge carrier density (i.e., resulting from doping by contaminants that are air pollutants, mainly oxygen and water vapor). The inventors have found that devices based on shapes with many edges, such as the cross shape of a Hall sensor, are more prone to contamination and thus benefit greatly from additional coating. As a result, the present method provides a more robust device than those of the prior art.

[0045] Accordingly, the method described herein preferably further comprises forming a coating layer either before or after forming one or more ohmic contacts to provide a continuous airtight coating on the layer structure (and its patterned dielectric). Accordingly, the continuous airtight coating coats at least the layer structure (including the etched 2D material layer and the patterned dielectric) and the adjacent area of the substrate, surrounds the layer structure, and protects all remaining portions of the exposed edges (i.e., all edges not in direct contact with the ohmic contacts). As described herein, the coating layer may be patterned to leave a portion of the contact exposed for connection to the circuit. Alternatively, the coating layer may be formed across the substrate to coat the entire substrate, all of the layer structure (and edges), and all of the one or more contacts.

[0046] The airtight coating may sometimes be referred to as an encapsulation coating. The coating may have an oxygen transmission rate of less than 10 -1 cm 3 / m 2 / day / atm, preferably less than 10 -3 cm 3 / m 2 / day / atm, more preferably less than 10 -5 cm 3 / m 2 / day / atm. The airtight coating may also have a water vapor transmission rate of less than 10 -2 g / m 2 / day, preferably less than 10 -4 g / m 2 / day, more preferably less than 10 -5 g / m 2 / day. Such transmission rates are generally accepted in the art as required for use in electronic devices such as LEDs, although more preferred transmission rates are required for OLEDs and Hall sensors.

[0047] The inventors have also found that using plasma etching to etch the layer structure of the uncoated region is particularly advantageous when combined with additional coating layers. This is because the plasma etching process does not form deposits on the layer structure or the substrate and does not affect the substrate surface roughness that can result from alternative techniques such as laser etching (e.g., due to pitting). This significantly improves the properties of the coating layer.

[0048] Preferably, the coating layer is an inorganic oxide, nitride, carbide, fluoride, or sulfide, preferably alumina or silica. Preferably, the thickness of the coating layer is greater than 10 nm, preferably greater than 25 nm, more preferably greater than 50 nm. Thicknesses greater than 10 μm or greater than 1 μm may simply increase the weight and thickness of the device precursor while providing limited additional protective properties, but there is no specific upper limit. Additionally, for example, the deposition rate by ALD can be a slow process, and a thicker coating will unduly extend the manufacturing time. Thus, an ALD layer thickness up to 500 nm, preferably up to 100 nm, is also preferred.

[0049] The inventors have found different solutions to the various problems encountered during the manufacture of such electronic device precursors comprising a coating layer, and each solution described herein has its own advantages and disadvantages.

[0050] One preferred embodiment of the invention includes forming a coating layer after the ohmic contact, and thus the ohmic contact is formed on a plasma-resistant substrate. In this embodiment, the coating layer is formed by atomic layer deposition (ALD) over the plasma-resistant substrate, providing a continuous air-resistant coating over at least one coated region of the layer structure, the ohmic contact, and the remaining exposed edge surfaces.

[0051] ALD is a technique known in the art and involves the reaction of at least two precursors in a continuous and self-limiting manner. By repeating the cycles to the individual precursors, a thin film can be grown conformally (i.e., with a uniform thickness across the entire substrate) due to the layer-by-layer growth mechanism. Alumina is a particularly preferred coating material and can be formed by sequentially exposing trimethylaluminum (TMA) and an oxygen source, preferably one or more of water (H2O), O2, and ozone (O3), preferably water. ALD is particularly advantageous because the coating can be reliably formed across the entire substrate (i.e., provides a conformal coating). However, the inventors have also found that although an excellent protective coating layer can be formed by ALD, a complete coating can pose a dicing problem when an array of electronic device precursors is fabricated on a substrate. Dicing (or cutting) then necessarily involves dicing through the coating layer to separate the individual device precursors, and this process can easily introduce microcracks into the coating layer.

[0052] Such a coating layer also coats the entire contact, thereby sealing the contact. Nevertheless, the inventors have found that wire bonding can be used to pierce the coating layer and attach the wire to the contact. Thus, the method preferably includes the step of wire bonding to an ohmic contact of the device precursor through the coating layer. Although ALD provides a very uniform protective coating, the coating can be damaged when pierced to make wire bond contact.

[0053] Accordingly, the inventors have developed a further preferred embodiment in which the ohmic contact is still formed on the plasma-resistant substrate before coating, but the coating layer is formed by patterning the coating layer on the plasma-resistant substrate to provide a continuous air-resistant coating to at least one coated region of the layer structure and the remaining exposed edge surfaces.

[0054] The coating layer is preferably patterned using the same techniques described herein with respect to dielectric patterning. One difference is that the pattern is geometrically larger to cover the exposed edges of the layer structure, thus the adjacent portions of the substrate as well as portions of the contacts, such that portions of the contacts remain exposed. For example, patterning of alumina can still be performed using electron beam evaporation.

[0055] Thus, this embodiment is advantageous in that the portion of the substrate (or simply the substrate portion) between adjacent layer structures of the array remains exposed (which may be referred to as a "street" or "die street"). Thus, the substrate can be diced without risk of damaging the coating layer. Further, since the contacts remain exposed, the contacts may be wire bonded without risk of damaging or cracking the coating layer, or solder bumps may be deposited on the contacts.

[0056] Unlike the use of ALD to provide a conformal coating over the entire substrate, evaporation is not conformal and there is a risk that edges will remain exposed. In particular, electron beam evaporation is directional in that shadows, particularly those created by contacts, limit the uniform growth of the coating. However, it is known in the art to rotate the substrate during coating to minimize this effect.

[0057] Alternatively, a further preferred embodiment includes providing a coating layer before forming the contacts and selectively etching away one or more portions of the coating layer to expose corresponding portions of the edge surface. The step of then forming the contacts includes forming ohmic contacts that directly contact each exposed portion of the edge surface.

[0058] Accordingly, the coating layer can be provided by ALD or electron beam evaporation. Since this embodiment involves forming a coating before any ohmic contacts, electron beam evaporation can also achieve a better coating, thereby keeping the streets transparent. The inventors have found that in order to enable the formation of ohmic contacts, it is necessary to etch the coating in selected areas to expose the corresponding parts of the underlying edge surface. Selective etching is preferably performed using laser etching, reactive ion etching (so-called "dry etching"), chemical etching (so-called "wet etching") and / or photolithography. Since the 2D material is substantially protected from contamination, such methods can be used without significant adverse effects. Nevertheless, laser etching and reactive ion etching are preferred because they are "dry" methods with a reduced risk of doping the 2D material, and reactive ion etching is most preferred. In some embodiments, the selective etching may be performed for a time sufficient to etch away the coating layer and expose the corresponding edge surface of the plasma-etchable layer structure.

[0059] Accordingly, this method requires the formation of ohmic contacts that directly contact the edge surface exposed by selective etching in each etched part. This is advantageous since the contacts are exposed for connection to the electronic circuit. In particular, the method can further include the step of depositing solder bumps (or solder balls) on the ohmic contacts. This allows the electronic device precursor to be used as a so-called "flip chip". Nevertheless, wire bonding is also preferred. Wire bonding is known in the art and can include ball bonding, wedge bonding, or compliant bonding.

[0060] However, the inventors have found that this embodiment introduces additional complexity to the alignment required for selective etching and contact deposition within the selectively etched portions. Nevertheless, etching also carries the risk of forming cracks in the coating.

[0061] In a second aspect of the present invention, an electronic device precursor is provided, the electronic device precursor comprising a substrate having a layer structure thereon, the layer structure comprising a lower layer on a first region of the substrate, the lower layer comprising one or more graphene layers extending across the lower layer, and an upper layer on the lower layer, the upper layer formed of a dielectric material, wherein the lower layer and the upper layer share a continuous outer edge surface, the substrate having a layer structure comprising the upper layer, and an ohmic contact provided on a further region of the substrate and in direct contact with one or more graphene layers via the continuous outer edge surface, and a continuous airtight coating layer spanning the substrate, the layer structure, and at least one ohmic contact.

[0062] In a third aspect of the present invention, an electronic device precursor is provided, the electronic device precursor comprising a substrate having a layer structure thereon, the layer structure comprising a lower layer on a first region of the substrate, the lower layer comprising one or more graphene layers extending across the lower layer, and an upper layer on the lower layer, the upper layer formed of a dielectric material, wherein the lower layer and the upper layer share a continuous outer edge surface, the substrate having a layer structure comprising the upper layer, and an ohmic contact provided on a further region of the substrate and in direct contact with one or more graphene layers via the continuous outer edge surface, and a continuous airtight coating layer surrounding the layer structure.

[0063] In a fourth aspect of the present invention, an electronic device precursor is provided, the electronic device precursor comprising A substrate having a layer structure thereon, the layer structure comprising: A lower layer on a first region of the substrate, the lower layer including one or more graphene layers extending across the lower layer, and An upper layer on the lower layer and formed of a dielectric material, The lower layer and the upper layer share a continuous outer edge surface, and the substrate having the layer structure comprising the upper layer, An ohmic contact in direct contact with one or more graphene layers through the continuous outer edge surface, and A continuous airtight coating layer surrounding the layer structure.

[0064] The electronic device precursor of a further aspect of the invention disclosed herein can preferably be obtained by the method described herein. Accordingly, all features described in connection with the first aspect can equally apply to further aspects of the invention as necessary.

[0065] Accordingly, the electronic device precursor of a further aspect of the invention shares the characteristics of a layer structure including a lower layer containing one or more graphene layers and an upper layer formed of a dielectric material, and the lower layer and the upper layer share a continuous outer edge surface. Thus, this provides excellent protection for the graphene from air pollution, resulting in improved stability of device performance over a long period and an extended device lifetime.

[0066] Furthermore, an ohmic contact is provided for connection to an electronic circuit, and the ohmic contact is only in direct contact with the edge of the graphene layer and not in direct contact with the upper (or lower) plane. Edge contact provides improved charge injection over surface contact and substantially avoids doping of the graphene. This is particularly useful when the device precursor is intended for use at high temperatures, as an increase in temperature can result in doping of the 2D material by the metal of the ohmic contact, for example, during and after manufacture and subsequent use.

[0067] In a preferred embodiment of the present invention, the electronic device precursor is for a transistor or a Hall sensor, most preferably for a Hall sensor. Nevertheless, many other electronic devices can be manufactured using the methods described herein and / or from the electronic device precursors described herein, including capacitors, diodes and inductors.

[0068] In a particularly preferred embodiment of the present invention, the method described herein comprises (i) providing a plasma-etchable layer structure on a plasma-resistant substrate, the layer structure having an exposed upper surface; (ii) patterning a plasma-resistant dielectric on the exposed upper surface to form an intermediate having at least one coated region and at least one uncoated region of the layer structure; (iii) subjecting the intermediate to plasma etching, thereby etching away at least one uncoated region of the layer structure to form at least one coated region of the layer structure having an exposed edge surface; (iv) forming an ohmic contact on the plasma-resistant substrate in direct contact with a portion of the exposed edge surface; (v) forming a coating layer by ALD across the plasma-resistant substrate to provide a continuous air-resistant coating on at least one coated region of the layer structure, the ohmic contact, and the remaining exposed edge surface. The plasma-etchable layer structure comprises or consists of one or more graphene layers extending to the exposed edge surface across the coated region of the layer structure. Thus, the electronic device precursor of the second aspect described herein can preferably be obtained by this method, and more preferably is obtained.

[0069] The device precursor of the second aspect comprises a substrate, a layer structure, and a continuous air-resistant coating layer over at least one ohmic contact, which may also be considered to surround the layer structure according to the third and fourth aspects disclosed herein.

[0070] In a particularly preferred embodiment of the present invention, the method described herein comprises (i) providing a plasma-etchable layer structure on a plasma-resistant substrate, the layer structure having an exposed upper surface; (ii) patterning a plasma-resistant dielectric on the exposed upper surface to form an intermediate having at least one coated region and at least one uncoated region of the layer structure; (iii) subjecting the intermediate to plasma etching, thereby etching away at least one uncoated region of the layer structure to form at least one coated region of the layer structure having an exposed edge surface; (iv) forming an ohmic contact on the plasma-resistant substrate that is in direct contact with a portion of the exposed edge surface; (v) patterning a coating layer on the plasma-resistant substrate to provide a continuous air-resistant coating on at least one coated region of the layer structure and the remaining exposed edge surface, The plasma-etchable layer structure comprises or consists of one or more graphene layers extending to the exposed edge surface across the coated region of the layer structure. Accordingly, the electronic device precursor of the third and / or fourth aspect described herein can preferably be obtained by this method, and more preferably is obtained.

[0071] In a particularly preferred embodiment of the present invention, the method described herein comprises (i) providing a plasma-etchable layer structure on a plasma-resistant substrate, the layer structure having an exposed upper surface; (ii) patterning a plasma-resistant dielectric on the exposed upper surface to form an intermediate having at least one coated region and at least one uncoated region of the layer structure; (iii) subjecting the intermediate to plasma etching, thereby etching away at least one uncoated region of the layer structure to form at least one coated region of the layer structure having an exposed edge surface; (iv) Forming a coating layer on the plasma-resistant substrate to provide a continuous air-resistant coating on at least one coated region and the exposed edge surface of the layer structure; (v) Selectively etching away one or more portions of the coating layer to expose the corresponding portions of the edge surface; (vi) Forming ohmic contacts that directly contact each exposed portion of the edge surface, The plasma-etchable layer structure includes or consists of one or more graphene layers extending to the exposed edge surface across the coated region of the layer structure. Thus, the electronic device precursor of the fourth aspect described herein can preferably be obtained by this method, and more preferably is obtained.

[0072] In an even more preferred embodiment of the present invention, the method described herein (i) Providing a single layer of graphene on a sapphire substrate by MOCVD, wherein the single layer of graphene has an exposed upper surface; (ii) Patterning alumina as one or more cross-shaped regions on the exposed upper surface to form an intermediate having at least one coated region and at least one uncoated region of the single layer of graphene; (iii) Subjecting the intermediate to oxygen plasma etching to thereby etch away at least one uncoated region of the single layer of graphene to form at least one coated region of single-layer graphene having an exposed edge surface; (iv) Forming four gold ohmic contacts on the sapphire substrate for each cross-shaped region formed in step (ii), each contact directly contacting the distal portion of the exposed edge surface of the four arms of the cross; (v) Forming an alumina coating layer by ALD across the sapphire substrate to provide a continuous air-resistant coating on at least one coated region of the single layer of graphene, the ohmic contacts, and the remaining exposed edge surface. The single layer of graphene extends to an edge surface exposed across at least one covered region, and the electronic device precursor is for forming a Hall sensor.

[0073] Accordingly, a preferred electronic device precursor is an electronic device precursor for a Hall sensor, and the electronic device precursor is a sapphire substrate having a layer structure thereon, and the layer structure includes a single layer of graphene on a first region of the sapphire substrate, and an alumina layer on the graphene single layer, where the graphene and the alumina are in a cross shape and share a continuous outer edge surface, and the alumina layer, and four gold ohmic contacts, each contact being provided on a further region of the sapphire substrate and in direct contact with the distal portion of the exposed edge surface of each of the four arms of each cross, and the four gold ohmic contacts, and a continuous alumina coating layer covering the sapphire substrate, the layer structure, and the contacts.

[0074] In yet another more preferred embodiment of the present invention, the method described herein comprises: (i) providing a single layer of graphene on a sapphire substrate by MOCVD, the single layer of graphene having an exposed upper surface; (ii) patterning alumina as one or more cross-shaped regions on the exposed upper surface to form an intermediate having at least one covered region and at least one non-covered region of the graphene single layer; (iii) subjecting the intermediate to oxygen plasma etching to etch away at least one non-covered region of the single layer of graphene, thereby forming at least one covered region of the single layer of graphene having an exposed edge surface; and (iv) forming four gold ohmic contacts on the sapphire substrate for each cross-shaped region formed in step (ii), each contact being in direct contact with the distal portion of the exposed edge surface of the four arms of each cross. ​ (v) Patterning an alumina coating layer by electron beam evaporation on a sapphire substrate to provide a continuous air-resistant coating on at least one coated region of monolayer graphene and the remaining exposed edge surfaces, The monolayer of graphene extends to the exposed edge surfaces across at least one coated region, and the electronic device precursor is for forming a Hall sensor.

[0075] Similarly, in yet another more preferred embodiment of the present invention, the method described herein (i) Providing a monolayer of graphene on a sapphire substrate by MOCVD, wherein the monolayer of graphene has an exposed upper surface, (ii) Patterning alumina as one or more cross-shaped regions on the exposed upper surface to form an intermediate having at least one coated region and at least one uncoated region of the monolayer graphene, (iii) Subjecting the intermediate to oxygen plasma etching, thereby etching away at least one uncoated region of the monolayer graphene to form at least one coated region of monolayer graphene having exposed edge surfaces, (iv) Forming an alumina coating layer on the sapphire substrate to provide a continuous air-resistant coating on at least one coated region of monolayer graphene and the exposed edge surfaces, (v) Selectively laser etching four portions of the alumina coating layer to expose corresponding portions of the edge surfaces of the monolayer graphene and to expose the distal portions of the edge surfaces of the four arms of each cross, (vi) Forming four gold ohmic contacts in direct contact with each of the four exposed portions of the edge surfaces, The monolayer of graphene extends to the exposed edge surfaces across at least one coated region, and the electronic device precursor is for forming a Hall sensor.

[0076] Accordingly, a preferred electronic device precursor is an electronic device precursor for a Hall sensor, and the electronic device precursor is a sapphire substrate having a layer structure thereon, and the layer structure is a single layer of graphene on a first region of the sapphire substrate, and an alumina layer on the graphene monolayer, where the graphene and the alumina are in a cross shape and share a continuous outer edge surface, the alumina layer, and four gold ohmic contacts, each contact being provided on a further region of the sapphire substrate and in direct contact with the distal portion of the exposed edge surface of each of the four arms of the cross, the four gold ohmic contacts, and a continuous alumina coating layer surrounding the layer structure.

[0077] Accordingly, a preferred electronic device precursor includes an alumina coating layer encapsulating a layer structure that protects the edges of the single layer of graphene. The contacts of the device precursor are at least partially exposed, i.e., not coated by the alumina coating layer like at least a partially exposed sapphire substrate. Typically, at least a region of the substrate between adjacent device precursors as part of an array to enable providing a plurality of device precursors without the risk of damaging the coating during dicing of a common substrate.

[0078] In embodiments where the coating layer is first deposited and then etched to expose the edge surface of the graphene to provide such an electronic device precursor, the contacts are disposed in the laser-etched openings of the coating and thus are vertically exposed.

[0079] In embodiments where the coating layer is patterned after the formation of the contacts, partial coating of the contacts during patterning can leave the top surface of the contacts exposed. However, it is also possible to pattern the coating layer on the top surface of the contacts, and patterning of the coating layer leaves at least the edge surfaces exposed. In other words, the contacts are not completely encapsulated by the coating layer in the final electronic device precursor, thereby enabling simple wire bonding or soldering for connection to the electronic circuit without the need to pierce the coating layer.

[0080] Figure The present invention will be further described with reference to the following non-limiting figures.

Brief Description of the Drawings

[0081]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Modes for Carrying Out the Invention

[0082] Figure 1 is a flowchart showing the method 100 of the present invention. The method 100 includes several essential steps (105, 110, 115, and 120), and can further include one of three optional steps (125a, 125b, 125c) representing three alternative and preferably specific embodiments of the method 100.

[0083] Method 100 is for forming an electronic device precursor suitable for a Hall sensor and includes a first step 105 of providing a plasma-etchable layer structure on a plasma-resistant substrate. In an exemplary method 100, the plasma-etchable layer structure consists of a single layer of graphene provided directly on a sapphire substrate by MOCVD.

[0084] Next, a further step 110 includes patterning an array of alumina cross-shaped regions by electron beam evaporation on the exposed upper surface of the single layer of graphene to form an array of intermediates. This method will be further described with reference to one intermediate, but it will be understood that all the intermediates of the array are processed simultaneously. Step 115 includes subjecting the intermediate to oxygen plasma etching, thereby etching the exposed single layer of graphene to form an array of cross-shaped regions of graphene covered with alumina, and the graphene covered with alumina has a continuous exposed edge surface.

[0085] Method 100 further includes a step 120 of forming a metal ohmic contact that directly contacts a part of the exposed edge surface of the etched single layer of graphene. In particular, four metal contacts are formed at each end of each of the cross-shaped "arms".

[0086] In a first particular embodiment of method 100, method 100 further includes a step 125a that is executed after step 120, and step 125a includes forming a coating layer of alumina by ALD across the sapphire substrate, thereby coating the alumina-coated graphene, the ohmic contact, and the exposed substrate with a continuous air-resistant coating.

[0087] In a second specific embodiment, method 100 further includes step 125b, which is executed after step 120. Step 125b includes patterning an alumina coating layer on a substrate by electron beam evaporation, thereby coating the graphene coated with alumina with a continuous air-resistant coating. Thus, the alumina coating provided by step 125b covers the exposed edges not in contact with the ohmic contacts to protect from air pollution, and the pattern of the coating is the same geometric cross shape but geometrically larger. For example, the maximum width and / or maximum height of the shape may be 10% larger, or may be 20% larger, than the patterned alumina of step 110. The patterning step also leaves a portion of each metal contact exposed for connection to the electronic circuit.

[0088] In a third specific embodiment, method 100 further includes step 125c of forming a coating layer before step 120. Step 125c includes forming a coating layer to provide a continuous air-resistant coating of alumina on the single-layer graphene coated with alumina (i.e., such that the exposed edge surfaces are coated). In this embodiment, step 120 further includes selectively laser etching four portions of the coating layer at each end of each of the underlying cross-shaped "arms" to expose the corresponding portions of the edge surface of the graphene. As required by method 100, step 120 then includes forming metal ohmic contacts that directly contact the exposed edge surfaces in each of the selectively etched portions.

[0089] Figure 2 is a cross-sectional view of an electronic device precursor 200. The precursor 200 can be obtained by the method described herein, which includes forming a coating layer by ALD after forming the ohmic contacts.

[0090] The electronic device precursor 200 is formed from a sapphire substrate 205 on which there is a plasma-etchable 2D material layer 210 containing a graphene layer structure. The 2D material layer 210 has a shape defined by an alumina layer 215 formed thereon. Thus, the 2D material layer and the alumina share a continuous edge surface to which the graphene layer structure extends up to this edge.

[0091] The precursor 200 further includes two ohmic contacts 220a and 220b, each in direct contact with the 2D material layer 210 and thus the edge of the graphene layer structure. Since the alumina and the 2D material share a continuous edge surface and have the same shape, there is no contact material on the surface of the 2D material layer 210. Advantageously, the contacts do not result in a perceivable doping of the 2D material such as would be observed when the contacts are provided on the plane of the 2D material. Further, the edge contacts provide improved charge injection compared to surface charge injection that improves the overall efficiency (e.g., by reducing electrical losses as heat).

[0092] On the alumina coating 215, the contacts 220a, 220b and the substrate 205, there is formed a continuous air-resistant coating layer of silica. The coating 225 provides excellent protection from atmospheric contamination, for example by preventing the ingress of oxygen gas and water vapor. The precursor 200 further comprises wires 230a and 230b wire-bonded to the ohmic contacts 220a and 220b respectively. The wires 230a and 230b provide electrical connection means to the ohmic contacts and thus protrude from the coating layer.

[0093] The inventors have found that the electronic device precursor 200 provides excellent stability to the electronic device. In particular, the inventors have found that a device formed from the precursor 200 exhibits a degradation rate of less than 0.01% / day (measured with respect to the initial carrier concentration at the time of the device and manufacture and thus sensitivity).

[0094] As a comparison, a device formed from a precursor in which a coating layer (e.g., coating layer 215) is not provided and instead a ceramic lid is used to "seal" the component (well-known in the art and can also be used in combination with the present invention) was found to have the sensitivity of such a device decreasing at a rate exceeding 0.5% / day. Similarly, the inventors have found that it is even significantly larger in the absence of a coating layer or a ceramic lid.

[0095] As a further comparison, the inventors have found that a device formed using an organic PMMA coating layer provides greater protection against degradation than a known ceramic lid, and such a device has a degradation rate of 0.03% / day to 0.1% / day.

[0096] The inventors have also found that when a metal contact is deposited on graphene before patterning of the dielectric layer, the metal causes heavy doping of the graphene exceeding 10 12 cm -2 and even exceeding 10 13 cm -2 thereby significantly reducing the sensitivity.

[0097] FIG. 3 is a cross-sectional view of an electronic device precursor 300. The precursor 300 can be obtained by the method described herein that includes forming a coating layer before the step of forming an ohmic contact.

[0098] The electronic device precursor 300 includes a sapphire substrate 305 on which a plasma-etchable 2D material layer 310 is present. In this embodiment, the 2D material layer consists of bilayer graphene (i.e., a single layer of graphene having two layers of graphene). On top of it, a patterned silica layer 315 is formed that shares a continuous edge surface with the bilayer graphene 310. A continuous air-resistant coating 325 is deposited on the surface of the patterned silica layer 315. The coating 325 is also deposited on an adjacent portion of the surface of the substrate 305. FIG. 3 is a cross-sectional view of the precursor 300, and the cross-section bisects two ohmic contacts 320 deposited on the substrate 305. In another cross-section, it will be understood that the coating layer 325 is continuous.

[0099] The contacts 320 are in direct contact with the edge surface of the bilayer graphene, as well as the silica and alumina coatings thereon. The precursor 300 can be obtained by the method described herein, which includes the step of selectively etching a coating layer formed prior to forming the ohmic contacts. Thus, the contacts extend from the surface of the substrate 305 exposed during the etching process to the surface of the coating layer 325. In this embodiment, solder balls (or solder bumps) 330 are provided on the exposed portions of the ohmic contacts so that the precursor 300 can be described as a "flip chip".

[0100] Figure 4 is a plan view of an electronic device precursor 400. The precursor 400 is suitable for a Hall sensor and is formed in a 2D material layer, specifically in a cross shape under an alumina layer 415 of the same shape / pattern, all of which are formed on a silicon substrate 405. Each end (i.e., the distal portion) of the four "arms" of the cross-shaped layer structure of the 2D material and the patterned alumina 415 is in direct contact with each of the four titanium contacts (420a, 420b, 420c, 420d). A continuous air-resistant alumina coating 425 is provided over the layer structure and a portion of each contact in a manner sufficient to enclose the edges of the underlying 2D material layer and leave a portion of each titanium contact exposed. The coating layer 425 may be provided by electron beam evaporation. In FIG. 4, the coating layer 425 is shown semi-transparent to show the presence of the underlying patterned alumina 415. As will be understood, the 2D material layer has the same shape as the alumina layer 415. The precursor 400 is an individual component that can be obtained by dicing a substrate formed from an array of equivalent precursors sharing a common substrate. The precursor 400 is advantageous in this regard because dicing does not involve cutting the coating layer 425 since the coating layer does not extend into the so-called "streets" or portions of the substrate between the arrays of components being fabricated.

[0101] The inventors have used Raman spectra obtained at various positions of the device precursor to confirm the presence (and quality) of graphene. In particular, the method of the present invention facilitates the clean etching of graphene up to the edges of the patterned alumina so that ohmic contacts can be provided without the need to remove the protective alumina layer. Further, the Raman spectrum of graphene demonstrates that the quality of the graphene near the edge can remain equivalent to the quality of the remainder of the protected portion of the underlying graphene (e.g., at the location of label 415 of the stack of graphene and patterned alumina in FIG. 4). Further, the inventors have demonstrated, using Raman spectroscopy, that there is no graphene present outside the patterned dielectric between the coating layer and the substrate (e.g., at the location of label 425 of the coating layer in FIG. 4).

[0102] FIG. 5 is a plan view of an electronic device precursor 500. The precursor 500 is suitable for a Hall sensor and is formed in a specific cruciform shape under an alumina layer 515 of the same shape / pattern with a 2D material layer, all of which are formed on a sapphire substrate. Separate gold contacts 520 are provided in direct contact with the corresponding edges of the underlying 2D material layer at four portions of the cruciform, specifically, at four distal portions that are the ends of each arm of the cross. A continuous air-resistant coating 525 of silica formed by ALD is coated over the entire substrate and the layer structure of the 2D material and alumina 515 (thus, all edges not in direct contact with the contacts 520) along with all of the contacts 520 themselves. Similar to FIG. 4, the coating layer 525 is shown as semi-transparent to indicate the presence of the underlying patterned alumina 515.

[0103] FIG. 6 is a perspective view of an array 600 of electronic device precursors. The array 600 is formed from four electronic device precursors that can be separated by dicing the substrate along the streets 635. Each precursor includes a portion (605a, 605b, 605c, 605d) of the substrate, and coating layers (625a, 625b, 625c, 625d) encapsulating a layer structure of a 2D material and a patterned dielectric layer are formed on each portion. Further, each precursor includes two ohmic contacts (620a and 620a'), a portion of which is not encapsulated by the coating layer (625a).

Example

[0104] Example According to the first example, 1. Graphene was grown on a sapphire substrate according to the process of WO 2017 / 029470 pamphlet.

[0105] 2. Al2O3 was evaporated onto the graphene using thermal evaporation through a shadow mask having a cross-shaped opening. The thickness of the evaporated Al2O3 was 10 nm.

[0106] 3. The graphene in the regions that remained exposed as the top layer was removed by plasma etching. The settings used for this were an oxygen flow rate of 6 sccm for 30 seconds and 40% output (of a 100 W device).

[0107] 4. Ti / Au bar-shaped contacts were evaporated onto the ends of the arms of the cross using another shadow mask. These were made by evaporating 10 nm of Ti and then 120 nm of Au. These were arranged with respect to the cross arms such that they contacted the edge of the graphene at the ends of the cross arms and extended laterally away from the cross arms.

[0108] 5. A second layer of evaporated Al2O3 was deposited on top of the first in a cross shape larger than the first so as to cover the first cross and leave the exposed portions of each bar contact.

[0109] 6. As a result, devices were obtained on the wafer, which were then processed by standard BEOL processing.

Example

[0110] According to the second example, 1. Graphene was grown on a sapphire substrate according to the process of WO 2017 / 029470 pamphlet.

[0111] 2. Al2O3 was evaporated onto the graphene using thermal evaporation through a shadow mask having a cross-shaped opening. The thickness of the evaporated Al2O3 was 10 nm.

[0112] 3. The graphene in the regions that remained exposed as the top layer was removed by plasma etching. The settings used for this were an oxygen flow rate of 6 sccm for 30 seconds at 40% output (of a 100 W device).

[0113] 4. Ti / Au bar-shaped contacts were evaporated onto the ends of the cross arms using another shadow mask. These were fabricated by evaporating 10 nm of Ti and then 120 nm of Au. These were arranged with respect to the cross arms such that they contacted the edge of the graphene at the ends of the cross arms and extended laterally away from the cross arms.

[0114] 5. A second layer of Al2O3 was deposited over the entire wafer using ALD. The thickness of this layer was 65 nm.

[0115] 6. As a result, devices were obtained on the wafer, which were then processed by standard BEOL processing.

[0116] As used herein, the singular forms "a", "an" and "the" include plural referents unless the context clearly dictates otherwise. The use of the term "comprising" is intended to mean that such features are included but do not exclude other features, and is also intended to include options of features that are not necessarily limited to those described. In other words, this term includes the limitations of "consisting essentially of" (meaning that certain additional components may exist provided that they do not materially affect the essential characteristics of the described features) and "consisting of" (meaning that when the components are expressed as percentages in that proportion, other features should not be included such that they add up to 100% taking into account inevitable impurities) unless the context clearly dictates otherwise.

[0117] As used herein, terms such as "first", "second" etc. can be used to describe various elements, layers and / or parts, but it should be understood that these elements, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, layer or part from another. It should be understood that the term "on" is intended to mean "directly on" such that there is no intervening layer between one material that is said to be "on" another material. Spatially relative terms such as "below", "beneath", "lower", "above", "upper" etc. can be used herein to facilitate description of the relationship of one element or feature to another. It should be understood that spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the figures. For example, if the device in the figure is turned over, an element described as "below" or "directly below" another element or feature will be oriented "above" the other element or feature. Thus, the exemplary term "below" can encompass both upward and downward orientations. The device may be oriented in other directions, and the spatially relative descriptors used herein will be interpreted accordingly.

[0118] The foregoing detailed description is provided by way of explanation and illustration and is not intended to limit the appended claims. Many variations of the presently preferred embodiments shown herein will be apparent to those skilled in the art and remain within the scope of the appended claims and their equivalents.

Claims

1. A method for manufacturing a precursor of an electronic device, comprising: (i) providing a plasma-etchable layer structure on a plasma-resistant substrate, the layer structure having an exposed upper surface; (ii) patterning a plasma-resistant dielectric by physical vapor deposition on the exposed upper surface to form an intermediate having at least one coated region and at least one uncoated region of the layer structure; (iii) subjecting the intermediate to plasma etching, thereby etching away the at least one uncoated region of the layer structure to form at least one coated region of the layer structure having an exposed edge surface; (iv) forming an ohmic contact in direct contact with a part of the exposed edge surface; The plasma-etchable layer structure includes one or more graphene layers extending to the exposed edge surface across the coated region of the layer structure; Further comprising, either before or after step (iv), (v) forming a coating layer to provide a continuous air-resistant coating on the coated region of the layer structure.

2. The method according to claim 1, wherein the plasma-resistant substrate is sapphire, silicon, silicon dioxide, silicon nitride, silicon carbide, germanium, or a group III-V semiconductor.

3. The method according to claim 1, wherein the plasma-resistant dielectric and / or the coating layer are each an inorganic oxide, nitride, carbide, fluoride, or sulfide.

4. The method according to claim 1, wherein the plasma etching includes oxygen plasma etching.

5. The method according to claim 1, wherein the plasma-etchable layer structure consists of one or more 2D material layers.

6. The method according to claim 5, wherein the plasma-etchable layer structure comprises one or more graphene layers and, optionally, one or more layers of silicene, germanene, h-BN, borophene and / or TMDC.

7. The method according to claim 6, wherein the one or more graphene layers and the one or more layers of silicene, germanene, h-BN, borophene and / or TMDC are each formed by CVD or MOCVD.

8. Step (ii) comprises (I) one or more rectangular regions of the plasma-resistant dielectric, wherein the electronic device precursor is for forming a transistor, or (II) forming one or more cross-shaped regions of the plasma-resistant dielectric, wherein the electronic device precursor is for forming a Hall sensor, the method according to claim 1.

9. The method according to claim 1, wherein step (ii) comprises patterning the plasma-resistant dielectric by electron beam evaporation.

10. The method according to any one of claims 1 to 9, comprising forming an array of coating regions each corresponding to an electronic device precursor.

11. Step (v) is carried out after step (iv), the ohmic contact is formed on the plasma-resistant substrate, and the coating layer is formed by ALD across the plasma-resistant substrate to provide a continuous air-resistant coating on the at least one coating region of the layer structure, the ohmic contact, and the remaining exposed edge surfaces, the method according to claim 1.

12. The method according to claim 11, further comprising the step of wire bonding the ohmic contact of the electronic device precursor through the coating layer. **Claim 13** Step (v) is performed after step (iv), the ohmic contact is formed on the plasma-resistant substrate, and the coating layer is formed by patterning a coating layer on the plasma-resistant substrate to provide a continuous air-resistant coating on the at least one coated region of the layer structure and the remaining exposed edge surfaces. The method according to claim 1. **Claim 14** The method according to claim 13, wherein the coating layer is formed by electron beam evaporation. **Claim 15** Step (v) is performed before step (iv) and includes the step of selectively etching away one or more portions of the coating layer to expose corresponding portions of the exposed edge surface, and step (iv) includes the step of forming an ohmic contact that directly contacts each exposed portion of the exposed edge surface. The method according to claim 1. **Claim 16** The method according to claim 15, wherein the step of selectively etching away is performed by laser etching or reactive ion etching. **Claim 17** The method according to any one of claims 13 to 16, further comprising the step of depositing solder bumps on the ohmic contact or the step of wire bonding the ohmic contact. **Claim 18** An electronic device precursor, comprising a plasma-resistant substrate having a layer structure thereon, the layer structure comprising a lower layer on a first region of the plasma-resistant substrate, the lower layer including one or more graphene layers extending across the lower layer, and An upper layer formed of a plasma-resistant dielectric material and located above the lower layer, wherein the lower layer and the upper layer share a continuous outer edge surface, and the upper layer, and An ohmic contact provided on a further region of the plasma-resistant substrate and in direct contact with the one or more graphene layers via the continuous outer edge surface, and A continuous air-resistant coating layer covering (i) the plasma-resistant substrate, the layer structure, and at least one of the ohmic contacts, or (ii) surrounding the layer structure, and The electronic device precursor is for forming a Hall sensor, and the charge carrier density of the one or more graphene layers is 8×10 １１ cm －２ Less than, an electronic device precursor. Claim 19 The lower layer further comprises one or more layers of silicene, germanene, h-BN, borophene, and / or TMDC extending across the lower layer, the electronic device precursor according to claim 18.

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