Memory Checkpoint Processing Method, Memory Checkpoint Processing Apparatus, Computer Device, and Computer Program

Abstract

The present application relates to a method, device, equipment, storage medium, and computer program product for processing check pins of a memory. The method is applicable to the application scenarios of cloud technology and in-vehicle terminals, and includes the steps of: receiving a first data signal and a sampling pulse signal returned from each check pin of a target memory based on a first data read command; obtaining a first delay parameter by time-shifting each first data signal by a delay circuit so that the target level value of each first data signal after time-shifting is aligned with the sampling pulse signal; receiving a second data signal returned from each check pin of the target memory, obtaining a second delay parameter by time-shifting each target data signal in each second data signal by a delay circuit so that the target level value of each second data signal after time-shifting is aligned; and determining a sampling delay parameter of the check pin based on the first delay parameter and the second delay parameter. This method can ensure the accuracy of sampling the data signal based on the sampling pulse signal.

Description

Technical Field

[0001] This application claims priority based on a Chinese patent application filed with the China National Patent Office on May 9, 2022, with an application number of No. 202210497004X and an invention title of "Method, Apparatus, Device, and Storage Medium for Check Pin Processing of Memory", and all of its contents are incorporated herein by reference.

[0002] This application relates to the technical field of computers, and in particular, to a method, apparatus, device, storage medium, and computer program product for check pin processing of memory.

Background Art

[0003] High Bandwidth Memory (HBM) is a new type of internal memory with high speed and high bandwidth, and is mainly applied in the field of artificial intelligence chips. The transmission path of the read data signal of HBM is easily affected by chip process, operating voltage, environmental temperature, and signal crosstalk, resulting in errors in the transmitted read data signal. Therefore, it is necessary to detect whether there is a transmission error in the read data signal.

[0004] In the conventional detection method, mainly the read data signal is transmitted together with the parity check (PAR) signal of the read data signal and the sampling pulse signal of the read data signal. Thereby, the receiving side samples the parity check signal based on the sampling pulse signal to obtain check information, and further checks whether there is a transmission error in the read data signal based on the check information.

[0005] However, the parity check signal is also affected by the chip process, operating voltage, environmental temperature, and signal cross-talk, and there may be a shift between the parity check signal and the sampling pulse signal. When the receiving side samples the parity check signal based on the sampling pulse signal, it may obtain incorrect check information due to sampling errors, and further the check result of the data signal may become an error.

Summary of the Invention

Problems to be Solved by the Invention

[0006] According to various embodiments of the present application, a method, apparatus, device, storage medium, and computer program product for processing check pins of a memory are provided.

Means for Solving the Problems

[0007] According to a first aspect, the present application provides a method for processing check pins of a memory, which is executed by a computer device. The method includes: sending a first data read command to a target memory; receiving a first data signal and a sampling pulse signal returned from each check pin of the target memory; obtaining a first delay parameter by time-shifting each of the first data signals by a delay circuit so that the target level value in each of the time-shifted first data signals aligns with the sampling pulse signal; when receiving a second data signal returned from each of the check pins of the target memory, obtaining a second delay parameter by time-shifting each target data signal in each of the second data signals by the delay circuit so that the target level values in each of the time-shifted second data signals align; determining a sampling delay parameter of the check pin based on the first delay parameter and the second delay parameter.

[0008] According to the second aspect, in the present application, a memory check pin processing device is further provided. The device includes a command transmission module that transmits a first data read command to a target memory, a signal reception module that receives a first data signal and a sampling pulse signal returned from each check pin of the target memory, a signal time shift module that obtains a first delay parameter by time shifting each of the first data signals by a delay circuit so that the target level value in each of the time-shifted first data signals aligns with the sampling pulse signal, and when receiving a second data signal returned from each of the check pins of the target memory, obtains a second delay parameter by time shifting the target data signal in each of the second data signals by the delay circuit so that the target level value in each of the time-shifted second data signals aligns; and a delay determination module that determines a sampling delay parameter of the check pin based on the first delay parameter and the second delay parameter.

[0009] According to the third aspect, in the present application, a computer device is further provided. The computer device includes a memory and a processor. A computer program is stored in the memory. When the processor executes the computer program, it performs a step of transmitting a first data read command to a target memory, a step of receiving a first data signal and a sampling pulse signal returned from each check pin of the target memory, a step of obtaining a first delay parameter by time shifting each of the first data signals by a delay circuit so that the target level value in each of the time-shifted first data signals aligns with the sampling pulse signal, When receiving the second data signals returned from the respective check pins of the target memory, the target data signals in the respective second data signals after time shift are time-shifted by the delay circuit so that the target level values in the respective second data signals after time shift are aligned, thereby obtaining a second delay parameter; determining a sampling delay parameter of the check pin based on the first delay parameter and the second delay parameter.

[0010] According to a fourth aspect, the present application further provides a computer-readable storage medium. A computer program is stored in the computer-readable storage medium, and when the computer program is executed by a processor, transmitting a first data read command to a target memory; receiving a first data signal and a sampling pulse signal returned from each check pin of the target memory; when receiving the first data signals returned from the respective check pins of the target memory, the target data signals in the respective first data signals after time shift are time-shifted by the delay circuit so that the target level values in the respective first data signals after time shift are aligned with the sampling pulse signal, thereby obtaining a first delay parameter; When receiving the second data signals returned from the respective check pins of the target memory, the target data signals in the respective second data signals after time shift are time-shifted by the delay circuit so that the target level values in the respective second data signals after time shift are aligned, thereby obtaining a second delay parameter; determining a sampling delay parameter of the check pin based on the first delay parameter and the second delay parameter.

[0011] According to the fifth aspect, the present application further provides a computer program product. The computer program product includes a computer program, and when the computer program is executed by a processor, sending a first data read command to a target memory; receiving a first data signal and a sampling pulse signal returned from each check pin of the target memory; obtaining a first delay parameter by time-shifting each of the first data signals by a delay circuit so that the target level values in each of the time-shifted first data signals align with the sampling pulse signal; when receiving a second data signal returned from each of the check pins of the target memory, obtaining a second delay parameter by time-shifting the target data signal in each of the second data signals by the delay circuit so that the target level values in each of the time-shifted second data signals align; determining a sampling delay parameter of the check pin based on the first delay parameter and the second delay parameter.

[0012] Details of one or more embodiments of the present application are described in the following drawings and description. Other features and advantages of the present application will become apparent from the specification, drawings, and claims.

Brief Description of the Drawings

[0013] The drawings described herein are provided for a further understanding of the present application and constitute a part of the present application. The schematic embodiments and their descriptions of the present application are for interpreting the present application and do not constitute an improper limitation of the present application.

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Embodiment for Carrying Out the Invention

[0014] To make the object, configuration, and advantages of the present application clearer, the present application will be described in more detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only for the purpose of interpreting the present application and do not limit the present application.

[0015] The memory check pin processing method provided in the embodiment of the present application is executed by a computer device, and specifically, it is applicable to the application environment shown in FIG. 1. Here, the terminal 102 communicates with the server 104 via a network. The memory check pin processing method may be executed by the terminal 102 or the server 104, or may be executed by the cooperation of the terminal 102 and the server 104. In some embodiments, a memory controller is provided in the terminal 102 and the server 104. Specifically, the memory check pin processing method may be executed by the memory controller. When the memory check pin processing method is executed by the terminal 102, the terminal 102 sends a first data read command to the target memory, receives the first data signal and the sampling pulse signal returned from each check pin of the target memory, and delays each first data signal by a delay circuit so that the target level value in each time-shifted first data signal aligns with the sampling pulse signal, thereby obtaining a first delay parameter. When receiving the second data signal returned from each check pin of the target memory, the target data signal in each second data signal is time-shifted by a delay circuit so that the target level value in each time-shifted second data signal aligns, thereby obtaining a second delay parameter. Based on the first delay parameter and the second delay parameter, the sampling delay parameter of the check pin is determined.

[0016] Here, the terminal 102 may be, but is not limited to, a smartphone, a tablet computer, a notebook computer, a desktop computer, a smart speaker, a smartwatch, a smart voice interaction device, a smart home appliance, an in-vehicle terminal, etc. in which an AI chip is incorporated. This AI chip may be a chip that combines an AI processor and a memory (for example, a high-bandwidth memory). The memory may include a data storage area and a controller. Alternatively, the controller may exist independently and control the memory.

[0017] The server 104 may be an independent physical server in which an AI chip is incorporated, or may be a service node in a blockchain system. Each service node in the blockchain system constitutes a peer-to-peer (P2P) network, and the P2P protocol is an application layer protocol that runs on top of a protocol such as the Transmission Control Protocol (TCP).

[0018] Further, the server 104 may be a server cluster composed of a plurality of physical servers in which an AI chip is incorporated, and may be a cloud server that provides cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communications, middleware services, domain name services, security services, a content delivery network (CDN), and basic cloud computing services such as big data and artificial intelligence platforms.

[0019] The terminal 102 and the server 104 can be connected by a communication connection method such as Bluetooth, Universal Serial Bus (USB), or a network. The present application is not limited here.

[0020] Before explaining the memory check pin processing method provided in the embodiments of the present application, first, the data reading process of the memory in the conventional configuration will be explained.

[0021] In the conventional configuration, after a computer device sends a single burst data read command to the target memory, the target memory reads the read data based on the received read command and returns the read data to the computer device. Shown in FIG. 2 is a schematic diagram of a single read (READ) command transmitted in the conventional configuration. Here, the burst length may be 2 or 4. FIG. 3 is a schematic diagram of the read data (DQ) returned based on this read (READ) command. The related timing parameters included in FIG. 3 are as follows. tDQSCK(min / max) refers to the minimum and maximum time ranges between the rising edge of RDQS_c (or the falling edge of RDQS_t) and the rising edge of CK_c (or the falling edge of CK_t). tDQSCK describes the time delay between the rising edge of RDQS and the rising edge of CK. tQSH describes the time delay during which the RDQS signal remains at a high level. tQSL describes the time delay during which the RDQS signal remains at a low level. tLZ(min / max) describes the minimum and maximum time ranges from the continuous high-impedance state to the low-impedance state of the read data. tHZ(min / max) describes the minimum and maximum time ranges from the continuous low-impedance state to the high-impedance state of the read data. tDQSQ describes the time delay from the rising edge of RDQS_t (or the falling edge of RDQS_c) to the reading of DQ, DM, and DBI data. tQH describes the time delay from the rising edge of RDQS_t (or the falling edge of RDQS_c) until the DQ, DM, and DBI data are read and stabilized. RDQS (Read DQ Strobe) is a read data strobe and is also called a sampling pulse signal. DQ is a read data bus and is also called read data. DM (Data Mask) is a data mask. DBI (Data Bus Inversion) is a data bus inversion.Here, a burst refers to a method in which adjacent memory cells in the same row of the target memory transmit data continuously, and the number of cycles of continuous transmission is the burst length (BL: Burst Lengths).

[0022] In the conventional configuration, after a computer device sends a single burst data read command to the target memory, in addition to the target memory replying the read data to the computer device based on the received read command, the parity check data of the read data is also replied to the computer device together. Here, the parity check signal corresponding to the parity check data may be transmitted simultaneously with the read data signal of the read data, or may be transmitted with a delay relative to the read data signal of the read data. Usually, the number of delay cycles of the parity check signal with respect to the read data signal is described by a parity check delay (PL: parity latency) parameter. Specifically, the PL parameter may be set from 0 to 3 clock cycles. The setting of the PL parameter is controlled by the mode register bit MR4 (Mode Register 4) of HBM. Specifically, it is as shown in the following table.

Table 1

[0023] The role of the PL parameter will be described with examples. As shown in FIG. 4, since the corresponding read burst length (BL) = 2, PL = 0, and read latency (RL) = 7, the read data signal reaches the rising edge of the clock at time T7. Since PL = 0, the parity check signal also reaches the rising edge of the clock at time T7. Referring to FIG. 5, since the corresponding RL (Read burst length) = 2, PL = 1, and RL (Read Latency) = 6, the read data signal reaches the rising edge of the clock at time T6. Since PL = 1, the parity check signal also reaches the rising edge of the clock at time T7.

[0024] As can be seen from the above description, when the computer device sends a single data read command to the target memory, as shown in FIG. 6, the target memory returns a read data signal (DQ), a parity check signal (PAR) for the read data signal, and a corresponding sampling pulse signal (RDQS) to the computer device. The computer device samples the read data signal and the parity check signal using RDQS as the sampling signal to obtain the data to be read and the parity check data. Therefore, the sampling accuracy is the highest only when the centers of the eye patterns of the sampling pulse signal and the parity check signal are aligned. Here, ACT is a single row activation command, and PRE is a single precharge command.

[0025] The following describes the sampling accuracy with examples. As shown in Figure 7, in the figure, Data is sampled with CLK. In the scenario of HBM read check data, CLK is the RDQS signal returned from the HBM DRAM, and Data includes the PAR data returned from the HBM DRAM. In Figure 7A, the rising edge of CLK (i.e., the sampling edge) is at the center position of the data of Data. In this case, the sampling accuracy is the highest. In Figures 7B and 7C, the center position of the data of Data may not align with the rising edge of CLK. In Figure 7B, the rising edge of CLK has drifted from the data window of Data. In Figure 7C, although the rising edge of CLK has not drifted from the data window of Data, the distance between the sampling edge and the establishment (or withdrawal) edge of the data is too close, resulting in a timing violation of the setup timing (or hold timing) for this sampling. In both situations shown in Figures 7B and 7C, sampling errors of the read data occur.

[0026] In one embodiment, as shown in Figure 8, a method for processing check pins of a memory is provided. Taking the case of applying this method to the computer device (terminal or server) in Figure 1 as an example, this method includes the following steps.

[0027] In S802, a first data read command is sent to the target memory.

[0028] Here, the target memory may be a high bandwidth memory (HBM), specifically, it may be an HBM dynamic random access memory (DRAM). The first data read command is for reading data from the target memory.

[0029] In addition, in the embodiments of the present application, sending one first data read command to the target memory means, that is, starting one read operation on the target memory. The read operation in the embodiments of the present application is generally a burst read operation. Burst refers to a method in which adjacent memory cells in the same row of the target memory transmit data continuously, and the number of cycles of continuous transmission is the burst length (BL: Burst Lengths).

[0030] Specifically, the computer device generates a first data read command, sends the first data read command to the target memory in target mode, and in target mode, the target memory reads the read data from the register cell of the target memory based on the received data read command. FIG. 2 is a schematic diagram of the first data read command in the embodiments of the present application.

[0031] Here, the target mode is one of the operation modes of the memory. Specifically, the operation mode of the memory may be set by a mode register, and the mode register is for defining a specific operation mode of the HBM. This definition includes the selection of burst length, burst type, CAS latency, operation mode, and write burst mode. The operation mode in the embodiments of the present application is specifically set by the mode register bit MR7. Specifically, reference may be made to the function description information of the mode register bit MR7 shown in FIG. 9.

[0032] In one embodiment, before sending a first data read command to the target memory, the computer device also needs to set the operating mode of the target memory. The process of setting the operating mode of the target memory specifically includes: sending an operating mode setting command to the target memory, so that the target memory sets the operating mode to the target mode based on the operating mode setting command; and when the target memory is in the target mode, sending a first data read command to the target memory in the target mode.

[0033] Here, the target mode is a data word (DWORD: Data Word) read linear feedback shift register (LFSR: Linear Feedback Shift Register) mode.

[0034] Specifically, after the computer device sets the target memory to the data word read linear feedback shift register (DWORD LFSR) mode, it sends a first data read command to the target memory in the data word read linear feedback shift register mode, and the target memory reads the read data based on the received first data read command in the data word read linear feedback shift register mode, and may store the read data in the register cell of the target memory. Thereby, the computer device can obtain the read data stored in the register cell.

[0035] In the above embodiment, by the computer device sending an operating mode setting command to the target memory, the target memory sets the operating mode to the target mode based on the operating mode setting command, and in the target mode, the memory returns a first data signal and a sampling pulse signal through each check pin, and the sampling delay parameter of the check pin can be further determined.

[0036] In one embodiment, the process of setting the operating mode of the target memory to the target mode based on the operating mode setting command includes initializing the read command processing circuit of the target memory and setting the operating mode of the read command processing circuit to the target mode based on the operating mode setting command.

[0037] Here, the operating mode setting command includes 8-bit data bits, and different commands are generated by changing the values of the data bits of different bits. The command processing circuit may be a multi-input shift register (MISR) circuit.

[0038] Note that the multiple-input shift register (MISR) circuit may include a plurality of flip-flops and a plurality of input selectors that are serially coupled to each other alternately, and the plurality of input selectors may each correspond to a plurality of flip-flops. FIG. 10 shows a schematic diagram of an MISR circuit in one embodiment. FIG. 10 shows four flip-flops and four input selectors for storing and outputting 4-bit data bits. Referring to FIG. 10, when both M0 and M1 of the input control signal are 1, that is, when both M0 and M1 of the input control signal are input at the logic high level, the MISR circuit corresponds to the multiple-input shift register mode (MISR mode), that is, the MISR circuit can perform the function of a multiple-input shift register. When the M0 bit of the input control signal is 0 and the M1 bit is 1, that is, when M0 of the input control signal is input at the logic low level and M1 is input at the logic high level, the MISR circuit corresponds to the simple register mode (Register mode), that is, the MISR circuit can perform the function of a simple register (Register). When the M0 bit of the input control signal is 1 and the M1 bit is 0, that is, when M0 of the input control signal is input at the logic high level and M1 is input at the logic low level, the MISR circuit corresponds to the linear feedback shift register mode (LFSR mode), that is, the MISR circuit can perform the function of a linear feedback shift register (LFSR).

[0039] As can be understood, when the command processing circuit supports 20-bit data bits, the corresponding MISR circuit may include 20 flip-flops and 20 input selectors for storing and outputting 20-bit data bits. This 20-bit MISR circuit can be mathematically described by the following polynomial.

Number

[0040] When the command processing circuit supports 4-bit data bits, the corresponding MISR circuit may include four flip-flops and four input selectors for storing and outputting 4-bit data bits. This 4-bit MISR circuit can be mathematically described by the following polynomial.

Number

[0041] Specifically, the computer device generates an initialization command, sends the initialization command to the target memory, and after the target memory receives the initialization command, initializes the read command processing circuit based on the initialization command. Then, the computer device sends an operation mode setting command to the target memory, and the initialized target memory sets the operation mode of the read command processing circuit of the target memory to the target mode based on the operation mode setting command.

[0042] For example, the operation of setting the DWORD MISR circuit of the HBM to the DWORD read LFSR mode is specifically executed by setting the mode register MR7 of the HBM. The steps of setting the HBM to the DWORD read LFSR mode are specifically as follows. First, set the command value of MR7 to 8’b00000001. Referring to FIG. 9, here, OP0 is 1, representing the enable of the DWORD Loopback mode, OP[5:3] is 3’b000, representing resetting the default value of the DWORD register to 0xAAAAAh, and the other bits are all default values. Based on this command of MR7, the read command processing circuit is initialized. Next, set the command value of MR7 to 8’b00001011. Here, OP0 is 1, representing the enable of the DWORD Loopback mode, OP[2:1] is 2’b01, representing the reading of the value of the MISR register (since its value was reset during the initialization process, the read value is 0xAAAAAh), OP[5:3] is 3’b001, representing setting the DWORD register to the read LFSR mode, and the other bits are all default values. Based on this command of MR7, the operation mode of the read command processing circuit of the target memory is set to the DWORD read LFSR mode.

[0043] In the above embodiment, the read command processing circuit of the target memory is initialized, and based on the operation mode setting command, the operation mode of the read command processing circuit is set to the target mode, so that in the target mode, the target memory returns the first data signal and the sampling pulse signal through each check pin, and the sampling delay parameter of the check pin can be further determined.

[0044] In S804, the first data signal and the sampling pulse signal returned from each check pin of the target memory are received.

[0045] Here, the first data signal is generated based on the target data bits in the read data, and the read data is the data read from the register of the target memory by the target memory based on the first data read command.

[0046] Note that the operation mode of the target memory is the target mode, and the data output from each check pin in the target mode does not represent the check data of the read data, but returns the value of the target data bit in the read data close to the distance from each pin to the corresponding check pin.

[0047] Specifically, when the target memory receives the first data read command, it executes a read operation based on the first data read command to obtain the read data, returns the value of the target data bit in the read data to the corresponding check pin, and the check pin outputs the value of the target data bit as the first data signal.

[0048] For example, the read data and parity check pins of a single channel of HBM DRAM include the following related interfaces.

Table 2

[0049] Note that, for example, in the DWORD read LFSR mode, the data returned from the check pin does not really represent the content of the check data of the read data and is not affected by the settings corresponding to the DQ bus read parity check of MR0. Here, the functional description information of the mode register bit MR0 is as shown in FIG. 11. In the DWORD read LFSR mode, HBM DRAM returns the target data bits in the read data (DQ) close to the distance from each check pin to the corresponding check pin. Shown in the following table are the data bits of the read data actually returned corresponding to each check (PAR) pin.

Table 3

[0050] In the read LFSR mode, PAR[0] does not represent the parity check data of the 32-bit data of DQ[31:0], but only returns the value of DQ[2] to PAR[0]. Similarly, the value of DQ

[34] is returned to PAR[1], the value of DQ

[66] is returned to PAR[2], and the value of DQ

[98] is returned to PAR[3]. At the same time, the setting content of PL also stops functioning, and PAR and DQ reach at the same time, that is, it returns to the delay when PL = 0.

[0051] Referring to the schematic diagram of the structure of the read data shown in FIG. 12, one complete data word (DWORD) in the embodiment of the present application can be divided into four groups: DWORD0, DWORD1, DWORD2, and DWORD3. Here, each DWORD can be further divided into a total of four data units: Byte0, Byte1, Byte2, and Byte3. That is, the 128-bit read data (DQ) is distributed over 16 Bytes, with 8-bit DQ included for each Byte. As shown in FIG. 12, from bit 19 to bit 0 of each Byte are respectively the data words at the falling edge of DBI and the data words at the rising edge of DBI, the data words at the falling edge of each bit of the 8-bit DQ and the data words at the rising edge of DBI, the data words at the falling edge of DM and the data words at the rising edge of DBI. That is, each Byte contains a 20-bit value, and when the DWORD register is reset, the value becomes 0xAAAAAh. Therefore, the initial value of each check pin is as shown in the following table.

Table 4

[0052] As can be understood, the number of check pins is the same as the number of first data signals. For example, if there are four check pins, there are also four corresponding first data signals. For example, if the check pins are PAR[0], PAR[1], PAR[2], and PAR[3] respectively, the read data is data1, data2, data3, data4, and the first data signals returned from PAR[0] are respectively generated based on the values of the data bits DQ[2] of data1, data2, data3, data4, the first data signals returned from PAR[1] are respectively generated based on the values of the data bits DQ

[34] of data1, data2, data3, data4, the first data signals returned from PAR[2] are respectively generated based on the values of the data bits DQ

[66] of data1, data2, data3, data4, and the first data signals returned from PAR[3] are respectively generated based on the values of the data bits DQ

[98] of data1, data2, data3, data4.

[0053] In S806, a first delay parameter is obtained by time-shifting each first data signal by a delay circuit so that the target level values in each first data signal after time-shifting are aligned with the sampling pulse signal.

[0054] Here, there is a corresponding delay circuit for each of the check pins. The delay circuit is for time-shifting the data signal returned from the corresponding check pin. Time-shifting refers to moving the data signal in time. Specifically, the data signal can be time-shifted by adjusting the time delay in the transmission path corresponding to each data signal. The direction of time-shifting specifically includes a first direction and a second direction. Here, the first direction refers to the direction in which time is delayed, and the second direction refers to the direction in which time advances.

[0055] The target level value may be the first high level of the first data signal. The alignment of the target level value with the sampling pulse signal means that the first high level of the first data signal is aligned with the rising edge of the sampling pulse signal. Specifically, the alignment of the first high level of the first data signal with the rising edge of the sampling pulse signal may be at least one of the following: the rising edge of the first high level of the first data signal is aligned with the rising edge of the sampling pulse signal; the falling edge of the first high level of the first data signal is aligned with the rising edge of the sampling pulse signal; and the center of the eye pattern of the first high level of the first data signal is aligned with the rising edge of the sampling pulse signal.

[0056] The first delay parameter is the delay time for aligning the center of the eye pattern of the first high level of the time-shifted first data signal with the sampling pulse signal. That is, when the first data signal is time-shifted by the first delay parameter, the center of the eye pattern of the first high level of the time-shifted first data signal is aligned with the rising edge of the sampling pulse signal.

[0057] Referring to FIG. 7, assuming that the Data in FIG. 7C is the first data signal received by a certain check pin and the center of the eye pattern of the first high level of the first data signal is on the left side of the rising edge of the sampling pulse signal (CLK), by the delay circuit corresponding to the check pin, the first data signal is time-shifted in the first direction by the first delay parameter, so that the center of the eye pattern of the first high level of the time-shifted first data signal shown in FIG. 7A can be aligned with the rising edge of the sampling pulse signal (CLK).

[0058] FIG. 13 shows a schematic diagram of a delay circuit in an embodiment. Here, each delay circuit corresponding to each check pin includes a plurality of delay elements (DEs), each delay element includes four inverter circuits, and each DE includes a tap output after each of them. As shown in FIG. 14, by a step counter, the data signal can be controlled to come out from any one of the tap outputs, and the purpose of time-shifting the data signal can be achieved. Here, the time difference between two adjacent tap outputs is one time-shift step size. For example, in the initial state, the first data signal of a certain check pin comes out from the i-th tap output of the delay circuit. That is, in the default state, the computer device receives the first data signal from the i-th tap output of the delay circuit. When it is necessary to perform a first-direction time shift on the first data signal, by receiving the first data signal from the (i + 1)-th and subsequent tap outputs, the purpose of performing a first-direction time shift on the first data signal can be achieved. When it is necessary to perform a second-direction time shift on the first data signal, by receiving the first data signal from the (i - 1)-th and subsequent tap outputs, the purpose of performing a second-direction time shift on the first data signal can be achieved.

[0059] In one embodiment, S806 specifically includes: obtaining a first time shift parameter by time shifting each first data signal along a first direction by a delay circuit so that the rising edge of the target level value in each time-shifted first data signal aligns with the rising edge of the sampling pulse signal; obtaining a second time shift parameter by time shifting each first data signal along a second direction by a delay circuit so that the falling edge of the target level value in each time-shifted first data signal aligns with the rising edge of the sampling pulse signal, where the first direction and the second direction are opposite directions; and determining a first delay parameter corresponding to each check pin based on the first time shift parameter and the second time shift parameter.

[0060] Regarding time-shifting each first data signal along the first direction, the specific process is as follows. After the computer device acquires the first data signal, it sets the time-shift length corresponding to each check pin, returns to the step of sending the first data read command to the target memory, receives the first data signal returned again from each check pin, time-shifts the first data signal by the set time-shift length, and determines whether the rising edge of the target level value in the time-shifted first data signal aligns with the sampling pulse signal. When the rising edge of the target level value in the first data signal corresponding to each check pin aligns with the sampling pulse signal, it determines the set time-shift length and the first direction corresponding to each check pin as the first time-shift parameters corresponding to each pin. When the rising edge of the target level value in the first data signal corresponding to at least one of the check pins does not align with the sampling pulse signal, it resets the time-shift length corresponding to each check pin until the rising edge of the target level value in the first data signal corresponding to each check pin aligns with the sampling pulse signal, returns to the step of sending the first data read command to the target memory, and determines the time-shift length and the first direction corresponding to each check pin in the case of alignment as the first time-shift parameters of the corresponding check pin.

[0061] Taking one of the check pins as an example for explanation. Referring to FIG. 15, the data signal corresponding to phase 0 is the first data signal received by the computer device from the i-th (initial default) tap outlet of the delay circuit. That is, the data signal corresponding to phase 0 is the first data signal without time shift. After receiving the first data signal, the computer device sets, by the delay circuit shown in FIG. 14, the time shift direction of the check pin to be the first direction and the time shift length to be n (where n refers to the number of times of time shift) time shift step sizes, that is, it will receive the first data signal from the (i + n)-th tap outlet, returns to the step of sending the first data read command to the target memory, and after receiving the first data signal returned again from each check pin, by receiving the first data signal from the (i + n)-th tap outlet, obtains the time-shifted first data signal, and determines whether the rising edge of the target level value of the time-shifted first data signal aligns with the sampling pulse signal. If it aligns, the time shift length and the first direction corresponding to the check pin are determined as the first time shift parameters of the check pin. As shown in FIG. 15, the data signal corresponding to phase 1 is the time-shifted first data signal after several times of time shift.

[0062] Regarding the time shift of each first data signal along the second direction, the specific process is as follows. After the computer device acquires the first data signal, it sets the time shift length corresponding to each check pin, returns to the step of sending the first data read command to the target memory, receives the first data signal returned again from each check pin, then time-shifts the first data signal by the set time shift length, and determines whether the falling edge of the target level value in the time-shifted first data signal aligns with the sampling pulse signal. When the falling edge of the target level value in the first data signal corresponding to each check pin aligns with the sampling pulse signal, it determines the set time shift length and the second direction corresponding to each check pin as the second time shift parameters corresponding to each pin. When the falling edge of the target level value in the first data signal corresponding to at least one of the check pins does not align with the sampling pulse signal, it resets the time shift length corresponding to the at least one check pin until the falling edge of the target level value in the first data signal corresponding to each check pin aligns with the sampling pulse signal, then returns to the step of sending the first data read command to the target memory, and determines the time shift length and the second direction corresponding to each check pin in the case of alignment as the second time shift parameters of the corresponding check pins.

[0063] Taking one of the check pins as an example for explanation. Referring to FIG. 15, the data signal corresponding to phase 0 is the first data signal received by the computer device from the i-th (initial default) tap output of the delay circuit. That is, the data signal corresponding to phase 0 is the first data signal without time shift. After receiving the first data signal, the computer device uses the delay circuit shown in FIG. 14 to set the time shift direction of the check pin to the second direction and the time shift length to n (n refers to the number of times of time shift) time shift step sizes, that is, it will receive the first data signal from the (i - n)-th tap output, return to the step of sending the first data read command to the target memory, and after receiving the first data signal returned again from each check pin, by receiving the first data signal from the (i - n)-th tap output, obtain the first data signal after time shift, and determine whether the falling edge of the target level value of the first data signal after time shift aligns with the sampling pulse signal. If it aligns, determine the time shift length corresponding to the check pin as the second time shift parameter of the check pin. As shown in FIG. 15, the data signal corresponding to phase 2 is the first data signal after time shift that has undergone several time shifts.

[0064] In one embodiment, after the computer device obtains the first time shift parameter and the second time shift parameter of any check pin, it inputs these first time shift parameter and the second time shift parameter into the following mathematical formula to determine the first delay parameter of the check pin.

Equation

[0065] In the above embodiment, the computer device time-shifts each first data signal along the first direction by a delay circuit so that the rising edge of the target level value in each time-shifted first data signal aligns with the rising edge of the sampling pulse signal, thereby obtaining a first time-shift parameter. The computer device time-shifts each first data signal along the second direction opposite to the first direction by a delay circuit so that the falling edge of the target level value in each time-shifted first data signal aligns with the rising edge of the sampling pulse signal, thereby obtaining a second time-shift parameter. Based on the first time-shift parameter and the second time-shift parameter, a first delay parameter corresponding to each check pin is determined. Thereby, after receiving the data signal returned from each check pin subsequently, that is, after receiving the parity check signal, the parity check signal is time-shifted with the determined first delay parameter so that the time-shifted parity check signal aligns with the rising edge of the sampling pulse signal, and a second delay parameter can be further determined.

[0066] In S808, when receiving the second data signal returned from each check pin of the target memory, the target data signal in each second data signal is time-shifted by a delay circuit so that the target level values in the time-shifted second data signals align, thereby obtaining a second delay parameter.

[0067] In one embodiment, the computer device may time-shift each first data signal by a delay circuit so that the target level value in each time-shifted first data signal aligns with the sampling pulse signal, then transmit a second data read command to the target memory, and receive the second data signal and the sampling pulse signal returned from each check pin of the target memory.

[0068] Here, the second data read command may be the same as the first data read command or different from the first data read command. The second data signal is generated based on the target data bits in the read data, and the read data is the data read by the target memory from the register of the target memory based on the second data read command.

[0069] Note that the operation mode of the target memory is the target mode. In the target mode, the data output from each check pin does not represent the check data of the read data, but returns the value of the target data bit in the read data close to each pin to the corresponding check pin.

[0070] Specifically, when the target memory receives the second data read command, it executes a read operation based on the second data read command to obtain the read data, returns the value of the target data bit in the read data to the corresponding check pin, and the check pin outputs the value of the target data bit as the second data signal.

[0071] In one embodiment, after obtaining the second data signal, the computer device may obtain the fourth sampling data by sampling the second data signal time-shifted by the first delay parameter with a sampling pulse signal. The process of obtaining the second delay parameter by time-shifting the target data signal in the second data signal by a delay circuit so that the target level values in each second data signal after time-shifting are aligned is specifically as follows: when the target data bits of the target sampling data in each fourth sampling data are different from the target data bits of other fourth sampling data, determining that the target data signal in the second data signal does not align with the target level values in other second data signals; and obtaining the second delay parameter by time-shifting the target data signal in the second data signal by a delay circuit so that the target level values in each second data signal after time-shifting are aligned.

[0072] Specifically, after obtaining the second data signal, the computer device obtains the second data signal after initial time-shifting by initially time-shifting the second data signal by the first delay parameter by a delay circuit, obtains the fourth sampling data by sampling the second data signal after initial time-shifting with a sampling pulse signal, searches for target sampling data in which the target data bits in each fourth sampling data are different from the target data bits of other fourth sampling data, determines that the second data signal after initial time-shifting corresponding to the target sampling data does not align with other second data signals after initial time-shifting, and corrects the time-shift of the target data signal in the second data signal after initial time-shifting by a delay circuit so that the target level values in each second data signal after time-shifting are aligned, and determines the time-shift length of the target data signal in the process of the correction time-shift as the second delay parameter.

[0073] Note that after the computer device initially time-shifts the second data signal corresponding to each check pin by a delay circuit with a first delay parameter, the center of the eye pattern of the target level value of the second data signal after the obtained initial time shift corresponds to the rising edge of the sampling pulse signal. The corresponding rising edge of the sampling pulse signal may be a rising edge within the same clock cycle or a rising edge within different clock cycles. As shown in FIG. 16A, for the second data signals corresponding to each of the four PAR pins from PAR[0] to PAR[3], after initially time-shifting the second data signal with the first delay parameter corresponding to each PAR pin, the result shown in FIG. 16B is obtained. As can be seen from FIG. 16B, the centers of the eye patterns of the target level values of the second data signals after the initial time shift of PAR[0], PAR[1], and PAR[3] align with the rising edge of the second clock cycle, and the center of the eye pattern of the target level value of the second data signal after the initial time shift of PAR[2] aligns with the rising edge of the third clock cycle. After acquiring the fourth sampling data by sampling the second data signals after the initial time shift of each of PAR[0], PAR[1], and PAR[3], the target data bits of PAR[0], PAR[1], and PAR[3] are all the first bit, and the target data bit of the fourth sampling data of PAR[2] is the second bit. Therefore, the fourth sampling data of PAR[2] is determined as the target sampling data, and the second data signal after the initial time shift corresponding to the fourth sampling data of PAR[2] is determined as the target second data signal.Until the target level value in the second data signal after the corrected time shift of PAR[2] obtained aligns with the target level values in the second data signals after the initial time shifts of PAR[0], PAR[1], and PAR[3] (as shown in FIG. 16C), the second data signal after the initial time shift of PAR[2] is correctedly time-shifted by a delay circuit, and the time shift length and direction of the corrected time shift corresponding to the second data signal after the corrected time shift of PAR[2] when they align are determined as the second delay parameter of PAR[2]. For PAR[0], PAR[1], and PAR[3] for which no corrected time shift is performed, the second delay parameter thereof may be determined to be 0.

[0074] In one embodiment, after acquiring the second data signal, the computer device acquires the second data signal after the initial time shift by initially time-shifting the second data signal by a first delay parameter using a delay circuit, acquires the fourth sampling data by sampling the second data signal after the initial time shift with a sampling pulse signal, determines that the target level values of the second data signals after the initial time shift corresponding to each fourth sampling data are aligned when the target data bits of each fourth sampling data are the same, and determines the second delay parameter corresponding to each check pin to be 0.

[0075] In the above embodiment, the computer device obtains fourth sampled data by sampling each second data signal time-shifted by the first delay parameter with a sampling pulse signal. When the target data bit of the target sampled data in the fourth sampled data is different from the target data bits of the other fourth sampled data, it is determined that the target data signal in the second data signal does not match the target level value in the other second data signals. The second time-shift parameter is obtained by time-shifting the target data signal in each second data signal by a delay circuit so that the target level values in each second data signal after time-shifting are aligned. Thereby, based on the second delay parameter, the sampling delay parameter of each check pin can be determined. Thereby, after receiving the data signals returned from each check pin subsequently, that is, after receiving the parity check signal, the determined sampling delay parameter is used to time-shift the parity check signal so that the parity check signal after time-shifting is aligned with the sampling pulse signal, and the accuracy when sampling the parity check signal based on the sampling pulse signal is ensured.

[0076] In S810, based on the first delay parameter and the second delay parameter, the sampling delay parameter of the check pin is determined.

[0077] Specifically, after the computer device obtains the first delay parameter and the second delay parameter corresponding to each check pin, it calculates the sum of the corresponding first delay parameter and the second delay parameter, and determines the obtained sum as the sampling delay parameter of the corresponding check pin. Thereby, after receiving the data signal returned from each check pin subsequently, that is, after receiving the parity check signal, the parity check signal after time shift can be time-shifted with the determined sampling delay parameter so that it aligns with the sampling pulse signal, and the accuracy when sampling the parity check signal based on the sampling pulse signal is ensured.

[0078] In the above embodiment, the computer device transmits a first data read command to the target memory, receives the first data signal and the sampling pulse signal returned from each check pin of the target memory, and time-shifts each first data signal by a delay circuit so that the target level value in each time-shifted first data signal aligns with the sampling pulse signal, thereby obtaining the first delay parameter. When receiving the second data signal returned from each check pin of the target memory, the target data signal in each second data signal is time-shifted by a delay circuit so that the target level values in the time-shifted second data signals align, thereby obtaining the second delay parameter. Based on the first delay parameter and the second delay parameter, the sampling delay parameter of the check pin is determined. Thereby, after receiving the data signal returned from each check pin subsequently, that is, after receiving the parity check signal, the parity check signal after time shift can be time-shifted with the determined sampling delay parameter so that it aligns with the sampling pulse signal, and the accuracy when sampling the parity check signal based on the sampling pulse signal is ensured.

[0079] In one embodiment, after acquiring a first data signal, a computer device acquires first sampled data by sampling the first data signal with a sampling pulse signal. The process of acquiring a first time shift parameter by time shifting each first data signal along a first direction by a delay circuit so that the rising edge of a target level value in each time-shifted first data signal aligns with the rising edge of the sampling pulse signal specifically includes: a step of time shifting each first data signal along the first direction by the delay circuit; a step of acquiring second sampled data by sampling the first data signal time-shifted along the first direction with the sampling pulse signal; a step of determining that the rising edge of the target level value in each time-shifted first data signal aligns with the rising edge of the sampling pulse signal when the value of a target data bit in each second sampled data is the same as the target value corresponding to the target data bit in the first sampled data; and a step of determining the time shift length corresponding to each second sampled data as the first time shift parameter.

[0080] Note that after the computer device acquires the first data signal, it acquires the first sampled data by sampling the first data signal with a sampling pulse signal. The value of the data bit corresponding to the target level value of the first data signal in the acquired first sampled data should be 1. When the rising edge of the target level value in each first data signal after time shift aligns with the rising edge of the sampling pulse signal, that is, when the rising edge of the first high level in each first data signal after time shift aligns with the rising edge of the sampling pulse signal, the value of the data bit of the corresponding bit obtained by sampling the first data signal after time shift based on the sampling pulse signal should be 0. As shown in FIG. 15, the data signal corresponding to phase 0 is the first data signal without time shift, and the value of the first data bit in the first sampled data obtained by sampling the first data signal with a sampling pulse signal should be 1. The data signal corresponding to phase 1 is the first data signal with time shift, and the value of the first data bit in the first sampled data obtained by sampling the first data signal after time shift with a sampling pulse signal should be 0.

[0081] Based on this, in the embodiment of the present application, the data bit corresponding to the target level value of the first data signal in the first sampled data is determined as the target data bit, and the target value corresponding to the target data bit in the first sampled data is set to 0.

[0082] Specifically, after acquiring each first data signal, the computer device acquires each first sampled data by sampling the first data signal at the rising edge of the sampling pulse signal, returns to the step of transmitting a first data read command to the target memory, and time-shifts each first data signal along the first direction by a delay circuit to acquire each time-shifted first data signal. Then, each second sampled data is acquired by sampling each time-shifted first data signal at the rising edge of the sampling pulse signal. It is determined whether the value of the target data bit in each second sampled data is the same as the target value corresponding to the target data bit in the corresponding first sampled data. If the value of the target data bit in the second sampled data is the same as the target value corresponding to the target data bit in the corresponding first sampled data, it is determined that the rising edge of the target level value in each time-shifted first data signal aligns with the rising edge of the sampling pulse signal, and the time-shift length and the first direction of the time-shifted first data signal corresponding to the second sampled data are determined as the first time-shift parameter.

[0083] For example, in the first sampled data obtained by sampling the first data signal of a certain check pin, the target data bit is the second data bit, the value of the second data bit is 1, and when the corresponding target value is 0, after acquiring second sampled data by sampling the first data signal after time shift time-shifted along the first direction, the value of the second data bit in the second sampled data is acquired. When the value of the second data bit in the second sampled data is 0, it is determined that the rising edge of the target level value of the first data signal after time shift time-shifted along the first direction aligns with the rising edge of the sampling pulse signal, and the time shift length and the first direction in which the first data signal after time shift is time-shifted along the first direction are determined as the first time shift parameter.

[0084] In the above embodiment, the computer device acquires first sampled data by sampling a first data signal with a sampling pulse signal, time-shifts each first data signal along a first direction by a delay circuit, and samples the first data signal time-shifted along the first direction with the sampling pulse signal to acquire second sampled data. When the value of the target data bit in each second sampled data is the same as the target value corresponding to the target data bit in the first sampled data, it is determined that the rising edge of the target level value in each first data signal after time shift aligns with the rising edge of the sampling pulse signal, and the time shift length corresponding to each second sampled data is determined as a first time shift parameter. Further, based on the first time shift parameter, the sampling delay parameter of the check pin can be determined. Thereby, after receiving the data signals returned from each check pin subsequently, that is, after receiving the parity check signal, the parity check signal can be time-shifted with the determined sampling delay parameter so that the time-shifted parity check signal aligns with the sampling pulse signal, and the accuracy when sampling the parity check signal based on the sampling pulse signal is ensured.

[0085] In one embodiment, when there is second sampled data in which the value of the target data bit is different from the target value corresponding to the target data bit in the first sampled data, until the rising edge of the target level value in each acquired first data signal after time shift aligns with the rising edge of the sampling pulse signal, the process returns to the step of transmitting a first data read command to the target memory, and the time shift length corresponding to each second sampled data is determined as a first time shift parameter.

[0086] Specifically, the computer device obtains each second sampling data by sampling each first data signal time-shifted along the first direction at the rising edge of the sampling pulse signal, determines whether the value of the target data bit in each second sampling data is the same as the target value corresponding to the target data bit in the corresponding first sampling data, and if the value of the target data bit in at least one second sampling data is different from the target value corresponding to the target data bit in the corresponding first sampling data, it is determined that the rising edge of the target level value in each first data signal after time shift corresponding to the at least one second sampling data does not align with the rising edge of the sampling pulse signal, and returns to the step of transmitting a first data read command to the target memory until the rising edge of the target level value in each obtained first data signal after time shift aligns with the rising edge of the sampling pulse signal. When they align, the time shift length and the first direction corresponding to each first data signal after time shift are determined as the first time shift parameter.

[0087] For example, in the first sampled data obtained by sampling the first data signal of a certain check pin, the target data bit is the second data bit, the value of this second data bit is 1, and when the corresponding target value is 0, after obtaining the second sampled data by sampling the time-shifted first data signal time-shifted along the first direction, the value of the second data bit in the second sampled data is obtained. When the value of the second data bit in the second sampled data is 1, that is, when the 1 which is the value of the second data bit in the second sampled data is different from the target value 0, it is determined that the rising edge of the target level value of the time-shifted first data signal time-shifted along the first direction does not align with the rising edge of the sampling pulse signal, and until the rising edge of the target level value in each of the obtained time-shifted first data signals aligns with the rising edge of the sampling pulse signal, return to the step of sending the first data read command to the target memory, and determine the time shift length and the first direction corresponding to each of the time-shifted first data signals in the case of alignment as the first time shift parameter.

[0088] In the above embodiment, when there is second sampling data in which the value of the target data bit is different from the target value corresponding to the target data bit in the first sampling data, the computer device returns to the step of transmitting a first data read command to the target memory until the rising edge of the target level value in each first data signal after the obtained time shift aligns with the rising edge of the sampling pulse signal, and determines the time shift length corresponding to each second sampling data as a first time shift parameter. Further, based on the first time shift parameter, a sampling delay parameter of the check pin can be determined. Thereby, after receiving the data signals returned from each check pin subsequently, that is, after receiving the parity check signal, the determined sampling delay parameter can be used to time shift the parity check signal so that the time-shifted parity check signal aligns with the sampling pulse signal, and the accuracy when sampling the parity check signal based on the sampling pulse signal is ensured.

[0089] In one embodiment, after acquiring a first data signal, a computer device acquires first sampled data by sampling the first data signal with a sampling pulse signal. The process of acquiring a second time shift parameter by time shifting each of the first data signals along a second direction by the delay circuit so that the falling edge of the target level value in each of the first data signals after time shift aligns with the rising edge of the sampling pulse signal specifically includes: a step of time shifting each first data signal along the second direction by the delay circuit; a step of acquiring third sampled data by sampling the first data signal time shifted along the second direction with the sampling pulse signal; a step of determining that the falling edge of the target level value in each of the first data signals after time shift aligns with the rising edge of the sampling pulse signal when the value of the target data bit in each third sampled data is the same as the target value corresponding to the target data bit in the first sampled data; and a step of determining the time shift length corresponding to each third sampled data as the second time shift parameter.

[0090] After the computer device acquires the first data signal, it acquires first sampled data by sampling the first data signal with a sampling pulse signal. The value of the data bit corresponding to the target level value of the first data signal in the acquired first sampled data should be 1. When the falling edge of the target level value in each first data signal after time shift aligns with the rising edge of the sampling pulse signal, that is, when the falling edge of the first high level in each first data signal after time shift aligns with the rising edge of the sampling pulse signal, the value of the data bit of the corresponding bit obtained by sampling the first data signal after time shift based on the sampling pulse signal should be 0. As shown in FIG. 15, the data signal corresponding to phase 0 is the first data signal without time shift, and the value of the first data bit in the first sampled data obtained by sampling the first data signal with a sampling pulse signal should be 1. The data signal corresponding to phase 2 is the first data signal with time shift, and the value of the first data bit in the first sampled data obtained by sampling the first data signal after time shift with a sampling pulse signal should be 0.

[0091] Based on this, in the embodiments of the present application, the data bit corresponding to the target level value of the first data signal in the first sampled data is determined as the target data bit, and the target value corresponding to the target data bit in the first sampled data is set to 0.

[0092] Specifically, after acquiring each first data signal, the computer device acquires each first sampled data by sampling the first data signal at the rising edge of the sampling pulse signal, returns to the step of transmitting a first data read command to the target memory, and time-shifts each first data signal along the second direction by a delay circuit to obtain each time-shifted first data signal. By sampling each time-shifted first data signal at the rising edge of the sampling pulse signal, each third sampled data is acquired. When the value of the target data bit in the third sampled data is the same as the target value corresponding to the target data bit in the corresponding first sampled data, it is determined that the rising edge of the target level value in each time-shifted first data signal aligns with the rising edge of the sampling pulse signal, and the time-shift length and the second direction of the time-shifted first data signal corresponding to the third sampled data are determined as the second time-shift parameter.

[0093] For example, in the first sampled data obtained by sampling the first data signal of a certain check pin, the target data bit is the second data bit, the value of this second data bit is 1, and the corresponding target value is 0. After acquiring the third sampled data by sampling the first data signal after time-shifting along the second direction, the value of the second data bit in the third sampled data is acquired. When the value of the second data bit in the third sampled data is 0, it is determined that the falling edge of the target level value of the first data signal after time-shifting along the second direction aligns with the rising edge of the sampling pulse signal, and the time-shift length and the second direction of the first data signal after time-shifting along the second direction are determined as the second time-shift parameter.

[0094] In the above embodiment, the computer device obtains first sampling data by sampling a first data signal with a sampling pulse signal, time-shifts each first data signal along a second direction by a delay circuit, and samples the first data signal time-shifted along the second direction with the sampling pulse signal to obtain third sampling data. When the value of the target data bit in each third sampling data is the same as the target value corresponding to the target data bit in the first sampling data, it is determined that the falling edge of the target level value in each first data signal after time-shifting aligns with the rising edge of the sampling pulse signal, and the time-shift length corresponding to each third sampling data is determined as the second time-shift parameter. Further, based on the second time-shift parameter, the sampling delay parameter of the check pin can be determined. Thereby, after receiving the data signal returned from each check pin subsequently, that is, after receiving the parity check signal, the parity check signal can be time-shifted with the determined sampling delay parameter so that the time-shifted parity check signal aligns with the sampling pulse signal, and the accuracy when sampling the parity check signal based on the sampling pulse signal is ensured.

[0095] In one embodiment, when there is third sampling data in which the value of the target data bit is different from the target value corresponding to the target data bit in the first sampling data, the process returns to the step of transmitting a first data read command to the target memory until the falling edge of the target level value in each obtained first data signal after time-shifting aligns with the rising edge of the sampling pulse signal, and the time-shift length corresponding to each third sampling data is determined as the second time-shift parameter.

[0096] Specifically, the computer device obtains each third sampling data by sampling each first data signal time-shifted along the second direction based on the rising edge of the sampling pulse signal, and determines whether the value of the target data bit in each third sampling data is the same as the target value corresponding to the target data bit in the corresponding first sampling data. If the value of the target data bit in at least one third sampling data is different from the target value corresponding to the target data bit in the corresponding first sampling data, it is determined that the falling edge of the target level value in each first data signal after time shift corresponding to the at least one third sampling data does not align with the rising edge of the sampling pulse signal. The process returns to the step of sending a first data read command to the target memory until the falling edge of the target level value in each obtained first data signal after time shift aligns with the rising edge of the sampling pulse signal. When they align, the time shift length and the second direction corresponding to each first data signal after time shift are determined as the second time shift parameter.

[0097] For example, in the first sampled data obtained by sampling the first data signal of a certain check pin, the target data bit is the second data bit, the value of this second data bit is 1, and when the corresponding target value is 0, after obtaining the third sampled data by sampling the time-shifted first data signal time-shifted along the second direction, the value of the second data bit in the third sampled data is obtained. When the value of the second data bit in the third sampled data is 1, that is, when the 1 which is the value of the second data bit in the third sampled data is different from the target value 0, it is determined that the falling edge of the target level value of the time-shifted first data signal time-shifted along the second direction does not align with the rising edge of the sampling pulse signal, and until the falling edge of the target level value in each of the obtained time-shifted first data signals aligns with the rising edge of the sampling pulse signal, the process returns to the step of transmitting the first data read command to the target memory, and when they align, the time shift length and the second direction corresponding to each of the time-shifted first data signals are determined as the second time shift parameter.

[0098] In the above embodiment, when there is third sampling data in which the value of the target data bit is different from the target value corresponding to the target data bit in the first sampling data, the computer device returns to the step of transmitting a first data read command to the target memory until the falling edge of the target level value in each first data signal after the obtained time shift aligns with the rising edge of the sampling pulse signal, and determines the time shift length corresponding to each third sampling data as the second time shift parameter. Further, based on the second time shift parameter, the sampling delay parameter of the check pin can be determined. Thereby, after receiving the data signals returned from each check pin subsequently, that is, after receiving the parity check signal, the parity check signal can be time-shifted with the determined sampling delay parameter so that the time-shifted parity check signal aligns with the sampling pulse signal, and the accuracy when sampling the parity check signal based on the sampling pulse signal is ensured.

[0099] In the present application, an application scenario is further provided. In this application scenario, a method for processing check pins of a memory is applied. Specifically, referring to the system architecture diagram shown in FIG. 17, the application of the method for processing check pins of the memory in this application scenario is as follows.

[0100] In step 1, the operation mode of the HBM DRAM is set to the target mode.

[0101] Specifically, the mode setting unit of the HBM host transmits an operation mode setting command to the HBM DRAM. Thereby, the HBM DRAM sets the HBM DRAM to the DWORD read LFSR mode based on the operation mode setting command.

[0102] In step 2, a read command is transmitted to the HBM DRAM.

[0103] Specifically, the HBM host sends a read command to the HBM DRAM through the command transmission unit. The HBM DRAM analyzes the received read command, inputs the analysis result into the DWORD MISR circuit, outputs the read data through the DWORD MISR circuit, and the read PAR transmission unit returns the target data bits in the read data to the HBM host.

[0104] In step 3, the read PAR data returned from each PAR pin is received.

[0105] Specifically, the read PAR data signal and the sampling pulse signal (RDQS) returned from each PAR pin are received respectively.

[0106] Step 4 is the per PAR training stage.

[0107] Specifically, the read PAR training unit determines whether the center of the first high-level eye pattern of each PAR data signal aligns with the rising edge of the sampling pulse signal (RDQS). If all are aligned, step 5 is executed. If the center of the first high-level eye pattern of at least one read PAR data signal does not align with the rising edge of the sampling pulse signal (RDQS), the read PAR path delay control circuit adjusts the delay of the PAR path corresponding to the at least one read PAR data signal, returns to steps 2 and 3, and after receiving each read PAR data signal, time-shifts the corresponding read PAR data signal by the determined delay, and determines whether the center of the first high-level eye pattern of each time-shifted PAR data signal aligns with the rising edge of the sampling pulse signal (RDQS). If all are aligned, step 5 is executed. If the center of the first high-level eye pattern of at least one time-shifted PAR data signal does not align with the rising edge of the sampling pulse signal (RDQS), the read PAR path delay control circuit adjusts the delay of the PAR path corresponding to the at least one time-shifted PAR data signal until the center of the first high-level eye pattern of all time-shifted PAR data signals aligns with the rising edge of the sampling pulse signal (RDQS), and returns to steps 2 and 3. The delay corresponding to each PAR pin in the case of alignment is determined as the first delay parameter.

[0108] For example, as shown in FIG. 15, the initial state of the data signal of a certain PAR pin is phase 0, and the value of the second data bit of the sampling data obtained by sampling the read PAR data signal in this phase 0 state based on the pulse signal is 1.

[0109] The Step Counter continuously increases the circuit delay corresponding to the PAR pin until finally the data signal of the PAR pin reaches the Phase 1 state. The value of the second data bit of the sampling data obtained by sampling the read PAR data signal in this Phase 1 state is 0. At this time, the value of the Step Counter is recorded as R_CNT, and R_CNT is the first delay parameter of the PAR pin.

[0110] By adjusting the Step Counter, the circuit delay corresponding to the PAR pin is continuously reduced until finally the data signal of the PAR pin reaches the Phase 2 state. The value of the second data bit of the sampling data obtained by sampling the read PAR data signal in this Phase 2 state is 0. At this time, the value of the Step Counter is recorded as L_CNT, and L_CNT is the second delay parameter of the PAR pin.

[0111] It can be seen that when the circuit delay of the PAR pin is (R_CNT + L_CNT) / 2, the purpose that the PAR data signal output from the delay circuit of the PAR pin aligns with the rising edge of the clock of the sampling pulse can be achieved.

[0112] Step 5 is the per slice training stage.

[0113] Return to Step 2 and Step 3, and obtain the read PAR data signals after the initial time shift by initially time-shifting the read PAR data signals returned from each PAR pin with the first delay parameter determined in Step 4. The read PAR training unit determines whether the first high levels of the read PAR data signals after each initial time shift are aligned. If the first high levels of at least one of the read PAR data signals after the initial time shift are not aligned with the first high levels of the other read PAR data signals after the initial time shift, the read PAR path delay control circuit adjusts the delay of the PAR path corresponding to the at least one read PAR data signal, returns to Step 2 and Step 3, and after receiving each read PAR data signal, time-shifts the corresponding read PAR data signal with the determined first delay parameter and the delay, time-shifts the other read PAR data signals with the determined first delay parameter, and determines whether the first high levels of the PAR data signals after each time shift are aligned. If the first high levels of at least one of the read PAR data signals after the time shift are not aligned with the first high levels of the other read PAR data signals after the time shift, the read PAR path delay control circuit adjusts the delay of the PAR path corresponding to the at least one read PAR data signal until the first high levels of the PAR data signals after each time shift are aligned, returns to Step 2 and Step 3, and when they are aligned, determines the delay determined at this stage of the read PAR data signals after each time shift as the second delay parameter.

[0114] For example, after receiving the read PAR data signal after the initial time shift from the delay circuit of each PAR pin at this stage, each read PAR data signal after the initial time shift is sampled by a sampling pulse to obtain each sampling data. When the first "1" data bit of each sampling data is the same, it is determined that the first high levels of the read PAR data signals after each initial time shift are aligned. When the first "1" data bit of at least one sampling data is different from the first "1" data bit of other sampling data (as shown in FIG. 16B), it is determined that the first high level of at least one read PAR data signal after the initial time shift is not aligned with the first high level of other read PAR data signals after the initial time shift. Until the first high levels of the read PAR data signals after each time shift are aligned (as shown in FIG. 16C), the delay of the PAR path corresponding to the at least one read PAR data signal is adjusted by the read PAR path delay control circuit, and the process returns to Step 2 and Step 3. When they are aligned, the delay determined at this stage of each read PAR data signal after the time shift is determined as the second delay parameter.

[0115] According to the above memory check pin processing method, the following technical effects can be achieved.

[0116] 1. Before the initial operation of bringing up the HBM chip, the read PAR pins can be trained by adopting the mechanism of the present application. Thereby, when the HBM chip is initially operated, if there are problems such as non-convergence of the backend timing and sampling errors in the read PAR channels of the chip due to production obstacles of the HBM chip, the accuracy of the PAR data returned from the HBM DRAM during the initial operation of the chip can be guaranteed, and it can be guaranteed that no error occurs in the process of the HBM Host checking the read data.

[0117] 2. When the HBM chip detects a significant drift in process, voltage, and temperature (PVT), the chip can be set by software to train the read PAR pins. This ensures that transmission data errors in the read PAR channels of the chip due to PVT drift do not occur.

[0118] 3. The read PAR training of the HBM chip can be performed periodically using the mechanism of periodic read PAR training included in the hardware. This ensures that sampling errors of the read PAR do not occur during the operation of the chip.

[0119] 4. In this application, since one-step read PAR training set by software is supported, it is also possible to set the read PAR training of the entire chip alone by software. Since the software can perform this operation when the system is not busy, it can ensure that sampling errors do not occur in the read PAR pins and can also ensure the efficiency of the entire system.

[0120] It should be understood that each step in the flowchart according to each of the above embodiments is sequentially shown according to the indication of the arrow, but these steps are not necessarily sequentially executed according to the order shown by the arrow. Unless clearly described in this specification, there are no strict restrictions on the execution order of these steps. These steps may be executed in other orders. Also, at least some of the steps in the flowchart according to each of the above embodiments may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time and may be executed at different times. The execution order of these steps or stages is not necessarily sequential and may be executed alternately or in place of at least some of the steps or stages in other steps or other steps.

[0121] Based on the same inventive concept, in an embodiment of the present application, a memory check pin processing apparatus for realizing the above-described memory check pin processing method is further provided. Since the implementation configuration for solving the problems provided by this apparatus is similar to the implementation configuration described in the above method, the specific limitations in the following embodiments of one or more memory check pin processing apparatuses provided may refer to the limitations of the above memory check pin processing method. The description is omitted here.

[0122] In one embodiment, as shown in FIG. 18, a memory check pin processing apparatus is provided. This apparatus includes a command transmission module 1802, a signal reception module 1804, a signal time shift module 1806, and a delay determination module 1808. Here, The command transmission module 1802 transmits a first data read command to the target memory.

[0123] The signal reception module 1804 receives the first data signal and the sampling pulse signal returned from each check pin of the target memory.

[0124] The signal time shift module 1806 obtains a first delay parameter by time-shifting each first data signal by a delay circuit so that the target level value in each time-shifted first data signal aligns with the sampling pulse signal. When receiving the second data signal returned from each check pin of the target memory, the signal time shift module 1806 obtains a second delay parameter by time-shifting the target data signal in each second data signal by a delay circuit so that the target level value in each time-shifted second data signal aligns.

[0125] The delay determination module 1808 determines the sampling delay parameter of the check pin based on the first delay parameter and the second delay parameter.

[0126] In the above embodiment, a first data read command is sent to the target memory, the first data signal and the sampling pulse signal returned from each check pin of the target memory are received, and each first data signal after time shift is time-shifted by a delay circuit so that the target level value in the first data signal aligns with the sampling pulse signal, thereby obtaining a first delay parameter. When the second data signal returned from each check pin of the target memory is received, the target data signal in each second data signal is time-shifted by a delay circuit so that the target level value in each second data signal after time shift aligns, thereby obtaining a second delay parameter. Based on the first delay parameter and the second delay parameter, the sampling delay parameter of the check pin is determined. Thereby, after receiving the data signal returned from each check pin subsequently, that is, after receiving the parity check signal, the parity check signal can be time-shifted with the determined sampling delay parameter so that the parity check signal after time shift aligns with the sampling pulse signal, ensuring the accuracy when sampling the parity check signal based on the sampling pulse signal.

[0127] In one embodiment, as shown in FIG. 19, the apparatus further includes a mode setting module 1810. Here, the mode setting module 1810 sets the operation mode of the target memory to the target mode based on the operation mode setting command by sending the operation mode setting command to the target memory, and the command transmission module 1802 further sends a first data read command to the target memory in the target mode.

[0128] In one embodiment, the mode setting module 1810 further initializes the read command processing circuit of the target memory and sets the operation mode of the read command processing circuit to the target mode based on the operation mode setting command.

[0129] In one embodiment, the first data signal is generated based on target data bits in the read data, and the read data is data read by the target memory from the register of the target memory based on the first data read command.

[0130] In one embodiment, the signal time shift module 1806 further time-shifts each first data signal along the first direction by a delay circuit so that the rising edge of the target level value in each time-shifted first data signal aligns with the rising edge of the sampling pulse signal, thereby obtaining a first time shift parameter. The signal time shift module 1806 time-shifts each first data signal along the second direction opposite to the first direction by a delay circuit so that the falling edge of the target level value in each time-shifted first data signal aligns with the rising edge of the sampling pulse signal, thereby obtaining a second time shift parameter. Based on the first time shift parameter and the second time shift parameter, a first delay parameter corresponding to each check pin is determined.

[0131] In one embodiment, the signal time shift module 1806 further samples the first data signal with the sampling pulse signal to obtain first sampling data, time-shifts each first data signal along the first direction by a delay circuit respectively, samples the first data signal time-shifted along the first direction with the sampling pulse signal to obtain second sampling data. When the value of the target data bit in each second sampling data is the same as the target value corresponding to the target data bit in the first sampling data, it is determined that the rising edge of the target level value in each time-shifted first data signal aligns with the rising edge of the sampling pulse signal, and the time shift length corresponding to each second sampling data is determined as the first time shift parameter.

[0132] In one embodiment, when there is second sampling data in which the value of the target data bit is different from the target value corresponding to the target data bit in the first sampling data, the signal time shift module 1806 further returns to the step of transmitting a first data read command to the target memory by the command transmission module 1802 until the rising edge of the target level value in each first data signal after time shift is aligned with the rising edge of the sampling pulse signal, and determines the time shift length corresponding to each second sampling data as a first time shift parameter.

[0133] In one embodiment, the signal time shift module 1806 further obtains first sampling data by sampling a first data signal with a sampling pulse signal, time-shifts each first data signal along a second direction by a delay circuit, obtains third sampling data by sampling the first data signal time-shifted along the second direction with the sampling pulse signal, and when the value of the target data bit in each third sampling data is the same as the target value corresponding to the target data bit in the first sampling data, determines that the falling edge of the target level value in each first data signal after time shift is aligned with the rising edge of the sampling pulse signal, and determines the time shift length corresponding to each third sampling data as a second time shift parameter.

[0134] In one embodiment, when there is third sampling data in which the value of the target data bit is different from the target value corresponding to the target data bit in the first sampling data, the signal time shift module 1806 further returns to the step of transmitting a first data read command to the target memory by the command transmission module 1802 until the falling edge of the target level value in each first data signal after the acquired time shift aligns with the rising edge of the sampling pulse signal, and determines the time shift length corresponding to each third sampling data as a second time shift parameter.

[0135] In one embodiment, after each first data signal is time shifted by a delay circuit so that the target level value in each first data signal after the time shift aligns with the sampling pulse signal, the command transmission module 1802 further transmits a second data read command to the target memory, and the signal reception module 1804 further receives the second data signal and the sampling pulse signal returned from each check pin of the target memory.

[0136] In one embodiment, the signal time shift module 1806 further samples each second data signal time shifted by a first delay parameter with a sampling pulse signal to obtain fourth sampling data, and when the target data bit of the target sampling data in each fourth sampling data is different from the target data bits of other fourth sampling data, determines that the target data signal in the second data signal does not align with the target level values in other second data signals, and obtains a second delay parameter by time shifting the target data signal in the second data signal by a delay circuit so that the target level values in each second data signal after the time shift align.

[0137] Each module of the memory check pin processing device may be implemented in whole or in part by software, hardware, or a combination thereof. Each of the above modules may be embedded in the processor of the computer device in the form of hardware or may be independent, or may be stored in the memory of the computer device in the form of software. This facilitates the processor to call and execute the operations corresponding to each of the above modules.

[0138] In one embodiment, a computer device is provided. The computer device may be a server, and its internal configuration diagram may be as shown in FIG. 20. The computer device includes a processor, a memory, an input / output interface (I / O), and a communication interface. Here, the processor, the memory, and the input / output interface are connected via a system bus, and the communication interface is connected to the system bus via the input / output interface. Here, the processor of the computer device provides functions of calculation and control. The memory of the computer device includes a non-volatile storage medium and an internal memory. The operating system, computer programs, and databases are stored in the non-volatile storage medium. The internal memory provides an environment for the execution of the operating system and computer programs in the non-volatile storage medium. The database of the computer device is for storing parity check data. The input / output interface of the computer device is for exchanging information between the processor and external devices. The communication interface of the computer device is for communicating with external terminals via a network connection. When the computer program is executed by the processor, it realizes the memory check pin processing method.

[0139] In one embodiment, a computer device is provided. The computer device may be a terminal, and its internal configuration diagram may be as shown in FIG. 21. The computer device includes a processor, a memory, an input / output interface, a communication interface, a display unit, and an input device. Here, the processor, the memory, and the input / output interface are connected via a system bus, and the communication interface, the display unit, and the input device are connected to the system bus via the input / output interface. Here, the processor of the computer device provides computing and control functions. The memory of the computer device includes a non-volatile storage medium and an internal memory. The operating system and computer programs are stored in the non-volatile storage medium. The internal memory provides an environment for the execution of the operating system and computer programs in the non-volatile storage medium. The input / output interface of the computer device is for exchanging information between the processor and external devices. The communication interface of the computer device is for wired or wireless communication with an external terminal, and the wireless method may be realized by WIFI, a mobile cellular network, near-field communication (NFC), or other technologies. When the computer program is executed by the processor, it realizes a memory check pin processing method. The display unit of the computer device is for forming a visually visible screen, and may be a display screen, a projection device, or a virtual reality imaging device. The display screen may be a liquid crystal display screen or an E-ink display screen. The input device of the computer device may be a touch layer superimposed on the display screen, a button provided on the housing of the computer device, a trackball, or a touch pad, or an external keyboard, touch pad, or mouse, etc.

[0140] As can be understood by those skilled in the art, the configurations shown in FIG. 20 or FIG. 21 are merely block diagrams of some of the configurations according to the present invention, and do not limit the computer device to which the present invention is applied. The specific computer device may include more or fewer components than shown in the figures, or may be a combination of some components, or may have different arrangements of components.

[0141] In one embodiment, a computer device comprising a memory and a processor is further provided. A computer program is stored in the memory, and when the processor executes the computer program, the steps in each of the above method embodiments are realized.

[0142] In one embodiment, a computer-readable storage medium storing a computer program is provided, and when the computer program is executed by a processor, the steps in each of the above method embodiments are realized.

[0143] In one embodiment, a computer program product including a computer program is provided, and when the computer program is executed by a processor, the steps in each of the above method embodiments are realized.

[0144] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to analysis data, storage data, display data, etc.) according to the present application are all information and data permitted by the user or sufficiently permitted by each party, and it is necessary to comply with the relevant laws, regulations and standards of the relevant countries and regions for the collection, use and processing of related data.

[0145] As can be understood by those skilled in the art, all or part of the flow of the method of the above embodiments may be executed by instructing related hardware via a computer program. The computer program may be stored in a non-volatile computer-readable storage medium. When this computer program is executed, the flow of the embodiments of each method as described above is executed. Here, any reference to a memory, a database, or other media used in each embodiment provided in the present application may include at least one of non-volatile and volatile memories. Non-volatile memory may include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, and the like. Volatile memory may include random access memory (RAM) or an external cache, etc. By way of illustration and not limitation, RAM may be in many forms such as, for example, static random access memory (SRAM) and dynamic random access memory (DRAM). The database according to each embodiment provided in the present application may include at least one of a relational database and a non-relational database. The non-relational database may include, but is not limited to, a distributed database based on a blockchain. The processor according to each embodiment provided in the present application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, etc., but is not limited thereto.

[0146] Each constituent element of the above-described embodiments may be arbitrarily combined. For the sake of brevity of description, not all possible combinations of the constituent elements of the above embodiments are described. However, combinations of these constituent elements should be considered to be within the scope described in this specification as long as there is no contradiction.

[0147] The above-described embodiments merely show some embodiments of the present application. Although the description is specific and detailed, it should not be construed as a limitation to the scope of the patent of the present application. For those skilled in the art, some modifications and improvements are possible on the premise of not departing from the concept of the present application. All of these modifications and improvements belong to the protection scope of the present application. Therefore, the protection scope of the present application should follow the scope of the appended claims.

Claims

1. A method for checking pins of a memory, executed by a computer device, comprising: transmitting a first data read command to a target memory; receiving a first data signal and a sampling pulse signal returned from each check pin of the target memory; obtaining a first delay parameter by time-shifting each of the first data signals by a delay circuit so that a target level value in each of the time-shifted first data signals aligns with the sampling pulse signal; when receiving a second data signal returned from each of the check pins of the target memory, obtaining a second delay parameter by time-shifting a target data signal in each of the second data signals by the delay circuit so that a target level value in each of the time-shifted second data signals aligns; determining a sampling delay parameter of the check pin based on the first delay parameter and the second delay parameter. A method characterized by the above.

2. further comprising transmitting an operation mode setting command to the target memory so that the target memory sets an operation mode to a target mode based on the operation mode setting command, wherein the step of transmitting a first data read command to the target memory includes transmitting a first data read command to the target memory in the target mode. The method according to claim 1, characterized by the above.

3. The step of setting the operation mode to the target mode based on the operation mode setting command includes initializing a read command processing circuit of the target memory. Based on the operation mode setting command, setting the operation mode of the read command processing circuit to the target mode; The method according to claim 2, characterized in that.

4. The first data signal is generated based on target data bits in the read data, The read data is data read by the target memory from a register of the target memory based on the first data read command. The method according to claim 1, characterized in that.

5. The step of obtaining the first delay parameter by time-shifting each of the first data signals by a delay circuit so that the target level value in each of the first data signals after time-shifting aligns with the sampling pulse signal is: Obtaining a first time-shift parameter by time-shifting each of the first data signals along a first direction by the delay circuit so that the rising edge of the target level value in each of the first data signals after time-shifting aligns with the rising edge of the sampling pulse signal; Obtaining a second time-shift parameter by time-shifting each of the first data signals along a second direction by the delay circuit so that the falling edge of the target level value in each of the first data signals after time-shifting aligns with the rising edge of the sampling pulse signal, wherein the first direction and the second direction are opposite directions; Determining a first delay parameter corresponding to each of the check pins based on the first time-shift parameter and the second time-shift parameter. The method according to claim 1, characterized in that.

6. Further including the step of obtaining first sampled data by sampling the first data signal with the sampling pulse signal, The step of obtaining a first time shift parameter by time shifting each of the first data signals along a first direction by the delay circuit so that the rising edge of the target level value in each of the first data signals after time shift aligns with the rising edge of the sampling pulse signal is The step of time shifting each of the first data signals along a first direction by the delay circuit, The step of obtaining second sampled data by sampling the first data signal time shifted along the first direction with the sampling pulse signal, When the value of the target data bit in each of the second sampled data is the same as the target value corresponding to the target data bit in the first sampled data, determining that the rising edge of the target level value in each of the first data signals after time shift aligns with the rising edge of the sampling pulse signal, The step of determining the time shift length corresponding to each of the second sampled data as a first time shift parameter, and including The method according to claim 5, characterized in that.

7. When there is second sampled data in which the value of the target data bit is different from the target value corresponding to the target data bit in the first sampled data, returning to the step of transmitting a first data read command to the target memory until the rising edge of the target level value in each of the obtained first data signals after time shift aligns with the rising edge of the sampling pulse signal, The step of determining the time shift length corresponding to each of the second sampled data as a first time shift parameter, and further including The method according to claim 6, characterized in that.

8. further comprising the step of obtaining first sampled data by sampling the first data signal with the sampling pulse signal, the step of obtaining a second time shift parameter by time shifting each of the first data signals along a second direction by the delay circuit such that a falling edge of a target level value in each of the time-shifted first data signals aligns with a rising edge of the sampling pulse signal, the step of time shifting each of the first data signals along a second direction by the delay circuit, the step of obtaining third sampled data by sampling the first data signal time-shifted along the second direction with the sampling pulse signal, when a value of a target data bit in each of the third sampled data is the same as a target value corresponding to the target data bit in the first sampled data, determining that a falling edge of a target level value in each of the time-shifted first data signals aligns with a rising edge of the sampling pulse signal, and the step of determining a time shift length corresponding to each of the third sampled data as a second time shift parameter. The method according to claim 5, characterized in that.

9. when there is third sampled data in which a value of a target data bit is different from a target value corresponding to the target data bit in the first sampled data, returning to the step of transmitting a first data read command to the target memory until a falling edge of a target level value in each of the obtained time-shifted first data signals aligns with a rising edge of the sampling pulse signal, and further comprising the step of determining a time shift length corresponding to each of the third sampled data as a second time shift parameter. The method according to claim 8, characterized in that...

10. After each of the first data signals after time shift is time-shifted by a delay circuit so that the target level value in each of the first data signals after time shift aligns with the sampling pulse signal, The step of transmitting a second data read command to the target memory; The method further includes the step of receiving the second data signal and the sampling pulse signal returned from each check pin of the target memory. The method according to claim 1, characterized in that...

11. The method further includes the step of obtaining fourth sampling data by sampling each of the second data signals time-shifted based on the first delay parameter with the sampling pulse signal, The step of obtaining the second delay parameter by time-shifting the target data signal in each of the second data signals by the delay circuit so that the target level value in each of the second data signals after time shift aligns, When the target data bit of the target sampling data in each of the fourth sampling data is different from the target data bits of the other fourth sampling data, the step of determining that the target data signal in the second data signal does not align with the target level values in the other second data signals; The method includes the step of obtaining the second delay parameter by time-shifting the target data signal in the second data signal by the delay circuit so that the target level value in each of the second data signals after time shift aligns. The method according to claim 10, characterized in that...

12. A check pin processing device for a memory, A command transmission module for transmitting a first data read command to the target memory; A signal receiving module that receives the first data signal and the sampling pulse signal returned from each check pin of the target memory; A signal time shift module that obtains a first delay parameter by time shifting each of the first data signals by a delay circuit so that the target level values in each of the first data signals after time shift align with the sampling pulse signal, and when receiving a second data signal returned from each of the check pins of the target memory, obtains a second delay parameter by time shifting the target data signal in each of the second data signals by the delay circuit so that the target level values in each of the second data signals after time shift align; A delay determination module that determines a sampling delay parameter of the check pin based on the first delay parameter and the second delay parameter; An apparatus characterized by the above.

13. A computer device comprising a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, the method according to any one of claims 1 to 11 is realized.

14. A computer program that causes a computer to execute the method according to any one of claims 1 to 11.

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