XOR Logic of In-Memory Resistive Change Memory Using Complementary Switching

Abstract

In a method of using or forming a semiconductor structure, the semiconductor structure can include a resistive random access memory (RRAM) gate having a first electrode and a second electrode. The RRAM gate can further include a switching layer including a dielectric material having a switching layer k value and a switching layer thermal conductivity. The RRAM gate can further include a complementary switching (CS) mitigation layer including a material having a CS k value less than the switching layer k value and a CS thermal conductivity greater than the switching layer thermal conductivity.

Description

Technical Field

[0001] The present invention generally relates to the field of non-volatile memories, and more particularly to providing an XOR gate that uses a single device within a resistive random access memory (RRAM).

Background Art

[0002] In an RRAM device, a memory cell can be programmed to one of two states, namely a set state and a reset state. In the set state, the memory cell has a "low" resistance. In the reset state, the memory cell has a "high" resistance. The set state and the reset state of the memory cell require different threshold voltages to switch the memory cell. The reset threshold voltage is the voltage drop across the entire memory cell that needs to be overcome to disconnect the current-carrying filament. The set threshold voltage is the voltage drop across the entire memory cell that needs to be overcome to reconnect the current-carrying filament. In the case of a complementary switching RRAM device, the threshold voltage of a memory cell in the reset state is relatively higher than the threshold voltage of a memory cell in the set state. Therefore, it is possible to apply a program voltage that switches the memory cell to the set state but not to the reset state, and it is possible to apply a program voltage that switches the memory cell to the reset state but not to the set state. However, it is impossible to apply a single program voltage that changes the memory from one state to another and then changes the memory back to its original state.

[0003] An XOR gate is a logic gate that outputs true (e.g., 1, "high") only when only one of two inputs is true, and outputs false (e.g., 0, "low") when both inputs are true or both inputs are false. An XOR gate can only be constructed from a combination of manufacturable logic gates (i.e., XNOR gate, AND gate, OR gate, or NOT gate).

Summary of the Invention

[0004] One aspect of an embodiment of the present invention discloses a resistive random access memory (RRAM) gate. The RRAM gate includes a first electrode and a second electrode. The RRAM gate further includes a switching layer made of a dielectric material having a switching layer k-value and a switching layer thermal conductivity. The RRAM gate further includes a complementary switching (CS) relaxation layer having a CS k-value lower than the switching layer k-value and a CS thermal conductivity greater than the switching layer thermal conductivity.

[0005] One aspect of an embodiment of the present invention further includes a method of operating an RRAM gate, such as the RRAM gate in the above embodiment. The method includes providing an RRAM gate and resetting the RRAM gate by applying a voltage pulse. The method can further include performing a logic operation by applying a first bias to the first electrode and a second bias to the second electrode. The first bias can include a selection from the group consisting of a zero voltage and a positive complementary switching voltage (Vset), and the second bias can include a selection from the group consisting of a zero voltage and a negative Vset. The method can further include detecting the bias state of the RRAM gate using a sense voltage lower than Vset. The Vset voltage from only the first electrode or only the second electrode can produce a bias state equal to 1, and the Vset voltage from both the first electrode and the second electrode, or the zero voltage from the first electrode and the second electrode, can produce a bias state equal to 0. reset

[0006] ​Aspects of one embodiment of the present invention may further include forming a semiconductor structure. The forming method may include forming a first electrode. The method may further include forming a switching layer made of a dielectric material having a switching layer k-value and a switching layer thermal conductivity. Forming the semiconductor structure may further include forming a complementary switching (CS) relaxation layer made of a CS k-value lower than the switching layer k-value and a CS thermal conductivity higher than the switching layer thermal conductivity. Forming the semiconductor structure may further include forming a second electrode on the side opposite to the first electrode of the switching layer and the CS relaxation layer.

Brief Description of the Drawings

[0007]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Modes for Carrying Out the Invention

[0008] As described in detail below, one aspect of the present invention is a method of operating and programming a resistive random access memory (RRAM) device that includes a plurality of memory cells. Each memory cell includes an RRAM gate having a switching layer and a complementary switching (CS) layer that can be implemented as an XOR gate. Generally, an XOR gate cannot be fabricated with a single gate structure. By combining the switching layer and the CS layer, the RRAM device can be operated as a logic XOR gate by forming an oxygen vacancy filament when only one of the two electrodes sends a "1" signal and forming an oxygen vacancy depletion region when both electrodes send a "1" signal. The oxygen vacancy depletion region is formed by complementary switching that occurs when the positive bias of one electrode drifts the positively charged oxygen vacancies, leaving a gap in the oxygen vacancy filament. Details of the operation are described in connection with the drawings presented below.

[0009] FIG. 1 shows a diagram of a memory system 100 according to one embodiment of the present invention. The memory system 100 includes a resistive random access memory (RRAM) device 102 having an RRAM array 104 that includes a plurality of memory cells 106. Each memory cell 106 can be used to perform an XOR logic operation. The RRAM array 104 is organized into rows and columns such that each memory cell 106 has a distinct memory address that is the intersection of one row line and one column line.

[0010] In an exemplary embodiment, the RRAM array 104 is paired with a write circuit 108. In certain embodiments, the write circuit 108 can be incorporated into the RRAM array 104 such that each row line and / or column line, or both, is paired with a write circuit 108. The write circuit 108 can include one or more pulse generators configured to apply a current pulse to the memory cell 106, thereby programming the memory cell 106. The current pulse applied by the write circuit 108 is adjusted to zero voltage or in the positive or negative direction of a complementary switching voltage (“Vset”) for the supplied RRAM gate 110. By applying the Vset voltage, an appropriate XOR logic operation can be reliably performed.

[0011] The positive or negative direction of the write current pulse applied to the memory cell 106 depends on the desired state of the memory cell 106. The write circuit 108 generates a Vset pulse adjusted to the complementary switching characteristics determined during the manufacture of the RRAM gate 110. The complementary switching characteristics of the RRAM gate 110 include, for example, the size and shape of the RRAM gate 110, the thermal conductivity of its material, the dielectric constant, the oxygen vacancy concentration and configuration of the RRAM gate 110. That is, the RRAM gate 110 can be manufactured to have a specific Vset, and the write circuit 108 is configured to generate this voltage as the positive direction for one electrode (i.e., a row line or a column line) and as the negative direction for the other electrode (the remaining row line or column line).

[0012] Figure 2 shows a cross-sectional view of an RRAM gate 110 according to one embodiment of the present invention. The RRAM gate 110 includes, in one embodiment, a first electrode 202 and a second electrode 204 formed of a conductive material such as Pd, Ti, Pt, Ir, Ru, Cu, Au, Ta, TaN, TiN, Al / Ti, Pt / Ti, and W / Zr. The first electrode 202 and the second electrode 204 are electrically connected to the word lines and column lines, as well as the write circuit 108. As described above, the first electrode 202 can be electrically connected to a pulse generator, while the second electrode 204 is electrically connected to a different pulse generator. The first electrode 202 and the second electrode 204 can be formed using deposition techniques known in the art. For example, the first electrode 202 and the second electrode 204 can be formed using atomic layer deposition (ALD), physical vapor deposition (PVD), or chemical vapor deposition (CVD).

[0013] The RRAM gate 110 includes a CS relaxation layer 206 and a switching layer 208 disposed between the first electrode 202 and the second electrode 204 and, in at least one embodiment, in direct contact with each other. FIG. 2 shows a single RRAM gate 110, but in practice, a plurality of such RRAM gates 110 can be arranged together to form an RRAM array 104. The RRAM array 104 can include upper word electrodes and lower column electrodes connected to the RRAM array 104 such that each of the single RRAM gates 110 can be individually addressed using respective pairs of upper and lower electrodes.

[0014] The switching layer 208 is made of a material having a defined k value (dielectric constant) and a defined thermal conductivity. The k value and the thermal conductivity are determined by selecting specific material and dimensional characteristics during manufacturing. The switching layer 208 is a dielectric metal oxide material, such as ZrO2, NiO, TiO2, MnO2, Al2O3, ZnO, RuNCs, ZnO, HfO2, HfO2, TaO x 、HfO2、Ta2O5、TiO2NPs、TaO x / 、TaO x / MgO、TiO2-x , a-ZnO, WO3 / Al2O3, TiO 2-x , HfO x , TiO 2-x , HfO2, a-TiO2, Zn2TiO4, Ta / TaO x , HfO x / AlO x , TaO x / TiO2, TiO x / HfO x , MnO / Ta2O5, HfO x / , and can include AgNPs and the like. The switching layer 208 can further be formed using techniques known in the art. Specifically, the switching layer 208 can be formed using ALD, PVD, or CVD. That is, for each RRAM gate 110 (or for the RRAM array 104), a pattern is applied to a substrate or other semiconductor structure, and a series of depositions are carried out to sequentially form the layers of the RRAM gate (the first electrode 202, the second electrode 204, the switching layer 208, etc.).

[0015] The CS relaxation layer 206 is also made of a material that defines the CSk value and the CS thermal conductivity for the RRAM gate 110. The CSk value and the CS thermal conductivity are determined by selecting specific material properties and dimensional properties during manufacturing. The CS relaxation layer 206 can include a material that replaces the material of the switching layer 208, such as metal oxide materials like aluminum oxide, aluminum nitride, and boron nitride. In certain embodiments, the CS relaxation layer 206 includes a material different from the material used in the same embodiment of the switching layer 208. The material of the CS relaxation layer 206 can be selected such that the CSk value is smaller than the k value of the switching layer and the CS thermal conductivity is larger than the thermal conductivity of the switching layer. Embodiments of the RRAM gate 110 having a CSk value smaller than the k value of the switching layer and a CS thermal conductivity larger than the thermal conductivity of the switching layer enhance the feasibility of complementary switching. By enhancing the feasibility of complementary switching, a more effective and accurate XOR logic operation becomes easier. The CS relaxation layer 206 can also be formed using techniques known in the art. Specifically, the CS relaxation layer 206 can be formed using ALD, PVD, or CVD.

[0016] Figure 3 shows a flowchart of the operation of the RRAM device 102 according to an embodiment of the present invention. The RRAM device 102 provides an RRAM gate (e.g., the RRAM gate 110 of FIGS. 1 and 2) having a switching layer (e.g., the switching layer 208 shown in FIG. 2) and a CS relaxation layer (e.g., the CS relaxation layer 206 shown in FIG. 2) (block 302). The provided RRAM gate enables set and reset states (i.e., logical "1" and "0") in the switching layer 208 by utilizing the formation of a conductive filament of oxygen vacancies (V o 2+ ).

[0017] FIG. 4 shows a schematic diagram of a conductive filament 412 formed in an RRAM gate 110 to enable set and reset states within an RRAM device (e.g., RRAM device 102) according to one embodiment of the present invention. When providing the RRAM gate 110, the RRAM device 102 applies a voltage across the first electrode 202 and the second electrode 204 (e.g., using the write circuit 108), causing movement of oxygen vacancies and oxygen ions (O 2- ). This movement enables the formation of a conductive filament 412 between the first electrode 202 and the second electrode 204. The formation of the conductive filament is initially caused by a soft breakdown of the dielectric layer 414 (i.e., the combination of the switching layer 208 and the CS relaxation layer 206 within the RRAM gate 110) by a high voltage pulse. The initial breakdown knocks oxygen atoms / ions out of the lattice of the dielectric layer 414, leaving oxygen vacancies within the dielectric layer 414. The oxygen ions ultimately leave the dielectric layer 414, and the oxygen vacancies form a conductive filament 412 within the dielectric layer 414. The provided RRAM gate 110 thus results in a low resistance state (i.e., logical "1").

[0018] Once the conductive filament 412 is formed, the RRAM device 102 resets the RRAM gate 110 (block 304) by applying a V reset voltage pulse. The reset process can involve different magnitudes of the V reset voltage, different polarities of the V reset voltage, or both, depending on whether the RRAM gate utilizes unipolar switching or bipolar switching. The V resetVoltage can generate Joule heat, and the Joule heat causes oxygen ions to return into the dielectric layer 414 and combine with oxygen vacancies or oxidize the conductive filament 412 to generate a high resistance state. In certain embodiments, the diffusion of oxygen ions is activated only by thermally utilizing the Joule heat current. Additionally or alternatively, certain embodiments can use an inverse electric field to move oxygen ions.

[0019] Returning to the method of FIG. 3, the RRAM device 102 further performs a logic operation (block 306) by applying a first bias to the first electrode 202 and a second bias to the second electrode 204. The first bias and the second bias can be applied simultaneously. The first bias includes one of zero voltage (logical "0") or positive Vset (logical "1"), and the second bias includes one of zero voltage (logical "0") or negative Vset (logical "1").

[0020] When both biases apply zero voltage, the RRAM device 102 remains in the high resistance state (logical "0") which is the result of the reset process.

[0021] When either, but not both, of the biases applies Vset (logical "1"), the RRAM gate 110 reforms the conductive filament 412 to be in the low resistance state (logical "1"). The conductive filament 412 is reformed by the rearrangement of oxygen vacancies in the dielectric layer 414 and reconnects to the first electrode 202 and the second electrode 204.

[0022] When both biases apply Vset (logical "1"), the RRAM gate 110 is driven into complementary switching that maintains the RRAM gate 110 in the high resistance state (logical "0").

[0023] FIG. 5 shows a schematic diagram of an RRAM gate 110 having a broken conductive filament 516 according to one embodiment of the present invention. The broken conductive filament 516 is the result of complementary switching that creates an oxygen vacancy depletion region 518 within the broken conductive filament 516. The oxygen vacancy depletion region 518 is caused by the drift of oxygen vacancies. Since oxygen vacancies have a positive charge, when the dielectric layer 414 undergoes soft breakdown due to the Vset voltage, the positive polarity of the first bias of the first electrode 202 repels the oxygen vacancies, forming the oxygen vacancy depletion region 518.

[0024] The CS relaxation layer 206 suppresses or relaxes or both the effects of the positive first bias on the oxygen vacancy depletion region 418. That is, the smaller the k value, the more effectively the positive bias interferes with and repels the oxygen vacancies, and the larger the thermal conductivity value, the slower the movement of the oxygen vacancies. Therefore, without the CS relaxation layer 206, the RRAM gate 110 cannot have a sufficient voltage window between set and reset.

[0025] Returning to the method of FIG. 3, the RRAM device 102 further detects the bias state of the RRAM gate 110 using a sense voltage lower than Vset (block 308). As described above, the Vset voltage (positive) from only the first electrode 202, or the Vset voltage (negative) from only the second electrode 204, results in a bias state equal to 1 detected by the RRAM device 102. As further described above, when the RRAM device 102 applies the Vset voltage from both the first electrode 202 and the second electrode 204, or when the RRAM device 102 applies a zero voltage bias to the first electrode 202 and the second electrode 204, the RRAM device 102 detects a bias state equal to 0.

[0026] The programs described herein are identified based on the uses in which they are implemented in particular embodiments of the present invention. However, any specific program nomenclature in this specification is for convenience only, and thus it should be recognized that the present invention should not be limited to use only in any specific use identified or implied or both by such nomenclature.

[0027] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagram can represent a module, segment, or portion of code that includes one or more executable instructions for implementing the specified logical function(s). Further, in some alternative implementations, the functions noted within the blocks can be performed in an order different from that shown. For example, two blocks shown in succession can in fact be executed substantially simultaneously, or the blocks can be executed in the reverse order, depending upon the functionality involved. It should also be noted that each block of the block diagrams or flowchart diagrams, or combinations of blocks in the block diagrams or flowchart diagrams, can be implemented by a dedicated hardware-based system for performing the specified function or operation, or by a combination of dedicated hardware and computer instructions.

Claims

1. a first electrode, a second electrode, a switching layer including a dielectric material, a complementary switching (CS) relaxation layer including a material having a CS k-value smaller than the k-value of the switching layer determined during manufacturing and a CS thermal conductivity larger than the thermal conductivity of the switching layer determined during manufacturing providing a resistive random access memory (RRAM) gate comprising: resetting the RRAM gate by applying a Vreset voltage pulse; performing a logic operation by applying a first bias to the first electrode and a second bias to the second electrode, wherein the first bias includes a selection from the group consisting of a zero voltage and a positive complementary switching voltage (Vset), and the second bias includes a selection from the group consisting of a zero voltage and a negative Vset; detecting a bias state of the RRAM gate using a sense voltage lower than Vset, wherein a Vset voltage from only the first electrode or only the second electrode results in a bias state equal to 1, and a Vset voltage from both the first electrode and the second electrode, or a zero voltage from the first electrode and the second electrode, results in a bias state equal to 0; A method comprising.

2. The method of claim 1, including waiting for a time between performing the logic operation and detecting the bias state of the RRAM gate.

3. The voltage for resetting includes a selection from the group consisting of (i) a voltage that is twice the Vset of the RRAM gate applied to the first electrode, (ii) a voltage that is twice the Vset of the RRAM gate applied to the second electrode, and (iii) a combination of a positive Vset for one of the first electrode and the second electrode and a negative Vset for the remainder of the first electrode and the second electrode, according to the method of claim 1.

4. Performing the logic operation includes forming a conductive filament in the switching layer, according to the method of claim 1.

5. The combination of the positive Vset and the negative Vset promotes the formation of an oxygen vacancy (Vo ２＋ )-deficient region, according to the method of claim 4.

6. The oxygen vacancy-deficient region occurs closer to the first electrode than the second electrode, according to the method of claim 5.

7. The switching layer includes a material selected from the group consisting of HfOx, TaOx, TiO x, NiO x, according to the method of claim 1.

8. Resetting the RRAM gate includes applying a Vreset voltage pulse after detecting the bias state of the RRAM gate, according to the method of claim 1.

9. A first electrode, A second electrode, A switching layer including a dielectric material having a switching layer k value and a switching layer thermal conductivity, A complementary switching (CS) relaxation layer including a material having a CS k value smaller than the switching layer k value determined during manufacturing and a CS thermal conductivity larger than the switching layer thermal conductivity determined during manufacturing A resistive random access memory (RRAM) gate comprising.

10. The CS relaxation layer is disposed between the first electrode and the switching layer, and the first electrode is configured to apply a positive complementary switching voltage (Vset). The RRAM gate according to claim 9.

11. The second electrode is configured to apply a negative Vset. The RRAM gate according to claim 10.

12. The CS relaxation layer includes a selection from the group consisting of aluminum oxide, aluminum nitride, and boron nitride. The RRAM gate according to claim 9.

13. The CS relaxation layer has dimensional characteristics adjusted to enhance the realizability of complementary switching. The RRAM gate according to claim 9.

14. The CS relaxation layer has dimensional characteristics adjusted to slow down the diffusion of oxygen vacancies (Vo ２＋ ) in the switching layer. The RRAM gate according to claim 9.

15. The voltage pulse applied to the first electrode is supplied to the second electrode through the switching layer and the CS relaxation layer. The RRAM gate according to claim 9.

16. The switching layer includes a selection from the group consisting of HfOx, TaOx, TiO x, and NiO x. The RRAM gate according to claim 9.

17. A method of forming a semiconductor structure, comprising: Forming a first electrode; Forming a switching layer including a dielectric material having a switching layer k value and a switching layer thermal conductivity; Forming a complementary switching (CS) relaxation layer including a material having a CS k value smaller than the switching layer k value determined during manufacturing and a CS thermal conductivity greater than the switching layer thermal conductivity determined during manufacturing; Forming a second electrode on the side opposite to the first electrode of the switching layer and the CS relaxation layer A method including this.

18. The method according to claim 17, wherein the CS relaxation layer includes a selection from the group consisting of aluminum oxide, aluminum nitride, and boron nitride.

19. The method according to claim 17, including adjusting the dimensional characteristics of the CS relaxation layer so as to increase the threshold voltage for complementary switching.

20. The method according to claim 17, wherein the switching layer includes a selection from the group consisting of HfOx, TaOx, TiO x, and NiO x.

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