Semiconductor wafer thinned by horizontal stealth lapping

Abstract

The method includes thinning a semiconductor wafer by a horizontal stealth lasing process, and the semiconductor wafers, dies, and devices formed thereby. After forming an integrated circuit layer on the semiconductor wafer, the wafer may be thinned by supporting the active surface of the wafer on a rotating chuck and focusing a horizontally oriented laser at different radii within the rotating wafer in multiple cycles. Upon completion of the multiple cycles, a portion of the wafer substrate may be removed to leave the wafer thinned to its final thickness. A vertical stealth lasing process may then be performed to cut individual semiconductor dies from the thinned wafer.

Description

Technical Field

[0001] (Cross - Reference to Related Applications) This application claims the benefit of the entire contents of U.S. Non - Provisional Application No. 17 / 841,357, entitled "Semiconductor Wafer Thinned by Horizontal Stealth Lapping", filed on Jun. 15, 2022, and incorporates the same herein by reference in its entirety for all purposes.

Background Art

[0002] Due to the strong growth in the demand for portable consumer electronics, the need for high - capacity storage devices is increasing. To meet the ever - growing requirements for the storage and exchange of digital information, non - volatile semiconductor memory devices such as flash memory storage cards are widely used. Such memory devices are ideal for use in a wide variety of electronic products, including, for example, digital cameras, digital music players, video game consoles, computer SSDs, PDAs, and cellular phones, due to their portability, versatility, rugged design, high reliability, and large capacity.

[0003] Currently, wafers are shipped from the wafer fab at a thickness of usually 760 microns to prevent damage during transportation and are thinned after individual semiconductor dice are defined within the wafer. To maximize the storage capacity of a storage device of a given form factor, semiconductor dice and the wafers on which they are manufactured are being made thinner and thinner. Currently, wafers are, for example, 36 microns, 25 microns, and getting even thinner.

[0004] Common methods for thinning semiconductor wafers include a back grinding process in which the non-active back surface of the wafer is thinned using a number of grinding wheels, while the active surface of the wafer is covered with a protective tape and supported by a chuck. Conventional back grinding processes have several drawbacks, including non-uniform thickness across the wafer surface. Back grinding can also exert forces on the wafer that can cause cracks, especially considering the fragile thickness of current semiconductor wafers. Since dies with cracks need to be discarded, the yield is reduced. Additionally, crack detection requires additional screening / inspection steps, increasing manufacturing costs and processing time. In conventional back grinding processes, furthermore, debris and foreign objects can occur that can cause cracks or adversely affect die manufacturing in the wafer.

Brief Description of the Drawings

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DETAILED DESCRIPTION OF THE INVENTION

[0018] Next, the present technology will be described with reference to the drawings, which generally relate to a method of thinning a semiconductor wafer by a horizontal stealth lapping process, as well as the semiconductor wafer, die, and device formed thereby. After forming an integrated circuit layer on the semiconductor wafer, the active surface of the wafer is supported on a rotating chuck, and a horizontally oriented laser is focused through the outer edge of the wafer in a plurality of cycles at different radii within the rotating wafer, whereby the wafer can be thinned. After a plurality of cycles are completed, a portion of the wafer substrate can be removed to leave a wafer thinned to a final thickness. Thereafter, a vertical stealth lapping process can be performed to dice individual semiconductor dies from the thinned wafer.

[0019] It is understood that the present invention can be embodied in many different forms and should not be construed as limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Indeed, the present invention is intended to cover alternatives, modifications, and equivalents of these embodiments within the scope and spirit of the invention as defined by the appended claims. Further, in the following detailed description of the present invention, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention may be practiced without such specific details.

[0020] Terms such as "top" and "bottom", "upper" and "lower", and "vertical" and "horizontal" as may be used herein are for purposes of illustration and description only and are not meant to limit the description of the technology since the positions and orientations of the items referred to can be interchanged. Also, as used herein, the terms "substantially", "approximately" and / or "about" mean that the specified dimension or parameter can vary within acceptable manufacturing tolerances for a given application. In one embodiment, the acceptable manufacturing tolerance is 0.15 mm, or ±2.5% of a given dimension.

[0021] For the purposes of the present disclosure, the connection may be a direct connection or an indirect connection (e.g., a connection through one or more other parts). In some cases, when it is mentioned that a first element is connected, fixed, attached, or coupled to a second element, the first element and the second element may be directly connected, fixed, attached, or coupled to each other, or may be indirectly connected, fixed, attached, or coupled to each other. When it is mentioned that a first element is directly connected, fixed, attached, or coupled to a second element, there is no intervening element between the first element and the second element (except perhaps something like an adhesive or a molten metal used to connect, fix, attach, or couple the first element and the second element).

[0022] Next, embodiments of the present technology will be described with reference to the flowchart of FIG. 1 and the diagrams of FIGS. 2 to 14. First, referring to the flowchart of FIG. 1, the semiconductor wafer 100 may start as an ingot of wafer material that can be formed in step 200. In one example, the ingot from which the wafer 100 is formed may be single-crystalline silicon grown according to either the Czochralski (CZ) or the floating zone (FZ) process. However, in further embodiments, the wafer 100 may be formed from other materials and by other processes.

[0023] In step 202, the semiconductor wafer 100 is cut from the ingot and may be polished on both the first major surface 102 (FIG. 2) and the second major surface 104 (FIG. 3) that faces the first major surface 102 to provide a smooth surface. In step 204, the wafer may be trimmed along the outer periphery to ensure that the edges of the wafer 100 at the outer periphery are perpendicular (parallel to the central axis of rotation of the wafer). These perpendicular edges prevent refraction of the laser by the outer peripheral edge, as will be described below.

[0024] In step 206, the first major surface 102 can divide the wafer 100 into respective semiconductor dies 106 (one of which is numbered in FIGS. 1 and 2) through various processing steps, and form integrated circuits of the respective semiconductor dies 106 in the active regions of the dies on and / or within the first major surface 102. These various processing steps may include photolithography steps, etching steps, and metallization steps for depositing metal layers, vias, and contacts for transferring signals to and from the integrated circuits. FIG. 3 is a cross-sectional side view of an exemplary semiconductor die 106 of the wafer 100 showing an integrated circuit layer 110 formed in the silicon substrate region 112. The integrated circuit layer 110 may generally include an integrated circuit 114 electrically coupled to a surface die bond pad 116 by a metallization layer 118. The integrated circuit 114 may be formed by various processes including, for example, deposition, patterning, and doping of metals, metal oxides, and silicon.

[0025] After forming the integrated circuit 114, the metallization layer 118 may be defined to include metal interconnects 120 and vias 124 sequentially stacked within a dielectric film 128. As known in the art, the metal interconnects 120, vias 124, and dielectric film 128 may be formed, for example, by performing a damascene process on one layer at a time by photolithography and thin film deposition. The metal interconnects 120 and vias 124 may be used to form conductive nodes for transferring signals and voltages between the die bond pad 116 and the integrated circuit 114. A passivation layer 130 may be formed on top of the upper dielectric film layer 128. The passivation layer 130 may be etched to expose the die bond pad 116.

[0026] In an embodiment, the semiconductor die 106 may be, for example, a flash memory die such as a 2D NAND flash memory or a 3D BiCS (bit cost scaling), V-NAND, or other 3D flash memory, although other types of die 106 may be used. These other types of semiconductor die include, but are not limited to, RAM, a controller, a SOC (system on chip), a processor, or other types of semiconductor die. The number of die 106 shown on the wafer 100 in FIG. 2 is for illustration purposes, and in further embodiments, the wafer 100 may include more semiconductor die 106 than shown. Similarly, the number of bond pads 116 on each semiconductor die 106 is shown for illustration purposes, and in further embodiments, each die 106 may include more die bond pads than shown.

[0027] After forming the integrated circuit layer 110 in step 206, the tape layer may be laminated onto the active first major surface 102 in step 210. The wafer 100 may then be flipped over and thinned in step 212. According to aspects of the present technology, the wafer 100 may be thinned by performing a horizontal stealth lapping step, as will be described with reference to FIGS. 4-12. Referring to the perspective view of FIG. 4, the wafer 100 may be supported on the chuck 134 or other support surface such that the tape layer 136 separates the active surface 102 from the chuck 134. The second major surface 104 faces upward. In an embodiment, the chuck 134 is configured to rotate about a central axis A C and is centered on the chuck 134, such that the wafer is also concentric with respect to the central axis A C .

[0028] The laser assembly 140 is provided to emit a pulsed laser beam through the circumferential outer edge 138 of the wafer into the depth of the wafer 100, specifically into the silicon substrate region 112. The laser assembly 140 may include a laser generator 142 for generating a laser beam 144 and an optical system 146 for focusing the laser beam 144 onto a point inside the wafer 100, as will be described below. The laser generator may generate an infrared or near-infrared laser, for example, at a wavelength of 1342 nm. Other wavelength lasers are conceivable. As described below, the peak power and beam area of the laser generator 142 together define the peak power density of the laser beam 144. Peak power density W / m 2 = Peak power (W) / Beam area (m 2 ). In one example, the peak power of the laser generator 142 may be 2 W, and the beam diameter may be about 2 - 4 μm. These values are for illustrative purposes only and may vary in further embodiments. In one example, the laser generator may pulse the laser beam 144 at 90 KHz.

[0029] The optical system 146 may include, for example, a collimating lens that can focus light of parallel wavelengths from the laser generator 142 onto a focus of maximum energy. The laser assembly 140 is shown schematically and may include additional components for the generation and focusing of the laser, including a controller for controlling the intensity and pulse frequency of the laser.

[0030] The laser assembly 140 is configured to emit a horizontal beam through the circumferential outer edge 138 of the wafer 100 in the x - y plane (when the central axis A C is perpendicular along the z - axis). In a further embodiment, the laser beam 144 is the central axis A CUnder the condition of being radiated onto a plane orthogonal to [the relevant direction], the laser beam 144 can be non-horizontal. According to this technology, the laser assembly 140 is positioned along the vertical z-axis and radiates the beam 144 onto the silicon substrate region 112 in a plane corresponding to the final thickness of the wafer 100. In an embodiment, this final thickness can be in the range of 20 μm to 100 μm, including 25 μm and 36 μm, but it is understood that the laser assembly 140 can be positioned to achieve other final thicknesses of the wafer 100 within or outside this range.

[0031] When the vertical height of the laser assembly 140 is set, the optical system 146 focuses the laser beam 144 at a predetermined first radius (as described below) adjacent to, for example, the central axis A of the rotation of the wafer 100. C Then, the wafer 100 is rotated through a full cycle (360°) on the chuck 134 while the laser emits light pulses at a predetermined frequency. After the first cycle is completed, the radius at which the laser is focused is then adjusted to a new radius, and the wafer is rotated through a full cycle again while the laser emits light pulses at a predetermined frequency. This process can continue in multiple cycles with increasing radii until the laser is focused at or near the outer edge 138 of the wafer 100.

[0032] Referring to FIG. 5, a cross-sectional top view of the wafer 100 is shown. In the illustrated example, the laser assembly 140 is focused at three different radii, namely r1, r2, and r3. The laser assembly emitted pulses at each radius at a predetermined frequency as the wafer 100 rotated on the chuck 134. When the laser beam hits the peak power density during the pulse at the focus, the wafer absorbs energy, and local pinpoint holes 150 are created at radii r1, r2, and r3 below the surface of the wafer and within the horizontal plane of the laser beam. A plurality of pinpoint holes 150 are created at each radius. In one example, the pinpoint holes 150 may be created once every 5 μm - 10 μm around a given radius, but in further embodiments, the pinpoint holes 150 may be arranged closer to each other or farther apart than that range. FIG. 5 shows a simplified example for illustrative purposes, and there may be more radii at which the laser cycle is executed. For example, for a 300 mm wafer, there could be 250 different cycles, each executed at equally spaced radii.

[0033] In one embodiment, the pulse rate of the laser generator 140 is constant. Given that the circumferential arc length at a radius near the center of the wafer is shorter and has fewer pinpoint holes than the circumferential arc length at the outer radius, the angular velocity of the chuck 134 can vary such that the number of pinpoint holes per unit length at a given radius is kept constant. In one example, the rotating chuck maintains a constant linear velocity of about 700 mm per second. Thus, the angular velocity of the chuck varies as follows. ω = v / r ω = 700 mm / r Where ω is the angular velocity, v is the linear velocity, and r is the radius. It is understood that in further embodiments, the linear velocity may be higher or lower than that. In further embodiments, the speed of the rotating chuck may be kept constant, and the predetermined pulse frequency of the laser generator 142 may vary according to the radial distance from the central axis of rotation.

[0034] Figures 6 and 7 are side views showing how the optical system 146 can control the focus of the laser assembly 140 at different radii in a given plane within the wafer 100. The optical system 146 can be mounted for translational movement on the fixture 152. As an example, the optical system 146 can be attached to a pinion gear that is rotationally driven by a motor along a stationary rack within the fixture. In further embodiments, other drive systems can be contemplated for translating the optical system within the fixture 152.

[0035] The optical system 146 can focus the laser at a point a predetermined distance forward from the optical system 146. When the optical system is positioned near the laser generator (Figure 6), the laser beam 144 focuses at a radius near the outer periphery of the wafer 100. When the cycle at a given radius is complete, the optical system can translate along the fixture 152 in the direction of arrow 154 to a new radius at which the laser beam 144 is focused, and a new cycle can begin. The laser generator 142 continues to generate pinpoint holes 150 at different radii until the optical system 146 focuses the laser beam 144 at or near the central axis A C of the wafer 100. In further embodiments, the laser can start at or near the central axis A C and operate outwardly such that the optical system translates in the direction opposite to arrow 154 on the fixture 152. The laser assembly 140 and the fixture 152 are shown schematically in Figures 6 and 7, and in further embodiments, both can vary in composition.

[0036] Thinning the wafer 100 according to aspects of the present technology provides several advantages including shortening the wafer manufacturing time. For example, the time taken to thin a single wafer can be calculated by dividing the sum of the circumferential arc lengths spanned by the laser over various radii by the linear velocity of the rotating chuck. The sum of the circumferences spanned by the laser over all radii is determined by the following equation. CL tot = CL1 + CL2 + CL3 + … + CL n Among them, CL1 is the arc length of the circumference at the first radius, CL2 is the arc length of the circumference at the second radius, …, and n is the total number of cycles (for example, 250). Since the arc length of the circumference is equal to 2πr, CL tot = 2π(r1 + r2 + r3 + … + r n ) is obtained. When the radii are equally spaced, the sum of the radius distances can be calculated as the sum of the first radius and the last radius multiplied by the total number of cycles and divided by 2. (r1 + r2 + r3 + … + r n ) = 250(r1 + r n ) / 2 Taking an example where the first radius is 0.6 mm from the center radius A C and the last radius is 150 mm from the center radius, the total distance of the circumferential arc length that the laser moves is as follows. CL tot = 2π * 250(0.6 mm + 150 mm) / 2 CL tot = 118,221 mm When the linear rotation speed of the chuck 134 is 700 mm / second, the total time for wafer thinning according to this technology is as follows. T tot = CL tot / V チャック T tot = 118,221 mm / 700 mm / s = 169 seconds In comparison, wafer thinning by conventional back grinding takes 500 - 600 seconds per wafer. Therefore, this technology improves the wafer thinning time by approximately 300% - 360%.

[0037] The speed of the wafer thinning operation according to this technology can be further reduced by adding an additional laser assembly. Figure 8 is a perspective view of a wafer being thinned by a pair of laser assemblies 140. Each laser assembly 140 can be the same structurally and operationally as those described above. The two laser assemblies 140 direct their respective beams 144 in the same horizontal plane (central axis A CIt can be attached so as to face inward within the wafer 100 (perpendicular to [the reference]). The laser assemblies may be spaced 180° from each other, but this is not necessary in further embodiments.

[0038] In one embodiment, the optics 146 of both laser assemblies 140 control their laser beams 144 to be focused to a radius that is at the same distance from the central axis A C Thus, after a 180° rotation, a complete cycle of the pinpoint holes 150 can be created over the entire circumference at a given radius. As a result, the time to thin the wafer can be further reduced by half. In further embodiments, each laser may be focused to a different radius, such that while 360° is required for the full cycle, the number of cycles is halved, again reducing the overall time to thin the wafer by half. To further reduce the wafer thinning processing time, the wafer thinning setup can include three, four, or more laser assemblies 140.

[0039] In the embodiments described herein, the horizontal stealth scribing process is performed by forming local pinpoint holes 150 at different radii as the wafer 100 rotates. However, in a further embodiment shown in FIG. 9, the local pinpoint holes 150 can be formed in rows along a straight line through the wafer while the wafer is stationary (not rotating). In this embodiment, the laser is mounted to a fixture configured to move the laser generator along the y-axis (in and out of the page of FIG. 9) and to move the optical system 146 along the x-axis to form multiple rows of pinpoint holes 150. In this embodiment, the optical system 146 is configured to move across the entire diameter of the wafer 100 (whereas in the embodiment of FIG. 4, the optical system 146 only needs to move across the radius distance of the wafer 100). In a further example, in the embodiment of FIG. 9, a second laser assembly 140 can be provided (as in FIG. 8). In such an embodiment, each laser can form pinpoint holes 150 along a straight row across half of the wafer. Thus, the laser assembly 140 on the left side of the wafer 100 forms pinpoint holes 150 on the left side of the wafer, and the laser assembly 140 on the right side of the wafer 100 forms pinpoint holes 150 on the right side of the wafer.

[0040] FIG. 10 is a side view of the wafer 100 after all cycles of the stealth horizontal lapping process of step 212 are completed. When the cycle of the pinpoint holes 150 is completed at each radius, cracks naturally propagate between the holes within the [1,1,0] crystal plane (within the x,y plane of FIG. 4), thereby effectively separating the first portion 100a from the second portion 100b in the x-y plane 156. This first portion 100a is the portion of the wafer that includes the active surface having the integrated circuit and is the wafer 100 of the final thickness. The second portion is part of the silicon substrate region 112 that can be discarded. In one example, prior to the horizontal lapping portion of the present technique, the wafer can have a total thickness of 760 μm. In one example, the final thickness of the first portion 100a of the wafer 100 can be 32 μm. Thus, the thickness of the silicon substrate region to be removed can be about 728 μm. These values are for illustrative purposes only and may vary in further embodiments. For example, the thickness of the completed wafer 100 may be 25 μm or less. If the completed wafer 100 is 25 μm, the thickness of the removed portion 100b of the wafer can be about 735 μm.

[0041] FIG. 11 is an edge view showing the removal of the portion 110b of the wafer 100 by the vacuum chuck 158 after the stealth horizontal lapping process of step 212. A portion of the silicon substrate region 112 remains as part of the first portion 100a, hereinafter simply referred to as the wafer 100 again. The separated portion 100b can be discarded. The new second major (back) surface 104 is the surface of the substrate wafer 100 defined by the removal of the portion 100b.

[0042] In an embodiment, after the stealth lapping step 212, the second major surface 104 can undergo a polishing step using, for example, a Z3 polishing wheel that rotates with respect to the back surface. In a further embodiment, the horizontal stealth lapping step 212 may leave the back surface 104 that does not require further polishing.

[0043] Thereafter, the wafer 100 can be diced in step 214. Dicing of the wafer can be performed by a vertical stealth dicing process as shown in FIG. 12. The vertical stealth dicing process can use a laser assembly 160 that includes a laser generator 162 that generates a laser beam 164 and an optical system 166 for focusing the laser beam 164 at a point below the surface of the wafer 100. The vertical laser assembly 160 can form a layer of voids in a vertical plane (orthogonal to planes 102, 104) around the contour of each semiconductor die 106 within the wafer 100. The vertical laser assembly 160 may be structurally and operationally identical to the horizontal laser assembly 140 and may in fact be the same laser assembly rotated from a horizontal orientation to a vertical orientation above the wafer 100. In further embodiments, the vertical laser assembly 160 may be structurally and / or operationally different from the horizontal laser assembly 140.

[0044] At least a portion of the vertical laser assembly 160 is mounted for translational movement over the wafer 100 in the x-y plane. With the wafer 100 still supported on the chuck 134 or other support surface such that the taped first major surface 102 contacts the chuck, the laser assembly 160 can emit a pulsed laser beam 164 that is focused at a point below the surface 104 of the wafer using the optical system 166. When the laser beam hits the peak power density at the focus, the wafer absorbs the energy and a pinpoint hole 170 is created below the surface of the wafer.

[0045] The vertical laser assembly can be moved in rows (along the x-axis) and columns (along the y-axis) in the x-y plane such that a large number of closely positioned pinpoint holes 170 are formed at an intermediate depth of the wafer (between the first major surface 102 and the second major surface 104) and can be activated at a large number of points. The rows and columns of the pinpoint holes 170 define the final shape and contour of each semiconductor die 106 diced from the wafer 100, as shown in FIG. 12. The laser assembly 160 can form a single layer of pinpoint holes 170 or multiple layers of vertically aligned pinpoint holes 170 at multiple depths by adjusting the vertical position of the optical system 166. When one or more layers of pinpoint holes 170 are created, cracks naturally propagate from the holes 170 to the first major surface 102 and the second major surface 104 within the [1,0,1] and [0,1,1] crystal planes, thereby effectively dicing each semiconductor die 106 from the wafer 100. Although a vertical stealth dicing process for dicing the wafer 100 has been described, it is understood that in further embodiments, the wafer 100 can be diced by other techniques including techniques using a dicing blade.

[0046] After the horizontal stealth lasing step 212 and the vertical stealth lasing step 214 are completed, in step 218, a layer of die attach film (DAF) adhered to a flexible dicing tape can be applied to the second major surface 104 of the wafer 100. In further embodiments, the DAF tape and the dicing tape may be applied to the surface 104 before the horizontal stealth lasing step 212 and / or the vertical stealth lasing step 214. In step 220, the wafer is flipped over on a support chuck such that the DAF and the dicing tape face the chuck, and the tape layer 136 laminated on the first major surface 102 can be removed. The flexible dicing tape can be stretched along orthogonal axes in step 224 to separate the individual semiconductor dice 106. Thereafter, in step 226, the individual semiconductor dice 106 can be removed by a pick and place robot.

[0047] FIG. 13 shows a perspective view of semiconductor die 106 as a sample thinned by the horizontal stealth lapping process of the present technology. Die bond pads 116 are shown, but as described above, the number and location of die bond pads 116 are shown by way of example, and in further embodiments, die 106 may include more die bond pads at other locations. Surface 104 (covered by DAF tape 176) is smooth and uniform.

[0048] FIG. 14 is a side view of a completed semiconductor device 180 including semiconductor die 106 thinned by a horizontal stealth lapping process according to an embodiment of the present technology. In the embodiment shown, semiconductor device 180 includes four semiconductor die 106 picked up from wafer 100 and placed into a die stack 182 constructed on top of substrate 184. However, in further embodiments, die stack 182 may include other numbers of semiconductor die 106, including, for example, 2, 8, 16, 32, 64. The die are fixed within die stack 182 and on substrate 184 using DAF layer 176 at the bottom of each die 106. Controller die 186 may be attached to substrate 184, which may be an ASIC in an embodiment, to control the transfer of data between die 106 within stack 182.

[0049] Die 106 may be electrically connected to each other and to substrate 184 using bond wires 188, but in further embodiments, die 106 may be electrically connected to each other and to substrate 184 by other schemes, including, for example, a scheme via silicon vias (TSVs). Die 106 are stacked in a stepped offset from each other to leave space for connection of bond wires 188 to bond pads 116 on each semiconductor die 106 within stack 182. In the embodiment of FIG. 14, all die within stack 182 may be stepped offset in the same direction. In further embodiments, they may be stacked in groups stepped offset in opposite directions.

[0050] Die 106, 186 and bond wire 188 can be encapsulated in a molding compound 190 which can be, for example, an epoxy resin, a phenolic resin, fused silica, crystalline silica, carbon black and / or a metal hydroxide. Other molding compounds are conceivable. In an embodiment, the semiconductor device 180 can be used as a BGA (Ball Grid Array) package soldered to a host device such as a printed circuit board. In such an embodiment, the semiconductor device 180 can further include solder balls 192 on the bottom surface of the substrate 184 to physically and electrically couple the semiconductor device 180 to the host device. In a further embodiment, the semiconductor device 180 may be used as an LGA (Land Grid Array) package configured for insertion into and removal from a slot of a host device. In such an embodiment, the solder balls 192 can be replaced by contact fingers (not shown) on the bottom surface of the substrate 184 for mating with pins within the host device slot. In a further embodiment, it is understood that the semiconductor device 180 may have other configurations.

[0051] As described above, horizontal stealth lapping for thinning the wafer 100 provides several advantages. As described above, horizontal stealth lapping can significantly reduce the manufacturing time in wafer thinning, thereby improving the yield of wafers and dies. Note that, as described in the background art, in a conventional back grinding process, cracks may occur in semiconductor wafers, particularly semiconductor wafers made at a currently thin and fragile thickness. The horizontal stealth dicing according to the present technology eliminates wafer cracking by the back grinding process. By eliminating such cracks, the yield of wafers and dies is improved, and additional screening / inspection steps are not required. It is also known to thin wafers by a vertical stealth lapping process. However, such a process may cause the second major surface to become rough or non-uniform, and as a result, the finished semiconductor die may be weak or cracked. The horizontal stealth lapping process provides a smooth, uniform and strong second major surface 104.

[0052] In addition, in a conventional back grinding process, fragments and foreign matters that may cause cracks or adversely affect the assembly process are generated. By eliminating the back grinding process, the generation of these fragments and foreign matters is prevented, thereby further improving the yield and die quality. Note that the plurality of back grinding wheels required for conventional wafer thinning add a significant amount of time, cost, and complexity to the packaging process. By omitting the back grinding wheel according to the present technology, each of these packaging parameters is improved.

[0053] In summary, an example of the present technology is a semiconductor die, including a first major surface, a plurality of integrated circuits formed on the first major surface of the wafer, and a second major surface facing the first major surface, the second major surface being defined by a plurality of locally generated pinpoint holes by a laser, and a die attach film (DAF) layer covering the second major surface.

[0054] In another example, the present technology relates to a semiconductor wafer including a first major surface, a plurality of semiconductor dies including integrated circuits formed on the first major surface of the wafer, and a second major surface opposite the first major surface, the second major surface being defined by a plurality of locally generated pinpoint holes by a laser.

[0055] In a further example, the present technology is a method of separating semiconductor dies from a wafer including a plurality of semiconductor dies, the wafer including a first major plane, a second major plane, and an outer edge extending between the first major plane and the second major plane, the method including forming an integrated circuit on the first major plane, thinning the wafer by applying one or more laser beams through the outer edge of the wafer, and dicing the semiconductor dies from the thinned wafer.

[0056] The foregoing detailed description of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teachings. The described embodiments were chosen in order to best explain the principles of the invention and its practical application to enable others skilled in the art to best utilize the invention in various embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims appended hereto.

Claims

1. A method for separating semiconductor dies from a wafer including a plurality of semiconductor dies, wherein the wafer includes a first main plane, a second main plane, and an outer edge extending between the first main plane and the second main plane, each die includes a plurality of integrated circuits formed on the first main plane of the wafer, and the method includes: rotating the wafer; emitting a laser beam through the outer edge of the wafer into the interior of the wafer without removing a part of the outer edge; pulsing the laser beam at a distinct point that is at a substrate region where the integrated circuits are formed inside the wafer and at a predetermined radial distance from the center of the wafer; pulsing the laser beam at distinct points that are at the substrate region inside the wafer and at a plurality of other radial distances from the center of the wafer; allowing cracks to propagate between the distinct points at the plurality of radial distances to thin the wafer; dicing the semiconductor dies from the thinned wafer. A method comprising.

2. For the step of thinning the wafer, the method according to claim 1, wherein the wafer is supported by the chuck such that the first main plane faces the chuck.

3. The method according to claim 2, wherein the chuck rotates during the step of thinning the wafer.

4. As the wafer rotates on the chuck, the focus of the laser beam is adjusted to different radial positions of the wafer to generate pinpoint holes at the different radial positions in a plane parallel to the first main plane. The method according to claim 2.

5. The step of thinning the wafer by applying one or more laser beams through the outer edge of the wafer includes the step of generating pinpoint holes from a pair of laser assemblies in a plane parallel to the first major plane of the wafer. The method according to claim 1.

6. The step of dicing the semiconductor die from the thinned wafer includes the step of generating pinpoint holes in a plane perpendicular to the first major plane of the wafer, and cracks propagating between the pinpoint holes to dice the die from the wafer. The method according to claim 1.

7. A method of separating semiconductor dies from a wafer including a plurality of semiconductor dies, the wafer including a first major plane, a second major plane, and an outer edge extending between the first major plane and the second major plane, each die including a plurality of integrated circuits formed in the first major plane of the wafer, the method including rotating the wafer; pulsing a laser beam passing through the outer edge of the wafer as the wafer rotates to form a focus on a substrate region where the integrated circuits are formed inside the wafer, each focus generating a local pinpoint hole around a circle; changing the distance of the focus from the laser generator or the position of the laser generator from the wafer to form a plurality of circles of the local pinpoint holes at different radii; thinning the wafer by cracks propagating between the local pinpoint holes at different radii; dicing the semiconductor die from the thinned wafer. A method including

8. For the step of thinning the wafer, the wafer is supported by the chuck such that the first major plane faces the chuck. The method according to claim 7.

9. The chuck rotates during the step of thinning the wafer. The method according to claim 8. **Claim 10**: The method according to claim 7, wherein the step of thinning the wafer by applying one or more laser beams through the outer edge of the wafer includes the step of generating pinpoint holes from a pair of laser assemblies in a plane parallel to the first major plane of the wafer. **Claim 11**: The method according to claim 7, wherein the step of dicing the semiconductor die from the thinned wafer includes the step of generating pinpoint holes in a plane orthogonal to the first major plane of the wafer and allowing cracks to propagate between the pinpoint holes to dice the die from the wafer.

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