Semiconductor manufacturing apparatus and method of manufacturing semiconductor device

Abstract

To provide a semiconductor manufacturing device capable of suitably processing a substrate to be stuck and a method for manufacturing a semiconductor device.SOLUTION: According to an embodiment, a semiconductor manufacturing device comprises: a modified layer forming unit which forms a modified layer between a first portion and a second portion in a first substrate by partly modifying the first substrate; a peeling layer forming unit which forms a peeling layer between a second substrate provided on a surface of the first substrate and the second portion; and a removal unit which leaves the first portion on the surface of the second substrate and removes the second portion from the surface of the second substrate. The removal unit comprises a heating unit which peels the second substrate and the second portion in the peeling layer by heating the first portion or the second portion and divides the first portion and the second portion, and a movement unit which removes the second portion from the surface of the second substrate while leaving the first portion on the surface of the second substrate by relatively moving the second substrate to the second portion.SELECTED DRAWING: Figure 12

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor manufacturing apparatus and a method for manufacturing a semiconductor device.

Background Art

[0002] When manufacturing a semiconductor device by bonding substrates together, these substrates are often processed, for example, by trimming or grinding. In such cases, it is desirable to process these substrates by a suitable method.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0004] To provide a semiconductor manufacturing apparatus and a method for manufacturing a semiconductor device capable of suitably processing substrates to be bonded.

Means for Solving the Problems

[0005] According to one embodiment, a semiconductor manufacturing apparatus includes a modified layer forming unit configured to partially modify a first substrate to form a modified layer between a first portion and a second portion in the first substrate, a peeling layer forming unit configured to form a peeling layer between a second substrate provided on a surface of the first substrate and the second portion, and a removing unit configured to remove the second portion from a surface of the second substrate while leaving the first portion on the surface of the second substrate. The removing unit includes a heating unit configured to heat the first portion or the second portion to peel the second substrate and the second portion at the peeling layer and to divide the first portion and the second portion, and a moving unit configured to relatively move the second substrate with respect to the second portion to remove the second portion from the surface of the second substrate while leaving the first portion on the surface of the second substrate.

Brief Description of the Drawings

[0006]

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Embodiments for Carrying Out the Invention

[0007] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In FIGS. 1 to 20, the same components are denoted by the same reference numerals, and redundant descriptions are omitted.

[0008] (First Embodiment) FIG. 1 is a plan view showing the structure of the semiconductor manufacturing apparatus according to the first embodiment.

[0009] The semiconductor manufacturing apparatus of this embodiment includes a mounting unit 1, a transfer unit 2, a detection unit 3, a modified layer forming unit 4, a release layer forming unit 5, a removal unit 6, and a control unit 7. The mounting unit 1 includes a plurality of load ports 1a, and the transfer unit 2 includes a transfer robot 2a. The modified layer forming unit 4 includes a chuck table 4a, and the release layer forming unit 5 includes a chuck table 5a.

[0010] FIG. 1 shows the X, Y, and Z directions perpendicular to each other. In this specification, the +Z direction is treated as the upward direction, and the -Z direction is treated as the downward direction. The -Z direction may or may not coincide with the direction of gravity.

[0011] The semiconductor manufacturing apparatus of this embodiment is used to process the wafer W. As will be described later, the wafer W of this embodiment includes a lower wafer and an upper wafer, and has a structure in which these two wafers are bonded together. Further details of the wafer W will be described later.

[0012] The mounting unit 1 is used to mount a FOUP (Front Opening Unified Pod) for accommodating the wafer W. When the wafer W is carried into the housing of the semiconductor manufacturing apparatus, the FOUP containing the wafer W is placed on any one of the load ports 1a, and the wafer W is carried into the housing from the FOUP. On the other hand, the wafer W carried out of the housing is accommodated in the FOUP on any one of the load ports 1a.

[0013] The transfer unit 2 transfers the wafer W in the housing by means of the transfer robot 2a. The detection unit 3 performs notch alignment of the wafer W transferred by the transfer unit 2 and further detects the center of the wafer W. The modification layer forming unit 4 places the wafer W transferred from the detection unit 3 on the chuck table 4a and forms a modification layer in the upper wafer included in the wafer W. The release layer forming unit 5 places the wafer W transferred from the modification layer forming unit 4 on the chuck table 5a and forms a release layer between the upper wafer and the lower wafer in the wafer W. The removal unit 6 partially removes the upper wafer in the wafer W transferred from the release layer forming unit 5. The wafer W that has passed through the detection unit 3, the modification layer forming unit 4, the release layer forming unit 5, and the removal unit 6 is carried out of the housing by the transfer unit 2.

[0014] The control unit 7 controls various operations of the semiconductor manufacturing apparatus of the present embodiment. For example, the control unit 7 controls the transfer robot 2a to transfer the wafer W or controls the chuck tables 4a and 5a to rotate the wafer W.

[0015] Figs. 2 to 11 are cross-sectional views and plan views showing a method for manufacturing a semiconductor device according to the first embodiment.

[0016] The semiconductor device of the present embodiment is manufactured from the wafer W shown in Fig. 1. Also, a part of the method for manufacturing the semiconductor device of the present embodiment is executed using the semiconductor manufacturing apparatus shown in Fig. 1. Therefore, in the following description, the reference numerals shown in Fig. 1 are appropriately used.

[0017] Fig. 2(a) shows the cross-sectional shape of the wafer W, and Fig. 2(b) shows the plan shape of the wafer W. The same applies to Figs. 3(a) to 11(b).

[0018] First, the wafer W shown in Figs. 2(a) and 2(b) is prepared. As described above, the wafer W of the present embodiment includes a lower wafer 10 and an upper wafer 20 and has a structure in which the surface (upper surface) of the lower wafer 10 and the surface (lower surface) of the upper wafer 20 are bonded together. The upper wafer 20 is an example of a first substrate. The lower wafer 10 is an example of a second substrate.

[0019] The lower wafer 10 includes a semiconductor wafer 11, a film 12 formed on the lower surface and side surfaces of the semiconductor wafer 11, and a film 13 formed on the upper surface of the semiconductor wafer 11. The upper wafer 20 includes a semiconductor wafer 21, a film 22 formed on the upper surface and side surfaces of the semiconductor wafer 21, and a film 23 formed on the lower surface of the semiconductor wafer 21. The upper wafer 20 is placed on the lower wafer 10 in such a manner that the film 13 and the film 23 are bonded together.

[0020] Each of the semiconductor wafers 11 and 21 is, for example, a silicon wafer. Each of the films 13 and 23 includes, for example, various insulating films such as an interlayer insulating film, a wiring layer, a plug layer, and a pad layer, a semiconductor layer, and a conductor layer. The films 13 and 23 may include devices such as a memory cell array and transistors. Each of the films 13 and 23 in the present embodiment includes a silicon oxide film at the interface between the film 13 and the film 23, and the silicon oxide film in the film 13 and the silicon oxide film in the film 23 are bonded together.

[0021] FIG. 2(a) and FIG. 2(b) show the center C of the upper wafer 20, a central portion 20a which is a portion on the center C side within the upper wafer 20, and an outer peripheral portion 20b which is a portion on the side opposite to the center C within the upper wafer 20. The center of the lower wafer 10 is located substantially directly below (-Z direction) the center C of the upper wafer 20. In the method for manufacturing a semiconductor device according to the present embodiment, the outer peripheral portion 20b of the upper wafer 20 is removed from the wafer W by a process described later. The central portion 20a is an example of the first portion, and the outer peripheral portion 20b is an example of the second portion.

[0022] Next, the wafer W is annealed (FIGS. 3(a) and 3(b)). As a result, the lower surface of the film 23 is joined to the upper surface of the film 13, and a joining layer 26 is formed in the vicinity of the interface between the film 13 and the film 23 within the films 13 and 23. In this way, the lower wafer 10 and the upper wafer 20 are joined by the joining layer 26.

[0023] Next, the upper wafer 20 is partially modified to form a modified layer 24 between the central portion 20a and the outer peripheral portion 20b in the upper wafer 20 (FIGS. 4(a) and 4(b)). FIG. 4(a) shows an emitting portion P1 provided in the modified layer forming portion 4 and emitting a laser L1. The modified layer 24 of the present embodiment is formed by irradiating the upper wafer 20 with the laser L1, and specifically, is formed at the location irradiated with the laser L1. In the present embodiment, the location irradiated with the laser L1 is amorphized. For example, monosilicon in the semiconductor wafer 21 changes to amorphous silicon. Therefore, an amorphous layer is formed as the modified layer 24.

[0024] As shown in FIG. 4(a), the modified layer 24 of the present embodiment is formed to extend in the -Z direction within the upper wafer 20 and penetrate the upper wafer 20. Further, as shown in FIG. 4(b), the modified layer 24 of the present embodiment is formed within the upper wafer 20 so as to have an annular planar shape. Therefore, the central portion 20a shown in FIG. 4(b), that is, the inner portion of the modified layer 24 in the upper wafer 20 has a circular planar shape. On the other hand, the outer peripheral portion 20b shown in FIG. 4(b), that is, the outer portion of the modified layer 24 in the upper wafer 20 has an annular planar shape and surrounds the central portion 20a annularly. The modified layer 24 is formed, for example, by placing the wafer W on the chuck table 4a and irradiating the wafer W with the laser L1 while rotating the chuck table 4a. The wavelength of the laser L1 is desirably set to a value that is not absorbed by the semiconductor wafer 21, and is set to, for example, 1117 nm or more.

[0025] Note that the modified layer 24 may be formed to have a shape different from those shown in FIGS. 4(a) and 4(b). For example, the modified layer 24 may be formed such that the planar shape of the central portion 20a is a shape other than circular. Further, when the planar shape of the central portion 20a is circular, the value of the diameter of the central portion 20a may be set to any value according to the size of the outer peripheral portion 20b to be removed from the wafer W. For example, the size of the semiconductor wafer 21 within the outer peripheral portion 20b may be larger or smaller than the size of the bevel portion of the semiconductor wafer 21. In this case, the distance between the innermost circumference and the outermost circumference of the outer peripheral portion 20b is, for example, 1 to 6 mm. Also, although the modified layer 24 is formed after the upper wafer 20 and the lower wafer 10 are bonded in the present embodiment, it may be formed before these are bonded instead.

[0026] Next, a release layer 25 for separating the lower wafer 10 and the outer peripheral portion 20b is formed between the lower wafer 10 and the outer peripheral portion 20b (FIGS. 5(a) and 5(b)). FIG. 5(a) shows an emitting portion P2 provided within the release layer forming portion 5 and emitting a laser L2. The release layer 25 of the present embodiment is formed by irradiating the films 13 and 23 with the laser L2, and specifically, is formed at the location irradiated with the laser L2. The release layer 25 of the present embodiment is formed by the laser L2 being absorbed by the films 13 and 23. Therefore, it is desirable that the interface of the films 13 and 23 of the present embodiment be formed of a material that absorbs the laser L2. An example of such a material is a silicon oxide film. The wavelength of the laser L2 is desirably set to a value that is absorbed by the films 13 and 23.

[0027] As shown in FIG. 5(a), the release layer 25 of the present embodiment is formed near the interface between the film 13 and the film 23 within the films 13 and 23. Further, as shown in FIG. 5(b), the release layer 25 of the present embodiment is formed to have an annular planar shape. Since the release layer 25 is formed between the lower wafer 10 and the outer peripheral portion 20b, it is formed on the side opposite to the center C with respect to the modified layer 24. The release layer 25 of the present embodiment is formed near the modified layer 24. Further, the release layer 25 of the present embodiment is formed only within the outer peripheral portion 20b among the central portion 20a and the outer peripheral portion 20b. Thereby, the outer peripheral portion 20b is easily peeled off from the lower wafer 10. The release layer 25 is formed, for example, by placing the wafer W on the chuck table 5a and irradiating the wafer W with the laser L2 while rotating the chuck table 5a.

[0028] Note that the release layer 25 may be formed to have a shape different from the shapes shown in FIGS. 5(a) and 5(b). Further, although the release layer 25 is formed after the modified layer 24 is formed in the present embodiment, it may be formed before the modified layer 24 is formed instead. Further, when the film 13 includes a laminated film including a plurality of layers, the release layer 25 may be formed between any two layers within this laminated film. Similarly, when the film 23 includes a laminated film including a plurality of layers, the release layer 25 may be formed between any two layers within this laminated film.

[0029] The annealing shown in FIGS. 3(a) and 3(b) may be performed such that only the inner peripheral portion 20a among the central portion 20a and the outer peripheral portion 20b is annealed. In this case, the bonding layer 26 is formed near the interface between the film 13 and the film 23 within the central portion 20a, but the bonding layer 26 is not formed near the interface between the film 13 and the film 23 within the outer peripheral portion 20b. Therefore, the outer peripheral portion 20b is easily peeled off from the lower wafer 10 even after annealing. Thus, in this case, the steps shown in FIGS. 5(a) and 5(b) may be omitted.

[0030] Next, the orientation of the wafer W is reversed (FIGS. 6(a) and 6(b)). As a result, the wafer W shown in FIG. 6(a) includes the upper wafer 20 on the lower side within the wafer W and the lower wafer 10 on the upper side within the wafer W. The removal unit 6 of the present embodiment includes a reversing unit (not shown), and the reversing unit reverses the orientation of the wafer W conveyed from the release layer forming unit 5 to the removal unit 6.

[0031] Next, the wafer W is held by adsorbing the wafer W with the upper vacuum chuck 31 in the removal unit 6 (FIGS. 7(a) and 7(b)). The upper vacuum chuck 31 can hold the lower wafer 10 by adsorption by contacting the lower wafer 10 from above the lower wafer 10. The upper vacuum chuck 31 can further move the lower wafer 10 held by adsorption. Further, since the lower wafer 10 is bonded to the upper wafer 20, the upper vacuum chuck 31 can move the upper wafer 20 together with the lower wafer 10. The upper vacuum chuck 31 is an example of the first holding unit of the moving unit.

[0032] The upper vacuum chuck 31 includes a vacuum groove 31a, and holds the lower wafer 10 by the adsorption force from the vacuum groove 31a. The upper vacuum chuck 31 may further include a cooling mechanism for cooling the lower wafer 10. Thereby, the lower wafer 10 held by the upper vacuum chuck 31 can be cooled by the cooling mechanism. The cooling mechanism cools the lower wafer 10 using a cooling fluid such as liquid nitrogen, for example. The cooling mechanism may indirectly cool the upper wafer 20 by cooling the lower wafer 10.

[0033] Next, the upper vacuum chuck 31 moves the wafer W and places the wafer W on the central vacuum chuck 32 and the outer peripheral vacuum chuck 33 (FIGS. 8(a) and 8(b)). The removing unit 6 includes one upper vacuum chuck 31 for holding the lower wafer 10 and two lower vacuum chucks (the central vacuum chuck 32 and the outer peripheral vacuum chuck 33) for holding the upper wafer 20. The central vacuum chuck 32 can hold the central portion 20a by suction by contacting the central portion 20a. The outer peripheral vacuum chuck 33 can hold the outer peripheral portion 20b by suction by contacting the outer peripheral portion 20b. The central vacuum chuck 32 is an example of the second holding portion of the moving unit. The outer peripheral vacuum chuck 33 is an example of the third holding portion of the moving unit.

[0034] The central vacuum chuck 32 includes a vacuum groove 32a and holds the central portion 20a by the suction force from the vacuum groove 32a. The central vacuum chuck 32 may further include a cooling mechanism for cooling the central portion 20a. Thereby, the central portion 20a held by the central vacuum chuck 32 can be cooled by the cooling mechanism. The cooling mechanism cools the central portion 20a using a cooling fluid such as liquid nitrogen, for example. The cooling mechanism may indirectly cool the lower wafer 10 by cooling the central portion 20a.

[0035] The outer peripheral vacuum chuck 33 has a vacuum groove 33a and holds the outer peripheral portion 20b by the suction force from the vacuum groove 33a. The outer peripheral vacuum chuck 33 further includes a heating portion 33b that heats the outer peripheral portion 20b. Thereby, it becomes possible to heat the outer peripheral portion 20b held by the outer peripheral vacuum chuck 33 by the heating portion 33b. In the present embodiment, before placing the wafer W on the outer peripheral vacuum chuck 33, the temperature of the heating portion 33b is set to a high temperature in advance. Therefore, when the wafer W is placed on the outer peripheral vacuum chuck 33, the outer peripheral portion 20b is rapidly heated by the heating portion 33b, and the temperature of the outer peripheral portion 20b rises rapidly. The outer peripheral portion 20b of the present embodiment is placed on the heating portion 33b as shown in FIG. 8(a). The upper surface of the heating portion 33b of the present embodiment is inclined with respect to the XY plane in order to easily hold the outer peripheral portion 20b and to easily contact the outer peripheral portion 20b.

[0036] In the present embodiment, by heating the outer peripheral portion 20b and cooling the central portion 20a, a temperature difference is generated between the outer peripheral portion 20b and the central portion 20a. As a result, a thermal stress is generated between the outer peripheral portion 20b and the central portion 20a, and cracks progress in the modified layer 24. Thereby, it becomes possible to divide the outer peripheral portion 20b and the central portion 20a. In addition, since the wafer W of the present embodiment has a release layer 25 between the outer peripheral portion 20b and the lower wafer 10, the outer peripheral portion 20b is easily peeled off from the lower wafer 10. Therefore, according to the present embodiment, it is possible to divide the outer peripheral portion 20b and the central portion 20a by thermal stress and to peel the outer peripheral portion 20b and the lower wafer 10 at the release layer 25 (FIGS. 9(a) and 9(b)).

[0037] The removal unit 6 of the present embodiment heats the outer peripheral portion 20b with the heating unit 33b so that the temperature of the outer peripheral portion 20b becomes higher than the temperature of the central portion 20a, and cools the central portion 20a and the lower wafer 10 with the cooling mechanism. It is desirable to perform these heating and cooling so that the temperature difference between the outer peripheral portion 20b and the central portion 20a is 200 to 400°C. Thereby, the difference in the amount of expansion and contraction between the outer peripheral portion 20b and the central portion 20a can be made sufficiently large, and sufficient thermal stress can be generated between the outer peripheral portion 20b and the central portion 20a. For example, when the semiconductor wafer 21 is a silicon substrate, the difference in the amount of expansion and contraction between the outer peripheral portion 20b and the central portion 20a is about 0.2 to 0.5 mm due to a temperature difference of 200 to 400°C.

[0038] Note that the temperature difference between the outer peripheral portion 20b and the central portion 20a may be generated by heating with the heating unit 33b and cooling with the cooling mechanism, or may be generated only by heating with the heating unit 33b. The former method has, for example, the advantage that it is not necessary to make the temperature of the outer peripheral portion 20b extremely high. The latter method has, for example, the advantage that the cooling mechanism becomes unnecessary for the removal unit 6. When the latter method is adopted, the temperature of the central portion 20a that is not cooled becomes room temperature. Similarly, the temperature of the lower wafer 10 that is not cooled also becomes room temperature. Further, the temperature difference between the outer peripheral portion 20b and the central portion 20a may be realized by heating only the central portion 20a, or may be realized by heating the central portion 20a and cooling the outer peripheral portion 20b.

[0039] After that, the removal unit 6 of the present embodiment raises the upper vacuum chuck 31, the central vacuum chuck 32, and the outer peripheral vacuum chuck 33 in the upward direction (+Z direction) while the lower wafer 10, the central portion 20a, and the outer peripheral portion 20b are held by suction (Figs. 9(a) and 9(b)). That is, the upper vacuum chuck 31 and the central vacuum chuck 32 are relatively moved with respect to the outer peripheral vacuum chuck 33. As a result, the lower wafer 10 and the central portion 20a rise while being sandwiched between the upper vacuum chuck 31 and the central vacuum chuck 32, and are separated from the outer peripheral portion 20b. Thereby, it becomes possible to remove the outer peripheral portion 20b from the surface of the upper wafer 10 while leaving the central portion 20a on the surface of the upper wafer 10. In other words, it becomes possible to trim the wafer W so that the outer peripheral portion 20b is removed.

[0040] For the outer peripheral vacuum chuck 33 to adsorb the outer peripheral portion 20b, for example, there are advantages such as making it easier to separate the lower wafer 10 and the central portion 20a from the outer peripheral portion 20b, and preventing the separated outer peripheral portion 20b from falling from the outer peripheral vacuum chuck 33 and cracking. Also, cooling the lower wafer 10 has effects such as suppressing the above-mentioned crack from progressing to the lower wafer 10 and advantages such as suppressing the peeling between the lower wafer 10 and the central portion 20a.

[0041] In the present embodiment, the modified layer 24 extends parallel to the Z direction, but may be inclined with respect to the Z direction. For example, the modified layer 24 may be inclined with respect to the Z direction such that the diameter of the central portion 20a is larger on the side of the film 23 and smaller on the opposite side of the film 23. Thereby, the central portion 20a having a circular planar shape can easily pass through the outer peripheral portion 20b having an annular planar shape, and it becomes easier to separate the central portion 20a from the outer peripheral portion 20b. In this case, the outer peripheral surface of the central portion 20a and the inner peripheral surface of the outer peripheral portion 20b become tapered surfaces.

[0042] Next, reverse the orientation of the wafer W again (Figs. 10(a) and 10(b)). As a result, the wafer W shown in Fig. 10(a) includes the lower wafer 10 on the lower side within the wafer W and the upper wafer 20 (central portion 20a) on the upper side within the wafer W. In the removal section 6 of the present embodiment, the above-described reversing section reverses the orientation of the wafer W after trimming.

[0043] Thereafter, the wafer W of the present embodiment is carried out of the housing of the semiconductor manufacturing apparatus by the transfer robot 2a. Also, the outer peripheral portion 20b removed from the wafer W is carried out of the housing by the transfer robot 2a. The transfer robot 2a is an example of a transfer mechanism. In general trimming, the outer peripheral portion 20b is removed by cutting the outer peripheral portion 20b, so the outer peripheral portion 20b becomes a large amount of powder and is removed from the wafer W. On the other hand, in the trimming of the present embodiment, the outer peripheral portion 20b is removed by dividing the outer peripheral portion 20b from the central portion 20a and peeling it off from the lower wafer 10, so the outer peripheral portion 20b is removed from the wafer W without becoming a large amount of powder. Therefore, according to the present embodiment, the outer peripheral portion 20b can be easily carried out of the housing by the transfer robot 2a, and the labor of removing a large amount of powder from the housing can be suppressed. Note that the semiconductor manufacturing apparatus of the present embodiment may carry the outer peripheral portion 20b out of the housing by a transfer mechanism other than the transfer robot 2a. The outer peripheral portion 20b is collected, for example, in a FOUP.

[0044] Next, grind the upper surface of the upper wafer 20 with the grinder P3 (Figs. 11(a) and 11(b)). As a result, the upper wafer 20 is thinned. Note that the steps shown in Figs. 11(a) and 11(b) are performed by an apparatus other than the semiconductor manufacturing apparatus of the present embodiment.

[0045] Thereafter, the wafer W is processed by various processes. In this way, the semiconductor device of the present embodiment is manufactured. The semiconductor device of the present embodiment is, for example, a three-dimensional semiconductor memory.

[0046] FIG. 12 is a cross-sectional view and a plan view showing the structure of the semiconductor manufacturing apparatus according to the first embodiment. Specifically, FIGS. 12(a) and 12(b) are a cross-sectional view and a plan view showing the structure of the removal unit 6 in the semiconductor manufacturing apparatus of the present embodiment, respectively.

[0047] As shown in FIG. 12(a), the removal unit 6 of the present embodiment includes the aforementioned upper vacuum chuck 31, central vacuum chuck 32, and outer peripheral vacuum chuck 33. The upper vacuum chuck 31 includes a vacuum groove 31a. The central vacuum chuck 32 includes a vacuum groove 32a. The outer peripheral vacuum chuck 33 includes a vacuum groove 33a and a heating unit 33b. FIG. 12(a) shows the wafer W in the steps shown in FIGS. 8(a) and 8(b). FIG. 12(a) further shows the above-described cooling mechanism provided in the upper vacuum chuck 31 by reference numeral C1, and the above-described cooling mechanism provided in the central vacuum chuck 32 by reference numeral C2.

[0048] The central vacuum chuck 32 and the outer peripheral vacuum chuck 33 are separated from each other with a gap G therebetween. The gap G of the present embodiment is filled with air. This makes it possible to improve the heat insulation between the central vacuum chuck 32 and the outer peripheral vacuum chuck 33. On the other hand, the removal unit 6 may include some member (for example, a heat insulating material) in the gap G.

[0049] FIG. 12(b) shows the planar shape of the central vacuum chuck 32 by cross-hatching, the planar shape of the outer peripheral vacuum chuck 33 by dot-hatching, and the planar shape of the gap G by white. FIG. 12(b) further shows the positions of the vacuum grooves 32a and 33a by thick solid lines, and the contour of the wafer W by a broken line.

[0050] As shown in FIG. 12(b), the central vacuum chuck 32 has a circular shape in plan view so as to easily hold the central portion 20a. On the other hand, the outer peripheral vacuum chuck 33 has an annular shape in plan view so as to easily hold the outer peripheral portion 20b, and surrounds the central portion 20a in an annular shape. Further, the vacuum groove 32a extends along a circle inside the central vacuum chuck 32, and the vacuum groove 33a extends along a circle inside the outer peripheral vacuum chuck 33. The same applies to the vacuum groove 31a. The vacuum groove 31a extends along a circle inside the upper vacuum chuck 31 (FIG. 12(a)).

[0051] FIG. 13 is a plan view showing the structure of the outer peripheral vacuum chuck 33 of the first embodiment.

[0052] Similar to FIG. 12(b), FIG. 13 shows the planar shape of the outer peripheral vacuum chuck 33 by dot hatching. FIG. 13 further shows the position of the vacuum groove 33a by a thick solid line and the contour of the heating portion 33b by a broken line. The heating portion 33b of the present embodiment has an annular shape in plan view so as to easily heat the outer peripheral portion 20b. Thereby, it becomes possible to rapidly heat the entire outer peripheral portion 20b.

[0053] Next, the manufacturing method of the semiconductor device of the present embodiment is compared with the manufacturing methods of the semiconductor devices of the first comparative example and the second comparative example.

[0054] (1) First Comparative Example FIGS. 14 to 16 are cross-sectional views showing the manufacturing method of the semiconductor device of the first comparative example of the first embodiment. In this comparative example, the upper wafer 20 is trimmed before bonding the lower wafer 10 and the upper wafer 20 together.

[0055] First, prepare the upper wafer 20 shown in FIG. 14(a), and trim the upper wafer 20 as shown in FIG. 14(b). FIG. 14(b) shows the trimming portion T1 of the upper wafer 20. Next, polish the film 23 in the upper wafer 20 using a CMP (Chemical Mechanical Polishing) apparatus P4 (FIG. 15(a)), and then bond the upper wafer 20 to the lower wafer 10 (FIG. 15(b)). Next, by annealing the wafer W, the lower surface of the film 23 is joined to the upper surface of the film 13 (FIG. 16(a)). Next, thin the upper wafer 20 by grinding the upper surface of the upper wafer 20 with a grinder P3 (FIG. 16(b)). At this time, the portion on the trimming portion T1 in the upper wafer 20 becomes the end material 20c.

[0056] In this comparative example, when the upper wafer 20 is trimmed in the process of FIG. 14(b), the trimming portion T1 becomes a large amount of powder. Also, in this comparative example, when the film 23 is polished in the process of FIG. 15(a), the edge of the film 23 may be over-polished. However, if the film 23 is not polished, the influence of trimming may remain in the film 23. Also, in this comparative example, a troublesome process for recovering the end material 20c is required. On the other hand, according to the present embodiment, these problems can be suppressed.

[0057] (2) Second Comparative Example FIGS. 17 and 18 are cross-sectional views showing a method of manufacturing a semiconductor device according to a second comparative example of the first embodiment. In this comparative example, after the lower wafer 10 and the upper wafer 20 are bonded together, the upper wafer 20 is trimmed.

[0058] First, bond the upper wafer 20 to the lower wafer 10 (FIG. 17(a)). Next, by annealing the wafer W, the lower surface of the film 23 is joined to the upper surface of the film 13 (FIG. 17(b)). Next, trim the upper wafer 20 with a blade P5 (FIG. 18(a)). FIG. 18(a) shows the trimming portion T2 of the upper wafer 20. Next, thin the upper wafer 20 by grinding the upper surface of the upper wafer 20 with a grinder P3 (FIG. 18(b)).

[0059] In this comparative example, when trimming the upper wafer 20 in the process of Fig. 18(a), the trimming portion T2 becomes a large amount of powder. Further, in this comparative example, when trimming the upper wafer 20 in the process of Fig. 18(a), there is a possibility that not only the upper wafer 20 but also the lower wafer 10 may be trimmed. On the other hand, according to the present embodiment, these problems can be suppressed.

[0060] In the trimming of the wafer W of the present embodiment, a modified layer 24 and a peeling layer 25 are formed in the wafer W, and the outer peripheral portion 20b in the wafer W is heated (see Figs. 8(a) and 8(b)). Thereby, the outer peripheral portion 20b is divided from the central portion 20a, and the outer peripheral portion 20b is peeled from the lower wafer 10, so that the outer peripheral portion 20b can be removed from the wafer W (see Figs. 9(a) and 9(b)). Therefore, according to the present embodiment, as described above, it is possible to remove the outer peripheral portion 20b from the wafer W without turning it into a large amount of powder.

[0061] On the other hand, it is conceivable that the trimming of the wafer W is performed by inserting a blade between the lower wafer 10 and the upper wafer 20 instead of heating the outer peripheral portion 20b in the wafer W. That is, it is conceivable that the trimming of the wafer W is realized by mechanical force applied from the blade instead of thermal stress generated by heating. According to the trimming by the blade, it is possible to remove the outer peripheral portion 20b from the wafer W without turning it into a large amount of powder, similar to the trimming by thermal stress. However, according to the trimming by the blade, if the blade is not properly operated, there is a possibility that the peeling between the lower wafer 10 and the upper wafer 20 may progress to the central portion 20a, or excessive force may be applied to the wafer W and chipping may occur. According to the present embodiment, these problems can also be suppressed.

[0062] As described above, in the present embodiment, by heating the wafer W, the outer peripheral portion 20b is separated from the central portion 20a and the outer peripheral portion 20b is peeled off from the lower wafer 10. Therefore, according to the present embodiment, it is possible to suitably process the wafer W, for example, it becomes possible to easily remove the outer peripheral portion 20b from the wafer W without turning it into a large amount of powder.

[0063] (Second Embodiment) FIG. 19 is a cross-sectional view and a plan view showing the structure of the semiconductor manufacturing apparatus of the second embodiment.

[0064] The semiconductor manufacturing apparatus of the present embodiment has the structure shown in FIG. 1 and is used to execute a part of the methods shown in FIGS. 2(a) to 11(b), similar to the semiconductor manufacturing apparatus of the first embodiment. On the other hand, the removal unit 6 of the semiconductor manufacturing apparatus of the first embodiment has the structure shown in FIGS. 12(a) and 12(b), while the removal unit 6 of the semiconductor manufacturing apparatus of the present embodiment has the structure shown in FIGS. 19(a) and 19(b). FIGS. 19(a) and 19(b) are a cross-sectional view and a plan view showing the structure of the removal unit 6 of the present embodiment, respectively.

[0065] The removal unit 6 of the present embodiment is different from the removal unit 6 of the first embodiment in the following two points. First, the upper vacuum chuck 31 of the present embodiment is provided with a rotation shaft 31b for rotating the upper vacuum chuck 31. The removal unit 6 of the present embodiment can rotate the wafer W held by the upper vacuum chuck 31 by rotating the upper vacuum chuck 31. Second, the outer peripheral vacuum chuck 33 of the present embodiment is provided with a plurality of heating units 33b described later. The removal unit 6 of the present embodiment can heat the outer peripheral portion 20b by these heating units 33b while rotating the wafer W by the rotation shaft 31b.

[0066] FIG. 20 is a plan view showing the structure of the outer peripheral vacuum chuck 33 of the second embodiment.

[0067] As shown in FIG. 20, the outer peripheral vacuum chuck 33 of the present embodiment includes a plurality of heating portions 33b. The number of the heating portions 33b is four in the present embodiment, but may be other than four. Further, the planar shape of each heating portion 33b is a quadrangle in the present embodiment, but may be other shapes. For example, the outer peripheral vacuum chuck 33 may include a plurality of heating portions 33b having an arcuate (sector-shaped) planar shape, or may include only one heating portion 33b having an arcuate (sector-shaped) planar shape.

[0068] If the outer peripheral portion 20b is heated without rotating the wafer W of the present embodiment, unevenness in temperature is likely to occur in the outer peripheral portion 20b. For example, in the outer peripheral portion 20b, the temperature of a location close to any one of the heating portions 33b is likely to be high. On the other hand, in the outer peripheral portion 20b, the temperature of a location far from any of the heating portions 33b is likely to be low. However, since the wafer W of the present embodiment is heated while being rotated, it is possible to suppress the occurrence of temperature unevenness in the outer peripheral portion 20b.

[0069] Note that the embodiment of the present invention may be implemented in the following manner.

[0070] (Appendix 1) A modified layer forming portion that partially modifies the first substrate to form a modified layer between a first portion and a second portion in the first substrate, A peeling layer forming portion that forms a peeling layer between a second substrate provided on the surface of the first substrate and the second portion, A removing portion that removes the second portion from the surface of the second substrate while leaving the first portion on the surface of the second substrate, The removing portion includes A heating portion that heats the first portion or the second portion to peel the second substrate and the second portion at the peeling layer and divide the first portion and the second portion, A moving portion that relatively moves the second substrate with respect to the second portion to remove the second portion from the surface of the second substrate while leaving the first portion on the surface of the second substrate, A semiconductor manufacturing apparatus comprising the same.

[0071] (Appendix 2) The semiconductor manufacturing apparatus according to Appendix 1, wherein the second part has a shape that annularly surrounds the first part.

[0072] (Appendix 3) The semiconductor manufacturing apparatus according to Appendix 1 or 2, wherein the modified layer forming part forms an amorphous layer as the modified layer by partially amorphizing the first substrate.

[0073] (Appendix 4) The semiconductor manufacturing apparatus according to any one of Appendices 1 to 3, wherein the modified layer forming part partially modifies the first substrate by a laser.

[0074] (Appendix 5) The semiconductor manufacturing apparatus according to any one of Appendices 1 to 4, wherein the peeling layer is formed only in the second part of the first part and the second part.

[0075] (Appendix 6) The semiconductor manufacturing apparatus according to any one of Appendices 1 to 5, wherein the peeling layer forming part forms the peeling layer by a laser.

[0076] (Appendix 7) The semiconductor manufacturing apparatus according to any one of Appendices 1 to 6, wherein the heating part heats the first part or the second part so that the temperature of the second part becomes higher than the temperature of the first part.

[0077] (Appendix 8) The semiconductor manufacturing apparatus according to any one of Appendices 1 to 7, wherein the heating part heats the first part or the second part so that the difference between the temperature of the first part and the temperature of the second part becomes 200 to 400 °C.

[0078] (Appendix 9) The semiconductor manufacturing apparatus according to any one of Appendices 1 to 8, wherein the heating part has an annular shape in plan view.

[0079] (Appendix 10) The removing unit rotates the first substrate and the second substrate, and heats the first portion or the second portion with the heating unit. The semiconductor manufacturing apparatus according to any one of Appendices 1 to 8.

[0080] (Appendix 11) The moving unit includes a first holding unit that holds the second substrate, a second holding unit that holds the first portion, and a third holding unit that holds the second portion. The semiconductor manufacturing apparatus according to any one of Appendices 1 to 10.

[0081] (Appendix 12) The first holding unit includes a mechanism for cooling the second substrate. The semiconductor manufacturing apparatus according to Appendix 11.

[0082] (Appendix 13) The second holding unit includes a mechanism for cooling the first portion. The semiconductor manufacturing apparatus according to Appendix 11 or 12.

[0083] (Appendix 14) The third holding unit includes the heating unit that heats the second portion. The semiconductor manufacturing apparatus according to any one of Appendices 11 to 13.

[0084] (Appendix 15) The third holding unit has an annular shape that surrounds the second holding unit. The semiconductor manufacturing apparatus according to any one of Appendices 11 to 14.

[0085] (Appendix 16) The semiconductor manufacturing apparatus according to any one of Appendices 1 to 15 further includes a transfer mechanism for transferring the second portion peeled off from the second substrate.

[0086] (Appendix 17) A heating unit that divides the first portion and the second portion by heating the first portion or the second portion in the first substrate provided on the surface of the second substrate, and A moving unit that relatively moves the second substrate with respect to the second portion to remove the second portion from the surface of the second substrate while leaving the first portion on the surface of the second substrate. A semiconductor manufacturing apparatus comprising the same.

[0087] (Appendix 18) The semiconductor manufacturing apparatus according to Appendix 17, further comprising a reforming layer forming unit that partially reforms the first substrate to form a reforming layer between the first portion and the second portion in the first substrate. After the formation of the reforming layer, the heating unit heats the first portion or the second portion.

[0088] (Appendix 19) The semiconductor manufacturing apparatus according to Appendix 17 or 18, further comprising a peeling layer forming unit that forms a peeling layer between the second substrate and the second portion. By heating the first portion or the second portion, the heating unit peels the second substrate and the second portion at the peeling layer and divides the first portion and the second portion.

[0089] (Appendix 20) Partially reform the first substrate to form a reforming layer between the first portion and the second portion in the first substrate. Form a peeling layer between the second substrate provided on the surface of the first substrate and the second portion. By heating the first portion or the second portion, peel the second substrate and the second portion at the peeling layer and divide the first portion and the second portion. By relatively moving the second substrate with respect to the second portion, remove the second portion from the surface of the second substrate while leaving the first portion on the surface of the second substrate. A method for manufacturing a semiconductor device including the above.

[0090] Although several embodiments have been described above, these embodiments are presented only as examples and are not intended to limit the scope of the invention. The novel devices and methods described in this specification can be implemented in various other forms. Also, various omissions, substitutions, and changes can be made to the forms of the devices and methods described in this specification without departing from the gist of the invention. The appended claims and their equivalents are intended to include such forms and modifications within the scope and gist of the invention.

Explanation of Reference Numerals

[0091] 1: Mounting portion, 1a: Load port, 2: Conveying portion, 2a: Conveying robot, 3: Detection portion, 4: Modified layer forming portion, 4a: Chuck table, 5: Release layer forming portion, 5a: Chuck table, 6: Removal portion, 7: Control portion, 10: Lower wafer, 11: Semiconductor wafer, 12: Film, 13: Film, 20: Upper wafer, 20a: Central portion, 20b: Outer peripheral portion, 20c: End material, 21: Semiconductor wafer, 22: Film, 23: Film, 24: Modified layer, 25: Release layer, 26: Bonding layer, 31: Upper vacuum chuck, 31a: Vacuum groove, 31b: Rotation axis, 32: Central vacuum chuck, 32a: Vacuum groove, 33: Outer peripheral vacuum chuck, 33a: Vacuum groove, 33b: Heating portion

Claims

1. A modified layer forming unit that partially modifies a first substrate to form a modified layer between a first portion and a second portion within the first substrate; A peeling layer forming unit that forms a peeling layer between a second substrate provided on the surface of the first substrate and the second portion; An removing unit that removes the second portion from the surface of the second substrate while leaving the first portion on the surface of the second substrate; The removing unit includes: A heating unit that heats the first portion or the second portion to peel the second substrate and the second portion at the peeling layer and to divide the first portion and the second portion; A moving unit that relatively moves the second substrate and the first portion with respect to the second portion by raising the second substrate and the first portion, thereby removing the second portion from the surface of the second substrate while leaving the first portion on the surface of the second substrate; A semiconductor manufacturing apparatus comprising the above.

2. The semiconductor manufacturing apparatus according to claim 1, wherein the heating unit heats the first portion or the second portion such that the temperature of the second portion becomes higher than the temperature of the first portion.

3. The semiconductor manufacturing apparatus according to claim 1 or 2, wherein the removing unit heats the first portion or the second portion by the heating unit while rotating the first substrate and the second substrate.

4. The semiconductor manufacturing apparatus according to any one of claims 1 to 3, wherein the moving unit includes a first holding unit that holds the second substrate, a second holding unit that holds the first portion, and a third holding unit that holds the second portion.

5. The semiconductor manufacturing apparatus according to any one of claims 1 to 4, wherein the moving unit removes the second portion from the surface of the second substrate in a state where the second portion has an annular shape.

6. The semiconductor manufacturing apparatus according to any one of claims 1 to 5, wherein the peeling layer is formed only in the second portion among the first portion and the second portion.

7. The semiconductor manufacturing apparatus according to any one of claims 1 to 6, wherein the peeling layer forming unit forms the peeling layer by laser.

8. A modified layer forming unit that partially modifies a first substrate provided on the surface of a second substrate to form a modified layer between a first portion and a second portion in the first substrate; A heating unit that divides the first portion and the second portion by heating the first portion or the second portion after the formation of the modified layer; A moving unit that relatively moves the second substrate and the first portion with respect to the second portion by raising the second substrate and the first portion, leaving the first portion on the surface of the second substrate while removing the second portion from the surface of the second substrate; A semiconductor manufacturing apparatus comprising:

9. Partially modify a first substrate to form a modified layer between a first portion and a second portion in the first substrate, Form a peeling layer between the second substrate provided on the surface of the first substrate and the second portion, By heating the first portion or the second portion, peeling the second substrate and the second portion at the peeling layer and dividing the first portion and the second portion, By raising the second substrate and the first portion, relatively moving the second substrate and the first portion with respect to the second portion, leaving the first portion on the surface of the second substrate while removing the second portion from the surface of the second substrate, A method for manufacturing a semiconductor device including:

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