Multi-time programmable memory device and method

Abstract

To provide a device that includes a memory cell including a reversible resistive switching memory element coupled in series with a selector element.SOLUTION: A memory cell 222a is selectively configured as either a rewritable memory cell or a multi-time programmable memory cell. A magnetic memory element Mx is a magnetic tunnel junction and a selector element Sx is a threshold value selector device. The selector element Sx is a conductive bridge threshold value selector device. The magnetic memory element Mx includes an upper ferromagnetic layer 230, a lower ferromagnetic layer 232, and a tunnel barrier (TB) 234, which is an insulation layer between the two ferromagnetic layers. The lower ferromagnetic layer is a free layer (FL) having a magnetization direction that can be switched, and the upper ferromagnetic layer is a pin or a fixed layer (PL) having a magnetization direction that cannot be easily changed.SELECTED DRAWING: Figure 2B

Description

Technical Field

[0001] (Claim of Priority) This application claims the priority of U.S. Provisional Patent Application No. 63 / 500,688, filed on May 8, 2023, entitled "MULTI-TIME PROGRAMMABLE MEMORY DEVICES AND METHODS", the entire content of which is incorporated herein by reference.

Background Art

[0002] Memory is widely used in various electronic devices such as mobile phones, digital cameras, personal digital assistants, medical electronic devices, mobile computing devices, non-mobile computing devices, and data servers. Memory can be non-volatile memory or volatile memory. Non-volatile memory enables the storage and retention of information even when the non-volatile memory is not connected to a power source (e.g., a battery).

[0003] An example of non-volatile memory is magnetic random access memory (MRAM), which uses magnetism to represent stored data, as opposed to some other memory technologies that use charge to store data. Generally, MRAM includes a large number of magnetic memory cells formed on a semiconductor substrate, and each memory cell represents 1 bit of data. Bits of data are written into the memory cells by changing the magnetization direction of magnetic elements in the memory cells, and the bits are read by measuring the resistance of the memory cells (low resistance typically represents a "0" bit, and high resistance typically represents a "1" bit). As used herein, the direction of magnetization is the direction of the orientation of the magnetic moment. Some memory cells may include a selector device such as an ovonic threshold switch or other selector device.

[0004] Although MRAM is a promising technology, many design and process challenges remain.

Brief Description of the Drawings

[0005]

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DETAILED DESCRIPTION OF THE INVENTION

[0006] Techniques for providing a memory cell that can be used either as a multi - time programmable memory cell or a rewritable memory cell are described. As used herein, a multi - time programmable memory cell is a memory cell that can be programmed a finite number of times (e.g., 1, 2, or 3 times, etc.). As used herein, a rewritable memory cell is a memory cell that can be programmed, erased, and reprogrammed (theoretically) an unlimited number of times.

[0007] Techniques for providing a memory cell that can be used either as a multi - time programmable memory cell or a rewritable memory cell, having the same structure, and manufactured using the same manufacturing process that uses the same materials and the same processing steps are described. The memory cell may be formed as a single memory array of memory cells, or may be formed as separate arrays of multi - time programmable memory cells and rewritable memory cells.

[0008] In one embodiment, the memory cell includes a memory element coupled in series with a selector device. In one embodiment, the memory element is a magnetic memory element. In one embodiment, the memory element is a magnetic tunnel junction memory element. In one embodiment, the selector device is an ovonic threshold switch. In one embodiment, the memory cell can be used as a multi - time programmable memory cell.

[0009] In one embodiment, the memory cells in the memory array may include non-volatile memory cells including reversible resistive switching elements. The reversible resistive switching element may include a reversible resistive switching material having a resistivity that can be reversibly switched between two or more states.

[0010] In one embodiment, the reversible resistive switching material may include a metal oxide, a solid electrolyte, a phase change material, a magnetic material, or other similar resistivity switching materials. Various metal oxides such as transition metal oxides can be used. Examples of metal oxides include, but are not limited to, NiO, Nb2O5, TiO2, HfO2, Al2O3, MgO x , CrO2, VO, BN, TaO2, Ta2O3, and AlN.

[0011] In one embodiment, the non-volatile memory cells in the memory array include multi-time programmable memory cells. In one embodiment, the non-volatile memory cells in the memory array include rewritable memory cells.

[0012] In one embodiment, the non-volatile memory cells in the memory array include memory cells that can be configured as multi-time programmable memory cells or rewritable memory cells.

[0013] In one embodiment, the non-volatile memory cells in the memory array include memory cells having the same structure and can be configured as multi-time programmable memory cells or rewritable memory cells.

[0014] In one embodiment, the non-volatile memory cells in the memory array include memory cells manufactured using the same manufacturing process and can be configured as multi-time programmable memory cells or rewritable memory cells.

[0015] FIG. 1A shows one embodiment of a memory system 100 and a host 102. The memory system 100 may include a non-volatile storage system that interfaces with a host 102 (e.g., a mobile computing device or a server). In some cases, the memory system 100 may be embedded within the host 102. By way of example, the memory system 100 may be a solid state drive (SSD) such as a memory card, a high density MLC SSD (e.g., 2 bits / cell or 3 bits / cell) or a high performance SLC SSD, or a hybrid HDD / SSD drive.

[0016] As shown, the memory system 100 includes a memory chip controller 104 and a memory chip 106. The memory chip 106 may include volatile memory and / or non-volatile memory. Although a single memory chip is shown, the memory system 100 may include two or more memory chips. The memory chip controller 104 can receive data and commands from the host 102 and provide memory chip data to the host 102.

[0017] The memory chip controller 104 may include one or more of a control circuit, a state machine, page registers, SRAM, a decoder, a sense amplifier, read / write circuitry, and / or a controller, or any combination thereof, to control the operation of the memory chip 106. One or more control circuits, state machines, page registers, SRAM, decoders, sense amplifiers, read / write circuitry, and / or controllers for controlling the operation of the memory chip may be referred to as a management circuit or a control circuit. The management circuit or control circuit can facilitate one or more memory array operations including a formation operation, an erase operation, a programming operation, or a read operation.

[0018] In some embodiments, a management circuit or a control circuit (or a part of the management circuit or the control circuit) for facilitating one or more memory array operations may be integrated within the memory chip 106. The memory chip controller 104 and the memory chip 106 may be disposed on a single integrated circuit or on a single die. In other embodiments, the memory chip controller 104 and the memory chip 106 may be disposed on different integrated circuits. In some cases, the memory chip controller 104 and the memory chip 106 may be integrated on a system board, a circuit logic board, or a PCB.

[0019] The memory chip 106 includes a memory core control circuit 108 and a memory core 110. The memory core control circuit 108 controls the selection of memory blocks (or arrays) within the memory core 110, controls the generation of a voltage reference for biasing a particular memory array into a read or write state, and may include logic for generating row and column addresses.

[0020] The memory core 110 may include one or more two-dimensional arrays of memory cells and / or one or more three-dimensional arrays of memory cells. In one embodiment, the memory core may include rewritable memory cells, one-time programmable memory cells, and / or multi-time programmable memory cells, or any combination thereof.

[0021] In one embodiment, the memory core control circuit 108 and the memory core 110 may be disposed on a single integrated circuit. In other embodiments, the memory core control circuit 108 (or a part of the memory core control circuit 108) and the memory core 110 may be disposed on different integrated circuits.

[0022] The memory operation can be initiated when the host 102 sends a command indicating that it desires to read data from the memory system 100 or write data to the memory system 100 to the memory chip controller 104. In the case of a write (or programming) operation, the host 102 can send both a write command and the data to be written to the memory chip controller 104.

[0023] The memory chip controller 104 can buffer the data to be written and can generate error correction code (ECC) data corresponding to the data to be written. The ECC data that enables detection and / or correction of data errors occurring during transmission or storage can be written to the memory core 110 or stored in a non-memory chip within the volatile memory controller 104. In one embodiment, the ECC data is generated and the data error is corrected by circuitry within the memory chip controller 104.

[0024] The memory chip controller 104 can control the operation of the memory chip 106. In one example, before issuing a write operation to the memory chip 106, the memory chip controller 104 can check the status register to confirm that the memory chip 106 can accept the data to be written.

[0025] In another example, before issuing a read operation to the memory chip 106, the memory chip controller 104 can pre-read the overhead information associated with the data to be read. The overhead information can include ECC data associated with the data to be read or a redirection pointer to a new memory location within the memory chip 106 from which the requested data is to be read.

[0026] When the memory chip controller 104 starts a read or write operation, the memory core control circuit 108 can generate appropriate bias voltages for the word lines and bit lines in the memory core 110, and can also generate appropriate memory block, row, and column addresses.

[0027] FIG. 1B shows an embodiment of the memory core control circuit 108. In one embodiment, the memory core control circuit 108 includes an address decoder 120, a voltage generator 122 for selected control lines, and a voltage generator 124 for unselected control lines. The control lines may include word lines, bit lines, or a combination of word lines and bit lines. The selected control lines may include selected word lines or selected bit lines, which are used to place memory cells in a selected state. The unselected control lines may include unselected word lines or unselected bit lines, which are used to place memory cells in an unselected state.

[0028] The voltage generator (or voltage regulator) 122 for the selected control lines may include one or more voltage generators for generating the selected control line voltage. The voltage generator 124 for the unselected control lines may include one or more voltage generators for generating the unselected control line voltage. The address decoder 120 can generate a memory block address, as well as row and column addresses for a particular memory block.

[0029] FIGS. 1C - 1F show an embodiment of a memory core organization that includes a memory core 110 having a plurality of memory banks, where each memory bank has a plurality of memory blocks. A memory core organization is disclosed in which a memory bank includes memory blocks and a memory block includes a group of memory cells, although other organizations or groupings can also be used with the techniques described herein.

[0030] FIG. 1C shows an embodiment of the memory core 110 of FIG. 1A. As shown, the memory core 110 includes a memory bay 130 and a memory bay 132. In some embodiments, the number of memory buses per memory core may vary for different implementations. For example, a memory core may include only a single memory bay or multiple memory bays (e.g., 16 memory bays, 256 memory bays, etc.).

[0031] FIG. 1D shows an embodiment of the memory bay 130 of FIG. 1C. As shown, the memory bay 130 includes memory blocks 140-144 and a read / write circuit 150. In some embodiments, the number of memory blocks per memory bay may vary for different implementations. For example, a memory bay may include one or more memory blocks (e.g., 32 memory blocks per memory bay).

[0032] The read / write circuit 150 includes circuitry for reading from and writing to memory cells within the memory blocks 140-144. As shown, the read / write circuit 150 may be shared across multiple memory blocks within a memory bay. Thereby, a single group of read / write circuits 150 can be used to support multiple memory blocks, reducing the chip area. However, in some embodiments, only a single memory block may be electrically coupled to the read / write circuit 150 at a given time to avoid signal contention.

[0033] In some embodiments, the read / write circuit 150 may be used to write one or more pages of data to the memory blocks 140-144 (or a subset of the memory blocks). The memory cells within the memory blocks 140-144 can enable direct overwriting of pages (i.e., data representing a page or a portion of a page can be written to the memory blocks 140-144 without performing an erase or reset operation on the memory cells prior to writing the data).

[0034] In one example, the memory system 100 of FIG. 1A can receive a write command that includes a target address and a set of data to be written to the target address. Before performing a write operation to write the set of data to the target address, the memory system 100 can perform a read-before-write (RBW) operation to read the data currently stored at the target address. The memory system 100 can then determine whether a particular memory cell can remain in its current state (i.e., the memory cell is already in the correct state), needs to be set to the "0" state, or needs to be reset to the "1" state.

[0035] The memory system 100 can then write a first subset of the memory cells to the "0" state and then write a second subset of the memory cells to the "1" state. Memory cells that are already in the correct state can be skipped, thereby improving the programming speed and reducing the cumulative voltage stress applied to non-selected memory cells.

[0036] A particular memory cell can be set to the "1" state by applying a first voltage difference across the particular memory cell of a first polarity (e.g., +1.5V). A particular memory cell can be reset to the "0" state by applying a second voltage difference across the particular memory cell of a second polarity opposite to the first (e.g., -1.5V).

[0037] In some cases, the read / write circuit 150 may be used to program a particular memory cell to one of three or more data / resistance states (i.e., the particular memory cell may include a multi-level memory cell). In one example, the read / write circuit 150 may apply a first voltage difference (e.g., 2V) across a particular memory cell to program the particular memory cell to a first state of three or more data / resistance states, or may apply a second voltage difference (e.g., 1V) across the particular memory cell that is less than the first voltage difference to program the particular memory cell to a second state of three or more data / resistance states.

[0038] By applying a smaller voltage difference across a particular memory cell, the particular memory cell can be partially programmed or programmed at a slower rate than when a larger voltage difference is applied. In another example, the read / write circuit 150 may apply a first voltage difference across the two ends of a particular memory cell for a first period (e.g., 150 ns) to program the particular memory cell to a first state of three or more data / resistance states, or may apply the first voltage difference across the two ends of the particular memory cell for a second period (e.g., 50 ns) that is shorter than the first period. One or more programming pulses following the memory cell verification phase can be used to program the particular memory cell to the correct state.

[0039] FIG. 1E shows one embodiment of the memory block 140 of FIG. 1D. As shown, the memory block 140 includes a memory array 160, a row decoder 162, and a column decoder 164. The memory array 160 may include a continuous group of memory cells having continuous word lines and bit lines. The memory array 160 can include one or more layers of memory cells and may include a two-dimensional memory array and / or a three-dimensional memory array.

[0040] The row decoder 162 decodes the row address and, when appropriate (e.g., when reading or writing to a memory cell in the memory array 160), selects a specific word line in the memory array 160. The column decoder 164 decodes the column address and selects a specific group of bit lines in the memory array 160 and is electrically coupled to a read / write circuit such as the read / write circuit 150 of FIG. 1D. In one embodiment, the number of word lines is 4K per memory layer, the number of bit lines is 1K per memory layer, and the number of memory layers is 4, providing a memory array 160 that includes 16M memory cells. Other numbers of word lines per layer, bit lines per layer, and number of layers may be used.

[0041] FIG. 1F shows one embodiment of the memory bay 170. The memory bay 170 is an example of an alternative implementation of the memory bay 130 of FIG. 1D. In some embodiments, the row decoder, column decoder, and read / write circuit may be divided or shared among the memory arrays. As shown, the row decoder 172 is shared between the memory arrays 174 and 176. This is because the row decoder 172 controls the word lines in both the memory arrays 174 and 176 (i.e., the word lines driven by the row decoder 172 are shared).

[0042] The row decoders 178 and 172 can be divided such that the even word lines in the memory array 174 are driven by the row decoder 178 and the odd word lines in the memory array 174 are driven by the row decoder 172. The column decoders 180 and 182 can be divided such that the even bit lines in the memory array 174 are controlled by the column decoder 182 and the odd bit lines in the memory array 174 are driven by the column decoder 180.

[0043] The selected bit lines controlled by column decoder 180 can be electrically coupled to read / write circuit 184. The selected bit lines controlled by column decoder 182 can be electrically coupled to read / write circuit 186. Dividing the read / write circuit into read / write circuits 184 and 186 when the column decoder is divided can enable a more efficient layout of the memory bank.

[0044] Row decoders 188 and 172 can be divided such that the even word lines in memory array 176 are driven by row decoder 188 and the odd word lines in memory array 176 are driven by row decoder 172. Column decoders 190 and 192 can be divided such that the even bit lines in memory array 176 are controlled by column decoder 192 and the odd bit lines in memory array 176 are driven by column decoder 190.

[0045] The selected bit lines controlled by column decoder 190 can be electrically coupled to read / write circuit 184. The selected bit lines controlled by column decoder 192 can be electrically coupled to read / write circuit 186. Dividing the read / write circuit into read / write circuits 184 and 186 when the column decoder is divided can enable a more efficient layout of the memory bank.

[0046] FIG. 1G shows an embodiment of a schematic diagram (including word lines and bit lines) corresponding to the memory bank 170 of FIG. 1F. As shown, word lines WL1, WL3, and WL5 are shared between memory arrays 174 and 176 and are controlled by row decoder 172 of FIG. 1F. Word lines WL0, WL2, WL4, and WL6 are driven from the left side of memory array 174 and are controlled by row decoder 178 of FIG. 1F. Word lines WL14, WL16, WL18, and WL20 are driven from the right side of memory array 176 and are controlled by row decoder 188 of FIG. 1F.

[0047] Bit lines BL0, BL2, BL4, and BL6 are driven from the bottom of the memory array 174 and controlled by the column decoder 182 in FIG. 1F. Bit lines BL1, BL3, and BL5 are driven from the top of the memory array 174 and controlled by the column decoder 180 in FIG. 1F. Bit lines BL7, BL9, BL11, and BL13 are driven from the bottom of the memory array 176 and controlled by the column decoder 192 in FIG. 1F. Bit lines BL8, BL10, and BL12 are driven from the top of the memory array 176 and controlled by the column decoder 190 in FIG. 1F.

[0048] In one embodiment, the memory arrays 174 and 176 may include a memory layer oriented in a plane horizontal to the support substrate. In another embodiment, the memory arrays 174 and 176 can include a memory layer oriented in a plane perpendicular to the support substrate (i.e., the vertical plane is substantially perpendicular to the support substrate). In this case, the bit lines of the memory array may include substantially vertical bit lines.

[0049] FIG. 1H shows an embodiment of a schematic diagram (including word lines and bit lines) corresponding to a memory bay configuration in which word lines and bit lines are shared across memory blocks and both row and column decoders are split. Sharing word lines and / or bit lines can help reduce the layout area because a single row decoder and / or column decoder can be used to support two memory arrays.

[0050] As shown, word lines WL1, WL3, and WL5 are shared between memory arrays 200 and 202. Bit lines BL1, BL3, and BL5 are shared between memory arrays 200 and 204. Word lines WL8, WL10, and WL12 are shared between memory arrays 204 and 206. Bit lines BL8, BL10, and BL12 are shared between memory arrays 202 and 206.

[0051] The row decoder is divided such that word lines WL0, WL2, WL4, and WL6 are driven from the left side of memory array 200, and word lines WL1, WL3, and WL5 are driven from the right side of memory array 200. Similarly, word lines WL7, WL9, WL11, and WL13 are driven from the left side of memory array 204, and word lines WL8, WL10, and WL12 are driven from the right side of memory array 204.

[0052] The column decoder is divided such that bit lines BL0, BL2, BL4, and BL6 are driven from the bottom of memory array 200, and bit lines BL1, BL3, and BL5 are driven from the top of memory array 200. Similarly, bit lines BL7, BL9, BL11, and BL13 are driven from the bottom of memory array 202, and bit lines BL8, BL10, and BL12 are driven from the top of memory array 202. Dividing the row and / or column decoder also helps to relax layout constraints (e.g., the divided column decoder only needs to drive every other bit line instead of each bit line, so the column decoder pitch can be relaxed by a factor of two).

[0053] FIG. 2A shows some embodiments of a monolithic three-dimensional memory array 210 including a first memory level 212 and a second memory level 214 disposed on top of the first memory level 212. Memory array 210 is an example of an implementation form of memory array 160 of FIG. 1E. Word lines 216, 218 are arranged in a first direction, and bit lines 220 are arranged in a second direction orthogonal to the first direction. As shown, the upper conductors of the first memory level 212 can be used as the lower conductors of the second memory level 214. In a memory array having additional layers of memory cells, there are corresponding additional layers of bit lines and word lines.

[0054] The memory array 210 includes a plurality of memory cells 222. In an embodiment, the memory cells 222 can include rewritable memory cells, one-time programmable memory cells, and multi-time programmable memory cells. In one embodiment, each of the memory cells 222 is vertically oriented. The memory cells 222 can include non-volatile memory cells or volatile memory cells. With respect to the first memory level 212, a first portion of the memory cells 222 is between and connected to a word line 216 and a bit line 220. With respect to the second memory level 214, a second portion of the memory cells 222 is between and connected to a word line 218 and a bit line 220.

[0055] In one embodiment, each memory cell 222 includes a selector element coupled in series with a resistive switching memory element, and each memory cell 222 represents one bit of data. In one embodiment, the resistive switching memory element can be a magnetic memory element, a ReRAM memory element, a phase change memory element, a memory element including a thin barrier layer that can be broken by a voltage of less than 5 volts, or other types of resistive switching memory elements.

[0056] In one embodiment, each memory cell 222 includes a selector element coupled in series with a magnetic memory element, and each memory cell 222 represents one bit of data. FIG. 2B is a simplified schematic diagram of a memory cell 222a, which is an exemplary implementation of one of the memory cells 222 of FIG. 2A.

[0057] In one embodiment, the memory cell 222a includes a selector element S x coupled in series with a magnetic memory element M x both coupled between a first terminal T1 and a second terminal T2. In one embodiment, the memory cell 222a is vertically oriented. In the embodiment of FIG. 2B, the magnetic memory element M x is disposed on top of the selector element S x . In other embodiments, the selector element S x may be disposed on top of the magnetic memory element M x .

[0058] In one embodiment, the magnetic memory element M x is a magnetic tunnel junction, and the selector element S x is a threshold selector device. In one embodiment, the selector element S x is a conductive bridge threshold selector device. In other embodiments, the selector element S x is an ovonic threshold switch (e.g., binary AsTeSi, CTe, BTe, AlTe, etc., or ternary types such as SiTe, AsTeGe, or AsTeGeSiN), a phase change material type of metal insulator transition (MIT) (e.g., VO2, NbO2, etc.), or other similar threshold selector devices.

[0059] In one embodiment, the magnetic memory element M x includes an upper ferromagnetic layer 230, a lower ferromagnetic layer 232, and a tunnel barrier (TB) 234 that is an insulating layer between the two ferromagnetic layers. In this example, the lower ferromagnetic layer 232 is a free layer (FL) having a magnetization direction that can be switched. The upper ferromagnetic layer 230 is a pinned (or fixed) layer (PL) having a magnetization direction that does not easily change.

[0060] In other embodiments, the magnetic memory element M x may include fewer layers, additional layers, or different layers than the layers shown in FIG. 2B. In other embodiments, the lower ferromagnetic layer 232 is a pinned layer (PL), and the upper ferromagnetic layer 230 is a free layer (FL).

[0061] When the magnetization direction of the free layer 232 is parallel to the magnetization direction of the pinned layer 230, the memory element M x has a relatively low resistance RP (referred to herein as "parallel resistance RP"). When the magnetization direction of the free layer 232 is antiparallel to the magnetization direction of the pinned layer 230, the memory element M x has a relatively high resistance RAP (referred to herein as "antiparallel resistance RAP").

[0062] In one embodiment, the magnetic memory element M xThe data state (“0” or “1”) is read by measuring the resistance of the magnetic memory element M x By design, both parallel and antiparallel configurations remain stable during the stationary state and / or during the read operation (with a sufficiently low read current).

[0063] In one embodiment, the selector element S x is an ovonic threshold switch including a first region 236 and optionally a second region 238 disposed on the first region 236. In one embodiment, the first region 236 is a SiTe alloy and the optional second region 238 is carbon nitride. Other materials can be used for the first region 236 and the optional second region 238. In other embodiments, the selector element S x is a conductive bridge threshold selector element. In one embodiment, the first region 236 is a solid electrolyte region and the second region 238 is an ion source region.

[0064] FIG. 2C is a diagram showing exemplary current-voltage (I-V) characteristics of the threshold selector device S x . Each threshold selector device S x is initially in a high resistance (off) state. To operate the threshold selector device S x as a threshold switch, an initial forming operation may be required so that the threshold selector device S x operates in a current range where switching can occur.

[0065] For example, the forming operation may include applying one or more pulses each having a magnitude greater than or equal to the forming voltage V1 to the threshold selector device S x . Alternatively, the forming operation may include applying one or more pulses each having a magnitude greater than or equal to the forming voltage -V1 (i.e., more negative) to the threshold selector device S x . Following the forming operation, the threshold selector device S x can be switched on and off and can be used as either a unipolar or bipolar threshold selector device. Thus, the threshold selector device Sx can be referred to as a bipolar threshold selector device. In one embodiment, the forming operation is irreversible. That is, following the forming operation, the threshold selector device S x cannot be "reset".

[0066] In the exemplary I-V characteristics of FIG. 2C, for a positive applied voltage, the threshold selector device S x remains in a high resistance state (HRS) (e.g., off) until the voltage across the device meets or exceeds a first threshold voltage V TP (i.e., is more positive), at which point the threshold selector device S x switches to a low resistance state (LRS) (e.g., on). The threshold selector device S x remains on until the voltage across the device drops below a first holding voltage V HP , at which point the threshold selector device 224 turns off.

[0067] For a negative applied voltage, the threshold selector device S x remains in HRS (e.g., off) until the voltage across the device meets or exceeds a second threshold voltage V TN (i.e., is more negative), at which point the threshold selector device 304 switches to LRS (e.g., on). The threshold selector device S x remains on until the voltage between the two ends of the device increases to or exceeds a second holding voltage V HN (i.e., is not more negative than it), at which point the threshold selector device S x turns off.

[0068] Referring again to FIG. 2B, in one embodiment, the magnetic memory element M x uses spin transfer torque (STT) switching. The magnetic memory element M xTo “set” the bit value (i.e., select the direction of magnetization of the free layer), a write current is applied from the first terminal T1 to the second terminal T2. Since the pin layer 230 is a ferromagnetic metal, the electrons in the write current are spin-polarized when passing through the pin layer 230.

[0069] Substantially most of the conduction electrons in the ferromagnetic body have a spin orientation parallel to the direction of magnetization, resulting in a net spin-polarized current. (The electron spin is proportional to the magnetic moment of the electron but points to the angular momentum that is anti-parallel to that direction. This distinction in direction will not be used hereafter to facilitate the discussion.)

[0070] When the spin-polarized electrons tunnel across TB234, the conservation of angular momentum can result in applying torque to both the free layer 232 and the pin layer 230, but this torque is (by design) insufficient to affect the direction of magnetization of the pin layer 230. In contrast, this torque is (by design) sufficient to switch the direction of magnetization of the free layer 232 to be parallel to the direction of magnetization of the pin layer 230 when the initial direction of magnetization of the free layer 232 is anti-parallel to the pin layer 230. In that case, the parallel magnetization remains stable before and after such a write current is turned off.

[0071] In contrast, when the magnetizations of the free layer 232 and the pin layer 230 are initially parallel, the direction of magnetization of the free layer 232 can be STT-switched to be anti-parallel to the direction of magnetization of the pin layer 230 by applying a write current in the opposite direction as in the previous case. Therefore, by the same STT physics, the direction of magnetization of the free layer 232 can be deterministically set to either of the two stable orientations by a judicious choice of the write current direction (polarity).

[0072] In the above example, spin-transfer torque (STT) switching is used for the magnetic memory element M x"Set" the bit value. In other embodiments, magnetic field induced switching, spin orbit torque (SOT) switching, VCMA (magnetoelectric) switching, or other switching techniques may be used.

[0073] Figures 3A - 3B are simplified schematic diagrams of an exemplary cross - point memory array 300 including a first memory level 300a and a second memory level 300b disposed on top of the first memory level 300a. The cross - point memory array 300 is an example of an implementation form of the memory array 160 of FIG. 1E. The cross - point memory array 300 may include three or more memory levels.

[0074] The cross - point memory array 300 includes word lines WL1a, WL2a, WL3a, WL1b, WL2b, and WL3b and bit lines BL1, BL2, and BL3. The first memory level 300a includes memory cells 302 coupled to the word lines WL1a, WL2a, WL3a and the bit lines BL1, BL2, and BL3 11a 、302 12a 、...、302 33a and the second memory level 300b includes memory cells 302 coupled to the word lines WL1b, WL2b, WL3b and the bit lines BL1, BL2, and BL3 11b 、302 12b 、...、302 33b In one embodiment, each of the memory cells 302 11a 、302 12a 、...、302 33a is vertically oriented. In one embodiment, each of the memory cells 302 11b 、302 12b 、...、302 33b is vertically oriented.

[0075] The first memory level 300a is an example of an implementation form of the first memory level 212 of the monolithic three-dimensional memory array 210 in FIG. 2B, and the second memory level 300b is an example of an implementation form of the second memory level 214 of the monolithic three-dimensional memory array 210 in FIG. 2B. In one embodiment, the memory cell 302 11a , 302 12a ,...,, 302 33a , 302 11b , 302 12b ,...,, 302 33b each is an implementation form of the memory cell 222a in FIG. 2B.

[0076] Those skilled in the art will understand that the cross-point memory array 300 may include more or fewer word lines than six, more or fewer bit lines than three, and more or fewer memory cells 302 11a , 302 12a ,...,, 302 33a , 302 11b , 302 12b ,...,, 302 33b than 18. In some embodiments, the cross-point memory array 300 may include 1000×1000 memory cells, but other array sizes may be used.

[0077] Each memory cell 302 11a , 302 12a ,...,, 302 33a , 302 11b , 302 12b ,...,, 302 33b is coupled to one of the word lines and one of the bit lines, and includes a corresponding magnetic memory element M 11a , M 12a ,...,, M 33a , M 11b , M 12b ,...,, M 33b respectively, and includes a corresponding selector element S 11a , S 12a ,...,, S 33a , S 11b , S 12b ,...,, S 33bare each coupled in series. In one embodiment, the magnetic memory element M 11a , M 12a ,..., M 33a , M 11b , M 12b ,..., M 33b each has the implementation form of the magnetic memory element M x in FIG. 2B, and each of the selector elements S 11a , S 12a ,..., S 33a , S 11b , S 12b ,..., S 33b each has the implementation form of the selector element S x in FIG. 2B.

[0078] Each memory cell 302 11a , 302 12a ,..., 302 33a has a first terminal coupled to one of the bit lines BL1, BL2, BL3 and a second terminal coupled to one of the word lines WL1a, WL2a, WL3a, and each memory cell 302 11b , 302 12b ,..., 302 33b has a first terminal coupled to one of the bit lines BL1, BL2, BL3 and a second terminal coupled to one of the word lines WL1b, WL2b, WL3b. For example, the memory cell 302 13a includes a magnetic memory element M 13a coupled in series with a selector element S 13a , and includes a first terminal coupled to the bit line BL3 and a second terminal coupled to the word line WL1a.

[0079] Similarly, the memory cell 302 22b includes a magnetic memory element M 22b coupled in series with a selector element S 22b , and includes a first terminal coupled to the bit line BL2 and a second terminal coupled to the word line WL2b. Similarly, the memory cell 302 33a includes a magnetic memory element M 33a coupled in series with a selector element S 33aincluding a first terminal coupled to bit line BL3 and a second terminal coupled to word line WL3a.

[0080] Magnetic memory element M 11a 、M 12a 、...、M 33a may be disposed respectively above or below the corresponding selector element S 11a 、S 12a 、...、S 33a Magnetic memory element M 11b 、M 12b 、...、M 33b may be disposed respectively above or below the corresponding selector element S 11b 、S 12b 、...、S 33b respectively.

[0081] In one embodiment, the memory cells 302 of the first memory level 300a 11a 、302 12a 、...、302 33a have the same orientation as the memory cells 302 of the second memory level 300b 11b 、302 12b 、...、302 33b .

[0082] In another embodiment, the memory cells 302 of the first memory level 300a 11a 、302 12a 、...、302 33a have an orientation opposite to that of the memory cells 302 of the second memory level 300b 11b 、302 12b 、...、302 33b .

[0083] Referring back to FIG. 1A, in one embodiment, the memory core 110 may include one or more two-dimensional arrays of memory cells and / or one or more three-dimensional arrays of memory cells. In one embodiment, the memory core 110 may include rewritable memory cells and / or multi-time programmable memory cells, or any combination thereof.

[0084] In fact, a memory system such as the memory system 100 of FIG. 1A may often include one-time programmable memory for storing data related to the operating parameters of the memory device, such as content management bits, trim bits, manufacturer data, format data, and other similar data. One technique for including such one-time programmable memory within the memory system 100 is to include one-time programmable memory cells along with rewritable memory cells within the memory core 110.

[0085] However, such prior art has often required different types of memory cell structures for one-time programmable memory cells and rewritable memory cells. In fact, in some prior art, the manufacture of one-time programmable memory cells requires different materials and / or additional processing steps than the materials and / or processing steps used to manufacture rewritable memory cells. As a result, the need for different materials and / or additional processing steps has increased the cost, complexity, and / or failure rate of prior art for providing one-time programmable memory cells and rewritable memory cells within the memory core 110.

[0086] In addition, a memory system such as the memory system 100 of FIG. 1A may have operating parameters of the memory device that may occasionally require modification. For example, an initial set of operating parameters may be determined, but after further analysis and use, the operating parameters may be changed one or more times. If such operating parameters are stored in one-time programmable memory cells, the operating parameters may not be changed, and thus, when a change to the operating parameters is made, the memory device may be considered useless.

[0087] It may be useful to store the operation parameters in a multi-time programmable memory cell (e.g., a memory cell that can be programmed a finite number of times (e.g., 1, 2, 3, etc.)) so that the memory device can continue to be used until it is determined that the operation parameters are "final" (e.g., no further changes are required).

[0088] Techniques for providing a memory cell that can be used as a multi-time programmable memory cell or a rewritable memory cell are described. The memory cells are manufactured using the same manufacturing process having the same structure, using the same materials and the same processing steps. The memory cells may be formed as a single memory array of memory cells, or as separate arrays of one-time / multi-time programmable memory cells and rewritable memory cells.

[0089] FIG. 4A is a simplified diagram of a memory core 110 that is an embodiment of the memory core 400a of FIG. 1A. The memory core 400a includes one or more memory arrays such as a memory array 402a. In one embodiment, the memory array 402a includes a first array of multi-time programmable memory cells 404a and a second array of rewritable memory cells 404b.

[0090] One of ordinary skill in the art will understand that the memory array 402a may alternatively include two or more first arrays of multi-time programmable memory cells 404a and two or more second arrays of rewritable memory cells 404b. For example, FIG. 4B is a simplified diagram of a memory core 110 that is an embodiment of the memory core 400b of FIG. 1A. The memory core 400b includes one or more memory arrays such as a memory array 402b.

[0091] In one embodiment, the memory array 402b includes a first array of multi-time programmable memory cells 404a including a first sub-array of multi-time programmable memory cells 404a1 and a second sub-array of multi-time programmable memory cells 404a2, and a second array of rewritable memory cells 404b including a first sub-array of rewritable memory cells 404b1 and a second sub-array of rewritable memory cells 404b2.

[0092] Referring again to FIG. 4A, in one embodiment, the first array of multi-time programmable memory cells 404a can be used to store the operating parameters of the memory system 100 (FIG. 1A), or other data that does not change over time or changes only a few times. Those skilled in the art will understand that other types of data may be stored in the first array of multi-time programmable memory cells 404a.

[0093] In contrast, in one embodiment, the second array of rewritable memory cells 404b can be used to store user data that can be written, erased, and rewritten multiple times and can change frequently over time. Those skilled in the art will understand that other types of data may be stored in the second array of rewritable memory cells 404b.

[0094] In one embodiment, the first array of multi-time programmable memory cells 404a and the second array of rewritable memory cells 404b each include the same type of memory cells. In one embodiment, the first array of multi-time programmable memory cells 404a and the second array of rewritable memory cells 404b each include memory cells including a threshold selector device (such as an ovonic threshold switch) coupled in series with a resistive switching memory element (such as a magnetic memory element, a ReRAM memory element, a phase change memory element, or other types of resistive switching memory elements).

[0095] For simplicity, in the remainder of the present description, a memory cell including an ovonic threshold switch coupled in series with a magnetic tunnel junction will be described. For example, each memory cell within the first array of multi-time programmable memory cells 404a and the second array of rewritable memory cells 404b may be the exemplary memory cell 222a of FIG. 2B. Those skilled in the art will understand that memory cells including other types of threshold selector devices and other types of memory elements may be used.

[0096] In one embodiment, the first array of multi-time programmable memory cells 404a and the second array of rewritable memory cells 404b are part of a single array of memory cells. For example, the memory array 402 may include M rows of memory cells (e.g., rows 0, 1, 2, ..., M-1). The first J rows of the memory array 402a (e.g., rows 0, 1, 2, ..., J-1) can constitute the first array of multi-time programmable memory cells 404a, and the remaining (M-J) rows of the memory array 402a (e.g., rows J, J+1, ..., M-1) can constitute the second array of rewritable memory cells 404b.

[0097] In other embodiments, the first array of multi-time programmable memory cells 404a and the second array of rewritable memory cells 404b are separate memory arrays. In one embodiment, the first array of multi-time programmable memory cells 404a and the second array of rewritable memory cells 404b are manufactured using the same process (e.g., the same semiconductor manufacturing process). In one embodiment, the first array of multi-time programmable memory cells 404a is manufactured using the same materials and the same manufacturing process steps as the second array of rewritable memory cells 404b.

[0098] In one embodiment, the memory cells in the first array of multi-time programmable memory cells 404a and the memory cells in the second array of rewritable memory cells 404b have the same structure. In one embodiment, the first array of multi-time programmable memory cells 404a and the second array of rewritable memory cells 404b each include a cross-point memory array, and each memory cell in the cross-point memory array includes a threshold selector device (such as an ovonic threshold switch) coupled in series with a magnetic memory element (such as a magnetic tunnel junction).

[0099] As described above, in one embodiment, each memory cell in the first array of multi-time programmable memory cells 404a and the second array of rewritable memory cells 404b is the exemplary memory cell 222a of FIG. 2B. In particular, in one embodiment, each memory cell in the first array of multi-time programmable memory cells 404a and the second array of rewritable memory cells 404b is an ovonic threshold switch S x coupled in series with a magnetic tunnel junction memory element M x and includes.

[0100] To avoid confusion, the memory cells in the first array of multi-time programmable memory cells 404a are referred to as multi-time programmable memory cells 222m in the remaining description, and the memory cells in the second array of rewritable memory cells 404b are referred to as rewritable memory cells 222r in the remaining description. Those skilled in the art will understand that in one embodiment, each multi-time programmable memory cell 222m and each rewritable memory cell 222r are instances of the exemplary memory cell 222a of FIG. 2B.

[0101] In one embodiment, each rewritable memory cell 222r in the second array of rewritable memory cells 404b is an ovonic threshold switch S xReceives a forming operation so that it can be selectively turned on and off. Following the forming operation, the magnetic tunnel junction memory element M of each rewritable memory cell 222r in the second array of the rewritable memory cells 404b x can be used to store the data state of the memory cell, and each rewritable memory cell 222r in the second array of the rewritable memory cells 404b is rewritable.

[0102] FIG. 5 shows diagrams of various exemplary voltages used to operate the multi-time programmable memory cell 222m and the rewritable memory cell 222r. Although FIG. 5 shows all voltages as having positive values, it should be noted that the techniques described below can also be used with voltages having negative values. For the rewritable memory cell 222r in the second array of the rewritable memory cells 404b, the forming operation may include applying one or more pulses each having a magnitude greater than or equal to a forming (first) voltage V1 to a threshold selector device S x may include applying to.

[0103] In one embodiment, prior to the forming operation, the threshold selector device S in the multi-time programmable memory cell 222m and the rewritable memory cell 222r x has a first switching resistance R OTS (UF). For example, the first switching resistance R OTS (UF) can be about 1 MΩ or some other value.

[0104] In one embodiment, after the forming operation, the threshold selector device S in the multi-time programmable memory cell 222m and the rewritable memory cell 222r x has a second switching resistance R OTS (F). For example, the second switching resistance R OTS (F) can be about 1 kΩ or some other value. In one embodiment, the forming operation is irreversible. That is, the resistance of the formed threshold selector device S x is the second switching resistance R OTS(F) to the first switch resistance R OTS It cannot be switched back to (UF).

[0105] In one embodiment, following the forming operation, one or more pulses each having a magnitude equal to the (switching) voltage V0 are applied to set the data state (“0” or “1”) of the memory cell, and the magnetic tunnel junction memory element M of the rewritable memory cell 222r in the second array of the rewritable memory cell 404b x The resistance of can be changed. In one embodiment, the switching voltage V0 is less than the forming (first) voltage V1.

[0106] Regarding the multi-time programmable memory cell 222m in the first array of the multi-time programmable memory cell 404a, in one embodiment, such a memory cell can be programmed multiple times by selectively applying voltage pulses of different magnitudes to the memory cell.

[0107] In one embodiment, the multi-time programmable memory cell 222m in the first array of the multi-time programmable memory cell 404a can be programmed multiple times by selectively applying a voltage pulse having a magnitude of one of three voltages. As will be described in more detail below, such multi-time programming includes irreversibly (or destructively) changing the resistance of one or both of x the threshold selector device S x and the magnetic tunnel junction memory element M.

[0108] In one embodiment, the multi-time programmable memory cell 222m in the first array of the multi-time programmable memory cell 404a can be programmed for the first time by selectively applying one or more voltage pulses having the magnitude of the first voltage V1 to the memory cell.

[0109] In one embodiment, the multi-time programmable memory cell 222m in the first array of the multi-time programmable memory cell 404a can be programmed a second time by selectively applying a voltage pulse having a magnitude of a second voltage V2 greater than the first voltage V1 to the memory cell.

[0110] In one embodiment, the multi-time programmable memory cell 222m in the first array of the multi-time programmable memory cell 404a can be programmed a third time by selectively applying a voltage pulse having a magnitude of a third voltage V3 greater than the second voltage V2 to the memory cell.

[0111] In one embodiment, the first voltage V1 is the formation voltage of the ovonic threshold switch S of the multi-time programmable memory cell 222m. In one embodiment, before applying the first voltage V1, each multi-time programmable memory cell 222m has a first resistance R1. x of the multi-time programmable memory cell 222m. In one embodiment, the first resistance R1 is substantially equal to the first switch resistance R of the unformed ovonic threshold switch S of the multi-time programmable memory cell 222m. x (UF). For example, the first resistance R1 can be about 1 MΩ or some other value. OTS (UF). For example, the first resistance R1 can be about 1 MΩ or some other value.

[0112] In one embodiment, after applying one or more pulses having the magnitude of the first voltage V1, the multi-time programmable memory cell 222m has a second resistance R2.

[0113] R2 = R OTS (F) + R MTJ (P / AP) In one embodiment, the second resistance R2 is substantially equal to the second switch resistance R of the formed ovonic threshold switch S plus the resistance R of the magnetic tunnel junction memory element M of the multi-time programmable memory cell 222m. x of the multi-time programmable memory cell 222m. OTS (F) plus the resistance R of the magnetic tunnel junction memory element M of the multi-time programmable memory cell 222m. x of the multi-time programmable memory cell 222m. MTJ (P / AP).

[0114] As described above, the forming operation is irreversible, and the resistance of the formed threshold selector device S x cannot be switched back from the second switch resistance R OTS (F) to the first switch resistance R OTS (UF). In this regard, when the multi-time programmable memory cell 222m is programmed for the first time by applying a voltage pulse having a magnitude of the first voltage V1, the resistance of the threshold selector device S x of the multi-time programmable memory cell 222m changes irreversibly (or destructively).

[0115] In one embodiment, the resistance R MTJ (P / AP) is either a first memory element resistance (e.g., parallel resistance RP) or a second memory element resistance (e.g., antiparallel resistance RAP) that depends on the data state of the magnetic tunnel junction memory element M x .

[0116] For example, the second switch resistance R OTS (F) can be about 1 KΩ, the first memory element (parallel) resistance RP can be about 1.5 KΩ, the second memory element (antiparallel) resistance RAP can be about 3 KΩ, and thus the second resistance R2 can be between about 2.5 KΩ and about 4 KΩ, or some other value.

[0117] In one embodiment, the second voltage V2 is the breakdown voltage of the magnetic tunnel junction memory element M x of the multi-time programmable memory cell 222m. In one embodiment, when the second voltage V2 is applied, the magnetic tunnel junction memory element M x is short-circuited. In one embodiment, after applying one or more pulses having a magnitude of the second voltage V2, the magnetic tunnel junction memory element M x has a third memory element resistance R MTJ (BD). For example, the third memory element resistance R MTJ (BD) can be about 100 Ω or some other value.

[0118] In one embodiment, applying the second voltage V2 causes a short circuit in the magnetic tunnel junction memory element M x and this is irreversible. In this regard, programming the multi-time programmable memory cell 222m for the second time by applying a voltage pulse having the magnitude of the second voltage V2 causes the magnetic tunnel junction memory element M x of the multi-time programmable memory cell 222m to irreversibly (or destructively) change its resistance.

[0119] In one embodiment, after applying one or more pulses having the magnitude of the second voltage V2, the multi-time programmable memory cell 222m has a third resistance R3. R3 = R OTS (F) + R MTJ (BD) That is, the third resistance is substantially equal to the sum of the second switch resistance R OTS (F) and the third memory element resistance R MTJ (BD). For example, the resistance R OTS (F) may be about 1 KΩ, the breakdown resistance RMTJ(BD) may be about 100 Ω, and thus the third resistance R3 may be about 1.1 KΩ or some other value.

[0120] In an embodiment, the third voltage V3 is the open circuit voltage of the ovonic threshold switch S x and the magnetic tunnel junction memory element M x of the multi-time programmable memory cell 222m. In one embodiment, applying the third voltage V3 causes an open circuit in the ovonic threshold switch S x and the magnetic tunnel junction memory element M x and this is irreversible. In this regard, programming the multi-time programmable memory cell 222m for the third time by applying a voltage pulse having the magnitude of the third voltage V3 causes the threshold selector device S x and the magnetic tunnel junction memory element M xirreversibly (or destructively) change the resistance.

[0121] In one embodiment, after applying one or more pulses having a magnitude of a third voltage V3, the multi-time programmable memory cell 222m has a fourth resistance R4. For example, the fourth resistance R4 can be about 10 MΩ or some other value.

[0122] Thus, in one embodiment, the second resistance R2 is less than the first resistance R1, the third resistance R3 is less than the second resistance R2, and the fourth resistance R4 is greater than the first resistance R1. R3 < R2 < R1 < R4 In one embodiment, after the first programming, each multi-time programmable memory cell 222m in the first array of the multi-time programmable memory cell 404a has a first resistance R1 (e.g., a high resistance state or a "1" data state) or a second resistance R2 (e.g., a low resistance state or a "0" data state).

[0123] FIG. 6A1 shows exemplary resistance values of the multi-time programmable memory cell 222m after the first programming. In one embodiment, using a first reference Ref1, a multi-time programmable memory cell 222m having a low resistance state (or a "0" data state) and a multi-time programmable memory cell 222m having a high resistance state (or a "1" data state) can be distinguished.

[0124] The first reference Ref1 is shown as a resistance value, but those skilled in the art will understand that a reference current can be used to distinguish between a multi-time programmable memory cell 222m in a low resistance state (or a "0" data state) and a high resistance state (or a "1" data state).

[0125] In one embodiment, after the second programming, each multi-time programmable memory cell 222m in the first array of the multi-time programmable memory cell 404a has a first resistance R1, a second resistance R2, or a third resistance R3. In one embodiment, a multi-time programmable memory cell 222m having the first resistance R1 or the second resistance R2 is regarded as being in a high resistance state (e.g., "1" data state), and a multi-time programmable memory cell 222m having the third resistance R3 is regarded as being in a low resistance state (e.g., "0" data state).

[0126] FIG. 6A2 shows exemplary resistance values of the multi-time programmable memory cell 222m after the second programming. In one embodiment, using a second reference Ref2, a multi-time programmable memory cell 222m having a low resistance state (or "0" data state) and a multi-time programmable memory cell 222m having a high resistance state (or "1" data state) can be distinguished.

[0127] The second reference Ref2 is shown as a resistance value, but those skilled in the art will understand that a reference current can be used to distinguish between a multi-time programmable memory cell 222m in a low resistance state (or "0" data state) and a high resistance state (or "1" data state).

[0128] In one embodiment, after the third programming, each multi-time programmable memory cell 222m in the first array of the multi-time programmable memory cell 404a has a second resistor R2, a third resistor R3, or a fourth resistor R4. In such an embodiment, for increased margin, all unformed multi-time programmable memory cells 222m in the first array of the multi-time programmable memory cell 404a are formed. In one embodiment, the multi-time programmable memory cell 222m having the fourth resistor R4 is considered to be in a high resistance state (e.g., "1" data state), and the multi-time programmable memory cell 222m having the second resistor R2 or the third resistor R3 is considered to be in a low resistance state (e.g., "0" data state).

[0129] FIG. 6A3 shows exemplary resistance values of the multi-time programmable memory cell 222m after the third programming. In one embodiment, using a third reference Ref3, a multi-time programmable memory cell 222m having a low resistance state (or "0" data state) and a multi-time programmable memory cell 222m having a high resistance state (or "1" data state) can be distinguished.

[0130] Although the third reference Ref3 is shown as a resistance value, those skilled in the art will understand that a reference current can also be used to distinguish between a multi-time programmable memory cell 222m in a low resistance state (or "0" data state) and a high resistance state (or "1" data state).

[0131] As described above, when the multi-time programmable memory cell 222m is programmed for the first, second, or third time, the threshold selector device S x and the magnetic tunnel junction memory element M x the resistance of one or both of them changes irreversibly (or destructively).

[0132] While not wishing to be bound by any particular theory, the threshold selector device S xand the magnetic tunnel junction memory element M x By irreversibly (or destructively) changing the resistance of one or both of them, very high retention is considered to be achieved in the multi-time programmable memory cell 222m.

[0133] FIG. 7 is a diagram showing an embodiment of a method 700 for forming a multi-time programmable memory cell and a rewritable memory cell and programming the multi-time programmable memory cell.

[0134] In step 702, a first memory cell and a second memory cell are formed using the same manufacturing process. In one embodiment, each first memory cell and each second memory cell include the same structure including a magnetic tunnel junction memory element coupled in series with an ovonic threshold switch. In one embodiment, the first memory cell includes a first resistance.

[0135] In step 704, the first memory cell is programmed for the first time by applying one or more pulses having a magnitude of a first voltage V1. The first memory cell programmed for the first time includes a second resistance lower than the first resistance.

[0136] In step 706, the first memory cell is programmed for the second time by applying one or more pulses having a magnitude of a second voltage V2 greater than the magnitude of the first voltage V1. The first memory cell programmed for the second time includes a third resistance lower than the second resistance.

[0137] In step 708, the first memory cell is programmed for the third time by applying one or more pulses having a magnitude of a third voltage V3 greater than the magnitude of the second voltage V2. The first memory cell programmed for the third time includes a fourth resistance greater than the first resistance.

[0138] Although not wishing to be bound by any particular theory, with respect to the multi-time programmable memory cell 222m described above, the magnetic tunnel junction memory element M x is considered to be not important and to have substantially no effect on the operation of the multi-time programmable memory cell 222m described above.

[0139] In fact, as shown in FIGS. 6A1 to 6A3, although not wishing to be bound by any particular theory, for each of the first programming, the second programming, and the third programming, the determination of the data state of the multi-time programmable memory cell 222m is considered not to depend on the data state (and resistance) of the magnetic tunnel junction memory element M x within the memory cell.

[0140] Furthermore, although not wishing to be bound by any particular theory, whether the magnetic tunnel junction memory element M x is in the 0 state or the 1 state is considered not to affect the operation of the multi-time programmable memory cell 222m described above.

[0141] In fact, although not wishing to be bound by any particular theory, the multi-time programmable memory cell 222m is considered to be very elastic with respect to the process used to form the magnetic tunnel junction memory element M x within it.

[0142] Although not wishing to be bound by any particular theory, the multi-time programmable memory cell 222m is considered to function regardless of whether the magnetic tunnel junction memory element M x can be turned on and off.

[0143] Although not wishing to be bound by any particular theory, the reliability of the multi-time programmable memory cell 222m described above is considered not to be affected by any state change of the magnetic tunnel junction memory element M x within it.

[0144] However, in the second programming, by programming the magnetic tunnel junction memory element M x in parallel with the inverse resistance RAP, a margin for distinguishing between the multi-time programmable memory cell 222m having the second resistance R2 and the multi-time programmable memory cell 222m having the third resistance R3 can be improved.

[0145] While not wishing to be bound by any particular theory, it is contemplated that a cross-point array of memory cells can be formed using a single semiconductor manufacturing process, where each memory cell includes an ovonic threshold switch in series with a magnetic tunnel junction memory element, a first portion of the memory cells within the cross-point array can be used as multi-time programmable memory cells, and a second portion of the memory cells within the cross-point array can be used as rewritable memory cells.

[0146] One embodiment of the disclosed technology includes a memory cell that includes a reversible resistive switching memory element coupled in series with a selector element. The memory cell can be selectively configured as either a rewritable memory cell or a multi-time programmable memory cell. The selector element includes a first switch resistance and a second switch resistance. The resistive switching memory element includes a first memory element resistance and a second memory element resistance. The memory cell functions as a multi-time programmable memory cell regardless of whether the resistive switching memory element has the first memory element resistance or the second memory element resistance.

[0147] One embodiment of the disclosed technology includes an apparatus that includes a cross-point memory array that includes a plurality of memory cells, where each memory cell includes a magnetic tunnel junction memory element coupled in series with a selector element. Each memory cell within the cross-point memory array can be selectively configured as either a rewritable memory cell or a multi-time programmable memory cell that can be programmed the first, second, and third times.

[0148] One embodiment of the disclosed technology uses the same manufacturing process to form a first memory cell and a second memory cell, each first memory cell and each second memory cell having the same structure comprising a magnetic tunnel junction memory element coupled in series with an ovonic threshold switch, the first memory cell having a first resistance, forming the first memory cell and the second memory cell, and programming the first memory cell for the first time by applying one or more pulses including the magnitude of a first voltage, the first memory cell programmed for the first time including a second resistance lower than the first resistance, programming the first memory cell for the second time by applying one or more pulses including the magnitude of a second voltage greater than the magnitude of the first voltage, the first memory cell programmed for the second time including a third resistance lower than the second resistance, programming the first memory cell for the third time by applying one or more pulses including the magnitude of a third voltage greater than the magnitude of the second voltage, the first memory cell programmed for the third time including a fourth resistance greater than the first resistance, and a method including the above. The first memory cell includes a multi-time programmable memory cell, and the second memory cell includes a rewritable memory cell.

[0149] For the purposes of this document, the first layer may span or be above the second layer, if zero or one or more intervening layers are between the first layer and the second layer.

[0150] Note that for the purposes of this document, the dimensions of the various features shown in the drawings need not necessarily be drawn to scale.

[0151] For the purposes of this specification, references to "one embodiment", "an embodiment", "some embodiments" or "another embodiment" in the specification are used to describe different embodiments and need not necessarily refer to the same embodiment.

[0152] For the purposes of this specification, a connection may be a direct connection or an indirect connection (e.g., via another part). In some cases, when an element is referred to as being connected or coupled to another element, this element may be directly connected to the other element or indirectly connected to the other element via an intervening element. When an element is referred to as being directly connected to another element, there is no intervening element between this element and the other element.

[0153] For the purposes of this specification, the term "based on" can be read as "at least partially based on".

[0154] For the purposes of this specification, the use of numerical terms such as "first", "second", and "third" objects, without additional context, does not imply an order of the objects and may instead be used for identification purposes to distinguish different objects.

[0155] For the purposes of this specification, the term "set" of objects may refer to a "set" of one or more of the objects.

[0156] The subject matter is described in language specific to structural features and / or methodological acts, but it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as exemplary forms for carrying out the claims.

Claims

1. 1. An apparatus comprising: a memory cell comprising a reversible resistive switching memory element coupled in series with a selector element; the memory cells being selectively configurable as either rewritable memory cells or multi-time programmable memory cells; the selector element comprises a first switch resistor and a second switch resistor; the resistive switching memory element comprises a first memory element resistor and a second memory element resistor; the memory cell functions as a multiple-time programmable memory cell regardless of whether the resistive switching memory element has the first memory element resistance or the second memory element resistance; The memory cell is configured to be programmed a first time by applying one or more pulses comprising a first voltage; The device, wherein the memory cell is configured to be programmed a second time by applying one or more pulses comprising a second voltage greater than the first voltage.

2. The apparatus of claim 1 , wherein the first voltage comprises a configuration voltage for the selector element.

3. 10. The apparatus of claim 1, wherein the memory cell is configured to be programmed a third time by applying one or more pulses including a third voltage greater than the second voltage.

4. An apparatus comprising: a memory cell comprising a reversible resistive switching memory element coupled in series with a selector element; the memory cells being selectively configurable as either rewritable memory cells or multi-time programmable memory cells; the selector element comprises a first switch resistor and a second switch resistor; the resistive switching memory element comprises a first memory element resistor and a second memory element resistor; the memory cell functions as a multiple-time programmable memory cell regardless of whether the resistive switching memory element has the first memory element resistance or the second memory element resistance; the memory cell being configured as a multiple time programmable memory cell capable of having a first resistance and a second resistance; the first resistor comprises the first switch resistor, and the second resistor comprises the second switch resistor; The apparatus, wherein the memory cell is configured as a multiple time programmable memory cell capable of having a third resistance that comprises the second switch resistance.

5. 5. The apparatus of claim 4, wherein the third resistance further comprises a third memory element resistance lower than the first memory element resistance and the second memory element resistance.

6. An apparatus comprising: a memory cell comprising a reversible resistive switching memory element coupled in series with a selector element; the memory cells being selectively configurable as either rewritable memory cells or multi-time programmable memory cells; the selector element comprises a first switch resistor and a second switch resistor; the resistive switching memory element comprises a first memory element resistor and a second memory element resistor; the memory cell functions as a multiple-time programmable memory cell regardless of whether the resistive switching memory element has the first memory element resistance or the second memory element resistance; the memory cell being configured as a multiple time programmable memory cell capable of having a first resistance and a second resistance; the first resistor comprises the first switch resistor, and the second resistor comprises the second switch resistor; The apparatus, wherein the memory cells are configured as multiple time programmable memory cells capable of having a fourth resistance comprising an open circuit resistance of the resistive switching memory element and the selector element.

7. 7. Apparatus according to claim 1, wherein the first switch resistance is the resistance of the selector element as manufactured.

8. 7. The apparatus of claim 1, wherein the selector element is configured to irreversibly switch from the first switch resistance to the second switch resistance in response to a forming operation performed on the selector element.

9. 7. The apparatus of claim 4, wherein the second resistance further comprises the first memory element resistance or the second memory element resistance.

10. The apparatus of claim 1 , wherein the reversible resistive switching memory element comprises a magnetic tunnel junction memory element.

11. 7. Apparatus according to any preceding claim, wherein the selector element comprises an Ovonic threshold switch.

12. 1. An apparatus comprising: a cross point memory array comprising a plurality of memory cells, each memory cell comprising a magnetic tunnel junction memory element coupled in series with a selector element; each memory cell in the cross point memory array can be selectively configured as either a rewritable memory cell or a multi-time programmable memory cell that can be programmed a first time, a second time, and a third time; Each memory cell is configured to be programmed a first time by applying one or more pulses including a first voltage; Each memory cell is configured to be programmed a second time by applying one or more pulses including a second voltage greater than the first voltage; The device, wherein each memory cell is configured to be programmed a third time by applying one or more pulses including a third voltage greater than the second voltage.

13. An apparatus comprising: a cross point memory array comprising a plurality of memory cells, each memory cell comprising a magnetic tunnel junction memory element coupled in series with a selector element; each memory cell in the cross point memory array can be selectively configured as either a rewritable memory cell or a multi-time programmable memory cell that can be programmed a first time and a second time; Each memory cell is configured to be programmed a first time by applying one or more pulses including a first voltage; The device, wherein each memory cell is configured to be programmed a second time by applying one or more pulses including a second voltage greater than the first voltage.

14. 14. Apparatus according to claim 12 or claim 13, wherein the selector element comprises an Ovonic threshold switch.

15. Each selector element comprises a first switch resistor and a second switch resistor; each magnetic tunnel junction memory element configured to reversibly switch between a first memory element resistance and a second memory element resistance; each memory cell is configured as a multiple-time programmable memory cell that functions regardless of whether the magnetic tunnel junction memory element has the first memory element resistance or the second memory element resistance; 14. Apparatus according to claim 12 or claim 13.

16. 1. A method comprising: forming a first memory cell and a second memory cell using the same fabrication process, each of the first memory cell and each of the second memory cells having the same structure comprising a magnetic tunnel junction memory element coupled in series with an Ovonic threshold switch, the first memory cell comprising a first resistance; programming the first memory cell a first time by applying one or more pulses having a first voltage magnitude, the first programmed first memory cell comprising a second resistance lower than the first resistance; programming the first memory cell a second time by applying one or more pulses including a second voltage magnitude greater than the magnitude of the first voltage, the second programmed first memory cell including a third resistance lower than the second resistance; programming the first memory cell a third time by applying one or more pulses including a third voltage magnitude greater than the magnitude of the second voltage, the third programmed first memory cell including a fourth resistance greater than the first resistance; The method, wherein the first memory cells comprise multi-time programmable memory cells and the second memory cells comprise re-writeable memory cells.

17. A method comprising: forming a first memory cell and a second memory cell using the same fabrication process, each of the first memory cell and each of the second memory cells having the same structure comprising a magnetic tunnel junction memory element coupled in series with an Ovonic threshold switch, the first memory cell comprising a first resistance; programming the first memory cell a first time by applying one or more pulses having a first voltage magnitude; programming the first memory cell a second time by applying one or more pulses comprising a second voltage magnitude greater than the magnitude of the first voltage; The method, wherein the first memory cells comprise multi-time programmable memory cells and the second memory cells comprise re-writeable memory cells.

18. The method of claim 17, further comprising programming the first memory cell a third time by applying one or more pulses including a third voltage magnitude greater than the magnitude of the second voltage.

19. 19. The method of claim 16, wherein the first memory cell and the second memory cell comprise a cross-point memory array.

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