Control Circuit and Semiconductor Memory Device

Abstract

To provide a control circuit that can prevent the delay operation from becoming long and complete a sequence for adjusting the delay of an internal clock signal using a DLL circuit within a specified execution period.SOLUTION: A control circuit 1 includes a control unit that sets a delay amount on the basis of the phase difference between an input clock signal clk and an output clock signal, and a delay line unit 14 that performs a delay operation of delaying the input clock signal clk in accordance with the delay amount to generate an output clock signal, the delay line unit 14 includes a plurality of delay units each having one or more delay elements that delay the input clock signal clk, and the number of delay elements in one delay unit is greater than the number of delay elements in another delay unit.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present invention relates to a control circuit and a semiconductor memory device.

Background Art

[0002] DRAM (Dynamic Random Access Memory), which is a type of semiconductor memory device, is a volatile memory that stores information by accumulating electric charges in capacitors, and the stored information is lost when the power supply is cut off. A delay locked loop (DLL) circuit is provided in the DRAM as a phase synchronization circuit. The DRAM uses the DLL circuit to generate an internal clock signal for outputting a data signal in synchronization with an input clock signal input from the outside (see, for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] By the way, when adjusting the delay of the internal clock signal using the DLL circuit, for example, a sequence including a reset operation of the DLL circuit, a delay (lock) operation of the DLL circuit (for example, an operation of synchronizing the external clock and the internal clock while activating one delay line at a time), and a detection operation of an N value indicating the number of delay clock cycles between the input clock signal and the internal clock signal is executed.

[0005] Here, the lock time Tdll due to the delay operation of the DLL circuit can be expressed by the following formula. Tint + Tdll = N × tCK

[0006] In the above formula, Tint represents the inherent delay time in the DLL circuit, and tCK represents the clock cycle. For example, when the clock cycle (tCK) becomes longer than the inherent delay time (Tint) due to the temperature or the like inside the semiconductor memory device, the lock time (Tdll) due to the delay operation of the DLL circuit also becomes longer as shown in the above formula. When the lock time becomes longer in this way, the execution time of the entire above sequence becomes longer, and there is a risk that the execution of the next sequence is delayed or that the execution period (tDLLK) of the predetermined sequence is exceeded.

[0007] The present invention has been made in view of the above problems, and aims to provide a control circuit, a semiconductor memory device, and a control method for a semiconductor memory device that can suppress the prolongation of the delay operation and complete a sequence for adjusting the delay of an internal clock signal using a DLL circuit within a predetermined execution period.

Means for Solving the Problems

[0008] The control circuit of the present invention is a control circuit including a control unit that sets a delay amount based on a phase difference between an input clock signal and an output clock signal, and a delay line unit that performs a delay operation of delaying the input clock signal to generate the output clock signal corresponding to the delay amount, wherein the delay line unit includes a plurality of delay units each having one or more delay elements for delaying the input clock signal, and the number of delay elements included in one of the delay units is larger than the number of delay elements included in another delay unit.

[0009] Since the number of delay elements included in one of the delay units is larger than the number of delay elements included in another delay unit, a large number of delay elements can be used only by activating one unit, and the delay amount can be achieved quickly. Therefore, the lock time required to cancel the same delay amount can be shortened, the prolongation of the delay operation can be suppressed, and a sequence for adjusting the delay of an internal clock signal using a DLL circuit can be completed within a predetermined execution period.

[0010] The delay units are connected in series and are used in order from one end side to the other end side according to the set delay amount, and the number of the delay elements included in the delay unit on the other end side is preferably larger than the number of the delay elements included in the delay unit on the one end side.

[0011] The number of the delay elements included in each of the delay units from the other end side to a predetermined position is preferably larger than the number of the delay elements included in each of the delay units from the predetermined position to the one end side.

[0012] The number of each of the delay units from the other end side to a predetermined position is preferably larger than the number of each of the delay units from the predetermined position to the one end side. The number of the delay elements included in the adjacent delay units via the predetermined position preferably differs by one. It is preferable to provide a plurality of the predetermined positions and the number of the delay units between each of the predetermined positions is the same. It is preferable to provide a plurality of the predetermined positions and the number of the delay elements included in the adjacent delay units via the predetermined position differs by one.

[0013] The control unit preferably sets the number of the delay units to be used for the delay operation corresponding to the delay amount.

[0014] The delay line unit preferably activates, among the delay units connected in series, the delay units from the delay unit at the one end side where the input clock signal is input to the delay units corresponding to the set number of the delay units, and delays the input clock signal using these activated delay units.

[0015] The delay line unit preferably activates the delay units corresponding to the number of the delay units, among the delay units connected in series, and delays the input clock signal using the delay unit at the one end side where the output clock signal is output from the activated delay unit.

[0016] It is preferable that the delay element is composed of a NAND gate. It is preferable that the delay element included in the delay unit is composed of two NAND gates or three NAND gates.

[0017] The semiconductor memory device of the present invention preferably includes the control circuit described in any of the above. The semiconductor memory device is preferably a dynamic random access memory.

Advantages of the Invention

[0018] According to the control circuit and the semiconductor memory device of the present invention, it is possible to suppress the prolongation of the delay operation and complete the sequence for adjusting the delay of the internal clock signal using the DLL circuit within a predetermined execution period.

Brief Description of the Drawings

[0019]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Embodiments for Carrying Out the Invention

[0020] Hereinafter, a control circuit, a semiconductor memory device, and a control method of the semiconductor memory device according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings. However, this embodiment is an example, and the present invention is not limited thereto.

[0021] (Embodiment 1) FIG. 1 shows a configuration example of a control circuit according to an embodiment of the present invention. In this embodiment, the control circuit 1 is provided in a semiconductor memory device such as a DRAM. In this embodiment, for simplicity of explanation, well-known configurations provided in a semiconductor memory device such as a DRAM (for example, a command decoder, a memory cell array, an input / output interface unit, etc.) are not shown.

[0022] The control circuit 1 includes an input buffer 11, a phase detection unit 12, a DLL control unit 13, a delay line unit 14, a replica unit 15, and an output buffer 16.

[0023] The input buffer 11 buffers an external clock signal CK input to the input buffer 11 to generate an input clock signal clk. The generated input clock signal clk is transmitted to the delay line unit 14 and the phase detection unit 12. Although details will be described later, the delay line unit 14 generates a delayed signal (output clock signal) dll_clk obtained by delaying the input input clock signal clk, and transmits it to the output buffer 16 and the replica unit 15. The replica unit 15 outputs the delayed signal dll_clk generated by the delay line unit 14 to the phase detection unit 12 as a feedback signal fb_clk.

[0024] The phase detection unit 12 detects the phase difference between the input clock signal clk and the feedback signal fb_clk. The input clock signal clk and the feedback signal fb_clk are input to the phase detection unit 12. In the phase detection unit 12, a phase signal up / down indicating the advance or delay of the phase of the feedback signal fb_clk with respect to the input clock signal clk is generated and input to the DLL control unit 13.

[0025] The DLL control unit 13 determines the delay amount from the phase difference detected by the phase detection unit 12. Then, as a signal indicating the delay amount in the lock operation (an example of the "delay operation" of the present invention), the DLL control unit 13 generates and outputs a control signal dll_code and a selection control signal select (described later), which are composed of a plurality of bits. The output control signal dll_code and selection control signal select are input to the delay line unit 14.

[0026] The delay line unit 14 is a variable delay unit that performs a lock operation of delaying the input clock signal clk based on the delay amount and generating a delay signal dll_clk (output clock signal) every time the delay amount is set by the DLL control unit 13, and outputs it to the output buffer 16.

[0027] The configuration of the delay line unit 14 will be described with reference to FIG. 2. As shown in FIG. 2, the delay line unit 14 includes a multiplexer 21 and a NAND gate array 22 configured by connecting a plurality of NAND gates N (when distinguishing them individually, a number is attached after N) in series. The delay element is composed of a component (NAND gate N) that delays the clock signal, and in this embodiment, it is composed of two NAND gates N connected in series. Note that only a part of the NAND gate array 22 is shown in FIG. 2.

[0028] For each NAND gate N, the input clock signal clk is input to the NAND gate N1 which is the most upstream side (the leftmost end in the figure) in the NAND gate array 22, and the output from the immediately preceding serially connected NAND gate N is input to the other NAND gates N. Here, the end side where the input clock signal clk is input in the NAND gate array 22 is referred to as the upstream side, and the opposite side is referred to as the downstream side.

[0029] Further, the NAND gate array 22 is divided into a plurality of units U (delay units. When distinguishing individual units below, a number is appended after U). That is, in the present embodiment, not only the NAND gates N but also the units U are connected in series. The units U are configured such that the numbers of the units U1, U2, etc. increase from the upstream side toward the downstream side with the unit U1 being the upstream most unit.

[0030] Here, the code signal of the control signal dll_code composed of a plurality of bits generated by the DLL control unit 13 <n>is input for each unit U. That is, for unit Un, the code signal <n>is input, and the NAND gates N included in one unit U each have the same code signal <n>is input. This code signal <n>determines which unit to activate, <n>If it is "1", the unit Un is configured to be activated. For example, the NAND gates N1 and N2 included in the unit U1 are each input with the code signal <1> of the same control signal dll_code. If the value of the code signal is "1", the NAND gates N1 and N2 (unit U1) are activated.

[0031] Also, in each unit U, the output of the NAND gate N at the last stage (the most downstream side) is input as the unit signal unit for the multiplexer 21. A selection control signal select is input to the multiplexer 21. The selection control signal select is a signal indicating which unit signal unit of which unit U is to be selected. Among the unit signals unit for the multiplexer 21, the unit signal unit selected by the selection control signal select is input and output as the delay signal dll_clk.

[0032] In the lock operation, the input clock signal clk is input from the unit U1 on the upstream side (one end side. In the present invention, among the serially connected units U, the first used unit U corresponds to the one end side). The units Un corresponding to the number of NAND gates N required to achieve the delay amount set by the DLL control unit 13 are sequentially activated, and the input clock signal clk is delayed using these activated units U. For example, when it is set that the unit U9 is to be activated to achieve the delay amount by the DLL control unit 13, the DLL control unit 13 generates a selection control signal select indicating that the unit U9 is to be selected, and a control signal dll_code including a code signal for activating the units from U1 to U9 is generated, and these are input to the delay line unit 14. In this case, the units from U1 to U9 are activated and a unit signal unit9 with the input clock signal clk delayed is generated. Then, in the multiplexer 21, the unit signal unit9 from the unit U9 is selected and output as the delay signal dll_clk.

[0033] Here, in the present embodiment, the number of stages of the NAND gates N varies among the respective units U. For example, unit U1 consists of two-stage NAND gates (NAND gates N1 and N2), and unit U8 consists of four-stage NAND (NAND gates N7, N8, N9, and N10). This will be described with reference to FIG. 3. FIG. 3 is a diagram schematically showing the relationship between the unit U and the NAND gate N in the delay line section 14 of the present embodiment. Each square represents a unit U, and the number of the unit U (for example, "1" represents unit U1) is shown at the upper left of the square, and the number of stages of the NAND gate N included in the unit U is shown inside the square. The larger the number of NAND gates N included in each unit U, the larger the display of each unit. As shown in this FIG. 3, in the present embodiment, from unit U1 to unit U8, the NAND gate N has two stages respectively, from unit U9 to unit U16, the NAND gate N has four stages, from unit U17 to unit U24, the NAND gate N has six stages, and from unit U25 to unit U32, the NAND gate N has eight stages, and the NAND gate array 22 is configured accordingly.

[0034] The conventional delay line section was also configured by connecting a plurality of NAND gates N in series and was divided into a plurality of units U. However, the difference between the present embodiment and the conventional delay line section is that all units in the conventional delay line section consist of two-stage NAND gates. In a control circuit having such a conventional delay line section, it took time to activate a desired number of delay units when the delay amount was large. That is, conventionally, even when the delay amount was large, each unit was activated sequentially from one end side to delay the input clock signal until it matched the output clock signal, and a locking operation was performed. In this case, when the delay amount was large, if the input clock signal was sequentially activated from the unit at the end until it matched the clock signal and used for the delay operation, the locking operation took a long time.

[0035] In contrast, in the present embodiment, unlike such a conventional delay line unit, since the number of stages of the NAND gate N varies depending on the unit U, it is possible to suppress the lengthening of the lock time Tdll. That is, in order to activate the unit U corresponding to the number of NAND gates N required to achieve the delay amount, when activating the unit U from one end side in order, since there is a portion where the number of stages of the NAND gate N included in the unit U is large, many NAND gates N can be activated by activating only one unit U, so that the delay amount can be achieved quickly. This will be described with reference to FIGS. 4 and 5. FIG. 4 schematically shows the number of stages of NAND gates required for the delay amount, and FIG. 5 schematically shows the lock time (Tdll) required for the delay amount.

[0036] In the case of the lock operation for the delay amount that requires delaying using 36 stages of the NAND gate N, in the conventional delay line unit shown in FIG. 4(1), it is necessary to sequentially activate 18 units U from unit U1 to unit U18. However, in the case of the delay line unit 14 of the present embodiment shown in FIG. 4(2), in the case of the lock operation for the delay amount that requires delaying using 36 stages of the NAND gate N, it is only necessary to sequentially activate 13 units U from unit U1 to unit U13. This is because in the present embodiment, up to unit U8, the NAND gate N of each unit U is 2 stages each, but from unit U9, the number of NAND gates N of each unit U is 4 stages each, and in order to activate 36 stages of the NAND gate N, it is only necessary to activate 13 units.

[0037] In this case, as shown in FIG. 5(1), in the case of the conventional delay line unit, 18 units' worth of lock time was required to complete the lock operation, but in the delay line unit 14 of the present embodiment, since it is only necessary to activate 13 units, the lock operation can be completed with 13 units' worth of lock time.

[0038] Thus, in this embodiment, since the number of stages of the NAND gates N constituting the downstream unit U is larger than the number of stages of the NAND gates N of the upstream unit U, activation of the number of NAND gates N required to eliminate the delay time can be achieved earlier, and the lock time Tdll can be shortened. As a result, the execution time Tdllk of the sequence corresponding to the lock time can also be shortened. When increasing the number of stages of the NAND gates N, since each delay element, that is, in this embodiment, two NAND gates N are regarded as one set (delay element), the number of NAND gates N is increased by two at a time.

[0039] Furthermore, in this embodiment, without changing the control in the DLL control unit 13, it can be configured simply by changing the number of stages of the NAND gates N in the unit U from the conventional delay circuit (that is, by only changing the wiring), and the lock time Tdll can be shortened, so it can be executed very simply.

[0040] Also, in this embodiment, the number of stages of the NAND gates N of the downstream unit U is made larger than that of the upstream side. However, at least in the NAND gate array 22, it is sufficient that there is a unit U in which the number of NAND gates N is larger than the number of NAND gates N of other units U. Even in this case, activation of the number of NAND gates N required to eliminate the delay time can be achieved earlier.

[0041] If only the reduction of the lock time is considered, it may be possible to increase the number of stages of the NAND gate N in all units U compared to the conventional case. However, as described above, it is preferable to increase the number of NAND gates N in at least some of the units U because appropriate control according to the delay amount can be performed. In particular, by increasing the number of stages of the NAND gate in the downstream unit U more than that in the upstream unit as in the present embodiment, it is possible to perform more appropriate control according to the delay amount. That is, in the present embodiment, the number of stages of the NAND gate N in each unit U is set to be small (for example, two stages as in the conventional case) in the upstream unit U, and the number of stages is increased in the downstream unit U. When the delay amount is small, the lock operation can be appropriately performed sufficiently using only these upstream units U. When the delay amount is large, the downstream unit U with a large number of stages will be used. However, in these downstream units U, since the number of stages of the NAND gate N is large, it is possible to end the lock operation earlier than in the conventional case.

[0042] Therefore, in the present embodiment, as shown in FIG. 3, the number of stages of the NAND gate N is increased by two for every eight units, but it is not limited to this. It may be configured such that the number of NAND gates N in the unit U increases at least on the downstream side (the other end side) rather than the upstream side (one end side). That is, one predetermined position is set, and all the units U included from the upstream side to the predetermined position have the same number of stages of the NAND gate N, and all the units U included from the predetermined position to the downstream side have the same number of stages of the NAND gate N.

[0043] Also, it is preferable to install such a predetermined position relatively downstream (the other end side). For example, one predetermined position is set after the unit U16, and up to the units U1 to U16, each unit U includes two NAND gates N in each stage, and only the last units U17 to U are configured to include four NAND gates N in each stage. With this configuration, in these downstream units U, since the number of stages of the NAND gates N is large, even when the delay amount using the unit U17 is very large, it is possible to end the lock operation earlier than before. Also, the predetermined position may be provided irregularly in the NAND gate array 22. For example, if the predetermined positions are provided at the 8th unit and the 12th unit respectively, up to the units U1 to U8, each unit U includes two NAND gates N in each stage, up to the units U9 to U12, each unit U includes four NAND gates N in each stage, and only the last units U13 to U24 are configured to include six NAND gates N in each stage. Even with this configuration, in these downstream units U, since the number of stages of the NAND gates N is large, it is possible to end the lock operation earlier than before.

[0044] Also, in this embodiment, the number of stages of the NAND gates N increases by one delay element for each predetermined position and by two NAND gates N in terms of the number of NAND gates N, but this is not limited. For example, if one predetermined position is set after the unit U16, up to the 16th unit, each unit U includes two NAND gates N in each stage, and only the last 17th to 24th units are configured to include eight NAND gates N in each stage. It is preferable for fine control that the number of stages gradually increases, but when performing the lock operation using the latter units U, since the lock time is prolonged, the number of stages may be increased significantly at once.

[0045] (Embodiment 2) In the above-described embodiment, the multiplexer 21 was provided on the output side. However, in this embodiment, the delay line unit 14 is configured using a selector on the input side instead of the multiplexer 21, which is different from the first embodiment. The delay line unit 14 of this embodiment will be described with reference to FIG. 6. In this embodiment, the delay line unit 14 includes a selector (not shown) and a NAND gate array 32 composed of a plurality of NAND gates N. Note that only a part of the NAND gate array 32 is shown in FIG. 6.

[0046] The NAND gate array 32 is composed of two columns of NAND gate arrays. Specifically, the NAND gate array 32 includes a first NAND gate array 33 and a second NAND gate array 34. The first NAND gate array 33 is configured by connecting a plurality of NAND gates N in series and has odd-numbered NAND gates NA and even-numbered NAND gates NB. The second NAND gate array 34 is composed of a plurality of NAND gates NC that are connected in parallel and each is connected to the even-stage NAND gate NB. These NAND gates NA, NB, and NC are configured as one delay element.

[0047] In this embodiment, the NAND gate array 32 is divided so as to include one or more delay elements, and each unit U is configured. That is, also in this embodiment, the units U are connected in series, and the number of NAND gates N is different for each unit U. Further, in this embodiment, the unit U is numbered from the downstream side (one end side), which is the opposite side of the upstream side (the other end side) to which the input clock signal clk is input. For example, the total number of NAND gates N included in the downstream unit U8 is 3, but the number of NAND gates N in the adjacent unit U9 is 6. Thus, in this embodiment, the predetermined position is at unit U8, and all of the units U16 (not shown) to U9 on the upstream side across the predetermined position have 4 stages of NAND gates N, and all of the units U8 to U1 on the downstream side (one end side) across the predetermined position are configured to have 2 stages of NAND gates N.

[0048] To the even-stage NAND gate NB in the first NAND gate column 33, the output of the odd-stage NAND gate NA and the output of the NAND gate NC are input. To the NAND gate NC, the input clock signal clk and the code signal or 0 signal of the control signal dll_code are input. The code signal is the code signal of the same number as the number of the corresponding unit U <n>is input. For example, a code signal <7> is input to the unit U7.

[0049] In this embodiment, only the unit U selected by the control signal input to the selector is activated. In the activated unit U, the input clock signal clk is delayed through the NAND gates NC and NB of the unit U, and the input clock signal clk input to the NAND gate NB is further input to the adjacent NAND gate NA and delayed while passing through the units U of the NAND gate column 33, and is output as a delayed signal dll_clk.

[0050] That is, in this embodiment, the delay line unit 14 activates only the units U corresponding to the number of NAND gates N required to achieve the set delay amount among the serially connected units U, and from this activated unit U to the unit U1 at the downstream end from which the delay signal dll_clk is output, the input clock signal clk is delayed. For example, when it is set that the unit U9 is activated by the DLL control unit 13, a selection control signal select indicating that the unit U9 is selected is input, the unit U9 is activated, and as a result, from the unit U1 to the unit U9 are used for the delay operation, and a delayed signal dll_clk obtained by delaying the input clock signal clk is generated and output. At this time, the number of stages of the NAND gate N of the unit U8 used for the delay operation is 2 stages, and the number of stages of the NAND gate N of the unit U9 used for the delay operation is 4 stages, and the delay amount is the same as that of the units U8 and U9 in the first embodiment. In addition, in a unit U including a plurality of delay elements such as the unit U9, the NAND gates NC other than the upstream NAND gate NC are input with the input clock signal clk and the 0 signal.

[0051] Also in this embodiment, since the number of NAND gates N constituting the unit U from a predetermined position to a predetermined position is larger than that of the NAND gates N of other units U, when the delay amount is large, a desired number of NAND gates N can be used quickly, and as a result, the lock time Tdll can be shortened. As a result, the execution time (Tdllk) of the sequence corresponding to the lock time can also be shortened. (Modification example)

[0052] In the above-described embodiments, the delay element is the NAND gate N in all cases, but the present invention is not limited to this. Further, the configuration of the delay line unit 14 is not limited either.

[0053] In the above-described embodiments, the case where the semiconductor recording device including the control circuit is a DRAM has been described as an example, but the present invention is not limited to this case. For example, the semiconductor memory device may be an SRAM (Static Random Access Memory), a flash memory, or other semiconductor memory devices.

[0054] The above-described embodiments and modification examples have been described to facilitate the understanding of the present invention, and are not described to limit the present invention. Therefore, each element disclosed in the above embodiments and modification examples is intended to include all design changes and equivalents belonging to the technical scope of the present invention.

[0055] The configuration of the DLL circuit 10 in the above-described embodiment is an example, and may be appropriately changed, or various other configurations may be adopted.

Description of reference numerals

[0056] 1 Control circuit 10 DLL circuit 11 Input buffer 12 Phase detection unit 13 DLL control unit 14 Delay line unit 15 Replica unit 16 Output buffer 21 Multiplexer 22 NAND gate array 24 delay line section 32 NAND gate array 33 First NAND gate array 34 Second NAND gate array CK External clock signal N NAND gates U Unit clk Input clock signal dll_clk Delay signal (output clock signal) dll_code Control signal fb Feedback signal select Selection control signal unit Unit signal up / down Phase signal< / n> < / n> < / n> < / n> < / n> < / n>

Claims

1. A control circuit comprising: a control unit configured to set a delay amount based on a phase difference between an input clock signal and an output clock signal; and a delay line unit configured to perform a delay operation of delaying the input clock signal in accordance with the delay amount to generate the output clock signal, wherein the delay line unit includes a plurality of delay units each having one or more serially-connected delay elements for delaying the input clock signal, the number of delay elements included in one of the delay units is larger than the number of delay elements included in another one of the delay units, and the delay line unit activates delay units corresponding to the set number of delay units from a delay unit at one end side where the input clock signal is input among the serially-connected delay units, and delays the input clock signal using these activated delay units.

2. The delay units are serially connected and are used in order from one end side to the other end side according to the set delay amount, and the number of delay elements included in the delay unit at the other end side is larger than the number of delay elements included in the delay unit at the one end side. The control circuit according to claim 1.

3. The number of delay elements included in each of the delay units from the other end side to a predetermined position is larger than the number of delay elements included in each of the delay units from the predetermined position to the one end side. The control circuit according to claim 2.

4. The number of each of the delay units from the other end side to a predetermined position is larger than the number of each of the delay units from the predetermined position to the one end side. The control circuit according to claim 2.

5. The number of delay elements included in the delay units adjacent to each other via the predetermined position differs by one. The control circuit according to claim 3.

6. The control circuit includes a plurality of the predetermined positions, and the number of delay units between each of the predetermined positions is the same. The control circuit according to claim 3.

7. The control circuit includes a plurality of the predetermined positions, and the number of delay elements included in the delay units adjacent to each other via the predetermined position differs by one. The control circuit according to claim 3.

8. The control unit sets the number of delay units to be used for the delay operation according to the delay amount. The control circuit according to claim 2.

9. A replica part configured to generate a feedback signal according to the output clock signal; A phase detection part coupled between the replica part and the control part, which receives the input clock signal and the feedback signal and is configured to generate a phase signal for indicating the phase difference to the control part; The control part generates a control signal and a selection control signal indicating the delay amount according to the phase signal, and the delay line part activates a corresponding delay element among the one or more delay elements according to the control signal and the selection control signal to delay the input clock signal. The control circuit according to claim 1.

10. A control circuit including a control part configured to set a delay amount based on a phase difference between an input clock signal and an output clock signal, and a delay line part configured to perform a delay operation of delaying the input clock signal according to the delay amount to generate the output clock signal. The delay line part includes a plurality of delay units having one or more delay elements connected in series for delaying the input clock signal. The number of delay elements included in one of the delay units is larger than the number of delay elements included in another delay unit. The delay line part activates the delay unit corresponding to the number of the delay units among the delay units connected in series, and uses the delay unit at one end side from which the output clock signal is output among the activated delay units to delay the input clock signal. The control circuit is characterized in that.

11. The control circuit according to claim 2, wherein the delay element is composed of a NAND gate.

12. The control circuit according to claim 9, wherein the delay element included in the delay unit is composed of two NAND gates.

13. The control circuit according to claim 10, wherein the delay element included in the delay unit is composed of three NAND gates.

14. A semiconductor memory device characterized by comprising the control circuit according to any one of claims 1 to 13.

15. The semiconductor memory device according to claim 14, wherein the semiconductor memory device is a dynamic random access memory.

16. The delay units are connected in series and are used in order from one end side to the other end side according to the set delay amount, and the number of the delay elements included in the delay unit on the other end side is larger than the number of the delay elements included in the delay unit on the one end side. The control circuit according to claim 10, characterized in that.

17. A replica unit configured to generate a feedback signal according to the output clock signal; A phase detection unit coupled between the replica unit and the control unit, the phase detection unit receiving the input clock signal and the feedback signal and configured to generate a phase signal for indicating the phase difference to the control unit. A phase detection unit; The control unit generates a control signal and a selection control signal indicating the delay amount according to the phase signal, and the delay line unit corresponds to the one or more delay elements according to the control signal and the selection control signal. The control circuit according to claim 10, characterized in that the input clock signal is delayed by activating the delay element.

Images