Amplifying device and transmitting device

Abstract

To provide an amplifier that suppresses harmonics of an output signal.SOLUTION: An amplifier 1 according to an embodiment of the present invention includes a switching amplifier 11, and an adjustment portion, and the switching amplifier is driven on the basis of a control signal, and amplifies the input signal to be amplified to generate an amplified signal. The adjustment portion adjusts the control signal before it is inputted to the switching amplifier. Specifically, the adjustment portion adjusts at least one of the pulse width of the control signal and the delay time of the control signal with respect to the signal to be amplified.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] Embodiments of the present invention relate to a t-amplifier and a transmission device.

Background Art

[0002] Switching amplifiers used for amplifying rectangular signals are used in various devices, but the output signals from the switching amplifiers contain high-order harmonic components. Therefore, generally, it is necessary to separately provide a function for suppressing high-order harmonics. For example, a multi-stage band-pass filter (BPF), a load circuit for suppressing specific harmonics, etc. are used together with the switching amplifier.

[0003] However, if a function for suppressing high-order harmonics is separately provided, the circuit scale increases. In addition, there is also a problem that circuit adjustment takes time due to an increase in circuit parameters.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Summary of the Invention

Problems to be Solved by the Invention

[0005] One embodiment of the present invention provides an amplifier device that suppresses harmonics of an output signal.

Means for Solving the Problems

[0006] An amplifier according to an embodiment of the present invention includes a switching amplifier and an adjustment unit. The switching amplifier is driven based on a control signal and amplifies an input signal to be amplified to generate an amplified signal. The adjustment unit adjusts the control signal before it is input to the switching amplifier. Specifically, the adjustment unit adjusts at least one of the pulse width of the control signal and the delay time of the control signal with respect to the signal to be amplified.

Brief Description of the Drawings

[0007]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Embodiments for Carrying Out the Invention

[0008] Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[0009] (First Embodiment) FIG. 1 is a block diagram showing an example of an amplifier device 1 according to the first embodiment. The amplifier device 1 according to the present embodiment includes a switching amplifier 11 and an adjustment unit 12. The adjustment unit 12 includes a pulse width adjustment circuit 121 and a delay circuit 122.

[0010] The amplifier device 1 of the present embodiment is a device that amplifies a rectangular signal to be amplified input to the amplifier device 1. Hereinafter, the signal to be amplified will be referred to as the "amplification target signal", and the amplified signal will be referred to as the "amplified signal". It is assumed that the amplifier device 1 of the present embodiment may perform amplification once in each of the maximum (HIGH) section and the minimum (LOW) section of the amplification target signal. It is assumed that the period for performing amplification is not particularly defined.

[0011] Further, even if the amplifier device 1 does not include a band-pass filter (BPF) or the like, it suppresses high-order harmonic components included in the amplified signal. Specifically, based on the amplification target signal, the high-order harmonic components are suppressed by adjusting the drive timing and drive period of the switching amplifier 11.

[0012] The switching amplifier 11 amplifies the input amplification target signal to generate an amplified signal when driven. Whether to perform amplification is determined by a control signal input to the switching amplifier 11. That is, the control signal controls the drive (ON / OFF) of the switching amplifier 11, and the switching amplifier 11 is driven based on the control signal.

[0013] In this description, it is assumed that the control signal is represented by a binary value of 0 or 1. When the value of the control signal is 1, the switching amplifier 11 is turned on and an amplified signal is output. When the value of the control signal is 0, the switching amplifier 11 is turned off and there is no output. In other words, it is assumed that 0V is output.

[0014] If the switching amplifier 11 can be driven based on a control signal and amplify the signal to be amplified, its configuration is not particularly limited. For example, the switching amplifier 11 can be realized using a full-bridge circuit. The full-bridge circuit is composed of four transistors operating as switches configured in a full-bridge shape.

[0015] FIG. 2 is a diagram showing an example of the configuration of the switching amplifier 11. FIG. 2 shows an example in which the switching amplifier 11 is realized by a full-bridge circuit. The four transistors described above are referred to as the first transistor Q1, the second transistor Q2, the third transistor Q3, and the fourth transistor Q4. Specifically, the first transistor Q1 and the second transistor Q2 are connected in parallel, and the third transistor Q3 and the fourth transistor Q4 are also connected in parallel. Also, the first transistor Q1 and the third transistor Q3 are connected in series, and the second transistor Q2 and the fourth transistor Q4 are also connected in series.

[0016] In addition, the power supply voltage Vd is applied to the connection point between the first transistor Q1 and the second transistor Q2, and the connection point between the third transistor Q3 and the fourth transistor Q4 is connected to the ground (GND). The first transistor Q1 and the second transistor Q2 on the power supply voltage side are also referred to as the first high-side transistor and the second high-side transistor, respectively. The third transistor Q3 and the fourth transistor Q4 on the GND side are also referred to as the first low-side transistor and the second low-side transistor, respectively.

[0017] Also, in the example of Fig. 2, one transformer L is incorporated in the full-bridge circuit. It is assumed that the amplified voltage is output via this transformer L. One end of the transformer L is connected to the connection point between the first transistor Q1 and the third transistor Q3. On the other hand, the other end of the transformer L is connected to the connection point between the second transistor Q2 and the fourth transistor Q4. In the example of Fig. 2, amplification is performed by applying the power supply voltage to this transformer L. That is, when the control signal is 1, a potential difference is created between both ends of the transformer L, and when the control signal is 0, each transistor is controlled so that there is no potential difference between both ends of the transformer L.

[0018] Each transistor is controlled based on at least one of the signal to be amplified and the control signal. In the example of Fig. 2, the first transistor Q1 switches according to the input signal to be amplified. The second transistor Q2 switches according to the inverted signal of the signal to be amplified when the inverted signal is input. The third transistor Q3 switches according to the inverted signal of the signal to be amplified and the inverted signal of the control signal. In the example of Fig. 2, the inverted signal of the signal to be amplified is input to the input line of the third transistor Q3, and a first switch SW1 that switches according to the inverted signal of the control signal is connected to the input line. Thereby, the third transistor Q3 can switch according to the inverted signal of the signal to be amplified and the inverted signal of the control signal. The fourth transistor Q4 switches according to the signal to be amplified and the inverted signal of the control signal. In the example of Fig. 2, the signal to be amplified is input to the input line of the fourth transistor Q4, and a second switch SW2 that switches according to the inverted signal of the control signal is connected to the input line. Thereby, the fourth transistor Q4 can switch according to the signal to be amplified and the inverted signal of the control signal.

[0019] Each transistor turns ON when the value of the input signal is equal to or greater than the threshold value and turns OFF when the value is less than the threshold value. However, since the signal (amplification target signal or its inverted signal) input to each transistor is a rectangular wave, the transistor turns ON when the signal is HIGH and turns OFF when the signal is LOW. Also, each switch is assumed to turn ON when the value of the input signal is 1 (i.e., when the control signal is 0) and turn OFF when the value is 0 (i.e., when the control signal is 1).

[0020] In the case of the configuration shown in FIG. 2, if the control signal is 0, each switch turns ON and current flows to GND, so that each low-side transistor does not turn ON. Therefore, no current flows through transformer L, and ideally, the output power becomes zero. A switching amplifier 11 may be realized by a full-bridge circuit driven based on such an amplification target signal and a control signal.

[0021] The adjustment unit 12 adjusts the control signal input to the switching amplifier 11 before it is input to the switching amplifier 11. Specifically, the pulse width adjustment circuit 121 adjusts the pulse width, and the delay circuit 122 adjusts the delay time with respect to the amplification target signal.

[0022] In this embodiment, it is assumed that the adjustment unit 12 adjusts both the pulse width and the delay time, but only one of the pulse width and the delay time may be adjusted. In that case, the circuit for processing the unadjusted one may be omitted.

[0023] The pulse width of the control signal after adjustment by the pulse width adjustment circuit 121 is denoted as “TON”. That is, the control signal is adjusted by the pulse width adjustment circuit 121 before being input to the switching amplifier 11, and its pulse width becomes TON.

[0024] The delay time adjusted by the delay circuit 122 means the time length from when the signal to be amplified switches until the control signal switches for the first time. For example, taking the timing of the switching from LOW to HIGH of the signal to be amplified as a reference, it means the time length from this reference until the timing when the control signal switches from OFF to ON for the first time. The delay time of the adjusted control signal is denoted as "DELAY". That is, the control signal is adjusted by the delay circuit 122 before being input to the switching amplifier 11, and its delay time becomes DELAY.

[0025] FIG. 3 is a diagram showing the waveforms of the signal to be amplified and the control signal input to the switching amplifier 11. The control signal is after being adjusted by the pulse width adjustment circuit 121 and the delay circuit 122. Therefore, the pulse width of the control signal is TON, and the delay time is DELAY.

[0026] Note that in this embodiment, it is assumed that the control signal is generated by a device external to the amplification device 1 and input to the amplification device 1. Also, it is assumed that the control signal is generated so as to have a period that is half of the period of the signal to be amplified. Therefore, whether the signal to be amplified is in the HIGH section or the LOW section, the timing (rise) when the control signal changes from OFF to ON and the timing (fall) when the control signal changes from ON to OFF each occur once. The duty ratio of the control signal may be an arbitrary value.

[0027] In this way, the inventors discovered that when the pulse width and the delay time are adjusted, the power level (power spectrum) of the high-order harmonic changes. Therefore, by appropriately adjusting the pulse width and the delay time, the power level of the high-order harmonic can be suppressed.

[0028] FIG. 4 is a diagram showing the power levels of the frequency components of the amplified signal when the pulse width is adjusted. The fundamental wave is represented by the frequency f0, and the Nth (N is an integer of 2 or more) harmonic is represented by Nf0. For example, 3f0 represents the third harmonic.

[0029] In FIG. 4, the power levels of the amplified signals by three types of control signals (C1, C2, C3) with different TONs are shown. Note that the delay amounts of the respective control signals are the same. As shown in FIG. 4, it can be seen that the power levels of the frequency components of the amplified signal differ depending on the TON. Therefore, by adjusting the TON to an appropriate value, the power level of the harmonic can be suppressed. For example, when it is desired to suppress the third harmonic component, it can be seen that among the three types of control signals, the control signal C3 may be used.

[0030] In the example of FIG. 4, the frequency of the signal to be amplified is 500 kHz, the TON of the control signal C1 is 200 ns, the TON of the control signal C2 is 400 ns, and the TON of the control signal C3 is 600 ns. Also, the delay times of the respective control signals are not adjusted and the delay time is 0. Note that the decrease in the power level of the frequency component is not proportional to the magnitude of the TON. Also, the optimal TON differs depending on the fundamental frequency. Therefore, based on the frequency of the signal to be amplified used, the harmonic to be suppressed, etc., it is necessary to determine in advance the adjustment amount of the pulse width adjustment circuit 121.

[0031] FIG. 5 is a diagram showing the power levels of the frequency components of the amplified signal when the delay time is adjusted. Similar to FIG. 4, the fundamental wave is represented by the symbol f0, and the Nth harmonic is represented by Nf0.

[0032] In FIG. 5, the power levels of the amplified signals by three types of control signals (C4, C5, C6) with different DELAYs are shown. Note that the TONs of the respective control signals are the same. From FIG. 5, it can be seen that the power levels of the frequency components of the amplified signal differ depending on the DELAY. Therefore, by adjusting the DELAY to an appropriate value, the power level of the harmonic can be suppressed. For example, when it is desired to suppress the fifth harmonic component, it can be seen that among the three types of control signals, the control signal C5 may be used.

[0033] In the example of FIG. 5, the frequency of the signal to be amplified was 500 kHz, the DELAY of control signal C4 was 90 ns, the DELAY of control signal C5 was 20 ns, and the DELAY of control signal C6 was 40 ns. Also, the pulse width of each control signal was not adjusted and was set to 200 ns. Note that the decrease in the power level of the frequency component is not proportional to the magnitude of the DELAY. Also, the optimal DELAY varies depending on the fundamental frequency. Therefore, it is necessary to determine in advance the adjustment amount of delay circuit 122 based on the frequency of the signal to be amplified and the higher-order harmonics to be suppressed, etc.

[0034] Note that when continuously changing TON and DELAY, a variable resistor or the like can be used to realize pulse width adjustment circuit 121 and delay circuit 122. When discretely changing TON and DELAY, a switch or the like can be used to realize pulse width adjustment circuit 121 and delay circuit 122.

[0035] Also, pulse width adjustment circuit 121 and delay circuit 122 may store a table representing the relationship between the frequency of the signal to be amplified and the adjustment amount, and vary the adjustment amount according to the frequency of the signal to be amplified. Thereby, good characteristics can be obtained for any frequency. In that case, a circuit for measuring the frequency of the signal to be amplified may be separately provided in amplifier device 1.

[0036] Strictly speaking, it is preferable that the DELAY of the control signal reaches the desired value at the time when it is processed by switching amplifier 11. In adjustment unit 12, even if the delay times of the signal to be amplified and the control signal are adjusted to the desired values, it is assumed that the DELAY increases or decreases due to circuit delay until reaching the gate terminals of the respective transistors in switching amplifier 11. Therefore, adjustment unit 12 preferably adjusts so that the switching timings of the control signal and the signal to be amplified are aligned not at the adjustment time but at the time when they are processed by switching amplifier 11. That is, delay circuit 122 may operate so as to absorb the circuit delay until the signal to be amplified is applied to switching amplifier 11.

[0037] For example, it takes time T m In this case, the delay circuit 122 adds a time T m In this case, the actual DELAY of the signal output from the delay circuit 122 is the assumed DELAY+T m ". There is also a delay due to the circuits in the adjustment unit 12, that is, the pulse width / frequency adjustment circuit 123 and the delay circuit 122. The circuits in the adjustment unit 12 cause a delay of time T C In addition to the expected DELAY, the delay time T m Delay time T of the control signal from C In this case, the actual DELAY of the signal output from the delay circuit 122 is the assumed DELAY+T m -T C " is expressed as follows.

[0038] In this way, the adjustment unit 12 adjusts at least one of the pulse width and delay time of the signal to be amplified to TON or DELAY according to the frequency of the signal to be amplified. As a result, the switching amplifier 11 generates an amplified signal with a lower power level of higher harmonics than before the adjustment by the adjustment unit 12.

[0039] As shown in FIG. 2, when an amplified signal is output using a transformer, the coupling coefficient between the transformer of the amplifier 1 and the transformer of the output destination may be intentionally reduced. If the coupling coefficient is low, leakage inductance occurs, and the leakage inductance makes it difficult to transmit high-band frequencies. Therefore, by changing the arrangement or configuration of the transformer so that the coupling coefficient between the transformer of the amplifier 1 and the transformer of the output destination is equal to or less than a predetermined upper limit, the power level of the high-order harmonics at the output destination can be suppressed. For example, if the upper limit is set to 0.9, the power level of the high-order harmonics can be clearly reduced.

[0040] In order to reduce the coupling coefficient, for example, it is conceivable to increase the distance between the primary side and the secondary side of the transformer, provide a difference in the axial inclination between the primary side and the secondary side of the transformer, or shift the centers of the primary side and the secondary side of the transformer. Also, it is conceivable to loosely wind a wire around the core material. Since the coupling coefficient increases when the wire wound around the core material is wound in close contact without leaving a gap, it is conceivable to lower the coupling coefficient by winding with a gap. When using a plurality of transformers, for example, it is conceivable that no wire is wound around each core material on the secondary side, and the wire is wound so as to wrap a plurality of core materials together. After all, the coupling coefficient can be lowered by intentionally allowing magnetic flux leakage, such as by changing the configuration such as the arrangement and winding method of the transformers.

[0041] As described above, according to the first embodiment, the pulse width and delay time of the control signal are adjusted to optimize the driving timing and driving period of the switching amplifier 11. As a result, the power level of the higher-order harmonics of the amplified signal is lower than before the adjustment by the adjustment unit. Therefore, even in the amplification device 1 of the first embodiment in which a simple circuit is added to the switching amplifier 11, the higher-order harmonics included in the amplified signal can be suppressed. Accordingly, circuit complexity can be prevented, and circuit manufacturing costs and the like can be suppressed.

[0042] (Second Embodiment) In the second embodiment, a case will be described in which a plurality of switching amplifiers 11 are uniformly driven to increase the amplitude level of the amplified signal compared to when one switching amplifier 11 is driven.

[0043] FIG. 6 is a block diagram showing an example of the amplification device 1 according to the second embodiment. The amplification device 1 according to the present embodiment includes a plurality of switching amplifiers 11, an adjustment unit 12, and a synthesizer 13.

[0044] When it is desired to uniformly drive a plurality of switching amplifiers 11 to increase the amplitude level of the amplified signal, it is also possible to use the amplification device 1 of the plurality of first embodiments. However, TON and DELAY of the control signal input to the switching amplifier 11 of each amplification device 1 are the same for all the amplification devices 1. Therefore, there is no need to have a plurality of adjustment units 12. Thus, in the present embodiment, the adjusted control signal from one adjustment unit 12 is distributed to the plurality of switching amplifiers 11. Thereby, the manufacturing cost of the amplification device 1 can be suppressed.

[0045] The adjustment unit 12 operates in the same manner as in the first embodiment. The control signal adjusted by the adjustment unit 12 is distributed and input to each switching amplifier 11. Also, the signal to be amplified is distributed and input to each switching amplifier 11. Thereby, each switching amplifier 11 is driven at the same timing and operates in the same manner as in the first embodiment.

[0046] The synthesizer 13 synthesizes the amplified signals of the respective switching amplifiers 11. FIG. 7 is a diagram showing an example of the synthesizer 13. In the example of FIG. 7, the synthesizer 13 is realized using a transformer. The synthesizer 13 in the example of FIG. 7 has more transformers than the number of the respective switching amplifiers 11 in order to receive the output power from each switching amplifier 11. Each transformer of the synthesizer 13 is connected in series, one end of the entire connected transformer is grounded, and a synthesized signal is output from the other end. With such a configuration, the amplified signals of the respective switching amplifiers 11 are voltage-added and output as a synthesized signal.

[0047] As described in the first embodiment, the higher harmonics of the amplified signal output by the switching amplifier 11 are suppressed. This is the same even when there are a plurality of switching amplifiers 11. Also, in the synthesis by the synthesizer 13, no higher harmonics are generated. Therefore, the higher harmonics of the synthesized signal from the synthesizer 13 are also suppressed.

[0048] Note that, as described in the first embodiment, in order to suppress the power level of the higher harmonics, the arrangement or configuration of the transformer in the synthesizer 13 may also be changed so that the coupling coefficient with the switching amplifier 11 is equal to or less than the upper limit value.

[0049] As described above, according to the second embodiment, even when the amplitude level of the amplified signal is increased by using a plurality of switching amplifiers 11, the higher harmonics of the output composite signal can be suppressed. In addition, since complicated processing such as adjusting the control signal for each of the switching amplifiers 11 is not performed, the circuit in the amplification device 1 can be simplified, and the manufacturing cost of the circuit and the like can be suppressed.

[0050] (Third Embodiment) In the third embodiment, a case will be described in which the control signal is generated from the signal to be amplified instead of receiving the control signal from the outside.

[0051] FIG. 8 is a block diagram showing an example of the amplification device 1 according to the third embodiment. The amplification device 1 according to the present embodiment is different from the previous embodiments in that the adjustment unit 12 multiplies the frequency. In the example of FIG. 8, instead of the pulse width adjustment circuit 121, a pulse width - frequency adjustment circuit 123 that adjusts both the pulse width and the frequency is shown.

[0052] Note that, in the example of FIG. 8, a case where there are a plurality of switching amplifiers as in the second embodiment is shown, but there may be one switching amplifier as in the first embodiment.

[0053] The adjustment unit 12 of the present embodiment generates a control signal from the signal to be amplified. Therefore, the adjustment unit 12 can also be said to be a control signal generation unit. The pulse width - frequency adjustment circuit 123 can double the frequency and outputs a signal having a pulse width of TON and a period that is half of the period of the signal to be amplified.

[0054] FIG. 9 is a circuit diagram showing a first implementation example of the adjustment unit 12 of the third embodiment. The signal to be amplified input to the circuit of FIG. 9 is branched and input to a CR delay circuit 1231 composed of a capacitor and a resistor and an XOR circuit (exclusive OR circuit) 1232. The resistor of the CR delay circuit 1231 is a variable resistor, and the signal to be amplified can be delayed according to the change in the value of the variable resistor. The CR delay circuit 1231 outputs an analogously delayed signal, which is input to the XOR circuit 1232. The XOR circuit is used as a doubler, and a doubled signal is output to the XOR circuit output. In other words, the period of the output signal of the XOR circuit 1232 is half of the period of the input signal of the XOR circuit 1232. By adjusting the value of the variable resistor of the CR delay circuit 123, the pulse width of the output of the XOR circuit 1232 can be adjusted. Also, in order to achieve a large pulse width in the output signal of the XOR circuit, it is also possible to connect in series a plurality of combinations (units) of the CR delay circuit 1231 and a buffer circuit or the like provided at its output.

[0055] The signal output from the XOR circuit 1232 is analogously delayed by the CR delay circuit 1221 and input to the buffer circuit 1222. The buffer circuit 1222 converts the input signal into a digital signal. In this way, the adjustment unit 12 that doubles the frequency can be realized.

[0056] In addition, when realizing the XOR circuit 1232, buffer circuit 1222, etc. shown in FIG. 9 using a logic IC, variations in the threshold values of the logic IC may affect the performance. For example, when realizing a large pulse width, instead of the CR delay circuit 1231 in FIG. 9, a configuration may be adopted in which a plurality of units each composed of a CR delay circuit and a buffer circuit that receives its output are connected in series. In particular, in such a configuration, due to the threshold value of the buffer circuit and the imbalance between the HIGH and LOW threshold values of the XOR circuit 1232, the duty ratio of the output signal of the configuration with multiple units connected in series may deviate from 50%. As a result, the duty ratio of the output signal pulses of the XOR circuit 1232 may shift between even-numbered and odd-numbered ones, causing an imbalance. Also, a similar problem may occur due to the shift between the HIGH and LOW threshold values of the XOR circuit 1232. To avoid this, it is conceivable to provide 2M (M is an integer of 1 or more) units and use an inverter buffer as the buffer circuit for each unit.

[0057] FIG. 10 is a circuit diagram showing a second implementation example of the adjustment unit 12 of the third embodiment. In FIG. 10(A), instead of the CR delay circuit 1231 in FIG. 9, a CR delay circuit 1233, a first buffer circuit 1234, a CR delay circuit 1235, and a second buffer circuit 1236 are shown. The CR delay circuit 1233 and the first buffer circuit 1234 constitute the first unit, and the CR delay circuit 1235 and the second buffer circuit 1236 constitute the second unit. Note that the values of the variable resistors of the CR delay circuit 1233 and the CR delay circuit 1235 are the same.

[0058] FIG. 10(B) shows the change in the waveform of the signal to be amplified input to the circuit of FIG. 10(A) when the first buffer circuit 1234 and the second buffer circuit 1236 are non-inverting buffers. The top waveform in FIG. 10(B) represents the waveform at the time of input to the CR delay circuit 1233. Let the rising time of the signal to be amplified be t0. The pulse width at this time is T AIt is as follows. The second waveform in Fig. 10(B) represents the waveform at the time when it is output from the buffer circuit 1234. By the first unit, the rising time changes to t0 + α, and the falling time changes to t0 + T A + β. The third waveform in Fig. 10(B) represents the waveform at the time when it is output from the buffer circuit 1236. Also in the second unit, the same amount of change as in the first unit is added to the signal to be amplified. Therefore, the rising time changes to t0 + 2α, and the falling time changes to t0 + T A + 2β. Therefore, the difference in pulse width is 2β - 2α.

[0059] Fig. 10(C) shows the change in the waveform of the signal to be amplified input to the circuit of Fig. 10(A) when the second buffer circuit 1236 is an inverting buffer. The top waveform in Fig. 10(C) represents the waveform at the time when it is input to the CR delay circuit 1233. The waveform is the same as the top waveform in Fig. 10(B). The second waveform in Fig. 10(C) represents the waveform at the time when it is output from the buffer circuit 1234. In the case of Fig. 10(C), since delay and inversion are performed, the rising time t0 is delayed by α and becomes a fall. On the other hand, the falling time t0 + T A is delayed by β and becomes a rise. As a result, as shown in Fig. 10(C), the falling time changes to t0 + α, and the rising time is t0 + T A + β. The third waveform in Fig. 10(C) represents the waveform at the time when it is output from the buffer circuit 1236. Also here, since delay and inversion are performed, the falling time t0 + α is delayed by β and becomes a rise. On the other hand, the rising time t0 + T A + β is delayed by α and becomes a fall. As a result, as shown in Fig. 10(C), the falling time changes to t0 + α + β, and the falling time is t0 + T A + α + β. Therefore, the difference in pulse width is 0.

[0060] In such a configuration, by adjusting the values of the variable resistors so as to cancel out the deviation of the threshold value, the signal output from the XOR circuit 1232 has less disturbance in the pulse waveform due to the variation of the threshold value.

[0061] As described above, according to the third embodiment, it is possible to generate a control signal from the signal to be amplified.

[0062] (Fourth Embodiment) In the second and third embodiments, it is assumed that the plurality of switching amplifiers 11 are driven uniformly. However, it is also conceivable to drive a part of the plurality of switching amplifiers 11 and stop the rest. For example, when the signal to be amplified is a modulation signal, it is also conceivable to dynamically change the number of driven switching amplifiers 11 according to the amplitude level of the modulation signal.

[0063] FIG. 11 is a block diagram showing an example of an amplification device according to the fourth embodiment. In the present embodiment, the amplification device 1 of the third embodiment further includes a plurality of AND circuits 14. In addition, the amplification device 1 receives a plurality of drive control signals, which is different from the previous embodiments.

[0064] The AND circuit 14 is provided for each of the switching amplifiers 11, and the signal output from the adjustment unit 12 and the corresponding drive control signal are input thereto, and the logical product thereof is output to the switching amplifier 11. In other words, in the present embodiment, the control signal given to each switching amplifier 11 is a signal obtained by performing an AND operation on the signal output from the adjustment unit 12 and the drive control signal corresponding to each switching amplifier 11.

[0065] The drive control signal is a signal for determining whether to operate the switching amplifier 11. Similar to the control signal, the drive control signal is also represented by a binary value of 0 or 1. When the drive control signal is 1, the output of the AND circuit 14 is the same as the value of the control signal, so the switching amplifier 11 operates according to the control signal. When the drive control signal is 0, the output of the AND circuit 14 is 0, so the switching amplifier 11 does not operate. That is, the drive control signal can be considered as a signal for determining the validity of the control signal applied to the switching amplifier 11.

[0066] Note that the switching amplifiers may be grouped and each group may receive a drive control signal. In this case, the number of drive control signals is smaller than N. Therefore, when there are N switching amplifiers, the amplification device 1 receives a maximum of N drive control signals.

[0067] As described above, according to the fourth embodiment, in the configuration where a plurality of switching amplifiers 11 are operated in parallel according to the drive control signal and their outputs are combined, it is possible to dynamically change the number of driving switching amplifiers.

[0068] (Fifth Embodiment) In the fifth embodiment, as an example of the use of the amplification device 1, an example applied to the transmission device 2 is shown.

[0069] FIG. 12 is a block diagram showing an example of the transmission device 2 according to the fifth embodiment. The transmission device 2 according to the present embodiment includes a rectangular wave generation unit 21, the amplification device 1 according to the third embodiment, and an antenna unit 22.

[0070] The transmission device 2 of the present embodiment is a device that amplifies and transmits an input signal. The signal input to the transmission device 2 is referred to as a signal to be transmitted. The signal to be transmitted is not particularly limited, and an unmodulated carrier signal, a modulated signal generated by modulating a signal including information to be transmitted based on the carrier signal, etc. are assumed.

[0071] Note that, to show the effectiveness of the amplification device 1, an example in which the amplification device 1 is applied to the transmission device 2 that performs the above-described processing is shown, but the application destination of the amplification device 1 is not limited.

[0072] The rectangular wave generation unit 21 performs threshold determination on the transmission target signal and converts the transmission target signal into HIGH and LOW. Thereby, the waveform of the transmission target signal is converted into a rectangular wave. The converted rectangular wave signal is referred to as a rectangular wave transmission target signal. When a rectangular wave signal is input to the amplification device 1, the rectangular wave generation unit 21 may be omitted.

[0073] The amplification device 1 receives the rectangular wave transmission target signal as an amplification target signal. The processing of the amplification device 1 is as described in the third embodiment. That is, a control signal is generated from the rectangular wave transmission target signal by the adjustment unit 12, an amplified signal of the rectangular wave transmission target signal is generated by the switching amplifier 11, and a combined signal of each amplified signal is generated by the synthesizer 13. Also, as described in the third embodiment, the higher-order harmonics of the combined signal are reduced.

[0074] The antenna unit 22 has at least an antenna, and transmits the combined signal from the synthesizer 13 as radio waves through the antenna. The antenna unit 22 may independently have an amplifier, a filter, and the like. In FIG. 12, a filter 231 is shown inside the antenna unit 22. Note that the filter 231 may be any filter as long as it can remove the frequency components to be removed. For example, as general filters, there are a band-pass filter that passes only the desired signal band, a low-pass filter that passes frequencies below the desired frequency, a bypass filter that passes frequencies above the desired frequency, and the like, but the filter 231 may be any of them. Note that the filter 231 may exist independently of the antenna unit. The combined signal from the synthesizer 13 may be transmitted to the antenna unit via the filter 231.

[0075] As described above, the transmission device 2 of this embodiment including the amplification device 1 of the third embodiment can transmit a composite signal with suppressed higher harmonics. As a result, since the required specifications of the BPF are relaxed, or the BPF becomes unnecessary, the manufacturing cost of the transmission device 2 can be reduced.

[0076] Note that the present invention is not limited to the above-described embodiments as they are, and at the implementation stage, the components can be modified and embodied without departing from the gist thereof. Also, various inventions can be formed by appropriately combining a plurality of components disclosed in the above embodiments. For example, some components may be deleted from all the components shown in the embodiments. Further, components from different embodiments may be appropriately combined.

[0077] 1 Amplification device 11 Switching amplifier 12 Adjusting section 121 Pulse width adjustment circuit 122 Delay circuit 123 Pulse width / frequency adjustment circuit 1221 CR delay circuit 1222 Buffer circuit 1231 CR delay circuit 1232 XOR circuit 1233 CR delay circuit 1234 First buffer circuit 1235 CR delay circuit 1236 Second buffer circuit 13 Combiner 14 AND circuit 2 Transmission device 21 Square wave generation section 22 Antenna section 221 Filter Q1 First transistor Q2 Second transistor Q3 Third transistor Q4 Fourth transistor SW1 First switch SW2 Second switch L Transformer

Claims

1. An amplification device comprising a switching amplifier and an adjustment unit, wherein the switching amplifier includes: a full-bridge circuit including a first high-side transistor connected in series between a first reference voltage node and a second reference voltage node and having an amplification target signal input to its gate, and a first low-side transistor having an inverted signal of the amplification target signal input to its gate; a second high-side transistor connected in series between the first reference voltage node and the second reference voltage node and having an inverted signal of the amplification target signal input to its gate, and a second low-side transistor having the amplification target signal input to its gate; and a transformer connected between a connection node of the first high-side transistor and the first low-side transistor and a connection node of the second high-side transistor and the second low-side transistor; a first switch connected between the gate of the first low-side transistor and a predetermined reference voltage node and switching based on the logic of the inverted signal of the control signal; a second switch connected between the gate of the second low-side transistor and a predetermined reference voltage node and switching based on the logic of the inverted signal of the control signal; alternately switching a first current path that passes a current through the first high-side transistor, the transformer, and the second low-side transistor, or a second current path that passes a current through the second high-side transistor, the transformer, and the first low-side transistor according to the logic of the amplification target signal to generate an amplified signal, and controlling at least one of a period and a timing for generating the amplified signal based on a control signal; the adjustment unit generates the control signal based on the amplification target signal such that a period of the control signal is half of a period of the amplification target signal; an amplification device.

2. The adjustment unit adjusts at least one of a pulse width of the control signal or a delay time of the control signal with respect to the amplification target signal according to a frequency of the amplification target signal. The amplification device according to Claim 1.

3. The adjustment unit generates the control signal such that the switching amplifier generates an amplified signal having a lower power level of higher harmonics than before adjustment by the adjustment unit. The amplification device according to Claim 1 or 2.

4. The adjustment unit adjusts both the pulse width and the delay time of the control signal. The amplification device according to any one of claims 1 to 3.

5. A plurality of the switching amplifiers are provided, and further comprises a synthesizer that synthesizes each amplification signal from each of the switching amplifiers to generate a synthesized signal The amplification device according to any one of claims 1 to 4.

6. The synthesizer synthesizes the respective amplification signals by voltage addition. The amplification device according to claim 5.

7. The synthesizer is arranged or configured such that a coupling coefficient with each of the switching amplifiers is equal to or less than an upper limit value, wherein the upper limit value is 0.9 The amplification device according to claim 6.

8. further comprises one or more AND circuits, the adjustment unit adjusts the signal to be amplified, and by inputting the adjusted signal to be amplified and a signal for determining the drive of the switching amplifier into the AND circuit, a control signal for the switching amplifier corresponding to the AND circuit is generated The amplification device according to any one of claims 5 to 7.

9. The adjustment unit generates the control signal by adjusting the signal to be amplified. The amplification device according to any one of claims 1 to 6.

10. The adjustment unit generates the control signal such that a period of the control signal is half of a period of the signal to be amplified. The amplification device according to claim 9.

11. receives a rectangular signal as the signal to be amplified and outputs the synthesized signal The amplification device according to any one of claims 5 to 8, and an antenna unit that transmits the synthesized signal, A transmission device comprising.

12. further comprises a rectangular wave generation unit that generates the rectangular signal by converting a waveform of an input signal into a rectangular wave The transmission device according to claim 11.

13. further comprises a filter that removes a predetermined frequency component included in the synthesized signal The transmission device according to claim 11 or 12.

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