Semiconductor device

Abstract

To provide a semiconductor device in which a plurality of pads are arranged along one of sides of a semiconductor substrate, and it is preferred to increase an area of an element region.SOLUTION: A semiconductor device provided with a transistor section and a diode section on a semiconductor substrate comprises: a plurality of pads arranged along a first end side of the semiconductor substrate in top view; an inter-pad region as a region sandwiched between the pads in the top view; and a first conductivity type cathode region provided in a region in contact with a bottom surface of the semiconductor substrate and at least partially arranged in the inter-pad region in the top view.SELECTED DRAWING: Figure 9

Description

Technical Field

[0001] The present invention relates to a semiconductor device.

Background Art

[0002] Conventionally, a semiconductor device in which a transistor element such as an insulated gate bipolar transistor (IGBT) and a diode element such as a freewheeling diode (FWD) are provided on the same semiconductor substrate is known (see, for example, Patent Document 1). A plurality of pads connected to a transistor element, a diode element, or the like are provided on the semiconductor substrate. The following documents are related prior art documents. Patent Document 1 Japanese Patent Application Laid-Open No. 2017-147435 Patent Document 2 Japanese Patent Application Laid-Open No. 2017-69412 Patent Document 3 Japanese Patent Application Laid-Open No. 2007-173411

Summary of the Invention

Problems to be Solved by the Invention

[0003] The plurality of pads are arranged along any side of the semiconductor substrate. In the semiconductor device, it is preferable to increase the area of the element region. [General Disclosure]

[0004] In order to solve the above problems, in one aspect of the present invention, a semiconductor device is provided in which a transistor portion and a diode portion are provided on a semiconductor substrate. The semiconductor device may include a plurality of pads arranged along a first end side of the semiconductor substrate in a top view. Any of the semiconductor devices may include a pad interval region that is a region sandwiched by the pads in a top view. Any of the semiconductor devices may include a cathode region of a first conductivity type provided in a region in contact with the lower surface of the semiconductor substrate and at least a part of which is arranged in the pad interval region in a top view.

[0005] Any of the above semiconductor devices may include a collector region of a second conductivity type provided in a region in contact with the lower surface of the semiconductor substrate and at least partially disposed in the inter-pad region in a top view.

[0006] In any of the above semiconductor devices, the collector region may be disposed between the first side and the cathode region in the inter-pad region.

[0007] In any of the above semiconductor devices, the cathode region may also be disposed in a main active region, which is a region other than the inter-pad region among the regions where the transistor portion and the diode portion are provided.

[0008] In any of the above semiconductor devices, the cathode region may be provided from the main active region to the inter-pad region.

[0009] In any of the above semiconductor devices, any one of the plurality of pads may be disposed at an end in a first direction parallel to the first side.

[0010] Any of the above semiconductor devices may include a gate trench portion and a dummy trench portion as trench portions provided on the upper surface side of the semiconductor substrate and at least partially disposed in the inter-pad region.

[0011] In any of the above semiconductor devices, the gate trench portion and the dummy trench portion may extend in a second direction perpendicular to the first side.

[0012] Any of the above semiconductor devices may include an upper electrode provided on the upper surface of the semiconductor substrate via an insulating film. In any of the above semiconductor devices, the upper electrode may be in contact with the upper surface of the semiconductor substrate via a contact hole formed in the insulating film. In the inter-pad region of any of the above semiconductor devices, the contact hole may be provided between the trench portion closest to the pad and the pad.

[0013] In the region between the pads of any of the semiconductor devices described above, a plurality of the contact holes may be provided between the trench portion closest to the pad and the pad.

[0014] In the region between the pads of any of the semiconductor devices described above, a gate runner may be provided between the trench portion closest to the pad and the pad.

[0015] In any of the semiconductor devices described above, the gate trench portion and the dummy trench portion may extend in a first direction parallel to the first end side.

[0016] Any of the semiconductor devices described above may be provided on the upper surface side of the semiconductor substrate and include a base region of a second conductivity type at least partially disposed in the region between the pads. Any of the semiconductor devices described above may be provided on the upper surface side of the semiconductor substrate and include a well region of a second conductivity type deeper than the base region at least partially disposed in the region between the pads.

[0017] In order to solve the above problems, in another aspect of the present invention, a plurality of trench portions are provided on the upper surface side of a semiconductor substrate, and in a top view, a semiconductor device including a first end side and a second end side arranged to face each other in a first direction, and a third end side and a fourth end side arranged to face each other in a second direction perpendicular to the first direction is provided. The semiconductor device may include a plurality of gate trench portions that extend in the first direction and are arranged in the second direction. Any of the above semiconductor devices may have a first extension portion that extends in the second direction in a top view, and the first extension portion may include a first gate runner that is connected to an end portion of one or more gate trench portions facing the second end side via a first connection portion. Any of the above semiconductor devices may have a second extension portion that extends in the second direction in a top view, and the second extension portion may include a second gate runner that is connected to an end portion of one or more gate trench portions facing the first end side via a second connection portion. When a rectangular region between the position in the first direction of the first connection portion and the position in the first direction of the second connection portion in a top view of any of the above semiconductor devices is defined as a first region, at least one trench portion may be provided in a second region on the first end side of the first region.

[0018] In any of the above semiconductor devices, the semiconductor substrate may be a silicon substrate, a silicon carbide substrate, or a nitride substrate.

[0019] Note that the above summary of the invention does not list all the necessary features of the present invention. Also, sub-combinations of these feature groups may also be inventions.

Brief Description of the Drawings

[0020]

Figure 1

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Figure 10

Figure 11

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Figure 14

Embodiments for Carrying Out the Invention

[0021] Hereinafter, the present invention will be described through embodiments of the invention. However, the following embodiments do not limit the invention according to the claims. Also, not all combinations of features described in the embodiments are essential for the solution means of the invention.

[0022] In this specification, one side in the direction parallel to the depth direction of the semiconductor substrate is referred to as "upper", and the other side is referred to as "lower". Of the two main surfaces of the substrate, layer, or other member, one surface is referred to as the upper surface and the other surface is referred to as the lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the direction of attachment to the substrate or the like when mounting the semiconductor device.

[0023] In this specification, technical matters may be described using orthogonal coordinate axes of the X-axis, Y-axis, and Z-axis. In this specification, a plane parallel to the upper surface of the semiconductor substrate is defined as the XY plane, and the depth direction perpendicular to the upper surface of the semiconductor substrate is defined as the Z-axis.

[0024] In each embodiment, an example is shown where the first conductivity type is N-type and the second conductivity type is P-type. However, the first conductivity type may be P-type and the second conductivity type may be N-type. In this case, the conductivity types of the substrate, layers, regions, etc. in each embodiment will have opposite polarities. Also, when described as P+(or N+) in this specification, it means that the doping concentration is higher than that of P-type (or N-type), and when described as P-(or N-), it means that the doping concentration is lower than that of P-type (or N-type).

[0025] In this specification, the doping concentration refers to the concentration of impurities that have been donor- or acceptor-doped. In this specification, the concentration difference between donors and acceptors may be defined as the doping concentration. Also, in some cases, the peak value of the doping concentration distribution in the doping region is defined as the doping concentration in that doping region.

[0026] FIG. 1 is a diagram showing the structure of the upper surface of a semiconductor device 100 according to an embodiment of the present invention. The semiconductor device 100 includes a semiconductor substrate 10. The semiconductor substrate 10 may be a silicon substrate, may be a silicon carbide substrate, or may be a nitride semiconductor substrate such as gallium nitride. The semiconductor substrate 10 in this example is a silicon substrate.

[0027] In this specification, the outer peripheral end of the semiconductor substrate 10 in a top view is defined as the outer peripheral end 140. The top view refers to the case of viewing parallel to the Z-axis from the upper surface side of the semiconductor substrate 10. Also, among the outer peripheral ends 140 of the semiconductor substrate 10 in a top view, any one of the side edges is defined as the first side edge 142. In a top view, the direction parallel to the first side edge 142 is defined as the X-axis direction, and the direction perpendicular to the first side edge 142 is defined as the Y-axis direction.

[0028] The semiconductor device 100 includes a main active portion 120 and an edge termination structure portion 90. The main active portion 120 is a region other than the inter-pad region 130 described later among the active regions where current flows in the depth direction inside the semiconductor substrate 10 from the upper surface to the lower surface, or from the lower surface to the upper surface of the semiconductor substrate 10. For example, when the active region controls the transistor elements included in the semiconductor device 100 to be in the on state, or when the transistor elements transition from the on state to the off state, the main current flows between the upper surface and the lower surface of the semiconductor substrate 10. The main active portion 120 may refer to a region other than the pads and the inter-pad region 130 among the regions surrounded by the first gate runner 50 described later.

[0029] A transistor portion 70 and a diode portion 80 are provided in the main active portion 120. In this specification, the transistor portion 70 and the diode portion 80 may be referred to as element portions or element regions, respectively. In this example, the transistor portion 70 and the diode portion 80 are alternately provided in the X-axis direction in the main active portion 120.

[0030] Above the upper surface of the semiconductor substrate 10, a plurality of pads (in the example of FIG. 1, sense pad 114, emitter pad 115, gate pad 116, cathode pad 117, and anode pad 118) are provided. The sense pad 114 is connected to a current sense element 119. The current sense element 119 has the same structure as the transistor portion 70 and has a smaller area (corresponding to the channel area) in top view than the transistor portion 70. By detecting the current flowing through the current sense element 119, the current flowing through the entire semiconductor device 100 can be estimated. The emitter pad 115 is connected to an emitter electrode disposed above the upper surface of the semiconductor substrate 10. The gate pad 116 is connected to the gate electrode of the transistor portion 70. The gate pad 116 in this example is connected to a gate runner portion described later. The cathode pad 117 and the anode pad 118 are connected to a temperature sense portion 110 described later. Note that the number and types of pads provided on the semiconductor substrate 10 are not limited to the example shown in FIG. 1.

[0031] Each pad is formed of a metal material such as aluminum. The plurality of pads are arranged in a predetermined arrangement direction between the main active portion 120 and the first side 142 on the upper surface of the semiconductor substrate 10. The plurality of pads in this example are arranged sandwiched between the element region and the first side 142 in the Y-axis direction.

[0032] The arrangement direction of the plurality of pads may be the direction of a straight line connecting the centers in a top view of two pads (the sense pad 114 and the anode pad 118 in this example) arranged at both ends in a direction parallel to the first side 142 among the plurality of pads. The arrangement direction may be a direction parallel to the first side 142. Also, the arrangement direction may have an inclination within 30 degrees with respect to the first side 142. The inclination may be within 20 degrees, or may be within 10 degrees. The arrangement direction in this example is parallel to the first side 142.

[0033] The region sandwiched between two pads in a top view is defined as the inter-pad region 130. The inter-pad region 130 in this example is an overlapping region where the regions of two pads overlap when extended in a direction parallel to the X-axis toward each other's pads. In this example, the region between the overlapping region and the first gate runner 50 provided along the first side 142 is also included in the inter-pad region 130.

[0034] In the semiconductor device 100, an element region is also provided in at least one inter-pad region 130. In this example, a transistor portion 70 is provided in at least one inter-pad region 130. With such a structure, the area of the element region can be increased by effectively using the inter-pad region 130.

[0035] The semiconductor device 100 includes a gate runner section that transmits a gate voltage to the transistor section 70. The semiconductor device 100 in this example includes a first gate runner 50, a second gate runner 51, and a third gate runner 48 as the gate runner section. In this example, each gate runner is provided above the upper surface of the semiconductor substrate 10 and is insulated from the upper surface of the semiconductor substrate 10 by an interlayer insulating film.

[0036] The first gate runner 50 is provided so as to pass between the first edge 142 of the semiconductor substrate 10 and at least one pad in a top view. The first gate runner 50 in this example is provided parallel to the first edge 142 so as to pass between each of the sense pad 114, the emitter pad 115, the gate pad 116, the cathode pad 117, and the anode pad 118 and the first edge 142. The first gate runner 50 is connected to the gate pad 116.

[0037] Also, the first gate runner 50 is provided so as to surround the main active portion 120 between the other edge of the semiconductor substrate 10 and the main active portion 120. That is, the first gate runner 50 in this example is provided in an annular shape along each edge of the semiconductor substrate 10. The first gate runner 50 may be a metal wiring such as aluminum, or may be a semiconductor wiring such as polysilicon doped with impurities. The first gate runner 50 may have a structure in which a metal wiring and a semiconductor wiring are provided to overlap via an insulating film. The insulating film is provided with contact holes for connecting the metal wiring and the semiconductor wiring. The first gate runner 50 in this example is a metal wiring.

[0038] The materials of the second gate runner 51 and the third gate runner 48 may be the same as the materials described for the first gate runner 50. In this example, the second gate runner 51 is a metal wiring, and the third gate runner 48 is a semiconductor wiring.

[0039] The second gate runner 51 is provided so as to pass between at least one pad and the transistor section 70 in a top view. The at least one pad is a pad other than the emitter pad 115. The second gate runner 51 in this example is provided for all pads other than the emitter pad 115. The second gate runner 51 is arranged to be sandwiched between the pad and the main active section 120 (i.e., the transistor section 70 and the diode section 80) in the Y-axis direction. In any pad, the second gate runner 51 may be arranged along two or more sides of the pad.

[0040] For example, for a pad (anode pad 118 in this example) arranged at one end in the X-axis direction, the second gate runner 51 is arranged along two intersecting sides, and the first gate runner 50 is arranged along the other two sides.

[0041] Also, a current sense element 119 is provided in the pad-to-pad region 130 between the pad (sense pad 114 in this example) arranged at the other end in the X-axis direction and the emitter pad 115. The transistor section 70 and the diode section 80 do not have to be provided in the pad-to-pad region 130 where the current sense element 119 is provided. As an example, a P+-type well region described later may be provided in a region where the current sense element 119 is not provided in the pad-to-pad region 130.

[0042] Each pad in this example has two pairs of parallel sides in a top view. In the example of FIG. 1, each pad has two sides parallel to the X-axis and two sides parallel to the Y-axis. Among the sides of each pad, a gate runner portion may not be provided on the side facing the current sense element 119. In the sense pad 114 of this example, a second gate runner 51 is arranged along one side facing the main active portion 120, no gate runner portion is provided on the side facing the current sense element 119, and a first gate runner 50 is arranged along the other two sides. The second gate runner 51 arranged along the sense pad 114 may be connected to the second gate runner 51 provided along other pads via the third gate runner 48.

[0043] More specifically, the two second gate runners 51 provided on the two pads (in this example, the sense pad 114 and the gate pad 116) arranged with the emitter pad 115 sandwiched therebetween in the X-axis direction may be connected via the third gate runner 48. The third gate runner 48 is arranged between the main active portion 120 and the emitter pad 115 and the pad-to-pad region 130 in the Y-axis direction.

[0044] Also, for the pads provided at positions other than both ends in the X-axis direction (in this example, the gate pad 116 and the cathode pad 117), the second gate runner 51 is arranged along the three sides other than the side facing the first end side 142, and the first gate runner 50 is arranged along the side facing the first end side 142. The gate runner portions provided around each pad are connected to each other to surround the pad in a ring shape.

[0045] The transistor section 70 has a gate trench section that extends in an extending direction (the Y-axis direction in this example) different from the array direction in a top view. The structure of the gate trench section will be described later. The gate trench section provided in the inter-pad region 130 is directly or indirectly connected to a first gate runner 50 provided along a first end side 142. That is, the gate trench section provided in the inter-pad region 130 extends in the Y-axis direction to a position where it can be directly or indirectly connected to the first gate runner 50 arranged along the first end side 142 of the semiconductor substrate 10.

[0046] Also, the gate trench section of the main active section 120, which is arranged to face the second gate runner 51 in the extending direction (Y-axis direction), is directly or indirectly connected to the second gate runner 51. That is, the second gate runner 51 that extends in the X-axis direction between the pad and the main active section 120 and the gate trench section arranged to face each other in the Y-axis direction are directly or indirectly connected to the second gate runner 51.

[0047] With such a configuration, the gate trench sections of the transistor sections provided in the main active section 120 and the inter-pad region 130 can be connected to the gate runner section. Note that by using the first gate runner 50 and the second gate runner 51 as metal wirings, variations in the timing of transmitting the gate voltage to each gate trench section and variations in the attenuation amount of the gate voltage can be reduced.

[0048] Also, among the gate trench sections provided in the main active section 120, the gate trench section provided at a position facing the third gate runner 48 in the Y-axis direction may be connected to the third gate runner 48. Also, the gate trench section provided at a position facing the first gate runner 50 arranged along the end side opposite to the first end side 142 may be directly or indirectly connected to the first gate runner 50.

[0049] The transistor section 70 includes transistors such as IGBTs. The diode section 80 is alternately arranged with the transistor section 70 in the X-axis direction on the upper surface of the semiconductor substrate 10. Each diode section 80 is provided with an N+-type cathode region in a region in contact with the lower surface of the semiconductor substrate 10. The diode section 80 indicated by the solid line in FIG. 1 is a region where a cathode region is provided on the lower surface of the semiconductor substrate 10. In the semiconductor device 100 of this example, the region other than the cathode region among the regions in contact with the lower surface of the semiconductor substrate is a P+-type collector region.

[0050] The diode section 80 is a region obtained by projecting the cathode region in the Z-axis direction. The transistor section 70 is a region where a collector region is formed on the lower surface of the semiconductor substrate 10 and a unit structure including an N+-type emitter region is periodically formed on the upper surface of the semiconductor substrate 10. Among the active regions, a region obtained by extending in the Y-axis direction a region obtained by projecting the cathode region in the Z-axis direction may also be used as the diode section 80. A region other than the diode section 80 may be used as the transistor section 70. The boundary between the diode section 80 and the transistor section 70 in the X-axis direction is the boundary between the cathode region and the collector region.

[0051] In the main active section 120, transistor sections 70 may be provided at both ends in the Y-axis direction. The main active section 120 may be divided in the Y-axis direction by the third gate runner 48. In each divided region of the main active section 120, the transistor section 70 and the diode section 80 are alternately arranged in the X-axis direction. In the example of FIG. 1, the main active section 120 is divided into three by two third gate runners 48 extending in the X-axis direction. Also, the third gate runner 48 formed of a semiconductor may be provided along the first gate runner 50 and the second gate runner 51 formed of a metal.

[0052] The edge termination structure 90 is provided between the first gate runner 50 and the outer peripheral end 140 of the semiconductor substrate 10 on the upper surface of the semiconductor substrate 10. The edge termination structure 90 may be arranged in an annular shape so as to surround the first gate runner 50 on the upper surface of the semiconductor substrate 10. The edge termination structure 90 of this example is arranged along the outer peripheral end 140 of the semiconductor substrate 10. The edge termination structure 90 alleviates the electric field concentration on the upper surface side of the semiconductor substrate 10. The edge termination structure 90 has, for example, a guard ring, a field plate, a RESURF, and a structure combining these.

[0053] The semiconductor device 100 of this example includes a temperature sense unit 110, temperature sense wirings 112-1 and 112-2. The temperature sense unit 110 is provided above the main active part 120. The temperature sense unit 110 may be provided at the center of the main active part 120 in a top view of the upper surface of the semiconductor substrate 10. The temperature sense unit 110 may be provided above the transistor part 70 in a top view of the upper surface of the semiconductor substrate 10. The temperature sense unit 110 detects the temperature of the main active part 120. The temperature sense unit 110 may be a pn-type temperature sense diode formed of single-crystal or polycrystalline silicon.

[0054] The temperature sense wiring 112 is provided above the main active part 120. The temperature sense wiring 112 may be a semiconductor wiring. The temperature sense wiring 112 is connected to the temperature sense unit 110. The temperature sense wiring 112 extends to the region between the main active part 120 and the outer peripheral end 140 on the upper surface of the semiconductor substrate 10 and is connected to the cathode pad 117 and the anode pad 118. Note that the semiconductor device 100 does not necessarily include the temperature sense unit 110 and the temperature sense wiring 112. Also, the semiconductor device 100 does not necessarily include the current sense element 119.

[0055] Figure 2 is an enlarged view of the vicinity of region A in Figure 1. Region A includes a transistor portion 70, a diode portion 80, a first gate runner 50, and an edge termination structure portion 90. In this example, a third gate runner 48 is provided along the first gate runner 50. The third gate runner 48 may be disposed between the first gate runner 50 and the semiconductor substrate 10. Each of the first gate runner 50, the third gate runner 48, and the semiconductor substrate 10 is insulated by an interlayer insulating film. The semiconductor device 100 of this example is provided inside the semiconductor substrate 10 and includes a guard ring 92, a gate trench portion 40, a dummy trench portion 30, a P+-type well region 11, an N+-type emitter region 12, a P-type base region 14, and a P+-type contact region 15 that are exposed on the upper surface of the semiconductor substrate 10. In this specification, the gate trench portion 40 or the dummy trench portion 30 may be simply referred to as a trench portion. Further, the semiconductor device 100 of this example includes an emitter electrode 52 and a first gate runner 50 provided above the upper surface of the semiconductor substrate 10. The emitter electrode 52 and the first gate runner 50 are provided separately from each other.

[0056] An edge termination structure portion 90 is disposed outside (on the positive Y-axis direction side) of the first gate runner 50. The edge termination structure portion 90 may have one or more guard rings 92 as described above. The guard ring 92 is a P-type region formed inside the semiconductor substrate 10. The guard ring 92 is provided in an annular shape surrounding the first gate runner 50 outside the first gate runner 50.

[0057] An interlayer insulating film is formed between the emitter electrode 52 and the first gate runner 50 and the upper surface of the semiconductor substrate 10, but is omitted in Figure 2. Contact holes 56, 49, and 54 are formed through the interlayer insulating film of this example.

[0058] The emitter electrode 52 contacts the emitter region 12, the contact region 15, and the base region 14 on the upper surface of the semiconductor substrate 10 through the contact hole 54. Further, the emitter electrode 52 is connected to the dummy conductive portion in the dummy trench portion 30 through the contact hole 56. A connection portion 25 formed of a conductive material such as impurity-doped polysilicon may be provided between the emitter electrode 52 and the dummy conductive portion. An insulating film such as an oxide film is formed between the connection portion 25 and the upper surface of the semiconductor substrate 10.

[0059] The first gate runner 50 is connected to the third gate runner 48 through the contact hole 49 provided in the interlayer insulating film. The third gate runner 48 is connected to the gate conductive portion in the gate trench portion 40. The third gate runner 48 is not connected to the dummy conductive portion in the dummy trench portion 30. In this example, the gate trench portion 40 extends in the Y-axis direction to a position overlapping the third gate runner 48, and the dummy trench portion 30 is arranged to extend in the Y-axis direction in a range not overlapping the third gate runner 48.

[0060] The third gate runner 48 arranged along the first gate runner 50 is provided extending in the Y-axis direction from a position overlapping the first gate runner 50 to a position not overlapping the first gate runner 50. The third gate runner 48 is connected to the gate trench portion 40 at a position not overlapping the first gate runner 50. Note that the semiconductor device 100 may not have the third gate runner 48 along the first gate runner 50. In this case, the gate trench portion 40 may be directly connected to the first gate runner 50.

[0061] In this specification, when the gate trench portion 40 is directly connected to the first gate runner 50 (or the second gate runner 51), it means that the gate trench portion 40 is arranged to a position overlapping with the first gate runner 50 (or the second gate runner 51), and refers to a state where the gate trench portion 40 and the first gate runner 50 (or the second gate runner 51) are connected by a contact hole. When the gate trench portion 40 is indirectly connected to the first gate runner 50 (or the second gate runner 51), it means that a third gate runner 48 overlapping with the first gate runner 50 (or the second gate runner 51) is provided to extend in the Y-axis direction to a position not overlapping with the first gate runner 50 (or the second gate runner 51), and refers to a state where the gate trench portion 40 is connected to the first gate runner 50 (or the second gate runner 51) via the third gate runner 48. When the gate trench portion 40 and the first gate runner 50 are indirectly connected, the gate trench portion 40 and the third gate runner 48 are connected in the vicinity of the first gate runner 50. The distance in the Y-axis direction between the connection point of the gate trench portion 40 and the third gate runner 48 and the first gate runner 50 may be 10 times or less, or may be 5 times or less, of the width of the first gate runner 50 in the Y-axis direction. Similarly, when the gate trench portion 40 and the second gate runner 51 are indirectly connected, the gate trench portion 40 and the third gate runner 48 are connected in the vicinity of the second gate runner 51. The distance in the Y-axis direction between the connection point of the gate trench portion 40 and the third gate runner 48 and the second gate runner 51 may be 10 times or less, or may be 5 times or less, of the width of the second gate runner 51 in the Y-axis direction. In this specification, direct connection and indirect connection may be collectively referred to as connection in some cases.

[0062] In this example, the emitter electrode 52 and the first gate runner 50 are formed of a material containing metal. For example, at least a part of each electrode is formed of aluminum or an aluminum-silicon alloy. Each electrode may have a barrier metal formed of titanium, a titanium compound, or the like under a region formed of aluminum or the like, and may have a plug formed of tungsten or the like in the contact hole.

[0063] One or more gate trench portions 40 and one or more dummy trench portions 30 are arranged at predetermined intervals along a predetermined arrangement direction (the X-axis direction in this example) on the upper surface of the semiconductor substrate 10. In the transistor portion 70 of this example, one or more gate trench portions 40 and one or more dummy trench portions 30 are alternately formed along the arrangement direction.

[0064] The gate trench portion 40 of this example may have two linear portions 39 that linearly extend along an extending direction perpendicular to the arrangement direction (the Y-axis direction in this example), and a tip portion 41 that connects the two linear portions 39. At least a part of the tip portion 41 is preferably formed in a curved shape on the upper surface of the semiconductor substrate 10. By connecting the ends, which are linear-shaped ends along the extending direction, of the two linear portions 39 of the gate trench portion 40 with the tip portion 41, the electric field concentration at the ends of the linear portions 39 can be alleviated.

[0065] At least one dummy trench portion 30 is provided between the respective linear portions 39 of the gate trench portion 40. These dummy trench portions 30 may have a linear portion 29 and a tip portion 31 similar to the gate trench portion 40. In another example, the dummy trench portion 30 may have a linear portion 29 and may not have a tip portion 31. In the example shown in FIG. 3, in the transistor portion 70, two linear portions 29 of the dummy trench portion 30 are arranged between the two linear portions 39 of the gate trench portion 40.

[0066] In the diode section 80, a plurality of dummy trench sections 30 are arranged along the X-axis direction on the upper surface of the semiconductor substrate 10. The shape of the dummy trench section 30 in the XY plane in the diode section 80 may be the same as that of the dummy trench section 30 provided in the transistor section 70.

[0067] The tip portion 31 and the straight portion 29 of the dummy trench section 30 have the same shape as the tip portion 41 and the straight portion 39 of the gate trench section 40. The length in the Y-axis direction of the dummy trench section 30 provided in the diode section 80 and the straight-shaped dummy trench section 30 provided in the transistor section 70 may be the same.

[0068] The emitter electrode 52 is formed above the gate trench section 40, the dummy trench section 30, the well region 11, the emitter region 12, the base region 14, and the contact region 15. The well region 11 and the end on the side where the first gate runner 50 is provided among the ends in the extending direction of the contact hole 54 are provided apart from each other in the XY plane. The diffusion depth of the well region 11 may be deeper than the depths of the gate trench section 40 and the dummy trench section 30. A part of the regions of the gate trench section 40 and the dummy trench section 30 on the first gate runner 50 side is formed in the well region 11. The bottom in the Z-axis direction of the tip portion 41 of the gate trench section 40 and the bottom in the Z-axis direction of the tip portion 31 of the dummy trench section 30 may be covered by the well region 11.

[0069] In each of the transistor section 70 and the diode section 80, one or more mesa sections 60 are provided between the respective trench sections. The mesa section 60 is a region on the upper surface side of the deepest bottom of the trench section in the region of the semiconductor substrate 10 sandwiched between the trench sections.

[0070] The base region 14 is formed in the mesa section 60 sandwiched between the respective trench sections. The base region 14 has a second conductivity type (P-type) with a lower doping concentration than the well region 11.

[0071] On the upper surface of the base region 14 of the mesa portion 60, a contact region 15 of the second conductivity type having a doping concentration higher than that of the base region 14 is formed. The contact region 15 in this example is of P+ type. On the upper surface of the semiconductor substrate 10, the well region 11 may be formed away from the contact region 15 disposed at the outermost end in the Y-axis direction among the contact regions 15, in the direction of the first gate runner 50. On the upper surface of the semiconductor substrate 10, the base region 14 is exposed between the well region 11 and the contact region 15.

[0072] In the transistor portion 70, an emitter region 12 of the first conductivity type having a doping concentration higher than that of the drift region formed inside the semiconductor substrate 10 is selectively formed on the upper surface of the mesa portion 60-1. The emitter region 12 in this example is of N+ type. Among the base regions 14 adjacent to the emitter region 12 of the semiconductor substrate 10 in the depth direction (-Z-axis direction) of the emitter region 12, the portion in contact with the gate trench portion 40 functions as a channel portion. When an on-voltage is applied to the gate trench portion 40, in the base region 14 provided between the emitter region 12 and the drift region in the Z-axis direction, a channel, which is an inversion layer of electrons, is formed in the portion adjacent to the gate trench portion 40. When a channel is formed in the base region 14, carriers flow between the emitter region 12 and the drift region.

[0073] In this example, base regions 14-e are disposed at both ends in the Y-axis direction of each mesa portion 60. In this example, on the upper surface of each mesa portion 60, the region adjacent to the base region 14-e on the central side of the mesa portion 60 is the contact region 15. Further, the region in contact with the base region 14-e on the side opposite to the contact region 15 is the well region 11.

[0074] In the mesa portion 60-1 of the transistor portion 70 in this example, in the region sandwiched between the base regions 14-e at both ends in the Y-axis direction, the contact region 15 and the emitter region 12 are alternately arranged along the Y-axis direction. Each of the contact region 15 and the emitter region 12 is formed from one adjacent trench portion to the other trench portion.

[0075] Of the mesa portions 60 of the transistor portion 70, one or more mesa portions 60-2 provided at the boundary with the diode portion 80 are provided with a contact region 15 having a larger area than the contact region 15 of the mesa portion 60-1. The emitter region 12 may not be provided in the mesa portion 60-2. In the mesa portion 60-2 of this example, the contact region 15 is provided over the entire region sandwiched by the base regions 14-e.

[0076] In each mesa portion 60-1 of the transistor portion 70 of this example, the contact hole 54 is formed above each of the contact region 15 and the emitter region 12. The contact hole 54 in the mesa portion 60-2 is formed above the contact region 15. The contact hole 54 is not formed in the regions corresponding to the base region 14-e and the well region 11 in each mesa portion 60. The contact holes 54 in each mesa portion 60 of the transistor portion 70 may have the same length in the Y-axis direction.

[0077] In the diode portion 80, an N+-type cathode region 82 is formed in the region in contact with the lower surface of the semiconductor substrate 10. In FIG. 2, the region where the cathode region 82 is formed is indicated by a broken line. A P+-type collector region may be formed in the region where the cathode region 82 is not formed in the region in contact with the lower surface of the semiconductor substrate 10.

[0078] The transistor portion 70 may be a region where a mesa portion 60 in which the contact region 15 and the emitter region 12 are formed and a trench portion adjacent to the mesa portion 60 are provided among the regions overlapping the collector region in the Z-axis direction. However, in the mesa portion 60-2 at the boundary with the diode portion 80, the contact region 15 may be provided instead of the emitter region 12.

[0079] The base region 14 is disposed on the upper surface of the mesa portion 60-3 of the diode portion 80. However, a contact region 15 may be provided in a region adjacent to the base region 14-e. Above the contact region 15, the contact hole 54 terminates.

[0080] FIG. 3 is a diagram showing an example of a B-B cross section in FIG. 2. The B-B cross section includes the diode portion 80 and the transistor portion 70 and is an XZ plane passing through the emitter region 12.

[0081] In the semiconductor device 100 of this example, in the cross section, it has the semiconductor substrate 10, the interlayer insulating film 38, the emitter electrode 52, and the collector electrode 24. The interlayer insulating film 38 is formed to cover at least a part of the upper surface of the semiconductor substrate 10. Through holes such as the contact hole 54 are formed in the interlayer insulating film 38. The upper surface of the semiconductor substrate 10 is exposed by the contact hole 54. The interlayer insulating film 38 may be a silicate glass such as PSG or BPSG, or may be an oxide film, a nitride film, or the like.

[0082] The emitter electrode 52 is formed on the upper surfaces of the semiconductor substrate 10 and the interlayer insulating film 38 in the transistor portion 70 and the diode portion 80. The emitter electrode 52 is also formed inside the contact hole 54 and is in contact with the upper surface 21 of the semiconductor substrate 10 exposed by the contact hole 54.

[0083] The collector electrode 24 is formed on the lower surface 23 of the semiconductor substrate 10. The collector electrode 24 may be in contact with the entire lower surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are formed of a conductive material such as metal. In this specification, the direction connecting the emitter electrode 52 and the collector electrode 24 is referred to as the depth direction (Z-axis direction). The direction from the collector electrode 24 toward the emitter electrode 52 is defined as the positive direction of the Z-axis direction.

[0084] On the upper surface side of the semiconductor substrate 10 in the diode portion 80 and the transistor portion 70, a P-type base region 14 is formed. Inside the semiconductor substrate 10 and below the base region 14, an N-type drift region 18 is disposed. Each trench portion is provided from the upper surface of the semiconductor substrate 10, penetrating the base region 14 and reaching the drift region 18.

[0085] In the cross section, in each mesa portion 60-1 of the transistor portion 70, an N+-type emitter region 12, a P-type base region 14, and an N+-type accumulation region 16 are arranged in order from the upper surface side of the semiconductor substrate 10. In the accumulation region 16, donors are accumulated at a higher concentration than in the drift region 18. A drift region 18 is provided below the accumulation region 16. The accumulation region 16 may be provided so as to cover the entire lower surface of the base region 14 in each mesa portion 60. That is, the accumulation region 16 may be sandwiched in the X-axis direction by the trench portions. By providing an accumulation region 16 having a higher concentration than the drift region 18 between the drift region 18 and the base region 14, the carrier injection promotion effect (IE effect, Injection-Enhancement effect) can be enhanced, and the on-voltage in the transistor portion 70 can be reduced.

[0086] In the XZ cross section passing through the contact region 15 of the transistor portion 70, in each mesa portion 60-1 of the transistor portion 70, a contact region 15 is provided instead of the emitter region 12. Also, in the mesa portion 60-2, a contact region 15 is provided instead of the emitter region 12. The contact region 15 may function as a latch-up suppression layer for suppressing latch-up.

[0087] In the cross section, in each mesa portion 60-3 of the diode portion 80, a P-type base region 14 and an N+-type accumulation region 16 are arranged in order from the upper surface side of the semiconductor substrate 10. A drift region 18 is provided below the accumulation region 16. The diode portion 80 may not be provided with the accumulation region 16.

[0088] In the transistor section 70, a P+-type collector region 22 is provided in a region adjacent to the lower surface 23 of the semiconductor substrate 10. In the diode section 80, an N+-type cathode region 82 is provided in a region adjacent to the lower surface 23 of the semiconductor substrate 10.

[0089] In the semiconductor substrate 10 of this example, an N+-type buffer region 20 is provided between the drift region 18 and the collector region 22, and between the drift region 18 and the cathode region 82. The doping concentration of the buffer region 20 is higher than the doping concentration of the drift region 18. The buffer region 20 may function as a field stop layer that prevents the depletion layer spreading from the lower surface side of the base region 14 from reaching the P+-type collector region 22 and the N+-type cathode region 82.

[0090] On the upper surface 21 side of the semiconductor substrate 10, one or more gate trench portions 40 and one or more dummy trench portions 30 are formed. Each trench portion penetrates from the upper surface 21 of the semiconductor substrate 10 through the base region 14 and reaches the drift region 18. In a region where at least one of the emitter region 12, the contact region 15, and the accumulation region 16 is provided, each trench portion also penetrates these regions and reaches the drift region 18. The fact that the trench portion penetrates the doping region is not limited to the case where the trench portion is formed in the order of forming the doping region after forming the trench portion. Those in which the doping region is formed between the trench portions after forming the trench portion are also included in those in which the trench portion penetrates the doping region.

[0091] The gate trench portion 40 has a gate trench formed on the upper surface side of the semiconductor substrate 10, a gate insulating film 42, and a gate conductive portion 44. The gate insulating film 42 is formed to cover the inner wall of the gate trench. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate conductive portion 44 is formed inside the gate insulating film 42 in the gate trench. That is, the gate insulating film 42 insulates the gate conductive portion 44 and the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon.

[0092] The gate conductive portion 44 includes a region along the depth direction that faces at least the adjacent base region 14 with the gate insulating film 42 interposed therebetween in the depth direction. The gate trench portion 40 in the cross section is covered by the interlayer insulating film 38 on the upper surface of the semiconductor substrate 10. When a predetermined voltage is applied to the gate conductive portion 44, a channel formed by an electron inversion layer is formed on the surface layer of the interface of the base region 14 that contacts the gate trench.

[0093] The dummy trench portion 30 may have the same structure as the gate trench portion 40 in the cross section. The dummy trench portion 30 has a dummy trench, a dummy insulating film 32, and a dummy conductive portion 34 formed on the upper surface 21 side of the semiconductor substrate 10. The dummy insulating film 32 is formed to cover the inner wall of the dummy trench. The dummy conductive portion 34 is formed inside the dummy trench and inside the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy conductive portion 34 may be formed of the same material as the gate conductive portion 44. For example, the dummy conductive portion 34 is formed of a conductive material such as polysilicon. The dummy conductive portion 34 may have the same length as the gate conductive portion 44 in the depth direction. The dummy trench portion 30 in the cross section is covered by the interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. Note that the bottoms of the dummy trench portion 30 and the gate trench portion 40 may be curved convex downward (curved in the cross section).

[0094] FIG. 4 is an enlarged view of the vicinity of region B in FIG. 1. Region B is a region including a pad (in this example, the cathode pad 117), a second gate runner 51 arranged along the first side 132 of the pad, a first gate runner 50, and an inter-pad region 130. Region B faces the transistor portion 70 in the main active portion 120 in the Y-axis direction and does not face the diode portion 80. Also, the first side 132 of the cathode pad 117 is a side parallel to the Y-axis direction.

[0095] The second gate runner 51 is disposed between the first side 132 of the cathode pad 117 and the inter-pad region 130. A well region 11 may be exposed on the upper surface of the semiconductor substrate 10 between the second gate runner 51 and the cathode pad 117.

[0096] As described above, the gate trench portion 40 provided in the inter-pad region 130 is directly or indirectly connected to the first gate runner 50. The tip portion 41 of the gate trench portion 40 in this example is disposed below the third gate runner 48 and is connected to the third gate runner 48.

[0097] The gate trench portion 40 provided in the inter-pad region 130 may be a trench portion in which the gate trench portion 40 provided in the main active portion 120 extends in the Y-axis direction. That is, the gate trench portion 40 in the main active portion 120 and the gate trench portion 40 in the inter-pad region 130 may be continuous.

[0098] Also, a dummy trench portion 30 may be provided in the inter-pad region 130. The dummy trench portion 30 may also be provided by extending the dummy trench portion 30 provided in the main active portion 120 to the inter-pad region 130. A well region 11 is provided below the first gate runner 50, and the well region 11 extends in the Y-axis direction and is also provided in a part of the inter-pad region 130. The tip portion 31 of the dummy trench portion 30 is provided at a position overlapping the well region 11. The emitter electrode 52 is also provided from the main active portion 120 to a position overlapping the well region 11. The tip portion 31 of the dummy trench portion 30 is connected to the emitter electrode 52 via a contact hole 56. Note that a well region 11 is also provided below the second gate runner 51, and the well region 11 extends in the X-axis direction and is also provided in a part of the inter-pad region 130.

[0099] The structure of each mesa portion 60 in the inter-pad region 130 may be the same as the structure of the mesa portion 60 in the main active portion 120 described in FIGS. 2 and 3. On the upper surface of the mesa portion 60-1 in the inter-pad region 130, the contact region 15 and the emitter region 12 are alternately provided in the Y-axis direction.

[0100] Also, in the inter-pad region 130, a dummy trench portion 30 may be provided between the gate trench portion 40 disposed closest to the cathode pad 117 in the X-axis direction and the cathode pad 117. An mesa portion 60-2 without the emitter region 12 is disposed adjacent to the dummy trench portion 30. A plurality of mesa portions 60-2 may be arranged in the X-axis direction. Thereby, in the inter-pad region 130, the distance between the pad and the emitter region 12 can be increased.

[0101] Also, in the inter-pad region 130, a contact hole 54 may be provided between the gate trench portion 40 closest to the cathode pad 117 in the X-axis direction and the cathode pad 117. Also, in the inter-pad region 130, a contact hole 54 may be provided between the dummy trench portion 30 closest to the cathode pad 117 in the X-axis direction and the cathode pad 117. In the inter-pad region 130, a contact hole 54 may be provided between the trench portion closest to the cathode pad 117 in the X-axis direction and the cathode pad 117.

[0102] Also, the mesa portion 60 continuously provided in the Y-axis direction from the main active portion 120 to the inter-pad region 130 may have the same structure in the main active portion 120 and the inter-pad region 130 except for the tip portion in the Y-axis direction. For example, on the upper surface of the mesa portion 60-1, the contact region 15 and the emitter region 12 may be alternately provided in the Y-axis direction in both the main active portion 120 and the inter-pad region 130.

[0103] Further, the structure of the mesa portion 60 may be different between the inter-pad region 130 and the main active portion 120. For example, in some mesa portions 60-2, the emitter region 12 may not be provided in the inter-pad region 130, and the contact region 15 and the emitter region 12 may be alternately arranged in the main active portion 120.

[0104] FIG. 5 is an enlarged view of the vicinity of region C in FIG. 1. Region C is a region including a pad (in this example, the cathode pad 117), a second gate runner 51 arranged along the second side 134 of the pad, a transistor portion 70 and a diode portion 80 of the main active portion 120. Further, the second side 134 of the cathode pad 117 is a side parallel to the X-axis direction and is a side facing the main active portion 120.

[0105] The second gate runner 51 is arranged between the second side 134 of the cathode pad 117 and the transistor portion 70 and the diode portion 80. A well region 11 may be exposed on the upper surface of the semiconductor substrate 10 between the second gate runner 51 and the cathode pad 117.

[0106] As described above, the gate trench portion 40 arranged to face the second gate runner 51 in the Y-axis direction is directly or indirectly connected to the second gate runner 51. The tip portion 41 of the gate trench portion 40 in this example is arranged below the third gate runner 48 and is connected to the third gate runner 48.

[0107] Further, a well region 11 is provided below the second gate runner 51, and the well region 11 extends in the Y-axis direction and is provided up to the main active portion 120 side from the second gate runner 51. The tip portion 31 of the dummy trench portion 30 is provided at a position overlapping the well region 11. The tip portion 31 of the dummy trench portion 30 is connected to the emitter electrode 52 via the contact hole 56.

[0108] With the structures shown in FIGS. 4 and 5, each gate trench portion 40 can be easily connected directly or indirectly to the first gate runner 50 and the second gate runner 51 made of metal. Thereby, variations in the delay and attenuation of the gate voltage applied to each gate trench portion 40 can be reduced.

[0109] Also, the distance D1 between the pad and the second gate runner 51 in a top view may be 200 μm or less. The distance D1 may be 150 μm or less, may be 120 μm or less, or may be 100 μm or less. Further, the distance D1 may be 1.5 times or less, or may be 1 time or less, of the thickness of the semiconductor substrate 10 in the Z-axis direction. The distance D1 in the Y-axis direction may satisfy the above conditions, and the distance D1 in the X-axis direction may also satisfy the above conditions. By reducing the distance between the pad and the second gate runner 51, the area of the active region can be increased.

[0110] FIG. 6 is a diagram showing an arrangement example of the emitter electrode 52 in a top view. The emitter electrode 52 may be provided above the main active portion 120 and at least a part of the inter-pad region 130. The emitter electrode 52 in this example is not provided above the inter-pad region 130 where the current sense element 119 is provided. Also, the emitter electrode 52 may be provided at a position overlapping the emitter pad 115.

[0111] FIG. 7 is a diagram showing an arrangement example of the cathode region 82. In the inter-pad region 130 in this example, the cathode region 82 is not provided. That is, the cathode region 82 provided in the main active portion 120 does not extend to the inter-pad region 130. However, the structure of the diode portion 80 other than the cathode region 82 may be provided in the inter-pad region 130. With such a structure, the distance between the N+-type cathode region 82 and the relatively deeply formed P+-type well region 11 can be ensured, and a decrease in breakdown voltage due to providing an element region in the inter-pad region 130 can be suppressed.

[0112] Note that the cathode region 82-1 disposed to face the inter-pad region 130 in the Y-axis direction may be provided longer in the Y-axis direction than the cathode region 82-2 disposed to face the pad or the second gate runner 51 in the Y-axis direction. However, the cathode region 82-1 does not extend up to the inter-pad region 130. This makes it easier to secure the distance between the cathode region 82 and the well region 11 while increasing the area of the cathode region 82.

[0113] Note that each of the plurality of pads disposed along the first side 142 may be provided at least partially at a position facing the diode portion 80 (cathode region 82) in the Y-axis direction. This makes it easier to provide the structure of the transistor portion 70 provided in the main active portion 120 so as to extend up to the inter-pad region 130. Therefore, the area of the transistor portion 70 can be easily increased.

[0114] Also, the distance D2 in the X-axis direction between the pad disposed at the outermost end in the X-axis direction and the first gate runner 50 may be 500 μm or less. By disposing the pad near the first gate runner 50, the inter-pad region 130 can be enlarged in the X-axis direction. The distance D2 may be 300 μm or less, may be 200 μm or less, or may be 100 μm or less. The distance D2 may be 1.5 times or less the thickness of the semiconductor substrate 10, or may be 1 time or less.

[0115] FIG. 8 is an enlarged view of the vicinity of region D in FIG. 7. Region D is a region that faces the diode portion 80 and the transistor portion 70 of the main active portion 120 in the Y-axis direction in the inter-pad region 130.

[0116] As described with reference to FIG. 7, the cathode region 82 is not provided in the inter-pad region 130. However, the dummy trench portion 30 of the diode portion 80 disposed to face the inter-pad region 130 in the Y-axis direction is provided so as to extend up to the inter-pad region 130. Also, the mesa portion 60-3 of the diode portion 80 is provided so as to extend up to the inter-pad region 130.

[0117] With such a structure, while maintaining the structural continuity between the inter-pad region 130 and the main active portion 120, the distance between the cathode region 82 and the well region 11 can be ensured. By maintaining the structural continuity, the local concentration of the electric field can be suppressed.

[0118] FIG. 9 is a diagram showing another arrangement example of the cathode region 82. In the inter-pad region 130 in this example, the cathode region 82 is provided. For example, the cathode region 82 provided in the main active portion 120 extends to the inter-pad region 130. With such a structure, the area of the cathode region 82 can be increased, and the element region operating as the diode portion 80 can be enlarged.

[0119] Note that when the distance in the X-axis direction between the cathode region 82 and the well region 11 becomes too close, it is preferable not to extend the cathode region 82 of the main active portion 120 to the inter-pad region 130. As an example, on the condition that the distance in the X-axis direction between the cathode region 82 and the well region 11 is 200 μm or more, the cathode region 82 may be extended to the inter-pad region 130. The said distance may be 100 μm or more, and may also be equal to or greater than the thickness of the semiconductor substrate 10.

[0120] FIG. 10 is an enlarged view of the vicinity of region E in FIG. 9. Region E is a region in the inter-pad region 130 that faces the diode portion 80 and the transistor portion 70 of the main active portion 120 in the Y-axis direction.

[0121] As described with reference to FIG. 9, the cathode region 82 is provided in the inter-pad region 130. Also, the dummy trench portion 30 and the mesa portion 60-3 also extend to the inter-pad region 130. With such a structure, the area of the diode portion 80 can be enlarged.

[0122] FIG. 11 shows another example of region B in FIG. 1. In this example, among the gate trench portions 40 provided in the inter-pad region 130, the emitter region 12 is not provided in contact with the gate trench portion 40-1 closest to the pad in the X-axis direction. Thereby, the distance between the pad and the emitter region 12 can be made larger. A contact region 15 may be provided in the mesa portion 60 adjacent to the gate trench portion 40-1 instead of the emitter region 12.

[0123] FIG. 12 is a diagram showing an example of the arrangement of the gate trench portions 40 in the main active portion 120 and the inter-pad region 130. As described above, the gate trench portions 40 in the inter-pad region 130 may be provided continuously with the gate trench portions 40 in the main active portion 120. Similarly, the dummy trench portions 30 may also be provided continuously in the inter-pad region 130 and the main active portion 120.

[0124] FIG. 13 is a diagram showing another example of the arrangement of the gate trench portions 40 in the main active portion 120 and the inter-pad region 130. In this example, the gate trench portions 40 in the inter-pad region 130 are separated from the gate trench portions 40 in the main active portion 120. The gate trench portions 40 in the inter-pad region 130 may be provided extending in the X-axis direction. The gate trench portions 40 in the inter-pad region 130 may be directly or indirectly connected to the second gate runner 51 provided in the Y-axis direction. The gate trench portions 40 in this example are directly or indirectly connected to the second gate runners 51 provided at both ends of the inter-pad region 130 in the X-axis direction. The dummy trench portions 30 in the inter-pad region 130 may also be provided extending in a direction parallel to the gate trench portions 40.

[0125] Note that the gate trench portion 40 of the main active portion 120 facing the inter-pad region 130 in the Y-axis direction may be connected to a third gate runner 48 disposed between the inter-pad region 130 and the main active portion 120. The third gate runner 48 is connected to second gate runners 51 provided at both ends of the inter-pad region 130 in the X-axis direction. Even with such a structure, each gate trench portion 40 can be connected to the gate runner portion.

[0126] FIG. 14 is a diagram showing another arrangement example of the gate trench portion 40 in the main active portion 120 and the inter-pad region 130. In this example, the gate trench portion 40 in the inter-pad region 130 is separated from the gate trench portion 40 of the main active portion 120. In this example, the gate trench portion 40 in the inter-pad region 130 is provided so as to extend in the Y-axis direction.

[0127] The gate trench portion 40 of the inter-pad region 130 may be directly or indirectly connected to the first gate runner 50. The gate trench portion 40 of the main active portion 120 facing the inter-pad region 130 in the Y-axis direction may be connected to a third gate runner 48 disposed between the inter-pad region 130 and the main active portion 120. Even with such a structure, each gate trench portion 40 can be connected to the gate runner portion.

[0128] As described above, the present invention has been described using embodiments, but the technical scope of the present invention is not limited to the scope described in the above embodiments. It is obvious to those skilled in the art that various changes or improvements can be made to the above embodiments. It is clear from the description of the claims that forms with such changes or improvements can also be included in the technical scope of the present invention.

[0129] In the claims, the specification, and the drawings, the execution order of each process such as the operations, procedures, steps, and stages in the apparatus, system, program, and method shown is not explicitly indicated as "before" or "preceding" etc. in particular. It should be noted that, unless the output of the previous process is used in the subsequent process, it can be realized in any order. Regarding the operation flows in the claims, the specification, and the drawings, even if explanations are given using "first," "next," etc. for convenience, it does not mean that it is essential to implement in this order.

Explanation of Reference Numerals

[0130] 10 ··· semiconductor substrate, 11 ··· well region, 12 ··· emitter region, 14 ··· base region, 15 ··· contact region, 16 ··· accumulation region, 18 ··· drift region, 20 ··· buffer region, 21 ··· upper surface, 22 ··· collector region, 23 ··· lower surface, 24 ··· collector electrode, 25 ··· connection portion, 29 ··· straight portion, 30 ··· dummy trench portion, 31 ··· tip portion, 32 ··· dummy insulating film, 34 ··· dummy conductive portion, 38 ··· interlayer insulating film, 39 ··· straight portion, 40 ··· gate trench portion, 41 ··· tip portion, 42 ··· gate insulating film, 44 ··· gate conductive portion, 48 ··· third gate runner, 49 ··· contact hole, 50 ··· first gate runner, 51 ··· second gate runner, 52 ··· emitter electrode, 54 ··· contact hole, 56 ··· contact hole, 60 ··· mesa portion, 70 ··· transistor portion, 80 ··· diode portion, 82 ··· cathode region, 90 ··· edge termination structure portion, 92 ··· guard ring, 100 ··· semiconductor device, 110 ··· temperature sense portion, 112 ··· temperature sense wiring, 114 ··· sense pad, 115 ··· emitter pad, 116 ··· gate pad, 117 ··· cathode pad, 118 ··· anode pad, 119 ··· current sense element, 120 ··· main active portion, 130 ··· pad-to-pad region, 132 ··· first side, 134 ··· second side, 140 ··· outer peripheral end, 142 ··· first end side

Claims

1. A semiconductor device having a transistor portion and a diode portion provided on a semiconductor substrate, a plurality of pads arranged along a first edge of the semiconductor substrate in a top view; an inter-pad region that is a region sandwiched between the pads in a top view; a cathode region of a first conductivity type provided in a region in contact with a lower surface of the semiconductor substrate, at least a portion of which is disposed in the inter-pad region in a top view; A semiconductor device comprising:

2. a collector region of a second conductivity type provided in a region in contact with the lower surface of the semiconductor substrate, at least a portion of which is disposed in the inter-pad region when viewed from above; The semiconductor device according to claim 1 .

3. The collector region is disposed between the first edge and the cathode region of the inter-pad region. The semiconductor device according to claim 2 .

4. The cathode region is also disposed in a main active portion, which is a region other than the inter-pad region, among the regions in which the transistor portion and the diode portion are provided. The semiconductor device according to claim 1 .

5. The cathode region is provided from the main active portion to the inter-pad region. The semiconductor device according to claim 4.

6. Any of the plurality of pads is disposed at an end in a first direction parallel to the first end side. The semiconductor device according to claim 1 .

7. The semiconductor substrate includes a gate trench portion and a dummy trench portion as trench portions provided on an upper surface side of the semiconductor substrate and at least a portion of which is disposed in the inter-pad region. The semiconductor device according to claim 1 .

8. The gate trench portion and the dummy trench portion extend in a second direction perpendicular to the first end side. The semiconductor device according to claim 7.

9. an upper surface electrode provided on an upper surface of the semiconductor substrate via an insulating film; the upper electrode is in contact with the upper surface of the semiconductor substrate through a contact hole formed in the insulating film; In the inter-pad region, the contact hole is provided between the pad and the trench portion closest to the pad. The semiconductor device according to claim 8.

10. In the inter-pad region, a plurality of the contact holes are provided between the pad and the trench portion closest to the pad. The semiconductor device according to claim 9.

11. A gate runner is provided in the inter-pad region between the pad and the trench portion closest to the pad. The semiconductor device according to claim 8 .

12. The gate trench portion and the dummy trench portion extend in a first direction parallel to the first end side. The semiconductor device according to claim 7.

13. a second conductivity type base region provided on an upper surface side of the semiconductor substrate, at least a portion of which is disposed in the inter-pad region; a well region of a second conductivity type provided on an upper surface side of the semiconductor substrate, the well region being deeper than the base region and at least a portion of which is disposed in the inter-pad region; The semiconductor device according to claim 1 , comprising:

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