Silicon carbide MOSFET device and method for manufacturing the same

Abstract

The present application discloses a silicon carbide MOSFET device and a method for manufacturing the same, the silicon carbide MOSFET device including an epitaxial wafer including a semiconductor substrate and an epitaxial layer provided on a surface of the substrate, and a well region, a source region and a trench gate provided in the epitaxial layer, the trench gate including a trench located in a surface of the epitaxial layer opposite the substrate and a gate located in the trench, the source region surrounding the trench and contacting a sidewall of the trench, the well region being provided in the substrate in a direction toward the source region. the third-layer well region surrounds the trench and contacts a sidewall of the trench; a doped region is in the epitaxial layer below the trench; the first-layer well region surrounds the doped region and contacts the doped region; a partial epitaxial layer is between the first-layer well region and the third-layer well region; the second-layer well region is located on both sides of the partial epitaxial layer; a masking layer is in the partial epitaxial layer for protecting a bottom of the trench gate; and the masking layer is located below the trench.

Description

Cross-reference

[0001] This application claims the priority of a Chinese patent application filed with the State Intellectual Property Office of China on January 4, 2022, with the application number 202210004474.8 and the invention title "Silicon Carbide MOSFET Device and Its Manufacturing Method", and the entire content thereof is incorporated herein by reference.

[0002] This application claims the priority of a Chinese patent application filed with the State Intellectual Property Office of China on January 4, 2022, with the application number 202220017322.7 and the invention title "Silicon Carbide MOSFET Device", and the entire content thereof is incorporated herein by reference.

Technical Field

[0003] This application relates to the technical field of semiconductor devices, and particularly to silicon carbide (SiC) MOSFET devices and their manufacturing methods.

Background Art

[0004] With the continuous development of science and technology, more and more electronic devices are widely used in people's daily lives and work, bringing great convenience to people's daily lives and work, and becoming an indispensable and important tool for people today.

[0005] The main structure for electronic devices to achieve various functions is an integrated circuit, and the MOSFET device is an important component of the integrated circuit. The silicon carbide MOSFET device has become a major development direction in the semiconductor field due to its excellent characteristics in high-power applications.

[0006] Existing silicon carbide MOSFET devices still have drawbacks, and it is necessary to further optimize their structures and manufacturing methods to improve performance.

Summary of the Invention

[0007] An epitaxial wafer including a semiconductor substrate and an epitaxial layer provided on the surface of the substrate, In a silicon carbide MOSFET device including a well region, a source region, and a trench gate provided in the epitaxial layer,

[0008] The trench gate includes a trench located in the surface of the epitaxial layer opposite to the substrate, and a gate located in the trench, and there is a gate derivative layer between the gate and the trench. The source region surrounds the trench and is in contact with the side wall of the trench. The well region includes a first-layer well region, a second-layer well region, and a third-layer well region provided in sequence in the direction from the substrate toward the source region. The bottom of the trench is located between the first-layer well region and the third-layer well region. The third-layer well region surrounds the trench and is in contact with the side wall of the trench. There is a doping region in the epitaxial layer under the trench. The first-layer well region surrounds the doping region and is in contact with the doping region. There is a partial epitaxial layer between the first-layer well region and the third-layer well region. The second-layer well region is located on both sides of the partial epitaxial layer. There is a masking layer in the partial epitaxial layer for protecting the bottom of the trench gate. The masking layer is located under the trench. A silicon carbide MOSFET device having the same doping type as each layer of the well region.

[0009] Preferably, in the above silicon carbide MOSFET device, the vertical projection of the doping region on the substrate is located within the vertical projection of the trench on the substrate. The vertical projection of the trench on the substrate is located within the vertical projection of the partial epitaxial layer on the substrate, and the two vertical projections have a non-zero interval.

[0010] Preferably, in the above silicon carbide MOSFET device, there is also a connection region connecting the masking layer and the first-layer well region in the partial epitaxial layer, and the connection region has the same doping type as each layer of the well region.

[0011] Preferably, in the above silicon carbide MOSFET device, the first layer well region includes a first portion of the first layer well region and a second portion of the first layer well region, which are respectively located on both sides of the trench, The first portion of the first layer well region is connected to the masking layer through a plurality of the connection regions arranged in sequence in a first direction, and / or the second portion of the first layer well region is connected to the masking layer through a plurality of the connection regions arranged in sequence in a first direction, Here, the first direction is parallel to the substrate and parallel to the extending direction of the trench.

[0012] Preferably, in the above silicon carbide MOSFET device, there is at least one doping region under the trench, When there are a plurality of the doping regions, the plurality of the doping regions are arranged in sequence in a first direction, where the first direction is parallel to the substrate and parallel to the extending direction of the trench.

[0013] Preferably, in the above silicon carbide MOSFET device, in the direction perpendicular to the substrate, the distance from the masking layer to the bottom of the trench is smaller than the distance to the first layer well region.

[0014] Preferably, in the above silicon carbide MOSFET device, the masking layer is in contact with the bottom of the trench.

[0015] Preferably, in the above silicon carbide MOSFET device, the second layer well region includes a first portion of the second layer well region and a second portion of the second layer well region, which are respectively located on both sides of the trench, The first portion of the second layer well region and the second portion of the second layer well region are each an integrated structure.

[0016] Preferably, in the above silicon carbide MOSFET device, the second layer well region includes a first portion of the second layer well region and a second portion of the second layer well region that are respectively located on both sides of the trench, the first portion of the second layer well region and the second portion of the second layer well region each include a plurality of sub-regions arranged in order in a first direction, and in the first direction, there is a current expansion region having a doping type opposite to that of the sub-region between two adjacent sub-regions, where the first direction is parallel to the substrate and parallel to the extending direction of the trench.

[0017] Preferably, in the above silicon carbide MOSFET device, the doping types of the well regions of each layer, the masking layer, and the connection region are the same, and the doping concentration of the connection region is higher than the doping concentration of the well regions of each layer.

[0018] Preferably, in the above silicon carbide MOSFET device, for the same connection region, the connection region extends from the bottom of the trench to at least within the first layer well region, or a part of the connection region extends from the bottom of the trench to at least within the first layer well region, and the other part extends from the surface of the epitaxial layer along the side wall of the trench to at least within the first layer well region.

[0019] This application also provides a method for manufacturing the silicon carbide MOSFET device according to any one of the above items, providing an epitaxial wafer including a semiconductor substrate and an epitaxial layer provided on the surface of the substrate, forming a well region, a source region, and a trench gate in the epitaxial layer, in a manufacturing method including: the trench gate includes a trench located in the surface of the epitaxial layer opposite to the substrate and a gate located in the trench, and there is a gate derivative layer between the gate and the trench, The source region surrounds the trench and is in contact with the sidewall of the trench. The well region includes a first-layer well region, a second-layer well region, and a third-layer well region provided in order in a direction toward the source region of the substrate. The bottom of the trench is located between the first-layer well region and the third-layer well region. The third-layer well region surrounds the trench and is in contact with the sidewall of the trench. There is a doping region in the epitaxial layer under the trench. The first-layer well region surrounds the doping region and is in contact with the doping region. There is a partial epitaxial layer between the first-layer well region and the third-layer well region. The second-layer well region is located on both sides of the partial epitaxial layer. There is a masking layer for protecting the bottom of the trench gate in the partial epitaxial layer. The masking layer is located under the trench and has the same doping type as each layer of the well region.

[0020] Preferably, in the above manufacturing method, the epitaxial layer includes a first epitaxial layer provided on the surface of the substrate, a second epitaxial layer provided on the surface of the first epitaxial layer opposite to the substrate, and a third epitaxial layer provided on the surface of the second epitaxial layer opposite to the first epitaxial layer. The second epitaxial layer has an area to be implanted and a first-layer well region surrounding the area to be implanted. Forming a well region, a source region, and a trench gate in the epitaxial layer is Forming the source region, the second-layer well region, and the third-layer well region in the surface of the third epitaxial layer opposite to the substrate. Forming the trench in the surface of the third epitaxial layer opposite to the substrate. Forming the masking layer and the doping region based on the trench. Forming a connection region connecting the masking layer and the first-layer well region based on the trench. Forming a gate derivative layer and a gate in the trench.

[0021] As can be seen from the above description, in the silicon carbide MOSFET device and its manufacturing method provided by the technical solution of the present application, the silicon carbide MOSFET device includes an epitaxial wafer including a semiconductor substrate and an epitaxial layer provided on the surface of the substrate, a well region, a source region, and a trench gate provided in the epitaxial layer. Here, the trench gate includes a trench located in the surface of the epitaxial layer opposite to the substrate, and a gate located in the trench. There is a gate derivative layer between the gate and the trench. The source region surrounds the trench and is in contact with the side wall of the trench. The well region includes a first layer well region, a second layer well region, and a third layer well region provided in sequence in the direction of the substrate toward the source region. The bottom of the trench is located between the first layer well region and the third layer well region. The third layer well region surrounds the trench and is in contact with the side wall of the trench. There is a doping region in the epitaxial layer under the trench. The first layer well region surrounds the doping region and is in contact with the doping region. There is a partial epitaxial layer between the first layer well region and the third layer well region. The second layer well region is located on both sides of the partial epitaxial layer. There is a masking layer for protecting the bottom of the trench gate in the partial epitaxial layer. The masking layer is located under the trench and has the same doping type as each layer of the well region.

Brief Description of the Drawings

[0022] To more clearly illustrate the technical solutions in the embodiments or related technologies of the present application, the drawings necessary for use in the description of the embodiments or prior art are briefly described below. Obviously, the drawings in the following description are only embodiments of the present application, and those skilled in the art can obtain other drawings based on the provided drawings without creative efforts.

[0023] The structures, ratios, sizes, etc. shown in the drawings of this specification are only used to conform to the content disclosed in the specification for those skilled in the art to understand and read, and are not used to limit the limited conditions under which this application can be implemented, so they have no technical substantial significance. Any modification of the structure, change of the ratio relationship or adjustment of the size shall still be included within the scope of the technical content disclosed in this application without affecting the effects that can be produced by this application and the objectives that can be achieved.

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Embodiments for Carrying Out the Invention

[0024] Regarding the technical solution in the embodiments of the present invention, it will be clearly and completely described below with reference to the drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative efforts are included within the protection scope of the present invention.

[0025] To make the above objects, features, and advantages of the present invention clear and easy to understand, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0026] Due to its excellent properties, SiC material has strong attraction for high power and has become one of the most suitable materials for high-performance power MOSFETs. SiC vertical power MOSFET devices mainly include lateral double-diffused DMOSFETs and UMOSFETs with a vertical gate trench structure.

[0027] As shown in FIG. 1, FIG. 1 is a schematic structural diagram of a DMOSFET, including an n+ (n-type high-concentration doping) substrate 2, an n- (n-type low-concentration doping) drift region 3 provided on the surface of the substrate 2, a p-type well region 4 located within the drift region 3, and a source region 5 including an n+ doping region 51 and a p+ (p-type high-concentration doping) doping region 52 located within the p-type well region. A gate conductor layer 7 is provided on the surface of the drift region 3, and a gate 8 is provided on the surface of the gate conductor layer 7. A drain 1 is provided on the surface of the substrate 2 opposite to the drift region 3.

[0028] The DMOSFET structure adopts planar diffusion technology, uses a high-melting-point material such as polycrystalline silicon gate as a mask, and defines the p-base region and the n+ source region using the edge of the polycrystalline silicon gate. The name DMOS comes from this double-diffusion process. The surface channel region is formed by utilizing the lateral diffusion difference between the p-type base region and the n+ source region.

[0029] As shown in FIG. 2, FIG. 2 is a schematic structural diagram of a UMOSFET. The difference from the structure shown in FIG. 1 is that a U-shaped trench is provided in the UMOSFET. The surface of the U-shaped trench is covered by a gate conductor layer 7, and the gate 8 is filled in the U-shaped trench. The name of the UMOSFET with a vertical gate trench structure is derived from the U-shaped trench structure. This U-shaped trench structure is formed in the gate region using reactive ion etching. Since the U-shaped trench structure has a high channel density (the channel density is defined as the channel width of the active region), the resistance of the on-state characteristics of the device is significantly reduced.

[0030] After years of research on planar SiC MOSFETs in the industry, some manufacturers have taken the lead in launching commercial products. In a general lateral DMOSFET structure, due to modern technological advancements, it is impossible to reduce the on-resistance even when the MOS cell size is reduced. The main reason is that due to the limitation of the resistance in the JFET neck region, even when using a smaller photolithography size, it is difficult to reduce the on-resistance per unit area to 2 mΩ·cm 2 or less. However, the trench structure can effectively solve this problem. The U-shaped trench structure is shown in FIG. 2. By adopting trench etching technology in various processes for manufacturing memory storage capacitors, the conductive channel is changed from horizontal to vertical, eliminating the JFET neck resistance compared to the normal structure, significantly increasing the cell density, and improving the current handling capacity of the power semiconductor.

[0031] However, there are still some problems in the actual process fabrication and application of SiC UMOSFETs.

[0032] 1) A high electric field is generated in the gate conductor layer due to the high electric field in the SiC drift region. This problem is further exacerbated at the trench corner, causing the gate conductor layer to be rapidly damaged under a high drain voltage, resulting in low resistance to electrostatic effects in a harsh environment and high voltage spikes in the circuit.

[0033] 2) Since SiC power MOSFETs are mainly used in the fields of high voltage, high frequency, and large current, as shown in Figure 3, spike bars are generated during the high-frequency switching process due to parasitic parameters in the circuit. Figure 3 is a waveform diagram showing the voltage overshoot and oscillation phenomenon at the moment of MOSFET switching. Based on Figure 3, it can be seen that an instantaneous overvoltage occurs in the current path of the device, and the loss of the switching process increases, or a large surge voltage is generated due to changes such as power load. Therefore, the ability of the MOSFET to withstand the surge voltage and overvoltage protection are also very important.

[0034] Since conventional MOSFET devices themselves do not have the ability to self-suppress surge voltage and overvoltage protection, in actual applications, it is often necessary to design complex buffer circuits, surge voltage suppression circuits, and overvoltage protection circuits. However, such external matching suppression and overvoltage protection circuits often have time delays, and the high-frequency spike voltage surges during the actual switching process are still borne by the device itself, which gradually leads to breakdown failures in the channel area of the device and failures in the ohmic contact area between the gate structure and the electrode, which may cause reliability problems of the device.

[0035] 3) Since the depth of ion implantation is limited, it is technically difficult to realize many target trench gate protection structures and surge-resistant designs. Generally, the trench depth for forming a gate is 1 μm to 2 μm or more. Since it is necessary to protect the gate structure in the trench, the actual manufacturing process of the embedded protection structure cannot be directly completed by ion implantation. This is because in the silicon carbide process, the depth of ion implantation hardly exceeds 1 μm. Due to the characteristics of the silicon carbide material, in order to achieve doping at a deeper implantation depth, lattice damage occurs due to high-energy ion implantation. Therefore, when fabricating a silicon carbide MOSFET device with a deeper doping region, in the process of fabricating an epitaxial wafer, after forming the necessary doping region in the previously formed epitaxial layer by etching and ion implantation, it is necessary to form the next epitaxial layer. Therefore, in the conventional process, after forming the necessary doping region in the previously formed epitaxial layer by etching and ion implantation, it is common to form two P-type epitaxial layers with a specific structure, which complicates the manufacturing process and increases the manufacturing cost.

[0036] As shown in FIG. 4a, FIG. 4a is a schematic structural diagram of a silicon carbide MOSFET device provided according to an embodiment of the present application, including a semiconductor substrate 10 and an epitaxial wafer including an epitaxial layer provided on the surface of the substrate 10, and including a well region, a source region 15, and a trench gate provided in the epitaxial layer.

[0037] Here, the trench gate includes a trench 20 located in the surface of the epitaxial layer opposite to the substrate and a gate 18 located in the trench 20, and there is a gate derivative layer 181 between the gate 18 and the trench 20.

[0038] The source region 15 surrounds the trench 20 and is in contact with the side wall of the trench 20.

[0039] The well region includes a first-layer well region 141, a second-layer well region 142, and a third-layer well region 143 that are sequentially provided in a direction toward the source region 15 of the substrate 10. The bottom of the trench 20 is located between the first-layer well region 141 and the third-layer well region 143. The third-layer well region 143 surrounds the trench 20, contacts the sidewall of the trench 20, and there is a doping region 17 in the epitaxial layer under the trench 20. The first-layer well region 141 surrounds the doping region 17, contacts the doping region 17, and there is a partial epitaxial layer 100 between the first-layer well region 141 and the third-layer well region 143. The second-layer well region 142 is located on both sides of the partial epitaxial layer 100.

[0040] There is a metal drain 19 on the side of the substrate 10 opposite to the epitaxial layer. The source region 15 can include a first region 151 and a second region 152 having opposite doping types, and can be set such that the first region 151 is an n+-type doping region and the second region 152 is a p+-type doping region. The metal source 21 contacts both the first region 151 and the second region 152. There is an insulating layer 16 on the surface of the source region 15, and the insulating layer 16 exposes the metal source 21 and the gate 18. The gate 18 includes a filling conductor located in the trench 20 and a metal gate located on the surface of the filling conductor.

[0041] In the silicon carbide MOSFET device shown in FIG. 4a, the well region structure includes three layers: a first-layer well region 141, a second-layer well region 142, and a third-layer well region 143. The topmost third-layer well region 143 is located on both the left and right sides of the trench 20 and contacts the sidewall of the trench 20. The middle-layer second-layer well region 142 includes two parts located on both the left and right sides of the trench 20 and does not contact the sidewall of the trench 20. The bottommost first-layer well region 141 is located under the trench 20 and does not contact the trench 20.

[0042] The distance between the two left and right parts of the second-layer well region 142 and the vertical central axis of the cell structure is greater than the distance between the two left and right parts of the first-layer well region 141 and the vertical central axis of the cell structure. Specifically, the vertical central axis of the cell structure is the central axis of the trench 20. As shown by the dotted line in FIG. 4a, for the second-layer well region 142, the first-layer well region 141 is closer to the central axis. The first-layer well region 141 is closer to the trench sidewall than the second-layer well region 142, protects the trench corner at the bottom of the trench 20, forms a parasitic JFET, and can suppress high-frequency oscillation and surge. The second-layer well region 142 can enable the first-layer well region 141 to suppress surge by connecting the first-layer well region 141 as a source.

[0043] The doping region 17 can form a specific JFET structure on the current path between the source and the drain. Also, the conduction characteristics of the JFET structure can be optimized and adjusted by the pattern design, ion implantation concentration, and pattern profile of the doping region 17, thereby improving the performance of the MOSFET device.

[0044] The technical solution of this application cleverly designs the second epitaxial layer 12 and the doping region 17 penetrating the second epitaxial layer 12 in the epitaxial wafer, thereby solving the problems of shielding the gate oxide film structure of the SiC trench MOSFET and the deep implantation process of the silicon carbide material. At the same time, the doping region 17 can also introduce a JFET structure that can be modulated by ion implantation on the current path of the device, automatically adjust the on-resistance and self-locking protection effect of the device, and at the same time, maintain the device cell size small.

[0045] The silicon carbide MOSFET device shown in FIG. 4a has at least the following beneficial effects.

[0046] The silicon carbide MOSFET device can introduce a JFET structure into the current path of the cell structure, automatically adjust the on-resistance and self-locking protection effect of the device, and at the same time maintain a small device cell size. Also, the conduction characteristics of the JFET structure are optimized and adjusted by the pattern design, ion implantation concentration, and pattern profile of the doping region 17. The design and process are flexible and have good manufacturability.

[0047] Using an epitaxial wafer having an embedded layer (the second epitaxial layer 12) and a JFET structure modulated by the implantation of the doping region 17, the depletion regions on both sides can be automatically expanded under a large surge voltage to increase the on-resistance of the JFET structure, which is equivalent to a buffer circuit structure that uniquely suppresses surge spikes. At the same time, when the surge voltage is too large, the depletion regions on both sides continue to expand and overlap with each other, exerting a blocking effect, protecting the gate conductor layer on the inner trench surface, and playing a certain role in overvoltage protection of the spike voltage.

[0048] The introduction of the JFET structure increases the on-resistance to a certain extent, but there are switching buffer effects and surge voltage self-suppression effects.

[0049] The silicon carbide MOSFET device can enhance the device's self-suppression tolerance to surge voltage and overvoltage, and avoid device damage and reliability degradation caused by the actual time delay of the overvoltage protection circuit and overcurrent protection circuit.

[0050] At the same time, it buffers the spike jitter during the circuit switching process and reduces the switching loss. Since the buffer circuit and buffer circuit structure in the circuit design can be reduced and discrete components can be reduced, the cost can be reduced, the actual module volume can also be reduced, and the reliability is improved.

[0051] As shown in FIG. 4b, FIG. 4b is a schematic diagram of the main current path at the moment when the silicon carbide MOSFET device shown in FIG. 4a is turned on. There is a current path between the source and the drain. The central dotted curve shown in FIG. 4b represents the circuit path, and the current passes through the JFET structure formed based on the doping region 17. Due to the rapid change of the current, a high-frequency spike voltage is generated in the circuit. At the same time, due to the rapid change of the voltage on the current path, the depletion region of the JFET structure (the region between the two dotted curves on the left and right in FIG. 4b) rapidly expands or contracts in response to various voltage changes. At this time, the JFET structure becomes equivalent to a parallel structure of a variable resistor R and a junction capacitance C, as shown in FIG. 4c. FIG. 4c is a schematic diagram of the equivalent parasitic parameters of the silicon carbide MOSFET device shown in FIG. 4b.

[0052] Through specific circuit applications and electrical model simulations of the device, by selecting, optimizing, and adjusting the appropriate thickness d and doping concentration of the second epitaxial layer 12, as well as the pattern design, concentration, and pattern profile design of the ion implantation structure of the doping region 17, appropriate parasitic parameter values (the required variable resistor R and junction capacitance C) can be obtained. When actually used in circuit modules with different switching frequencies, voltage spikes can be effectively suppressed, and turn-on losses can be reduced.

[0053] In the silicon carbide MOSFET device shown in FIG. 4a, since it is necessary to further improve the breakdown voltage performance at the bottom of the trench gate, based on this, as shown in FIG. 5, FIG. 5 is a schematic structural diagram of another silicon carbide MOSFET device provided according to the embodiment of the present application. An epitaxial wafer including a semiconductor substrate 10 and an epitaxial layer provided on the surface of the substrate. It includes a well region, a source region 15, and a trench gate provided in the epitaxial layer.

[0054] Here, the trench gate includes a trench 20 located in the surface of the epitaxial layer opposite to the substrate 10, and a gate 18 located in the trench 20, and there is a gate derivative layer 181 between the gate 18 and the trench 20.

[0055] The source region 15 surrounds the trench 20 and is in contact with the side wall of the trench 20.

[0056] The well region includes a first-layer well region 141, a second-layer well region 142, and a third-layer well region 143 provided in order in the direction from the substrate 10 toward the source region 15. The bottom of the trench 20 is located between the first-layer well region 141 and the third-layer well region 143. The third-layer well region 143 surrounds the trench 20 and is in contact with the side wall 20 of the trench. There is a doping region 17 in the epitaxial layer under the trench 20. The first-layer well region 141 surrounds the doping region 17 and is in contact with the doping region 17. There is a partial epitaxial layer 100 between the first-layer well region 141 and the third-layer well region 143. The second-layer well region 142 is located on both sides of the partial epitaxial layer 100. There is a masking layer 31 for protecting the bottom of the trench gate in the partial epitaxial layer 100. The masking layer 31 is located under the trench 20 and has the same doping type as each layer of the well region. The doping types of each layer of the well region are the same.

[0057] Optionally, the well regions of each layer have the same doping type and the same concentration, that is, the doping types and doping concentrations of the first-layer well region 141, the second-layer well region 142, and the third-layer well region 143 are all the same. For example, they may all be p-doped. The masking layer 31 may have the same doping concentration as the well regions of each layer, may be p-doped, or may have a higher doping concentration than the doping concentrations of the well regions of each layer. For example, the masking layer 31 may be p+-doped. Obviously, in other embodiments, the doping concentrations of the first-layer well region 141, the second-layer well region 142, and the third-layer well region 143 may be different.

[0058] In the embodiment shown in FIG. 5, by providing the masking layer 31 under the trench 20, the bottom of the trench gate can be protected, and the breakdown voltage performance of the bottom of the trench gate can be improved.

[0059] Here, in the direction perpendicular to the substrate 10, the distance from the masking layer 31 to the bottom of the trench 20 is smaller than the distance to the first-layer well region 141 so that the bottom of the trench gate can be effectively protected. Optionally, the masking layer 31 is in contact with the bottom of the trench 20, that is, the distance from the masking layer 31 to the bottom of the trench 20 is 0.

[0060] In the embodiment shown in FIG. 5, the vertical projection of the doping region 17 on the substrate 10 is located within the vertical projection of the trench 20 on the substrate 10. The vertical projection of the trench 20 on the substrate 10 is located within the vertical projection of the partial epitaxial layer 100 on the substrate 10, and the two vertical projections have a non-zero interval, that is, the intervals between the two parts of the second-layer well region 142 and the sidewalls of the trench 20 in FIG. 5 are not zero.

[0061] As shown in FIG. 5, there is a connection region 32 in the partial epitaxial layer 100 that further connects the masking layer 31 and the first layer well region 141. The connection region 32 has the same doping type as the well regions of each layer. The connection region 32 connects the masking layer 31 and the first layer well region 141, and by skillfully wrapping the trench gate bottom in a "capsule" shape, better protection of the trench bottom is achieved.

[0062] By providing the connection region 32, the masking layer 31 can be connected to the third layer well region 143 through the connection region 32 and further connected to the source region 15, and can be grounded through the source 21. On the one hand, it avoids the accumulation effect caused by dynamic carrier capture during a long-term dynamic switching operation due to the floating potential of the masking layer 31, and can avoid the gradual loss of the protection of the trench gate bottom by the masking layer 31 due to the accumulation effect caused by dynamic carrier capture. On the other hand, it avoids the problem of an increase in the gate parasitic capacitance caused by the floating potential of the masking layer 31 and the problem of an increase in the switching loss caused by the parasitic capacitance.

[0063] The doping types of the well regions of each layer, the masking layer 31, and the connection region 32 are the same. To reduce the connection resistance between the masking layer 31 and the first layer well region 141, the doping concentration of the connection region 32 is higher than the doping concentration of the well regions of each layer. For example, it can be set that the well regions of each layer are p-doped and the connection region 32 is p+-doped.

[0064] As shown in FIGS. 6 to 9, FIG. 6 is a three-dimensional view of a silicon carbide MOSFET device provided according to an embodiment of the present application, FIG. 7 is a top view of a spacer well region, a trench, a doping region, and a connection region in the silicon carbide MOSFET device shown in FIG. 6, FIG. 8 is a first cross-sectional view of the silicon carbide MOSFET device shown in FIG. 6 in a direction perpendicular to the trench extension portion, and FIG. 9 is a second cross-sectional view of the silicon carbide MOSFET device shown in FIG. 6 in a direction perpendicular to the trench extension portion. Here, the cross-section of FIG. 8 passes through two opposing connection regions 32 on both sides of the doping region 17, and the cross-section of FIG. 9 passes through an interval region between two adjacent connection regions 32 in the first direction X.

[0065] As shown in FIG. 6, the first layer well region 141 includes a first portion of the first layer well region 141a and a second portion of the first layer well region 141b that are respectively located on both sides of the trench 20. The first portion of the first layer well region 141a is connected to the masking layer 31 through at least one of the connection regions 32, and / or the second portion of the first layer well region 141b is connected to the masking layer 31 through at least one of the connection regions 32.

[0066] In order to improve connection reliability and stability and reduce connection impedance, as shown in FIGS. 6 and 7, the first portion of the first layer well region 141a is connected to the masking layer 31 through a plurality of the connection regions 32 arranged in sequence in the first direction X, and / or the second portion of the first layer well region 141b is connected to the masking layer 31 through a plurality of the connection regions 32 arranged in sequence in the first direction X. Here, the first direction X is parallel to the substrate 10 and parallel to the extension direction of the trench 20.

[0067] For one of the trenches 20, it can be set such that there is at least one doping region 17 under the trench. When there are a plurality of doping regions 17 under the trench 20, the plurality of doping regions 17 are arranged in order in the first direction X. The number of doping regions 17 includes, but is not limited to, two as shown in FIG. 7, and can be set to any number as required. To ensure the protection effect of the trench gate bottom, the masking layer 31 is set as a monolithic structure located under the trench 20 and extending from one end of the trench 20 to the other end.

[0068] As shown in FIGS. 6 and 7, the second layer well region 142 includes a first part of the second layer well region and a second part of the second layer well region respectively located on both sides of the trench 20, and the first part of the second layer well region and the second part of the second layer well region are each an integrated structure.

[0069] As shown in FIGS. 10 and 11, FIG. 10 is a three-dimensional view of another silicon carbide MOSFET device provided according to an embodiment of the present application, and FIG. 11 is a top view of the spacer well region, trench, doping region, and connection region in the silicon carbide MOSFET device shown in FIG. 10. In this aspect, the second layer well region 142 includes a first part of the second layer well region 142a and a second part of the second layer well region 142b respectively located on both sides of the trench 20. The first part of the second layer well region 142a and the second part of the second layer well region 142b each include a plurality of sub-regions 33 arranged in order in the first direction X. In the first direction X, between two adjacent sub-regions 33, there is a current expansion region 34 having a doping type opposite to that of the sub-region 33. The partial epitaxial layer 100 includes the current expansion region 34.

[0070] Taking the first-layer well region 141 as an example of a P-type, when the inverse type of the first-layer well region 141 is an N-channel, the current spreads to the boundary of the second-layer well region 142, and the current expansion region 34 between two adjacent sub-regions 33 of the second-layer well region 142 can expand the current, further reduce the resistance, and reduce the loss.

[0071] In the above embodiment, for the same connection region 32, the connection region 32 extends at least into the first-layer well region 141 from the bottom of the trench 20. At this time, in the direction perpendicular to the substrate 10, the trench 20 completely blocks the connection region 32.

[0072] As shown in FIG. 12, FIG. 12 is a schematic structural diagram of still another silicon carbide MOSFET device provided according to an embodiment of the present application. Based on the above embodiment, in the aspect shown in FIG. 12, a part of the connection region 32 extends at least into the first-layer well region 141 from the bottom of the trench 20, and the other part extends at least into the first-layer well region 141 along the side wall of the trench 20 from the surface of the epitaxial layer. At this time, the trench 20 partially blocks the connection region 32. This aspect enables the masking layer 31 to be better connected by the source region 15 and can reduce the connection impedance.

[0073] In the embodiment of the present application, based on the trench 20, the connection region 32 is formed by ion implantation, and the ion implantation region is located in the trench 20 and is set not to overlap with the side wall of the trench 20. Then, the connection region 32 will be completely located under the trench 20. When the ion implantation region is close to one side of the trench 20 and has a predetermined incident angle with respect to the side wall of this side, a structure as shown in FIG. 12 can be formed.

[0074] In the embodiment of the present application, the lower end of the connection region 32 extends at least into the first-layer well region 141, but it may also penetrate the first-layer well region 141 downward.

[0075] Note that only one cell structure of the MOSFET device is shown in the drawings of the embodiments of the present application. In an actual product, the MOSFET device can have a plurality of cell structures. The number of cells and the layout method can be set as needed and are not particularly limited in the embodiments of the present application.

[0076] In the silicon carbide MOSFET device, since the thickness of the third epitaxial layer 13 does not exceed 1 μm, the ion implantation depths of the second well region 142 and the third well region 143 do not exceed 1 μm, and within the third epitaxial layer 13 of the silicon carbide material, the second well region 142 and the third well region 143 can be formed by ion implantation without causing lattice damage.

[0077] In the embodiment of the present application, since the distance between the bottom of the trench 20 and the first epitaxial layer 11 is less than 1 μm, when ion implantation based on the trench is performed to form the doping region 17, the ion implantation depth of the doping region 17 is less than 1 μm, and the doping region 17 can be formed by ion implantation within the second epitaxial layer 12 of the silicon carbide material without causing lattice damage. The distance between the doping region 17 and the bottom of the trench is not zero.

[0078] In the drawings of the above embodiment, in the direction in which the bottom of the trench 20 faces the opening, the width of the trench 20 satisfies a uniform condition, that is, the width of the trench is the same or substantially the same in this direction, that is, the trench 20 is a rectangular trench. A general second epitaxial layer 12 is an epitaxial layer with a uniform thickness. By setting the width of the trench to satisfy the uniform condition, it is easier to form a doping region 17 with a uniform width in the above direction.

[0079] In other embodiments, the width of the trench 20 may be set to gradually increase in the direction from the bottom of the trench toward the opening, that is, the trench may be set as a V-shaped trench or an inverted trapezoidal trench. In the case of a V-shaped trench, the doping region 17 has a V-shaped structure. In the case of an inverted trapezoidal trench, when the ion implantation window is larger than the trench bottom, the doping region has an inverted trapezoidal structure as shown in FIG. 11. When the ion implantation window is not larger than the trench bottom, the doping region has a rectangular structure.

[0080] In an embodiment of the present application, the width of the doping region 17 is not larger than the width of the trench so that ion implantation based on the trench can be performed to form the doping region 17 in order to reduce the depth of ion implantation.

[0081] The doping concentration of the doping region 17 is higher than the doping concentrations of the first epitaxial layer 11 and the third epitaxial layer 13. For example, the doping region 17 is n+-doped, and the first epitaxial layer 11 and the third epitaxial layer 13 are n--doped.

[0082] The substrate 10 is an n+-type substrate, the second epitaxial layer 12 is p--type doped, and the doping region 17 is n-type doped. In an embodiment of the present application, the relationship of the doping concentrations is n+ > n > n--, p+ > p > p--. n--, n, and n+ are isotype dopings and are all dopings of the first type. p--, p, and p+ are isotype dopings and are all dopings of the second type. The doping of the first type and the doping of the second type are opposite-type dopings.

[0083] The silicon carbide MOSFET device can be an NMOS or a PMO, and the doping type of each region can be set as needed to form an NMOS or a PMOS.

[0084] Based on the above embodiments, another embodiment of the present application also provides a manufacturing method for manufacturing the silicon carbide MOSFET device described in the above embodiments. As shown in FIGS. 13 to 19, FIGS. 13 to 19 are process flow diagrams of the manufacturing method of the silicon carbide MOSFET device provided by the embodiments of the present application. The manufacturing method includes the following steps.

[0085] Step S11: As shown in FIG. 13, provide an epitaxial wafer including a semiconductor substrate 10 and an epitaxial layer provided on the surface of the substrate.

[0086] Here, the epitaxial wafer is a silicon carbide epitaxial wafer, and the substrate 10 and each epitaxial layer on its surface are made of silicon carbide material.

[0087] Step S12: As shown in any of FIGS. 5 to 12, form a well region, a source region 15, and a trench gate in the epitaxial layer.

[0088] Here, the trench gate includes a trench 20 located in the surface of the epitaxial layer opposite to the substrate 10, and a gate located in the trench 20. There is a gate derivative layer 181 between the gate and the trench 20. The source region 15 surrounds the trench 20 and is in contact with the side wall of the trench 20. The well region includes a first-layer well region 141, a second-layer well region 142, and a third-layer well region 143 provided in order in a direction toward the source region 15 of the substrate 10. The bottom of the trench 20 is located between the first-layer well region 141 and the third-layer well region 143. The third-layer well region 143 surrounds the trench 20, contacts the side wall of the trench 20, and there is a doping region 17 in the epitaxial layer under the trench 20. The first-layer well region 141 surrounds the doping region 17 and contacts the doping region 17. There is a partial epitaxial layer 100 between the first-layer well region 141 and the third-layer well region 143. The second-layer well region 142 is located on both sides of the partial epitaxial layer 100. There is a masking layer 31 for protecting the trench gate bottom in the partial epitaxial layer 100. The masking layer 31 is located under the trench 20 and has the same doping type as each layer of the well region.

[0089] As shown in FIG. 13, the epitaxial layer includes a first epitaxial layer 11 provided on the surface of the substrate 10, a second epitaxial layer 12 provided on the surface of the first epitaxial layer 11 opposite to the substrate 10, and a third epitaxial layer 13 provided on the surface of the second epitaxial layer 12 opposite to the first epitaxial layer 11. The second epitaxial layer 12 includes an area 140 to be implanted and a first-layer well region 141 surrounding the area 140 to be implanted.

[0090] In the MOSFET device, the well region structure includes a first-layer well region 141, a second-layer well region 142, and a third-layer well region 143. The second epitaxial layer 12 includes an area to be implanted and a first-layer well region 141 surrounding the area to be implanted. The area 140 to be implanted is used to form the doping region 17.

[0091] In the manufacturing method described in the embodiments of the present application, the method for manufacturing the epitaxial wafer includes epitaxially forming the first epitaxial layer 11, the second epitaxial layer 12, and the third epitaxial layer 13 on the surface of the substrate 10 in this order. Here, the first epitaxial layer 11 has the same doping type as the third epitaxial layer 13 and is of the opposite type doping to the second epitaxial layer 12.

[0092] The substrate 10 can be set as an n+-type doped silicon carbide substrate, the first epitaxial layer 11 and the third epitaxial layer 13 are n−-type doped silicon carbide epitaxial layers, and the second epitaxial layer 12 is a p-type doped silicon carbide epitaxial layer. In this way, the p-type doped second epitaxial layer 12 is an embedded layer. By skillfully adopting the epitaxial wafer having this embedded layer, using the trench 20 required for the gate 18 and performing ion implantation to form the doping region 17, the shielding of the trench gate structure and the difficulty of the implantation process of the silicon carbide material are solved. Further, the doping region 17 can form a JFET structure that can be modulated in the device current path, automatically adjust the device resistance and the self-locking protection effect, and at the same time, the device cell size can be reduced.

[0093] In step S12 above, a well region, a source region 15, and a trench gate are formed in the epitaxial layer, including the following steps.

[0094] Step S121: As shown in FIGS. 14 to 16, a source region, a second layer well region, and a third layer well region are formed in the surface of the third epitaxial layer opposite to the substrate.

[0095] In this step, by ion implantation, a second-layer well region 142, a third-layer well region 143, and a source region 15 are sequentially formed in the third epitaxial layer 13. The second-layer well region 142 is located between the first-layer well region 141 and the third-layer well region 143, and the source region 15 is located on the side of the third-layer well region 143 opposite to the second-layer well region 142.

[0096] Specifically, as shown in FIG. 14, ion implantation is performed based on the mask layer 01 to form a second-layer well region 142 in the third epitaxial layer 13. The second-layer well region 142 incorporates a non-implanted region including the partial epitaxial layer 100. A necessary non-implanted region is formed based on the patterned mask layer 01. The vertical projections of the trench 20 and the doping region 17 are within this non-implanted region and have a spacing from this non-implanted region in a direction parallel to the epitaxial wafer (i.e., the horizontal direction in FIG. 14). Further, as shown in FIG. 15, again by ion implantation, a third-layer well region 143 is formed on the second-layer well region 142. The third-layer well region 143 covers the second-layer well region 142 and the non-implanted region surrounded by it. Further, as shown in FIG. 16, again by ion implantation, a source region 15 is formed on the third-layer well region 143.

[0097] Step S122: As shown in FIG. 17, a trench 20 is formed in the surface of the third epitaxial layer 13 opposite to the substrate 10. The bottom of the trench 20 is located between the second epitaxial layer 12 and the third-layer well region 143.

[0098] Here, the source region 15 and the third-layer well region 143 are in contact with the sidewalls of the trench 20. When forming the source region 15 by ion implantation, since the ion implantation region covers the region for forming the trench 20, after forming the trench, the remaining source region 15 that has not been removed can be brought into direct contact with the sidewalls of the trench 20. Similarly, when forming the third-layer well region 143 by ion implantation, since the ion implantation region covers the region for forming the trench 20, after forming the trench, the remaining third-layer well region 143 that has not been removed can be brought into direct contact with the sidewalls of the trench 20.

[0099] The second-layer well region 142 is spaced from the sidewalls of the trench 20. When the size of the non-implanted region surrounded by the second-layer well region 142 is larger than the size of the trench 20 and the vertical projection of the trench 20 is set to be located within the non-implanted region and spaced from the non-implanted region, the second-layer well region 142 can be prevented from contacting the sidewalls of the trench 20, and a gap can be provided between them.

[0100] Step S123: As shown in FIG. 18, form the masking layer 31 and the doping region 17 based on the trench.

[0101] The doping region 17 and the first epitaxial layer 11 have the same doping type as the third epitaxial layer 13.

[0102] By forming the masking layer 31 and the doping region 17 by ion implantation based on the trench 20, the masking layer 31 and the doping region 17 that meet the quality requirements can be formed within a large depth of the epitaxial layer. The first-layer well region 141 is an epitaxial layer, and the required first-layer well region 141 can be formed within a large depth of the epitaxial layer without ion implantation. The doping region 17 penetrates the second epitaxial layer 12.

[0103] Step S124: As shown in FIG. 19, based on the trench 20, a connection region 32 that connects the masking layer 31 and the first layer well region 141 is formed.

[0104] The connection region 32 can be formed by ion implantation. Based on the trench, by forming the connection region 32 by ion implantation, a connection region 32 that satisfies the quality requirements is formed within a large depth of the epitaxial layer.

[0105] Step S125: To form the silicon carbide MOSFET device described in the above embodiment, a gate derivative layer 181 and a gate 18 are formed in the trench 20.

[0106] The gate 18 includes a filling conductor that fills the trench 20 and a metal gate located on the surface of the filling conductor. There is a gate derivative layer 181 on the surface of the trench 20. After forming the gate derivative layer 181, the gate 18 is formed in the trench 20. The filling conductor 181 may be polycrystalline silicon or the like. Before forming the gate derivative layer 181 in the trench 20, a doping region 17 is formed.

[0107] In an embodiment of the present application, the manufacturing method further includes forming a metal source 21 connected to the source region 15 and forming a metal drain 19 on the surface of the substrate 10 opposite to the first epitaxial layer 11. The source region 15 includes a first region 151 and a second region 152 with opposite doping types, and the metal source 21 is in contact with both the first region 151 and the second region 152. The first region 151 can be set to be n+ doped and the second region 152 can be set to be p+ doped.

[0108] As shown in FIG. 20, FIG. 20 is a layout of the trench design and ion implantation area of the doping region of the silicon carbide MOSFET device provided by the embodiment of the present application. The implantation window of the doping region 17 is located within the trench 20, and the channel characteristics of the JFET structure can be adjusted by the pattern design, ion implantation concentration, and pattern profile design of the doping region 17. The implantation window area of the doping region 17 may be equal to or less than the area of the trench 20.

[0109] In the embodiment of the present application, only the silicon carbide MOSFET device is described in a single cell structure. Obviously, when manufacturing the MOSFET device, a plurality of cell structures can be manufactured simultaneously based on the wafer-level process, and then the wafer can be divided to form the silicon carbide MOSFET device, and the silicon carbide MOSFET device has a plurality of cell structures.

[0110] Each embodiment in this specification is described by progression, or parallel, or a combination of progression and parallel. However, each embodiment example focuses on the differences from other embodiments, and the same or similar parts of each embodiment may refer to each other.

[0111] It should be noted that in the description of the present application, the directions and positional relationships indicated by terms such as "upper", "lower", "top", "bottom", "inner", "outer", etc. are based on the directions and positional relationships shown in the drawings, and are only for the convenience of description and simplification of the present application, and do not indicate or imply that the devices or elements mentioned need to have a specific direction and be constructed and operated in a specific direction. Therefore, it should be understood that it cannot be construed as a limitation to the present application. When one component is considered to be "connected" to another component, it may be directly connected to the other component, or there may be components set in the middle that may exist simultaneously.

[0112] Also, in this specification, relational terms such as first and second are used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply the existence of such an actual relationship or order between these entities or operations. Further, the term "comprising", "including" or any other variation thereof is intended to cover non-exclusive inclusion, so that an article or device comprising a series of elements includes not only those elements but also other elements not expressly listed or elements inherent to such an article or device. Without further limitation, an element defined by the description "comprising..." does not exclude the existence of other identical elements in the article or device comprising the above element. From the above description of the disclosed embodiments, those skilled in the art can implement or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention is not limited to these embodiments shown herein, but rather conforms to the broadest scope consistent with the principles and novel features disclosed herein.

Claims

1. An epitaxial wafer including a semiconductor substrate and an epitaxial layer provided on the surface of the substrate, and a well region, a source region, and a trench gate provided in the epitaxial layer, in a silicon carbide MOSFET device, characterized in that the trench gate includes a trench located in the surface of the epitaxial layer opposite to the substrate and a gate located in the trench, and there is a gate derivative layer between the gate and the trench, the source region surrounds the trench and is in contact with the side wall of the trench, the well region includes a first layer well region, a second layer well region, and a third layer well region provided in this order in the direction from the substrate toward the source region, the bottom of the trench is located between the first layer well region and the third layer well region, the third layer well region surrounds the trench and is in contact with the side wall of the trench, there is a doping region in the epitaxial layer under the trench, the first layer well region surrounds the doping region and is in contact with the doping region, there is a partial epitaxial layer between the first layer well region and the third layer well region, the second layer well region is located on both sides of the partial epitaxial layer, there is a masking layer for protecting the bottom of the trench gate in the partial epitaxial layer, the masking layer is located under the trench, and has the same doping type as each layer of the well region, a silicon carbide MOSFET device in which the dopant in the doping region has the same polarity as the dopant in the first layer well region and has a higher concentration than the dopant in the first layer well region.

2. The vertical projection of the doping region on the substrate is located within the vertical projection of the trench on the substrate, The vertical projection of the trench on the substrate is located within the vertical projection of the partial epitaxial layer on the substrate, and the two vertical projections have a non-zero interval, the silicon carbide MOSFET device according to claim 1.

3. There is a connection region connecting the masking layer and the first layer well region in the partial epitaxial layer, and the connection region has the same doping type as each layer of the well region, the silicon carbide MOSFET device according to claim 1.

4. The first-layer well region includes a first-part first-layer well region and a second-part first-layer well region, which are respectively located on both sides of the trench. The first-part first-layer well region is connected to the masking layer through a plurality of the connection regions arranged in sequence in a first direction, and / or the second-part first-layer well region is connected to the masking layer through a plurality of the connection regions arranged in sequence in the first direction. The silicon carbide MOSFET device according to claim 3, wherein the first direction is parallel to the substrate and parallel to the extending direction of the trench.

5. There is at least one of the doping regions under the trench. When there are a plurality of the doping regions, the plurality of the doping regions are arranged in sequence in a first direction, where the first direction is parallel to the substrate and parallel to the extending direction of the trench. The silicon carbide MOSFET device according to claim 1 is characterized in that.

6. The silicon carbide MOSFET device according to claim 1, wherein in a direction perpendicular to the substrate, the distance from the masking layer to the bottom of the trench is smaller than the distance to the first-layer well region.

7. The silicon carbide MOSFET device according to claim 6, wherein the masking layer is in contact with the bottom of the trench.

8. The second-layer well region includes a first-part second-layer well region and a second-part second-layer well region, which are respectively located on both sides of the trench. The silicon carbide MOSFET device according to claim 1, wherein the first-part second-layer well region and the second-part second-layer well region are both of an integrated structure.

9. The second-layer well region includes a first-part second-layer well region and a second-part second-layer well region, which are respectively located on both sides of the trench. The silicon carbide MOSFET device according to claim 1, wherein the first-part second-layer well region and the second-part second-layer well region both include a plurality of sub-regions arranged in sequence in a first direction. In the first direction, between two adjacent sub-regions, there is a current expansion region having a doping type opposite to that of the sub-region. Here, the first direction is parallel to the substrate and parallel to the extending direction of the trench.

10. The doping type of the well regions of each layer, the masking layer, and the connection region is the same, and the doping concentration of the connection region is higher than the doping concentration of the well regions of each layer. The silicon carbide MOSFET device according to claim 3.

11. The same connection region is characterized in that the connection region extends at least into the first layer well region from the bottom of the trench, or a part of the connection region extends at least into the first layer well region from the bottom of the trench, and the other part extends at least into the first layer well region along the side wall of the trench from the surface of the epitaxial layer. The silicon carbide MOSFET device according to claim 3.

12. Providing an epitaxial wafer including a semiconductor substrate and an epitaxial layer provided on the surface of the substrate, Forming a well region, a source region, and a trench gate in the epitaxial layer. In the manufacturing method of the silicon carbide MOSFET device according to any one of claims 1 to 11, The trench gate includes a trench located in the surface of the epitaxial layer opposite to the substrate and a gate located in the trench, and there is a gate derivative layer between the gate and the trench. The source region surrounds the trench and is in contact with the side wall of the trench. The well region includes a first layer well region, a second layer well region, and a third layer well region provided in order in the direction from the substrate toward the source region. The bottom of the trench is located between the first layer well region and the third layer well region. The third layer well region surrounds the trench and is in contact with the side wall of the trench. There is a doping region in the epitaxial layer under the trench. The first layer well region surrounds the doping region and is in contact with the doping region. There is a partial epitaxial layer between the first layer well region and the third layer well region. The second layer well region is located on both sides of the partial epitaxial layer. There is a masking layer for protecting the bottom of the trench gate in the partial epitaxial layer. The masking layer is located under the trench and has the same doping type as the well regions of each layer. A manufacturing method in which the dopant in the doping region has the same polarity as the dopant in the first layer well region and has a higher concentration than the dopant in the first layer well region.

13. The epitaxial layer includes a first epitaxial layer provided on the surface of the substrate, a second epitaxial layer provided on the surface of the first epitaxial layer opposite to the substrate, and a third epitaxial layer provided on the surface of the second epitaxial layer opposite to the first epitaxial layer. The second epitaxial layer has a region to be implanted and a first layer well region surrounding the region to be implanted. Forming a well region, a source region, and a trench gate in the epitaxial layer. Forming the source region, the second layer well region, and the third layer well region in the surface of the third epitaxial layer opposite to the substrate. Forming the trench in the surface of the third epitaxial layer opposite to the substrate. Forming the masking layer and the doping region based on the trench. Forming a connection region connecting the masking layer and the first layer well region based on the trench. The manufacturing method according to claim 12, characterized by including forming a gate derivative layer and a gate in the trench.

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