Variable capacitance element and method for manufacturing the same

Abstract

To provide a variable capacitance element with a high linearity in a capacity variable ratio with respect to magnitude of the capacity variable ratio and applied voltage.SOLUTION: A variable capacitance element 100 includes: a semiconductor substrate 20; and a cap layer 10 provided on a main surface of the semiconductor substrate 20. The semiconductor substrate 20 includes: a first semiconductor layer 22 of a first conductivity type; and a second semiconductor layer 23 of the first conductivity type located between the first semiconductor layer 22 and the cap layer 10. The cap layer 10 includes: a conductor layer 12; and an insulator layer 11 located between the conductor layer 12 and the second semiconductor layer 23. The second semiconductor layer 23 has an impurity concentration which decreases as being separated from the insulator layer 11 in a lamination direction.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a variable capacitance element and a method for manufacturing the same.

Background Art

[0002] Variable capacitance elements are used in voltage controlled oscillators (VCOs) such as high-frequency filters, TV tuners, and voltage controlled crystal oscillators (VCXOs) using crystal oscillators as resonators.

[0003] As variable capacitance elements, for example, variable capacitance diodes using pn junctions as described in Patent Documents 1 and 2 are known. The variable capacitance element disclosed in Patent Document 1 has a structure in which an annular contact layer of a second conductivity type is formed around a diffusion layer of a first conductivity type as a unit, and the units are arranged in an array.

[0004] The variable capacitance element disclosed in Patent Document 2 includes a first conductivity type impurity diffusion region formed on the surface of a semiconductor substrate, a second conductivity type impurity diffusion region formed on the surface of the semiconductor substrate so as to overlap the first conductivity type impurity diffusion region, a first electrode made of aluminum silicon having a silicon content of 3 wt% or more and 10 wt% or less formed on the surface of the second conductivity type impurity diffusion region, and a second electrode formed on the back surface of the semiconductor substrate.

[0005] In addition, Patent Document 3 discloses a method for manufacturing a variable capacitance element including a step of forming a groove in a variable capacitance element formation region on a semiconductor substrate of a first conductivity type having a low impurity concentration, a step of forming a semiconductor region of the first conductivity type having a medium impurity concentration on the inner wall of the groove, a step of embedding a semiconductor material of the second conductivity type having a high impurity concentration in the groove, and a heat treatment step of activating the semiconductor region of the first conductivity type having a medium impurity concentration in the semiconductor substrate.

Prior Art Documents

Patent Documents

[0006] Patent Document 1 Japanese Patent Application Laid-Open No. 2005-183813 Patent Document 2 Japanese Patent Application Laid-Open No. 2002-343980 Patent Document 3 Japanese Patent Application Laid-Open No. 2005-294714 Summary of the Invention Problems to be Solved by the Invention

[0007] The variable capacitance elements as described in Patent Documents 1 to 3 are located on the surface side of the semiconductor substrate, and in the stacking direction, there are a first region where the impurity concentration increases as it moves away from the surface of the semiconductor substrate, and a second region that is located below the first region so as to be adjacent to the first region and where the impurity concentration of the semiconductor substrate decreases. In a variable capacitance element having such an impurity concentration profile, when ion implantation is performed along the crystal axis of the semiconductor substrate, ions are implanted deep into the semiconductor crystal due to channeling, so that the impurity concentration gradually decreases in the depth direction, resulting in a so-called "flared" profile, and it is difficult to obtain a stepped junction profile with a steep concentration gradient of the impurity concentration. Therefore, it has been difficult to obtain a variable capacitance element with a high capacitance variable ratio and high linearity of the capacitance variable ratio with respect to the magnitude of the applied voltage.

[0008] The present invention has been made in view of the above circumstances, and an object thereof is to provide a variable capacitance element having a high capacitance variable ratio and high linearity of the capacitance variable ratio with respect to the magnitude of the applied voltage. Means for Solving the Problems

[0009] (1) The variable capacitance element according to the first aspect of the present invention includes a semiconductor substrate and a cap layer provided on the main surface of the semiconductor substrate. The semiconductor substrate has a first semiconductor layer of a first conductivity type and a second semiconductor layer of the first conductivity type disposed between the first semiconductor layer and the cap layer. The cap layer has a conductor layer and an insulator layer positioned between the conductor layer and the second semiconductor layer. The impurity concentration of the second semiconductor layer decreases as it moves away from the insulator layer in the stacking direction.

[0010] (2) In the variable capacitance element according to the above aspect, the impurity concentration of the second semiconductor layer may have a concentration gradient of -5 {log 10 (pieces·cm -3 ) / μm} or less.

[0011] (3) In the variable capacitance element according to the above aspect, the semiconductor substrate may have a minimum value of impurity concentration at the interface between the first semiconductor layer and the second semiconductor layer in the stacking direction.

[0012] (4) In the variable capacitance element according to the above aspect, the thickness of the cap layer may be 50 nm or more.

[0013] (5) In the variable capacitance element according to the above aspect, the semiconductor substrate may be made of silicon containing an impurity element, the insulator layer may be made of silicon dioxide, and the conductor layer may be made of polycrystalline silicon.

[0014] (6) The method for manufacturing a variable capacitance element according to the second aspect of the present invention includes a first step of forming an insulator layer on the main surface of a semiconductor substrate having a semiconductor region of a first conductivity type, a second step of forming a conductor layer on the main surface of the insulator layer and providing a cap layer having the insulator layer and the conductor layer on the main surface of the semiconductor substrate, and a third step of performing ion implantation on the semiconductor substrate from the conductor layer side of the cap layer through the conductor layer and the insulator layer, and forming a second semiconductor layer of the first conductivity type in which the impurity concentration decreases as it moves away from the insulator layer in the stacking direction in the region of the semiconductor region that contacts the insulator layer, and forming a first semiconductor layer of the first conductivity type in the remaining semiconductor region.

[0015] (7) In the manufacturing method of the variable capacitance element according to the above aspect, in the first step and the second step, the insulating layer and the conductor layer may be formed such that the thickness of the cap layer becomes 50 nm or more.

[0016] (8) In the manufacturing method of the variable capacitance element according to the above aspect, in the first step and the second step, a cap layer composed of the insulating layer and the conductor layer may be formed at a position overlapping with the region where the second semiconductor layer is planned to be formed.

[0017] (9) In the manufacturing method of the variable capacitance element according to the above aspect, in the third step, ion implantation may be performed on the semiconductor substrate to form the second semiconductor layer having the same shape as the conductor layer when viewed in a plan view from the stacking direction.

Advantages of the Invention

[0018] According to the present invention, it is possible to provide a variable capacitance element having a high linearity of the capacitance variable ratio with respect to the variable ratio and the magnitude of the applied voltage.

Brief Description of the Drawings

[0019]

Figure 1

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Figure 9

Embodiments for Carrying Out the Invention

[0020] Hereinafter, an example of an embodiment of the present invention will be described in detail with reference to the drawings. Note that the drawings used in the following description may show the characteristic parts enlarged for the sake of clarity of the features of the present invention. For this reason, the dimensional ratios of the respective components may be different from the actual ones.

[0021] [Variable Capacitance Element] <First Embodiment> FIG. 1 is a diagram schematically showing a cross-sectional structure of a MOS type variable capacitance element 100 according to the present embodiment. As shown in FIG. 1, the variable capacitance element 100 includes a semiconductor substrate 20 and a cap layer 10 provided on the main surface S of the semiconductor substrate. The semiconductor substrate 20 has a first semiconductor layer 22 of a first conductivity type and a second semiconductor layer 23 of the first conductivity type disposed between the first semiconductor layer 22 and the cap layer 10. The cap layer 10 has a conductor layer 12 and an insulator layer 11 located between the conductor layer 12 and the second semiconductor layer 23. The impurity concentration of the second semiconductor layer 23 decreases as it moves away from the insulator layer 11 in the stacking direction. Hereinafter, the case where the first conductivity type is p-type and the second conductivity type is n-type will be described as an example.

[0022] The semiconductor substrate 20 of the variable capacitance element 100 is made of, for example, silicon containing an impurity element. The semiconductor substrate 20 has a first semiconductor layer (well) 22 overlapping the base substrate 21, a second semiconductor layer 23, a low concentration layer 24 provided above the base substrate 21 and outside the second semiconductor layer in the in-plane direction, diffusion layers 25a and 25b provided outside the low concentration layer 24 in the in-plane direction, and an epitaxial region 26 provided above the base substrate 21 and outside the diffusion layer 25b in the in-plane direction.

[0023] The low-concentration layers 24a and 24b and the epitaxial region 26 are not limited to the configuration of being directly in contact with the base substrate 21, and include configurations in which they are separated from the base substrate 21, for example, configurations provided via one or more other layers on the base substrate 21. Note that the upward direction does not necessarily coincide with the direction along the gravitational direction. In FIG. 1, the region surrounded by the dashed-dotted line is referred to as a stacked structure 50.

[0024] The base substrate 21 is, for example, a p-type semiconductor substrate containing low-concentration impurity elements. The low-concentration layer 24 is, for example, a p-type region having an impurity concentration lower than the impurity concentration at the interface between the first semiconductor layer 22 and the second semiconductor layer 23. The low-concentration layer 24 is formed, for example, along the main surface S of the semiconductor substrate 20. The main surface S of the semiconductor substrate 20 20 and the end face S in the stacking direction of the low-concentration layer 24 24 The distance therebetween is, for example, the main surface S of the semiconductor substrate 20 20 and the end face S in the stacking direction of the second semiconductor layer 23 23 and is greater than or equal to that distance. By having the variable capacitance element 100 include the low-concentration layer 24, the circuit structure from the gate terminal a to the terminal wiring b can be controlled to partially include the component in the stacking direction of the semiconductor substrate 20.

[0025] The diffusion layers 25a and 25b contain, for example, p-type impurity elements. The diffusion layers 25a and 25b each have, for example, a first diffusion layer 25aa and 25ba containing impurity elements with a higher concentration than the first semiconductor layer 22, and a second diffusion layer 25ab and 25bb containing impurity elements with a higher concentration than the first diffusion layer 25aa and 25ba. The main surface S of the semiconductor substrate 20 20 and the end face S in the stacking direction of the second diffusion layers 25ab and 25bb 25b The distance therebetween is, for example, the main surface S of the semiconductor substrate 20 20 and the end face S in the stacking direction of the low-concentration layer 24 24 and is greater than that distance. The main surface S of the semiconductor substrate 20 20 and the end face S in the stacking direction of the first diffusion layers 25aa and 25ba 25a The distance therebetween is, for example, the main surface S of the semiconductor substrate 20 20 and the end face S in the stacking direction of the second diffusion layers 25ab and 25bb 25b and is greater than that distance.

[0026] Conductor wirings such as polysilicon wiring and aluminum wiring are connected to the diffusion layers 25a and 25b (terminal wiring b in the figure).

[0027] The epitaxial region 26 is, for example, an n-type epitaxial region (or well region) containing a low-concentration impurity element. Elements such as a p-type diffusion resistor and a PMOS transistor are formed in the epitaxial region 26. On the insulating layer 11 and at a position aligned with the conductor layer 12, a sidewall spacer 13 mainly containing silicon dioxide, for example, is provided.

[0028] <Stacked structure> FIG. 2 is an enlarged cross-sectional view of the stacked structure 50 in the variable capacitance element 100 of FIG. 1. The stacked structure 50 includes, for example, a semiconductor substrate 20 in which a base substrate 21, a first semiconductor layer 22, and a second semiconductor layer 23 are stacked in this order, and a cap layer 10 in which an insulating layer 11 and a conductor layer 12 are stacked in this order on the semiconductor substrate 20.

[0029] The semiconductor substrate 20 is made of, for example, silicon containing an impurity element. The insulating layer 11 and the conductor layer 12 are each made of, for example, an oxide or a polycrystalline semiconductor. As a specific example, the insulating layer 11 is made of silicon dioxide, and the conductor layer 12 is made of polycrystalline silicon. Thus, the stacked structure 50 has a MOS structure.

[0030] The base substrate 21, the first semiconductor layer 22, and the second semiconductor layer 23 are, for example, semiconductor regions containing a p-type impurity element. For example, the first semiconductor layer 22 is a p - layer, the second semiconductor layer 23 is a p layer, and the impurity concentration of the second semiconductor layer 23 is higher than that of the first semiconductor layer 22, for example.

[0031] The impurity concentration of the second semiconductor layer 23 decreases as it moves away from the insulating layer 11 in the stacking direction, as shown by the dot density in FIG. 2. The impurity concentration of the second semiconductor layer 23 is, for example, 1.0×1017 ~5.0×10 18 (pcs / cm 3 ), which is 4.0 × 10 17 ~2.0×10 18 (pcs / cm 3 The impurity concentration of the second semiconductor layer 23 is preferably, for example, −5{log 10 (pieces cm -3 ) / μm} or less, for example, -10{log 10 (pieces cm -3 The concentration gradient of the impurity concentration of the second semiconductor layer 23 is equal to or greater than the principal surface S of the semiconductor substrate 20 and the end surface S in the stacking direction of the second semiconductor layer 23. 23 The concentration gradient of the impurity concentration in the second semiconductor layer 23 can be obtained by dividing the difference in the impurity concentration in the second semiconductor layer 23 by the difference in the depth of the second semiconductor layer 23. That is, the concentration gradient of the impurity concentration in the second semiconductor layer 23 can be obtained by dividing the difference in the impurity concentration in the second semiconductor layer 23 by the difference in the depth of the second semiconductor layer 23. 10 (Lamination direction end surface S of the second semiconductor layer 23 23 (Impurity concentration at 10 (impurity concentration in the main surface S of the semiconductor substrate 20) / (difference in depth of the second semiconductor layer 23)) can be calculated.

[0032] End surface S of the second semiconductor layer 23 in the stacking direction 23 The position of the end surface S in the stacking direction can be determined based on, for example, the impurity concentration profile of the semiconductor substrate 20. Specifically, as described above, the impurity concentration of the second semiconductor layer 23 decreases with increasing distance from the main surface S of the semiconductor substrate 20, and as described later, the impurity concentration of the region of the first semiconductor layer 22 that contacts the second semiconductor layer 23 increases with increasing distance from the main surface S of the semiconductor substrate 20. 23 The impurity concentration at the interface between the first semiconductor layer 22 and the second semiconductor layer 23 is the minimum value of the impurity concentration profile in the stacking direction. Thus, the semiconductor substrate 20 has a minimum value of the impurity concentration at, for example, the interface in the stacking direction. Therefore, in the stacking direction, the minimum value of the impurity concentration closest to the main surface S of the semiconductor substrate is the end surface S in the stacking direction of the second semiconductor layer 23. 23 and can be defined as the interface between the second semiconductor layer 23 and the first semiconductor layer 22 in the stacking direction.

[0033] The first semiconductor layer 22, as shown by dot density in FIG. 2, for example, has a laminated-direction end face S of the second semiconductor layer 23 23 in contact therewith, and has a region R22a where the impurity concentration increases as it separates in the laminated direction from the laminated-direction end face S 23 and a region R22b that is in contact with the region R22a and where the impurity concentration increases as it separates from the laminated-direction end face. That is, the impurity concentration of the first semiconductor layer 22 is maximum at an interface 22i between these two regions R22a and R22b. It is preferable that the maximum value of the impurity concentration of the first semiconductor layer 22 is smaller than the maximum value of the impurity concentration of the second semiconductor layer 23. Also, it is preferable that the average impurity concentration in the first semiconductor layer 22 is lower than the average impurity concentration in the second semiconductor layer 23.

[0034] The cap layer 10 is composed of, for example, an insulating layer 11 laminated on the second semiconductor layer 23 and a conductor layer 12 laminated on the insulating layer 11.

[0035] The cap layer 10 is composed of, for example, an insulating layer 11 laminated on the second semiconductor layer 23 and a conductor layer 12 laminated on the insulating layer 11.

[0036] The insulating layer 11 is made of an insulator such as silicon dioxide. The insulating layer 11 is larger than the second semiconductor layer 23 in a direction intersecting the laminated direction (in-plane direction of the substrate). The insulating layer 11 overlaps, for example, when viewed in plan from the laminated direction, with the second semiconductor layer 23 and a low-concentration layer 24 arranged side by side with the second semiconductor layer 23.

[0037] The conductor layer 12 is made of a material having conductivity such as polysilicon. The conductor layer 12 overlaps with the second semiconductor layer 23 when viewed in plan from the laminated direction and, for example, has the same shape. The conductor layer 12 contains, for example, an n-type impurity element.

[0038] The thickness d of the cap layer 10 10 is, for example, 50 nm or more. The thickness of the cap layer 10 is, for example, 400 nm or less, and preferably 100 nm to 300 nm.

[0039] The thickness d of the cap layer 10 10 defines the impurity concentration distribution and thickness of the second semiconductor layer 23 together with the magnitude of the acceleration energy during ion implantation. The thickness d of the cap layer 10 10 being 50 nm or more makes it easy to obtain an effect of blocking a part of the impurity elements in the step (third step) of performing ion implantation on the semiconductor substrate and forming the second semiconductor layer 23 in the manufacturing process described later, and the impurity concentration of the second semiconductor layer 23 can have a profile that decreases as it moves away from the insulating layer 11 in the stacking direction. Also, when the thickness d of the cap layer 10 10 is large, it is necessary to increase the acceleration energy of ion implantation to form the second semiconductor layer 23. The thickness d of the cap layer 10 10 being 400 nm or less can easily suppress excessive channeling in the cap layer 10, increase the impurity concentration of the second semiconductor layer 23, and form a second semiconductor layer 23 with a thickness on the order of submicrons that is controlled to have a configuration that decreases as it moves away from the insulating layer 11.

[0040] The thickness d of the insulating layer 11 11 is, for example, 3 nm to 14 nm, and preferably 5 nm to 8 nm. Also, the thickness d of the conductor layer 12 12 is, for example, 50 nm to 400 nm, and preferably 100 nm to 300 nm.

[0041] In the variable capacitance element 100, the capacitance between the semiconductor substrate 20 and the conductor layer 12 can be changed by changing the potential difference between the gate terminal a and the terminal wiring b. Specifically, when a positive potential is applied to the potential of the gate terminal a to increase the potential difference between the gate terminal a and the terminal wiring b, a depletion layer is formed near the surface of the semiconductor substrate 20. When the potential of the gate terminal a is increased, the depletion layer expands in the stacking direction, and the capacitance between the semiconductor substrate 20 and the conductor layer 12 decreases.

[0042] Also, in the variable capacitance element 100, when a negative potential is applied to the gate terminal a to sufficiently increase the potential difference between the gate terminal a and the terminal wiring b, holes gather near the surface of the semiconductor substrate 20, and the variable capacitance element enters an accumulation state. As a result, the capacitance of the variable capacitance element 100 becomes substantially the same as the capacitance of the insulating layer 11 and takes the maximum value.

[0043] Therefore, if the impurity concentration of the second semiconductor layer 23 decreases as it moves away from the insulating layer 11 in the stacking direction, a uniform correlation such that the impurity concentration decreases as the depth direction distance increases in the second semiconductor layer 23 is obtained, and a step junction profile or a profile close to this can be obtained. For this reason, the capacitance variable ratio of the variable capacitance element 100 is high, and the linearity of the profile of the change in the capacitance variable ratio with respect to the change in the magnitude of the voltage applied to the conductor layer 12 is high. Also, when the concentration gradient of the impurity concentration of the second semiconductor layer 23 is -5{log 10 (pieces·cm -3 ) / μm} or less, a profile close to an ideal step junction can be obtained, and the linearity of the profile of the change in the capacitance variable ratio with respect to the change in the magnitude of the applied voltage can be made higher.

[0044] In addition, in the above embodiment, an example in which the semiconductor substrate 20 is made of silicon containing an impurity element is shown, but the semiconductor substrate 20 is not limited to the example made of silicon containing an impurity element, and may be made of germanium, selenium, etc. containing an impurity element.

[0045] In the above embodiment, the first semiconductor layer 22 is disclosed as having a region R22a in which the impurity concentration increases as it moves away from the stacking direction end face S 23 and a region R22b in which the impurity concentration decreases as it moves away from the stacking direction end face S 23 . However, not limited to this example, the first semiconductor layer 22 may be the stacking direction end face S 23The impurity concentration may monotonically decrease as the distance from increases, or the impurity concentration may monotonically decrease. In such a case, by comparing the graph of the impurity concentration profile in the stacking direction before forming the second semiconductor layer with the graph of the impurity concentration profile in the stacking direction after forming the second semiconductor layer, the interface between the first semiconductor layer 22 and the second semiconductor layer 23 can be defined.

[0046] Also, in the above embodiment, a variable capacitance element in which the first conductivity type is p-type and the second conductivity type is n-type has been described. However, the present invention is not limited to this, and the first conductivity type may be n-type and the second conductivity type may be p-type. For example, in the above embodiment, an example in which the first semiconductor layer 22 is a p - layer and the second semiconductor layer 23 is a p layer has been shown. However, the first semiconductor layer 22 may be an n - layer and the second semiconductor layer may be an n layer. Here, the p - layer and the n - layer each indicate that the average impurity concentration is lower than that of the p layer and the n layer. In such a configuration, when the potential of the gate terminal a is lowered, the depletion layer expands and the capacitance between the semiconductor substrate 20 and the conductor layer 12 decreases.

[0047] [Manufacturing Method of Variable Capacitance Element] Next, an example of the manufacturing method of the variable capacitance element according to the present embodiment will be described. Hereinafter, the process of forming the stacked structure 50 of the variable capacitance element 100 will be mainly described. In the present embodiment, reference is made to the manufacturing process of the variable capacitance element according to the present embodiment shown in FIGS. 3 to 7.

[0048] The manufacturing method of the variable capacitance element according to the present embodiment includes a first step of forming an insulating layer 11 on the main surface S of a semiconductor substrate 20 having a semiconductor region of a first conductivity type, and the main surface S of the insulating layer 11 11A second step of forming a conductor layer 12 and providing a cap layer 10 having an insulator layer 11 and the conductor layer on a main surface S of a semiconductor substrate 20; and ion implantation into the semiconductor substrate 20 from the conductor layer 12 side of the cap layer 10 through the conductor layer 12 and the insulator layer 11, and forming a second semiconductor layer 23 of a first conductivity type in which the impurity concentration decreases as it moves away from the insulator layer 11 in the stacking direction in a region of the semiconductor region that contacts the insulator layer 11, and forming a first semiconductor layer 22 of the first conductivity type in the remaining semiconductor region.

[0049] (Preparation step) When manufacturing the variable capacitance element 100 using a semiconductor substrate having no semiconductor region of the first conductivity type, for example, before performing the first step, as a preparation step, it has a first preparation step and a second preparation step. Note that when manufacturing the variable capacitance element 100 using a semiconductor substrate 20 having a semiconductor region of the first conductivity type, the preparation step can be omitted.

[0050] In the first preparation step, as shown in FIG. 3, for example, a semiconductor region of the second conductivity type is formed in the semiconductor substrate 20. Specifically, for example, an n-type epitaxial region 26 is formed on the main surface S side of a p-type semiconductor substrate 20.

[0051] In the second preparation step, as shown in FIG. 4, a semiconductor region of the first conductivity type is formed in the semiconductor substrate. Specifically, for example, ion implantation is performed on the semiconductor substrate 20 having the n-type epitaxial region 26 to form a well 22' of the first conductivity type up to a region farther from the main surface S than the epitaxial region 26. The well 22' is, for example, a p (p - )-type semiconductor region. For example, it has a region R22a' in which the impurity concentration increases as it moves away from the main surface S of the semiconductor substrate on the main surface S side of the semiconductor substrate, and a region R22b that contacts this region and in which the impurity concentration decreases as it moves away from the main surface S of the semiconductor substrate.

[0052] (First step) In the first step, as shown in FIG. 5, an insulating layer 11 is formed on a main surface S of a semiconductor substrate having a p-type semiconductor region (well 22′). In the first step, the semiconductor substrate is first heat-treated to form an insulating layer 11 having a thickness of, for example, d 11 A thermal oxide film having a thickness of 3 to 14 nm is formed. Next, a photoresist (not shown) or the like is used to cover the region where the insulating layer 11 is to be formed. Next, etching is performed using this photoresist as a mask to remove the thermal oxide film in the region other than the masked region, thereby forming the insulating layer 11.

[0053] (Second process) Next, as shown in FIG. 6, the main surface S of the insulating layer 11 is 11 A conductive layer 12 is formed on the main surface S of the semiconductor substrate, and a cap layer 10 having an insulating layer 11 and a conductive layer 12 is provided on the main surface S of the semiconductor substrate. 11 A polycrystalline semiconductor such as polysilicon is formed on the n-type conductive layer 12 and patterned to form the n-type conductive layer 12. The patterning in the second step is performed so that the size of the conductive layer 12 in the in-plane direction is smaller than the size of the insulating layer 11 in the in-plane direction (see FIG. 1).

[0054] In this second step, a cap layer 10 having an insulating layer 11 and a conductive layer 12 can be provided. That is, a cap layer 10 made of an insulating layer 11 and a conductive layer 12 may be provided, or a cap layer having other layers in addition to the insulating layer 11 and the conductive layer 12 may be provided. In the method for manufacturing a variable capacitance element according to this embodiment, in the first and second steps, a cap layer 10 made of an insulating layer 11 and a conductive layer 12 is formed at a position overlapping a region where a second semiconductor layer 23 described later is to be formed.

[0055] In the first and second steps, the thickness d of the cap layer 10 10 It is preferable to form the insulating layer 11 and the conductive layer 12 so that the thickness d 10 It is more preferable that the thickness d of the cap layer 10 is 100 nm or more in the first and second steps. 10It is preferable to form the insulator layer 11 and the conductor layer 12 so that it is 400 nm or less, and it is more preferable to make it 300 nm or less.

[0056] Also, on the insulator layer 11 and at positions aligned with the conductor layer 12, a sidewall spacer 13 is formed using, for example, silicon dioxide.

[0057] (Third step) Next, as shown in FIG. 7, ion implantation is performed from the conductor layer 12 side of the cap layer 10 into the semiconductor substrate 20 through the conductor layer 12 and the insulator layer 11. In the well 22', a second semiconductor layer 23 of the first conductivity type in which the impurity concentration decreases as it moves away from the insulator layer 11 in the stacking direction is formed in the region on the side in contact with the insulator layer 11, and a first semiconductor layer 22 of the first conductivity type is formed in the remaining well 22'. That is, in the third step, the second semiconductor layer 23 is formed in the well 22', and the portion of the well 22' other than the second semiconductor layer 23 becomes the first semiconductor layer 22. The first semiconductor layer 22 is, for example, a p(p)-type semiconductor region.

[0058] In the third step, for example, ion implantation is performed on the semiconductor substrate 20, and a second semiconductor layer 23 having the same shape as the conductor layer 12 can be formed when viewed in plan from the stacking direction.

[0059] In the third step, for example, the second semiconductor layer 23 can be formed by self-alignment, so a mask or the like is not required. The acceleration energy during ion implantation depends on the thickness of the cap layer 10 and the depth of the semiconductor region formed as the second semiconductor layer 23, but it can be, for example, 30 to 70 kEV. If the acceleration energy is too small, it is not possible to perform ion implantation into the semiconductor substrate through the cap layer 10, so it is preferable to set the acceleration energy to be equal to or greater than a predetermined value.

[0060] The conductor layer 12 is composed of disordered crystal grains. When ion implantation is performed on the semiconductor substrate 20 through the cap layer 10, the implanted ions are likely to collide with the atoms of the conductor layer 12 composed of crystal grains with disordered orientations, and part of the ions is blocked and stays in the cap layer 10. Therefore, by manufacturing the stacked structure 50 by the manufacturing method of the present embodiment, channeling is suppressed. Therefore, when ion implantation is directly performed without providing a cap layer on the semiconductor substrate as in the prior art, the impurity concentration increases as the distance from the main surface increases in the region on the main surface side, and in the region away from the main surface, the impurity concentration decreases as the distance from the main surface increases. In the present embodiment, the impurity concentration of the second semiconductor layer 23 has a concentration profile that decreases as the distance increases in the stacking direction. Thereby, the stacked structure 50 is formed.

[0061] Although the manufacturing method of the stacked structure 50 has been described above, for example, it may further include other steps, and a variable capacitance element 100 as shown in FIG. 1 can be manufactured by the following procedure.

[0062] When manufacturing the variable capacitance element 100, for example, a MOS transistor with a p-type LDD structure may be used. In such a case, the p-channel of the MOS transistor with a p-type LDD structure can be used as the low-concentration layer 24.

[0063] Furthermore, after the above preparation step and before the above first step, ion implantation may be performed in a state where a mask is provided on a portion of the main surface S that overlaps with a region other than the region where the low-concentration layer 24 is formed, and the low-concentration layer 24 may be formed as a p-type low-concentration region.

[0064] Also, in the above first step, when removing the thermal oxide film to form the insulator layer 11, a thermal oxide film covering the entire upper surface of the low-concentration layer 24 may be left.

[0065] Also, after the above first step and before the above second step, ion implantation may be performed on the semiconductor substrate through a mask having a predetermined pattern, and p-type first diffusion layers 25aa and 25ba may be formed in the well.

[0066] Also, after the second step and before the third step, ion implantation may be further performed on the first diffusion layers 25aa and 25ba to form second diffusion layers 25ab and 25bb having a higher impurity concentration than the first diffusion layers 25aa and 25ba.

[0067] Also, after the third step, a terminal wiring b may be connected to the diffusion layer 25b and installed so as to have the same potential as the base substrate 21. In this way, the variable capacitance element 100 as shown in FIG. 1 can be manufactured.

[0068] As described above, according to the variable capacitance element 100 of the present embodiment, in the MOS structure, the cap layer 10 has the conductor layer 12 and the insulating layer 11 located between the conductor layer 12 and the second semiconductor layer 23, and the impurity concentration of the second semiconductor layer 23 decreases as it moves away from the main surface S of the semiconductor substrate 20 in the stacking direction. Therefore, a variable capacitance element with a high capacitance variable ratio and a high linearity of the capacitance variable ratio with respect to the depth of the semiconductor substrate 20 can be provided. Further, when the variable capacitance element 100 has a first semiconductor layer 22 having an average impurity concentration lower than the average impurity concentration of the second semiconductor layer 23 on the side away from the main surface S with respect to the second semiconductor layer 23 in the stacking direction, during operation, due to the thermal diffusion from the first semiconductor layer 22, the p - boiling up causes the impurity concentration of the second semiconductor layer 23 to increase. Therefore, the series resistance can be suppressed.

[0069] Also, according to the method for manufacturing a variable capacitance element according to the present embodiment, in the third step, since ion implantation is performed through the cap layer 10 having the conductor layer 12, the ions to be implanted are likely to collide with the atoms of the conductor layer 12 composed of the orientations of disordered crystal grains, and channeling is suppressed. Therefore, the impurity concentration of the second semiconductor layer 23 decreases as it moves away from the insulating layer 11 in the stacking direction, and the concentration gradient of the impurity concentration can be increased. Therefore, the variable capacitance element 100 with a high capacitance variable ratio and a high linearity of the impurity concentration with respect to the depth of the semiconductor substrate 20 can be manufactured by a simple method.

[0070] <Applicable Example> FIG. 8 is an example of a circuit diagram of a voltage controlled oscillator 200 including the variable capacitance element 100 of the above embodiment. As shown in FIG. 8, the voltage controlled oscillator 200 has, for example, an internal circuit 71, a resistor 72, a protection diode 73, a VDD terminal 74, an input terminal 75, a VSS terminal 76, and a variable capacitance element 100. The voltage of the VDD terminal 74 is, for example, the ground voltage, and the voltage of the VSS terminal is the power supply voltage. In the voltage controlled oscillator 200, an internal circuit 71 is provided between the VDD terminal 74 and the VSS terminal 76. This internal circuit 71 is configured by, for example, a general oscillation circuit such as an inverting amplifier and a feedback resistor. The input terminal 75 is a terminal to which a piezoelectric vibrator such as a crystal is connected to the internal circuit 71 via the resistor 72, and a variable capacitance element 100 is provided between the input terminal 75 and the VSS terminal 76. Although not shown, a control voltage is applied to the input terminal 75 side of the variable capacitance element 100 through another terminal, and its capacitance value is adjusted. Further, a protection diode 73 is provided as a protection element between the VDD terminal 74 and the VSS terminal 76. Thus, the variable capacitance element 100 of the present embodiment can be applied to a voltage controlled oscillator 200 or the like using a crystal oscillator as a resonator.

[0071] So far, the variable capacitance element, its manufacturing method, and the voltage controlled oscillator using the variable capacitance element have been described, but the characteristic configurations of the above embodiments and modification examples may be combined respectively.

Example

[0072] Hereinafter, examples and comparative examples of the present invention will be described. The present invention is not limited to only the following examples.

[0073] [Example 1] As Example 1, a laminated structure as shown in FIG. 2 was fabricated by process simulation. The process simulation was performed using TCAD. In the process simulation, the processes under the following conditions were simulated.

[0074] In Example 1, first, as a first preparation step, an epitaxial region 26 was formed on a p-type silicon substrate. Next, as a second preparation step, B+ ions were implanted into the main surface of the silicon substrate at an acceleration energy of 120 keV with a dose of 2.5×10 13 ions / cm 2 to form a p-type semiconductor region on the base substrate 21.

[0075] Next, as a first step, the silicon substrate on which the p-type semiconductor region was formed was thermally oxidized in air at 800 °C to form an insulating layer with a thickness of 6.5 nm on the main surface of the silicon substrate.

[0076] Next, as a second step, by low-pressure CVD, a polysilicon layer with a thickness of 200 nm was formed on the main surface of the insulating layer to form a cap layer composed of the insulating layer and the polysilicon layer.

[0077] Next, as a third step, ion implantation was performed on the silicon substrate from the polysilicon layer side of the cap layer through the polysilicon layer and the insulating layer. The ion implantation was performed by implanting B+ ions at an acceleration energy of 50 keV with a dose of 2.0×10 13 ions / cm 2 ions / cm 2 In Example 1, in this way, a stacked structure as shown in FIG. 2 in which the base substrate, the first semiconductor layer, the second semiconductor layer, the insulating layer, and the polysilicon layer were provided in this order in the stacking direction was fabricated.

[0078] Next, the impurity concentration distribution in the stacking direction at one position in the in-plane direction of the fabricated stacked structure was obtained by simulation based on SIMS (Secondary Ion Mass Spectrometry) profile data.

[0079] [Comparative Example 1] As Comparative Example 1, a stacked structure formed by the following process was simulated by process simulation. In Comparative Example 1, the simulation was performed in the same manner as in Example 1.

[0080] B+ ions were implanted into the main surface of the silicon substrate at an acceleration energy of 160 keV with a dose of 1.5×10 13 ions / cm 2 to form a first semiconductor region. Next, B ions were implanted into the main surface of the silicon substrate where the first semiconductor region was formed near the surface layer portion at an acceleration energy of 50 keV with a dose of 2.0×10 + ions / cm 13 to create a stacked structure in which the first semiconductor region was formed on the base substrate and the second semiconductor region was formed on the first semiconductor region. 2 Then, the impurity concentration in the stacking direction of the fabricated stacked structure was determined in the same manner as in Example 1.

[0081] Next, the impurity concentration in the stacking direction of the fabricated stacked structure was determined in the same manner as in Example 1.

[0082] FIG. 9 shows a semi-logarithmic graph of the measurement results of the impurity concentration in the stacking direction of the stacked structures of Example 1 and Comparative Example 1. In FIG. 9, a depth of 0 μm is the main surface S of the semiconductor substrate. That is, a depth of 0 μm in Comparative Example 1 corresponds to the surface of the second semiconductor region, and a depth of 0 μm in Example 1 corresponds to the surface of the second semiconductor layer.

[0083] In Example 1, the second semiconductor layer is located at a depth of 0 μm to 0.14 μm, and the first semiconductor layer is located at a depth of 0.14 μm to approximately 0.6 μm. The second semiconductor layer of Example 1 shows an impurity concentration profile in which the impurity concentration decreases as it moves away from the main surface of the semiconductor substrate. In Example 1, the boundary between the first semiconductor layer and the second semiconductor layer corresponds to the minimum value of the impurity concentration.

[0084] From the results of FIG. 9, it was confirmed that in Example 1, the impurity concentration of the second semiconductor layer located on the main surface side of the semiconductor substrate decreases as it moves away from the insulating layer in the stacking direction.

[0085] On the one hand, in the method of directly performing ion implantation on a semiconductor substrate as in Comparative Example 1, it was confirmed that in the region on the main surface side, the impurity concentration increases as the distance from the main surface of the semiconductor substrate increases, and in the region away from the main surface, the impurity concentration profile shows that the impurity concentration decreases as the distance from the main surface of the semiconductor substrate increases.

[0086] Also, in Comparative Example 1, in the depth range of 0.2 μm to 0.35 μm, the concentration gradient of the impurity concentration is relatively steep, and the concentration gradient of the impurity concentration in this region is -2.65 {log 10 (pieces·cm -3 ) / μm}. In contrast, the concentration gradient of the impurity concentration in the second semiconductor layer (depth range of 0 μm to 0.14 μm) of Example 1 is -9.66 {log 10 (pieces·cm -3 ) / μm}. Therefore, by comparing Example 1 and Comparative Example 1, it was confirmed that the concentration gradient of the impurity concentration in the second semiconductor layer in Example 1 is about 3.6 times or more steeper than the region with a relatively steep concentration gradient of the impurity concentration in Comparative Example 1.

Explanation of Reference Signs

[0087] 10 Cap layer, 11 Insulating layer, 12 Conductor layer, 20 Semiconductor substrate, 21 Base substrate, 22 First semiconductor layer, 23 Second semiconductor layer, 24 Low-concentration layer, 25a·25b Diffusion layer, 25aa·25ba First diffusion layer, 25ab·25bb Second diffusion layer, 26 Epitaxial region

Claims

1. A semiconductor substrate and a cap layer provided on a main surface of the semiconductor substrate, The semiconductor substrate has a first semiconductor layer of a first conductivity type and a second semiconductor layer of the first conductivity type disposed between the first semiconductor layer and the cap layer, The cap layer has a conductor layer and an insulator layer positioned between the conductor layer and the second semiconductor layer, A variable capacitance element in which an impurity concentration of the second semiconductor layer decreases as it moves away from the insulator layer in a stacking direction.

2. The impurity concentration of the second semiconductor layer has a concentration gradient of -5 {log １０ (pieces / cm －３ ) / μm} or less. The variable capacitance element according to claim 1.

3. The semiconductor substrate has a minimum value of impurity concentration at an interface between the first semiconductor layer and the second semiconductor layer in a stacking direction. The variable capacitance element according to claim 1 or 2.

4. The thickness of the cap layer is 50 nm or more. The variable capacitance element according to any one of claims 1 to 3.

5. The semiconductor substrate is made of silicon containing an impurity element, The insulator layer is made of silicon dioxide, The conductor layer is made of polycrystalline silicon. The variable capacitance element according to any one of claims 1 to 4.

6. A first step of forming an insulator layer on a main surface of a semiconductor substrate having a semiconductor region of a first conductivity type, A second step of forming a conductor layer on a main surface of the insulator layer and providing a cap layer having the insulator layer and the conductor layer on the main surface of the semiconductor substrate, A third step of performing ion implantation on the semiconductor substrate from the conductor layer side of the cap layer through the conductor layer and the insulator layer, and forming a second semiconductor layer of the first conductivity type in a region of the semiconductor region that contacts the insulator layer and has an impurity concentration decreasing as it moves away from the insulator layer in a stacking direction, and forming a first semiconductor layer of the first conductivity type in the remaining semiconductor region. A method for manufacturing a variable capacitance element.

7. In the first step and the second step, the insulator layer and the conductor layer are formed such that the thickness of the cap layer is 50 nm or more. The method for manufacturing a variable capacitance element according to claim 6.

8. In the first step and the second step, a cap layer composed of the insulator layer and the conductor layer is formed at a position overlapping a region where the second semiconductor layer is to be formed. The method for manufacturing a variable capacitance element according to claim 6 or 7.

9. The method for manufacturing a variable capacitance element according to any one of claims 6 to 8, wherein in the third step, ion implantation is performed on the semiconductor substrate to form the second semiconductor layer having the same shape as the conductor layer when viewed in a plan view from the stacking direction.

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