Method and system for diffusing magnesium in a gallium nitride material using a sputtered magnesium source

Abstract

A method for forming a doped gallium nitride (GaN) layer includes providing a substrate structure including a gallium nitride layer, forming a dopant source layer on the gallium nitride layer, and depositing a capping structure on the dopant source layer. The method also includes annealing the substrate structure to diffuse dopants into the gallium nitride layer, removing the capping structure and the dopant source layer, and activating the diffused dopants.

Description

Technical Field

[0001] Cross - Reference to Related Applications

[0001] This application claims the benefit of priority to U.S. Provisional Patent Application No. 62 / 975,075, filed on February 11, 2020, the disclosure of which is hereby incorporated by reference in its entirety for all purposes.

Background Art

[0002]

[0002] Gallium nitride - based semiconductor devices, such as p - n diodes, p - i - n diodes, Schottky diodes, and high electron mobility transistors (HEMTs), can be applied to various power systems such as solar inverters, small power supplies (e.g., power factor correction circuits or PFCs), switched - mode power supplies (SMPSs), motor drive devices, RF power amplifiers, solid - state lighting (SSL), smart grids, and automotive motor drive systems. Therefore, in the art, improved methods and systems related to the formation of gallium nitride - based semiconductor devices are needed.

Summary of the Invention

[0003]

[0003] Embodiments of the present invention relate to semiconductor materials. More particularly, methods and systems related to the use of a sputtered magnesium source for diffusing magnesium into a gallium nitride material are provided by embodiments of the present invention.

[0004]

[0004] According to one embodiment of the present invention, a method of forming a p - type gallium nitride layer is provided. The method includes providing a substrate structure including an undoped gallium nitride layer, sputtering a dopant source including magnesium onto the undoped gallium nitride layer, and depositing a capping structure on the dopant source. The method also includes annealing the substrate structure to diffuse magnesium into the undoped gallium nitride layer, removing the capping structure and the dopant source, and activating the diffused magnesium to form a p - type gallium nitride layer.

[0005]

[0005] According to another embodiment of the present invention, a method for forming a doped gallium nitride layer is provided. The method includes providing a substrate structure including a gallium nitride layer, forming a dopant source layer on the gallium nitride layer, and depositing a capping structure on the dopant source layer. The method also includes annealing the substrate structure to diffuse dopants into the gallium nitride layer, removing the capping structure and the dopant source layer, and activating the diffused dopants.

[0006]

[0006] By the method of the present invention, many advantages over the prior art are achieved. For example, embodiments of the present invention provide a method and system for diffusing magnesium into GaN for device manufacturing. The methods and systems described herein are applicable to various optical, electronic, and optoelectronic devices. These and other embodiments of the present invention will be described in more detail below in conjunction with the following text and the accompanying drawings, along with many of their advantages and features.

Brief Description of the Drawings

[0007]

Figure 1

Figure 2

Figure 3A

Figure 3B

Figure 4

Figure 5

Figure 6A

Figure 6B

Figure 7

Figure 8

Figure 9

Mode for Carrying Out the Invention

[0008]

[0018] Gallium nitride (GaN) is a widely used III-V material system suitable for various optical, electronic, and optoelectronic applications. Since magnesium is an acceptor-type dopant with the smallest ionization energy, p-type doping can be achieved by magnesium doping in GaN. However, magnesium doping is associated with several problems. First, the passivation of magnesium dopants by hydrogen. Hydrogen forms neutral Mg-H complexes. Furthermore, a large ionization energy (about 200 meV) is associated with magnesium doping. Additionally, when implantation is used, implantation can cause damage due to surface decomposition that is difficult to anneal. When surface decomposition occurs, compensating donors are generated at the temperature at which the damage is annealed. Furthermore, surface decomposition can generate compensating donors at the temperature at which magnesium is known to diffuse, so diffusion can be hindered by surface decomposition.

[0009]

[0019] The present invention generally relates to a method of forming doped regions by diffusion in gallium nitride materials. Doping refers to the process of intentionally introducing impurities into a semiconductor material to change its electrical properties. Doping can be achieved, for example, by either diffusion or ion implantation. In the diffusion process, a semiconductor wafer can be held in a high-temperature quartz tube furnace and passed through an appropriate gas mixture. The dopant source can be a gas source, a liquid source, or a solid source. The diffusion coefficient may depend exponentially on temperature in the form of, for example [Number] , where k is the Boltzmann constant, T is the temperature, and E D is the activation energy.

[0010]

[0020] Referring to FIGS. 1 to 6B, a method of forming a p-type doped GaN layer (e.g., a magnesium-doped GaN layer) according to an embodiment of the present invention is shown.

[0011]

[0021] FIG. 1 is a simplified cross-sectional view showing a GaN substrate 110 according to an embodiment of the present invention. In FIG. 1, the GaN substrate 110 can include one or more materials, for example, an undoped or doped GaN substrate, a sapphire substrate having one or more GaN layers, a silicon carbide substrate having one or more GaN layers, a silicon substrate having one or more GaN layers, a gallium oxide substrate having one or more GaN layers, or a combination thereof. As an example, the GaN substrate 110 can include a bulk substrate, an epitaxially grown buffer layer, and an undoped GaN epitaxial layer. The GaN substrate 110 may have a designed substrate structure as shown in FIG. 8. When a designed substrate structure is utilized, it can include a ceramic-based substrate together with a thin silicon (Si) layer formed thereon. Therefore, the GaN substrate 110 is not limited to a bulk GaN substrate made of GaN, but is a substrate including one or more GaN layers. The term GaN layer refers to Al x Ga 1-xIt includes a substrate structure comprising N layers (x≥0) and including both GaN layers and AlGaN layers. The various substrates described herein provide a surface for epitaxial growth.

[0012]

[0022] One or more cleaning operations can be performed to prepare the GaN substrate 110 for subsequent processing. As an example, organic cleaning can be performed to remove organic residues from the growth and / or processing surface. Various solvents, including H2SO4 / H2O2 or O2 plasma, can be utilized during this cleaning process. Further, metal cleaning can be performed to remove organic residues from the growth and / or processing surface. Various solvents, including HCl / H2O2 or HCl, can be utilized during this cleaning process. Further, an oxide removal process can be performed to remove oxides present on the growth and / or processing surface. During this cleaning process, various oxide removal processes, including wet cleaning (HCl or HF) and / or dry cleaning (e.g., use of Cl-based plasma), can be utilized.

[0013]

[0023] In some embodiments, the surface preparation process is a three-step process of organic cleaning, metal cleaning, and then oxide removal. In other embodiments, one or more of these cleaning processes are not utilized. As described herein, one or more cleaning processes provide a clean surface to which a dopant source or capping structure, more fully described below, can be bonded and a surface that does not provide a barrier to magnesium diffusion.

[0014]

[0024] Figure 2 is a simplified cross-sectional view showing a GaN substrate and a magnesium source according to an embodiment of the present invention. Referring to Figure 2, in one embodiment, the magnesium source 210 is sputtered onto the GaN substrate 110 to provide a magnesium diffusion source. According to various embodiments of the present invention, the magnesium source 210 may be a sputtered magnesium metal layer having a thickness in the range of about 1 nm to 20 nm, for example 5 nm to 15 nm, or a magnesium metal layer having a thickness of 20 nm; a sputtered MgF2 layer having a thickness in the range of about 10 nm to 50 nm, for example 20 nm to 50 nm; or an AlN-Mg source that can be formed by co-sputtering AlN with Mg. The magnesium concentration in this AlN-Mg source can be a magnesium concentration of >1×10 19 cm 3 to 10%. The thickness of the AlN-Mg source can be in the range of 10 nm to 100 nm. The AlN-Mg source can be formed by simultaneously sputtering both AlN and Mg from separate sputtering sources. In other embodiments, other deposition techniques other than sputtering are used to form the magnesium source 210. Those skilled in the art will recognize many variations, modifications, and alternatives.

[0015]

[0025] As will be more fully described below, the magnesium source 210 provides a diffusion source that can be used in the manufacture of optical, electronic, and optoelectronic devices using doped regions formed by diffusion. It should be noted that the inventors have determined that the above-described thin layers result in improved magnesium diffusion. Without limiting the embodiments of the present invention, the inventors believe that GaN decomposition can be more accurately controlled by thin layers (e.g., magnesium sources from a few nanometers to tens of nanometers, e.g., sputtered magnesium sources). Without limiting the embodiments of the present invention, the inventors believe that as the thickness of the magnesium source 210 increases, the source layer behaves like a bulk material and reduces the effectiveness of the capping structure, which will be more fully described below.

[0016]

[0026] Figures 3A and 3B show two methods of forming the magnesium source 210 shown in FIG. 2. The ability to provide a patterned source region enables integration into a wide variety of semiconductor device process flows.

[0017]

[0027] FIG. 3A is a simplified process flow for manufacturing a magnesium diffusion source according to an embodiment of the present invention. In FIG. 3A, a lift-off based source patterning process is used to form a magnesium diffusion source. A photoresist layer 310 is deposited on the GaN substrate 110 and patterned to provide one or more openings. A magnesium diffusion source, which can be one of the magnesium sources described in connection with FIG. 2, is deposited, for example, using sputtering, to form regions 320 and 324 on the photoresist layer 310 and a magnesium diffusion source region 322 on the GaN substrate 110. The photoresist layer 310 and the source regions 320 and 324 on the photoresist layer 310 are removed using a lift-off process, and the magnesium diffusion source region 322 is formed with the desired patterning on the GaN substrate. As an example, a device that utilizes a doped region can utilize this lift-off process.

[0018]

[0028] Although a single magnesium diffusion source 322 is shown in FIG. 3A, it will be apparent to those skilled in the art that multiple magnesium diffusion sources can be formed as appropriate for the particular device being manufactured. Those skilled in the art will recognize many variations, modifications, and alternatives.

[0019]

[0029] Figure 3B is a simplified process flow for manufacturing a magnesium diffusion source according to another embodiment of the present invention. In Figure 3B, an etching-based source patterning process is used to form the magnesium diffusion source. In this embodiment, a magnesium diffusion source layer 330 is sputtered over the entire or a substantial portion of the GaN substrate, and a photoresist layer is deposited over the sputtered source layer. A magnesium diffusion source, which can be one of the magnesium diffusion sources described in connection with Figure 2, is sputtered to form a magnesium diffusion source layer 330 over the GaN substrate 110, which can then be patterned.

[0020]

[0030] The photoresist layer is deposited and patterned to provide one or more etching mask regions 340. The photoresist is used as an etching mask to pattern the magnesium diffusion source layer 330 to create magnesium diffusion source regions 332 on the GaN substrate with the desired patterning. Note that other etching masks including SiN x , SiO2, Ni, Pt, or Au can be used instead of or in combination with the photoresist etching mask. The remaining photoresist is then removed. As an example, a device that utilizes doped regions can utilize this etching-based process.

[0021]

[0031] Although a single magnesium diffusion source region 332 is shown in Figure 3A, it will be apparent to those skilled in the art that multiple magnesium diffusion sources can be formed as appropriate for the particular device being manufactured. Those skilled in the art will recognize many variations, modifications, and alternatives.

[0022]

[0032] FIG. 4 is a simplified cross-sectional view showing a capped GaN substrate according to an embodiment of the present invention. Referring to FIG. 4, a capping structure 410, also referred to as a capping layer or cap layer, is deposited on a magnesium source 210 which may be a sputtered magnesium source layer. The magnesium source 210 may be the patterned source region described in connection with FIGS. 3A and 3B, or may cover the entire GaN substrate 110. The capping structure can be formed using various deposition techniques, and several different magnesium sources can be utilized with the capping structure 410.

[0023]

[0033] The material of the capping structure can include AlN sputtered in the range of about 100 nm to 200 nm in thickness, combined with a layer of SiO2 that can be deposited by PECVD in the range of about 50 nm to 200 nm in thickness. In another embodiment, the capping structure includes AlN sputtered in the range of about 100 nm to 200 nm in thickness, combined with a layer of SiN that can be deposited by PECVD in the range of about 20 nm to 50 nm in thickness. x For a double-layer capping structure design (e.g., AlN / SiO2 or AlN / SiN x ), the first AlN layer can serve to protect the sputtered magnesium source layer, and the second SiO2 or SiN x layer can serve to protect the first AlN layer. The AlN nitride can be characterized by a low density and amorphous structure when sputtered, thereby making it vulnerable to oxidation and other processes. Thus, the double-layer capping structure design protects this first AlN layer.

[0024]

[0034] In some embodiments, to protect the sputtered magnesium source from oxidation, after the magnesium source is sputtered, the capping layer is deposited while the sputtered magnesium source is in a vacuum environment or a non-oxidizing environment. Thus, without breaking the vacuum, one or more portions of the capping layer (e.g., AlN / SiO2 or AlN / SiNx Before sputtering any of the first AlN layers of the bilayer capping structure design, a single system capable of sputtering a magnesium source can be used. Alternatively, multiple systems can be utilized along with appropriate load locks, etc. Those skilled in the art will recognize many variations, modifications, and alternatives.

[0025]

[0035] In yet another embodiment, the capping layer comprises a pyrolytic photoresist. In this embodiment, a 5 μm to 20 μm photoresist can be formed by spin coating and then pyrolyzed in forming gas (e.g., at a temperature of 600 - 800 °C).

[0026]

[0036] Executed within a semiconductor growth reactor, in contrast to a diffusion process that does not use a capping layer because the presence of the capping layer contaminates the growth reactor, using a capping layer can protect the underlying magnesium source during annealing. In particular, an amorphous capping layer, when introduced into a semiconductor growth reactor and exposed to a temperature suitable for diffusing dopants into a GaN layer or substrate, results in the decomposition of the capping layer and perhaps the redeposition of the capping layer material inside the growth reactor.

[0027]

[0037] The following examples show how various magnesium sources, such as sputtered magnesium sources, can be utilized with various capping structures.

[0028]

[0038] Mg metal using a photoresist capping layer: In this case, the photoresist can have a thickness in the range of 2 μm to 10 μm and functions as the main cap. In some embodiments, a thin AlN layer (e.g., having a thickness in the range of 20 nm to 50 nm) can be utilized on the magnesium to prevent oxidation of the magnesium. When used for this purpose, the AlN is generally deposited after the magnesium deposition without exposing the deposited magnesium to oxygen. This can be done, for example, by performing the deposition in the same tool / chamber or by keeping the magnesium surface in an inert gas atmosphere. In some embodiments, the AlN layer can have a thickness in the range of 10 nm to 100 nm.

[0029]

[0039] Mg metal present in MgF2 using an AlN / SiO2 capping structure: In this case, AlN is deposited or sputtered as the first layer of the capping structure, and a SiO2 layer is formed on the AlN layer. The thickness of the AlN layer can be in the range of 40 nm to 300 nm, and the thickness of the SiO2 layer can be in the range of 20 nm to 200 nm, such that the thickness of the capping structure is in the range of 60 nm to 500 nm. In other embodiments, various thicknesses can be utilized depending on the particular application.

[0030]

[0040] Sputtered AlN / SiN x Mg metal using a capping structure: In this case, it is advantageous if the magnesium metal deposition and subsequent AlN sputtering can be performed without exposing the magnesium metal surface to oxygen to avoid possible oxidation of the magnesium metal surface. This can be done, for example, by performing the deposition in the same tool / chamber or by keeping the magnesium metal surface in an inert gas atmosphere. The AlN can be deposited or sputtered as the first layer of the capping structure, and the SiN x layer is formed on the AlN layer. The thickness of the AlN layer can be in the range of 40 nm to 300 nm, and the SiN xThe thickness of the layer can be in the range of 20 nm to 200 nm, and as a result, the thickness of the capping structure is in the range of 60 nm to 500 nm. In other embodiments, various thicknesses can be utilized depending on the particular application.

[0031]

[0041] MgF2:MgF2 using a photoresist cap is inert with respect to exposure to air. When this combination of magnesium diffusion source and photoresist cap layer is utilized, special precautions beyond normal cleanroom cleanliness precautions are typically not utilized.

[0032]

[0042] MgF2:MgF2 using an AlN / SiNx cap is inert with respect to exposure to air. When this combination of magnesium diffusion source and capping structure is utilized, special precautions beyond normal cleanroom cleanliness precautions are typically not utilized.

[0033]

[0043] MgF2 can be used with a composite capping structure consisting of a stack of MgF2 / AlN / SiN / photoresist.

[0034]

[0044] AlN:AlN-Mg co-sputtered with Mg(AlN-Mg) using a photoresist cap is known to be prone to oxidation, although only at high temperatures. When this combination of AlN-Mg is used as a magnesium source for nucleic acids and the photoresist layer is used as a capping layer, special precautions beyond normal cleanroom cleanliness precautions are typically not utilized.

[0035]

[0045] AlN / SiN x During the formation of the AlN layer that constitutes the AlN-Mg:AlN-Mg diffusion source using an AlN / SiN cap, the sputtering of the second (e.g., undoped) AlN layer is most conveniently performed in the same tool simply by stopping the magnesium co-sputtering. Thus, on the GaN substrate 110, Mg / AlN / AlN / SiN x or Mg / AlN / SiN xThe structure is formed in the order of...

[0036]

[0046] FIG. 5 is a simplified cross-sectional view showing the GaN substrate structure after the annealing process according to an embodiment of the present invention.

[0037]

[0047] In order to form a diffusion-doped Mg-GaN layer in which magnesium diffuses into GaN for doping, the structure shown in FIG. 4 is annealed as shown in FIG. 5. Therefore, FIG. 5 shows the structure after annealing, including a GaN substrate 110, a magnesium-doped GaN layer 510, a magnesium source 210, and a capping structure 410. As an example, the annealing can be performed, for example, in a tubular furnace, under an environment of N2 or N2 / NH3 or N2 / H2, at a pressure in the range of 100 Torr to 3 bar, and at a temperature in the range of 1000°C to 1400°C, for example, 1100°C to 1200°C. As the temperature increases, the diffusion rate increases, and as the diffusion time (for example, 1 hour) increases, the depth of diffusion and the thickness of the resulting Mg-GaN layer 510 increase.

[0038]

[0048] As shown in FIG. 5, the p-type doped Mg-GaN layer 510 is formed by the diffusion of magnesium dopants into the GaN substrate 110, typically an undoped GaN substrate, during the annealing process shown in FIG. 5. The GaN substrate 110 can include one or more undoped or doped epitaxial layers. In the illustrated embodiment, the doped Mg-GaN layer 510, also referred to as the doped Mg-GaN region, has a thickness in the range of about 50 nm to 200 nm, for example, 75 nm to 100 nm, but this is not essential in the present invention. In other embodiments, the doped Mg-GaN layer 510 can be thinner or thicker depending on the specific application.

[0039]

[0049] Figure 6A is a simplified cross-sectional view showing a GaN substrate and an Mg-GaN layer according to an embodiment of the present invention. After the annealing and diffusion processes, the capping structure 410 and the magnesium source 210 are removed as shown in Figure 6A, and a GaN substrate 110 having a doped Mg-GaN layer 510 is obtained. Different processes can be utilized depending on the materials present in the capping structure 410 and the magnesium source 210. For an AlN / SiO2 capping structure, dry etching (Cl2+Ar based) can be used. For an AlN / SiN capping structure, wet etching (HF, then TMAH or KOH) or dry etching (fluorine based, then chlorine based) can be used. For a photoresist capping layer, dry etching (oxygen plasma based) can be used. The advantage provided by wet etching and dry etching to the thermal decomposition photoresist is that the etching process can self-terminate when it reaches the Mg-GaN region. Those skilled in the art will recognize many variations, modifications, and alternatives.

[0040]

[0050] Figure 6B is a simplified cross-sectional view showing a GaN substrate and a p-type doped GaN layer according to an embodiment of the present invention. Referring to Figure 6B, the activation of magnesium dopants for forming a p-type doped GaN layer 510 using a processing procedure for removing hydrogen from the doped Mg-GaN layer 610 is shown. As an example, activation at 800 °C for 5 minutes in a nitrogen atmosphere can be utilized. Using the processes shown in Figures 1-2 and 4-6B, a p-type doped Mg-GaN layer 610 is provided on a GaN substrate suitable for the manufacture of various optical, electronic, and optoelectronic devices, including a number of devices to be described in more detail below.

[0041]

[0051] Figure 7 is a plot showing the doping of GaN with magnesium according to one embodiment of the present invention. As shown in Figure 7 showing the secondary ion mass spectrometry (SIMS) profile of the doped structure, doping of the GaN epitaxial layer with magnesium can be achieved using the embodiments of the present invention. In the SIMS profile shown in Figure 7, a set of AlGaN marker layers 722, 724, 726 (as well as five additional AlGaN marker layers not labeled but shown in Figure 7) are utilized to characterize the depth of diffusion associated with the magnesium dopant, but it will be understood that similar results can be achieved using the GaN epitaxial layer present on the GaN substrate 110 as described herein. In Figure 7, the mole fraction of aluminum is plotted on the right axis in normalized units. The mole fraction or concentration of magnesium is plotted on the left axis in units of atoms / cm 3 to the power of.

[0042]

[0052] The doped GaN epitaxial layer shown by the SIMS profile of Figure 7 was formed using a magnesium diffusion source containing AlN-Mg, a capping structure including a 265 nm thick AlN layer and a 100 nm thick SiO2 layer. The GaN epitaxial layer having the magnesium diffusion source and the capping structure was annealed at 1100 °C for 1.5 hours in a process similar to the process shown in Figure 5.

[0043]

[0053] To characterize the depth to which the magnesium dopant diffuses into the GaN epitaxial layer, a set of AlGaN marker layers separated by 200 nm were formed within the GaN epitaxial layer, and the first AlGaN marker layer was placed at a depth of approximately 700 nm from the surface of the GaN epitaxial layer. In the plot, the surface is located at a depth of 500 nm.

[0044]

[0054] Referring to Figure 7, the SIMS profile shows significant magnesium diffusion into the GaN epitaxial layer. At a depth of approximately 300 nm from the surface, marked by the intersection 740 in Figure 7, the magnesium concentration is approximately 2×10 18 cm-3 It shows evidence of magnesium diffusion achieved using embodiments of the present invention.

[0045]

[0055] Various devices, including optical, electronic, and optoelectronic devices, can utilize a magnesium diffusion process based on a magnesium diffusion source that includes a sputtered magnesium source. The diffusion and dopant layer formation processes can be inserted at appropriate points during the semiconductor device manufacturing process. As an example, using the methods and systems described herein, the following can be created. · A p-n junction for realizing a p-n diode (e.g., of a power device) · A junction-termination-extension for realizing various vertical devices (e.g., a rectifier or a transistor) · A merged p-n Schottky diode active · Gate protection for FIN-FET type devices · A current blocking barrier layer for CAVET devices · The gate of a p-gate HEMT power device or an LJFET

[0046]

[0056] In some embodiments, magnesium can diffuse laterally beyond a defined source region as shown in FIGS. 3A and 3B, resulting in a p-type doped region that extends laterally under other parts of the semiconductor structure. Such lateral expansion typically does not occur in an ion implantation process. Although p-type doping of an undoped region is shown herein, other embodiments provide for p-type doping of an n-type region to lower the doping level from an initial n-type dopant density to a reduced n-type dopant density. Further, although p-type doping using magnesium is shown, other p-type dopants can also be utilized. Additionally, n-type doping using an n-type dopant can be utilized in a manner similar to the p-type doping process shown herein. Those skilled in the art will recognize many variations, modifications, and alternatives.

[0047]

[0057] FIG. 8 is a simplified schematic diagram showing a design substrate structure according to some embodiments of the present invention. As shown in FIG. 8, the design substrate structure may be suitable for various electronic and optical applications. The design substrate structure may include a core 810 (e.g., an AlN substrate) having a coefficient of thermal expansion (CTE) that substantially matches the CTE of an epitaxial material grown on a detached silicon (111) layer 825, such as the design substrate structure.

[0048]

[0058] In applications involving the growth of gallium nitride (GaN)-based materials (epitaxial layers including GaN-based layers), the core 810 may be polycrystalline aluminum nitride (AlN) that can include a bonding material such as a polycrystalline ceramic material, e.g., yttrium oxide. Other materials including polycrystalline gallium nitride (GaN), polycrystalline aluminum gallium nitride (AlGaN), polycrystalline silicon carbide (SiC), polycrystalline zinc oxide (ZnO), polycrystalline gallium trioxide (Ga2O3), etc. can be utilized for the core.

[0049]

[0059] The thickness of the core 810 can be on the order of 100 - 1,500 μm, e.g., 750 μm. The core 810 is encapsulated in an adhesive layer 812 that can be referred to as a shell or encapsulating shell. In one embodiment, the adhesive layer 812 includes a tetraethyl orthosilicate (TEOS) oxide layer having a thickness of about 1,000 Å. In other embodiments, the thickness of the adhesive layer 812 varies, e.g., from 100 Å to 2,000 Å. Although TEOS oxide is utilized for the adhesive layer 812 in some embodiments, other materials for adhering between a subsequently deposited layer and the underlying layer or material (e.g., ceramic, particularly polycrystalline ceramic) can be utilized according to an embodiment of the present invention. For example, SiO2 or other silicon oxides (Si x O y) adheres well to the ceramic material and provides a surface suitable for subsequent deposition of, for example, a conductive material. The adhesive layer 812, in some embodiments, completely surrounds the core 810, forming a completely encapsulated core 810, and can be formed using an LPCVD process, or a semiconductor process, particularly a polycrystalline or composite substrate and other suitable deposition processes compatible with layers. The adhesive layer 812 provides a surface onto which subsequent layers adhere to form elements of the designed substrate structure.

[0050]

[0060] In addition to the use of LPCVD processes, spin-on glass / dielectrics, furnace-based processes, etc. to form the encapsulating adhesive layer, other semiconductor processes including CVD processes or similar deposition processes can be utilized according to embodiments of the present invention. As an example, a deposition process that coats a portion of the core 810 can be utilized, the core 810 can be turned over, and the deposition process can be repeated to coat further portions of the core 810. Thus, in some embodiments, LPCVD technology is utilized to provide a completely encapsulated structure, but other film-forming technologies can be utilized depending on the particular application.

[0051]

[0061] A conductive layer 814 is formed to surround the adhesive layer 812. In one embodiment, the conductive layer 814 is a shell of polysilicon (i.e., polycrystalline silicon), and since polysilicon has poor adhesion to the ceramic material, it is formed to surround the adhesive layer 812. In embodiments where the conductive layer 814 is polysilicon, the thickness of the polysilicon layer can be on the order of 500 - 5,000 Å, for example 2,500 Å. In some embodiments, the polysilicon layer can be formed as a shell to completely surround the adhesive layer 812 (e.g., a TEOS oxide layer), thereby forming a completely encapsulated adhesive layer 812, and can be formed using an LPCVD process. In other embodiments, as will be described later, the conductive material can be formed on a portion of the adhesive layer 812, for example, the lower half of the substrate structure. In some embodiments, the conductive material can be formed as a completely encapsulating layer and then removed on one side of the substrate structure.

[0052]

[0062] In one embodiment, the conductive layer 814 can be a polysilicon layer doped to provide a highly conductive material, for example, a polysilicon layer doped with boron to provide a p-type polysilicon layer. In some embodiments, doping with boron is at 1×10 19 cm -3 ~1×10 20 cm -3 level. Other dopants with different dopant concentrations (e.g., phosphorus, arsenic, bismuth, etc. with dopant concentrations in the range of 1×10 16 cm -3 ~5×10 18 cm -3 can be utilized to provide an n-type or p-type semiconductor material suitable for use in the conductive layer 814. Those skilled in the art will recognize many variations, modifications, and alternatives.

[0053]

[0063] The presence of the conductive layer 814 is useful during electrostatic chucking of the design substrate to a semiconductor processing tool, such as a tool having an electrostatic chuck (ESC or e-chuck). By the conductive layer, it can be quickly released from the chuck after processing in the semiconductor processing tool. In embodiments of the present invention, the conductive layer 814 enables electrical contact with the chuck or capacitive coupling to the e-chuck during subsequent processing including bonding. Thus, embodiments of the present invention provide a substrate structure that can be processed in a manner utilized for conventional silicon wafers. Those skilled in the art will recognize many variations, modifications, and alternatives. Further, providing a high thermal conductivity to the substrate structure in combination with an electrostatic chuck can provide better deposition conditions for subsequent formation of design layers and epitaxial layers, as well as subsequent device manufacturing processes. For example, a desirable thermal profile can be provided that results in lower stress, more uniform deposition thickness, and good stoichiometry control through subsequent layer formation.

[0054]

[0064] A second adhesion layer 816 (e.g., a TEOS oxide layer about 1,000 Å thick) is formed surrounding the conductive layer 814. In some embodiments, the second adhesion layer 816 completely surrounds the conductive layer 814 to form a completely encapsulated structure and can be formed using any other suitable deposition process including an LPCVD process, a CVD process, or the deposition of a spin-on dielectric.

[0055]

[0065] A barrier layer 818, e.g., a silicon nitride layer, is formed surrounding the second adhesion layer 816. In one embodiment, the barrier layer 818 is a silicon nitride layer having a thickness of about 2,000 Å to 5,000 Å. In some embodiments, the barrier layer 818 completely surrounds the second adhesion layer 816 to form a completely encapsulated structure and can be formed using an LPCVD process. In addition to silicon nitride layers, amorphous materials including SiCN, SiON, AlN, SiC, etc. can be used as the barrier layer 818. In some implementation forms, the barrier layer 818 consists of several sub-layers constructed to form the barrier layer 818. Thus, the term barrier layer is not intended to indicate a single layer or a single material, but is intended to encompass one or more materials laminated in a composite manner. Those skilled in the art will recognize many variations, modifications, and alternatives.

[0056]

[0066] In some embodiments, the barrier layer 818, e.g., a silicon nitride layer, prevents the diffusion and / or gas release of elements present in the core, such as yttrium (element), yttrium oxide (i.e., yttria), oxygen, metal impurities, other trace elements, etc., into the environment of a semiconductor processing chamber where a design substrate may be present during a high-temperature (e.g., 1,000 °C) epitaxial growth process. Using the encapsulation layer described herein, a ceramic material containing polycrystalline AlN designed for a non-cleanroom environment can be utilized in a semiconductor process flow and a cleanroom environment.

[0057]

[0067] Typically, the ceramic material utilized to form the core is fired at a temperature in the range of 1,800 °C. This process is expected to drive out a significant amount of impurities present in the ceramic material. These impurities can include yttrium, calcium, as well as other elements and compounds resulting from the use of yttria as a sintering agent. Subsequently, the subsequent diffusion of these impurities during the epitaxial growth process, which is carried out at a much lower temperature in the range of 800 °C to 1,100 °C, is expected to be negligible. However, contrary to conventional expectations, the inventors have confirmed that there is significant diffusion of elements through the layers of the design substrate even during the epitaxial growth process at a temperature much lower than the firing temperature of the ceramic material. Accordingly, embodiments of the present invention integrate a barrier layer 818 into the design substrate structure to prevent this undesirable diffusion.

[0058]

[0068] The bonding layer 820 (e.g., a silicon oxide layer) is deposited on a part of the barrier layer 818, for example, on the upper surface of the barrier layer 818, and is then used during the bonding of a substantially single crystal layer 825 (e.g., a single crystal silicon layer such as the exfoliated silicon (111) layer shown in FIG. 1). The bonding layer 820 can be about 1.5 μm thick in some embodiments. In some embodiments, the thickness of the bonding layer 820 is 20 nm or more to relieve bonding-induced voids. In some embodiments, the thickness of the bonding layer 820 is within the range of 0.75 to 1.5 μm.

[0059]

[0069] The substantially single crystal layer 825 (e.g., exfoliated Si(111)) is suitable for use as a growth layer during an epitaxial growth process to form an epitaxial material. In some embodiments, the epitaxial material can include a GaN layer having a thickness of 2 μm to 10 μm, which can be utilized as one of a plurality of layers used in optoelectronic, RF, and power devices. In one embodiment, the substantially single crystal layer 825 includes a single crystal silicon layer attached to the bonding layer 820 using a layer transfer process.

[0060]

[0070] Further description of the design substrate structure is provided in U.S. Patent No. 10,297,445, filed on June 13, 2017, and U.S. Patent No. 10,134,589, filed on June 13, 2017, the disclosures of which are hereby incorporated by reference in their entirety for all purposes. FIG. 8 provides an example of a design substrate that can be used during epitaxial growth in some embodiments, but it will be understood that other substrates can be utilized, as discussed in connection with FIG. 1.

[0061]

[0071] FIG. 9 is a simplified flowchart showing a method of forming a doped GaN layer according to an embodiment of the present invention. In a particular embodiment, the doped GaN layer is a p-type layer doped with magnesium. Method 900 includes providing (910) a substrate structure including a gallium nitride layer. The gallium nitride layer may or may not initially be doped, depending on the particular application. In some embodiments, the gallium nitride layer is a component of a GaN substrate. In other embodiments, the gallium nitride layer is mechanically bonded to a design substrate. As an example, the substrate structure can include a design substrate structure including a polycrystalline ceramic core, a barrier layer encapsulating the polycrystalline ceramic core, a bonding layer bonded to the barrier layer, and a substantially single crystal layer bonded to the bonding layer.

[0062]

[0072] The method also includes forming a dopant source layer on the gallium nitride layer (912), for example, by sputtering a dopant source layer on the GaN layer, and depositing a capping structure on the dopant source layer (914). The dopant source layer can include magnesium metal having a thickness in the range of 5 nm to 20 nm. Alternatively, the dopant source layer can include a magnesium fluoride layer having a thickness in the range of 5 nm to 50 nm. The dopant source layer can include a magnesium aluminum nitride composite material having a thickness in the range of 10 nm to 50 nm. In this case, the magnesium concentration in the magnesium aluminum nitride composite material is 1×10 19 cm 3It can be in the range of ~10%. In addition to these dopant sources, various dopant sources discussed herein, including AlN-Mg and AlN-MgF2 dopant sources, can be utilized.

[0063]

[0073] In some embodiments, the method can include performing a surface preparation process, for example, before forming the dopant source layer by sputtering. The surface preparation process can include one or more or all of an organic cleaning process, a metal cleaning process, and / or an oxide removal process.

[0064]

[0074] The method further includes annealing the substrate structure to diffuse the dopant into the gallium nitride layer (916), removing the capping structure and the dopant source layer (918), and activating the diffused dopant (920). As an example, annealing the substrate structure can be performed at a temperature in the range of about 1000 °C to about 1400 °C.

[0065]

[0075] It should be understood that the specific steps shown in FIG. 9 provide a specific method for forming a doped (e.g., p-type) GaN layer according to some embodiments of the present invention. According to alternative embodiments, other sequences of steps can also be performed. For example, alternative embodiments of the present invention may perform the steps outlined above in a different order. Further, the individual steps shown in FIG. 9 can include a plurality of sub-steps that can be performed in various suitable orders similar to the individual steps. Further, additional steps can be added or removed depending on the specific application. Those skilled in the art will recognize many variations, modifications, and alternatives.

[0066]

[0076] Although the GaN layer is described herein, the present invention is not limited to GaN, and other III-V materials including AlGaN, InGaN, InAlGaN, combinations thereof, etc. can be utilized. Those skilled in the art will recognize many variations, modifications, and alternatives.

[0067]

[0077] Although some embodiments have been described from the perspective of layers, the term "layer" should be understood such that a layer can include several sub-layers that are constructed to form the layer of interest. Thus, the term "layer" is not intended to denote a single layer consisting of a single material, but rather is intended to encompass one or more materials that are compositely laminated to form the desired structure. Those skilled in the art will recognize many variations, modifications, and alternatives.

[0068]

[0078] Also, the examples and embodiments described herein are for illustrative purposes only, and in light of this, various modifications or changes will be suggested to those skilled in the art and should be included within the spirit and scope of this application as well as the appended claims.

Claims

1. A method of forming a p-type gallium nitride layer, comprising: providing a substrate structure including an epitaxial gallium nitride layer; sputtering a dopant source containing magnesium onto the epitaxial gallium nitride layer; patterning the dopant source to form a patterned dopant source region and one or more openings in the epitaxial gallium nitride layer; depositing a dielectric capping structure over the patterned dopant source region and the one or more openings; annealing the substrate structure at a temperature in the range of about 1000 °C to about 1400 °C to diffuse magnesium into the epitaxial gallium nitride layer; removing the dielectric capping structure and the patterned dopant source region; and subsequently activating the diffused magnesium to form the p-type gallium nitride layer. A method comprising the above steps.

2. The method according to claim 1, wherein the dopant source includes a layer of magnesium fluoride having a thickness in the range of 20 nm to 50 nm.

3. The method according to claim 1, wherein the dopant source includes a layer of aluminum magnesium nitride composite material having a thickness in the range of 5 nm to 50 nm.

4. The substrate structure according to claim 1, wherein the substrate structure includes: a polycrystalline ceramic core; a barrier layer encapsulating the polycrystalline ceramic core; a bonding layer bonded to the barrier layer; and a substantially single crystal layer bonded to the bonding layer. A method according to claim 1, including the above components.

5. A method of forming a doped gallium nitride layer, comprising: providing a substrate structure including an epitaxial gallium nitride layer; forming a dopant source layer over the epitaxial gallium nitride layer; patterning the dopant source layer to form a patterned dopant source region and one or more openings in the epitaxial gallium nitride layer; depositing a dielectric capping structure over the patterned dopant source region and the one or more openings; annealing the substrate structure at a temperature in the range of about 1000 °C to about 1400 °C to diffuse a dopant into the epitaxial gallium nitride layer; removing the dielectric capping structure and the patterned dopant source region; and subsequently activating the diffused dopant. A method including

6. The method according to claim 5, wherein forming the dopant source layer includes sputtering the dopant source layer above the epitaxial gallium nitride layer.

7. The method according to claim 5, further including performing a surface preparation process before forming the dopant source layer.

8. The method according to claim 7, wherein the surface preparation process includes an organic cleaning process or an oxide removal process.

9. The method according to claim 7, wherein the surface preparation process includes a metal cleaning process.

10. The dielectric capping structure includes AlN and at least one of SiO ２ or SiN Ｘ The method according to claim 1.

11. The method according to claim 7, wherein the surface preparation process includes an organic cleaning process, a metal cleaning process, and an oxide removal process.

12. The method according to claim 5, wherein the epitaxial gallium nitride layer is undoped.

13. The method according to claim 5, wherein the dopant source layer includes magnesium having a thickness in the range of 5 nm to 20 nm, and the epitaxial gallium nitride layer includes a p-type gallium nitride layer.

14. The method according to claim 5, wherein the dopant source layer includes magnesium fluoride having a thickness in the range of 20 nm to 50 nm.

15. The method according to claim 5, wherein the dopant source layer includes a magnesium aluminum nitride composite material having a thickness in the range of 5 nm to 50 nm.

16. The method according to claim 15, wherein the magnesium concentration in the magnesium aluminum nitride composite material is in the range of 1×10^19 cm^-3 or more.

17. The dielectric capping structure includes AlN and SiO ２ or SiN Ｘ The method according to claim 5, comprising at least one of them.

18. The substrate structure is a polycrystalline ceramic core, a barrier layer encapsulating the polycrystalline ceramic core, a bonding layer bonded to the barrier layer, and a substantially single crystal layer bonded to the bonding layer The method according to claim 5, including

19. The method according to claim 15, wherein the magnesium concentration in the magnesium aluminum nitride composite material is in the range of 1×10^19 cm^-3 to 8.9×10^21 cm^-3.

20. The method according to claim 5, further including forming a mask on the epitaxial gallium nitride layer before forming the dopant source layer, and the mask exposes one or more portions of the upper surface of the epitaxial gallium nitride layer.

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