Method of manufacturing a semiconductor device

Abstract

To provide a technology that efficiently performs division or coupling of a substrate which is composed of a compound semiconductor, and that suppresses damage.SOLUTION: A manufacturing method of a semiconductor device comprises the steps of: preparing a substrate (12) that is composed of a compound semiconductor including a first chemical element and a second chemical element which is coupled with the first chemical element and has electronegativity being less than the first chemical element with a difference being more than or equal to 1.5; flowing current through the substrate; and dividing the substrate including a region where the current of the substrate is flowed, and along with a cleavage plane of the substrate.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The technology disclosed in this specification relates to a method for manufacturing a semiconductor device.

[0002] In the method for manufacturing a semiconductor device, various methods for separating and bonding a substrate composed of a compound semiconductor have been proposed. Patent Document 1 discloses a method for cutting a substrate containing gallium oxide in the method for manufacturing a semiconductor device. In this manufacturing method, first, by scanning a laser beam along a planned cutting line of the substrate, a modified region that is more brittle than other regions of the substrate is formed along the planned cutting line of the substrate. Then, the substrate is cut along the planned cutting line by a dicing blade. In this manufacturing method, since the modified region formed along the planned cutting line is cut, the substrate can be cut at a high speed compared with conventional dicing.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In the manufacturing method of Patent Document 1, a laser beam is irradiated along the planned cutting line of the substrate so that the width of the modified region becomes wider than the width of the dicing blade. Therefore, when the substrate is cut by the dicing blade, a modified region remains on the cut surface. Since the modified region has been damaged by the laser beam, the cut surface becomes non-uniform, which may affect the performance of the semiconductor device. In this specification, a technology for efficiently performing the division and bonding of a substrate composed of a compound semiconductor and suppressing damage is proposed.

Means for Solving the Problems

[0005] The first manufacturing method of the semiconductor device disclosed in this specification includes a step of preparing a substrate (12) composed of a compound semiconductor containing a first element and a second element that is bonded to the first element and has an electronegativity 1.5 or more less than that of the first element, a step of passing an electric current through the substrate, and a step of dividing the substrate along a cleavage plane of the substrate including the region through which the electric current has passed through the substrate.

[0006] Note that electronegativity is a value indicating the ability of an atom in a molecule to attract electrons, and in this specification, it means Pauling electronegativity.

[0007] In this manufacturing method, a substrate composed of a compound semiconductor containing a first element and a second element bonded to the first element is prepared. Here, when the difference in electronegativity between the first element and the second element is 1.5 or more, it is known that the bond between the first element and the second element exhibits ionic bonding properties. In a compound semiconductor exhibiting ionic bonding properties, when an electric current flows, the charges generated move inside the compound semiconductor, and thus the polarity inside the crystal is likely to be disturbed. Further, when an electric current flows, thermal stress is generated and the crystal structure is likely to be distorted. Thus, a compound semiconductor exhibiting ionic bonding properties is likely to have its crystal structure changed by passing an electric current. In the above manufacturing method, by utilizing this property, an electric current is passed through a substrate composed of a compound semiconductor exhibiting ionic bonding properties, and the substrate is divided along the cleavage plane of the substrate. According to this manufacturing method, the substrate can be efficiently divided while suppressing damage to the divided surface.

[0008] The second manufacturing method of the semiconductor device disclosed in this specification includes a step of laminating a first substrate (52) and a second substrate (54), and a step of bonding the first substrate and the second substrate by passing an electric current between the first substrate and the second substrate. The first substrate and the second substrate are composed of a compound semiconductor, and the compound semiconductor contains a first element and a second element that is bonded to the first element and has an electronegativity 1.5 or more less than that of the first element.

[0009] In this manufacturing method, first, a first substrate and a second substrate are laminated. The first substrate and the second substrate are composed of a compound semiconductor containing a first element and a second element that is bonded to the first element and has an electronegativity difference of 1.5 or more less than that of the first element. As described above, a compound semiconductor exhibiting ionic bonding has a crystal structure that is easily disrupted when an electric current flows through it. Therefore, by passing an electric current between the first substrate and the second substrate, the crystal structure at the interface between the first substrate and the second substrate is disrupted, and the vicinity of the interface melts. Then, when the electric current is stopped, the disrupted crystal structure realigns during the process of solidification of the melted semiconductor material. Thereby, the first substrate and the second substrate can be efficiently bonded together.

Brief Description of the Drawings

[0010]

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Best Mode for Carrying Out the Invention

[0011] The technical elements disclosed in this specification are listed below. Each of the following technical elements is independently useful.

[0012] In an example of the manufacturing method disclosed in this specification, in the step of passing an electric current through the substrate, a probe may be brought into contact with the substrate, and an electric current may be passed between the substrate and the probe.

[0013] With such a configuration, by adjusting the position where the probe is brought into contact with the substrate, the region of the electric current flowing through the substrate can be controlled, so that it is easy to divide the substrate along the cleavage plane of the substrate.

[0014] In an example of the manufacturing method disclosed in this specification, the method may further include a step of forming an electrode on the surface of the region. In the step of passing an electric current through the substrate, the electric current may be passed through the substrate via the electrode.

[0015] With such a configuration, by adjusting the position where the electrode is formed on the substrate, the region of the electric current flowing through the substrate can be controlled, so that it is easy to divide the substrate along the cleavage plane of the substrate.

[0016] In an example of the manufacturing method disclosed in this specification, in the step of forming the electrode, the electrode may be formed on the surface of the region along the cleavage plane.

[0017] With such a configuration, the electrode is formed on the surface of the substrate along the cleavage plane. Therefore, an electric current easily flows along the cleavage plane, and it is easy to locally apply stress along the cleavage plane.

[0018] In an example of the manufacturing method disclosed in this specification, the method may further include a step of increasing the resistance of the region to be higher than that of the surrounding region by introducing a dopant or a different material different from the compound semiconductor into the region.

[0019] In such a configuration, by introducing a dopant or a different material into the region where current flows, the resistance of the region where current flows becomes higher than that of the surrounding regions. Therefore, when current flows, the temperature of this region is more likely to rise than that of the surrounding regions, and a large thermal stress can be applied to this region.

[0020] In an example of the manufacturing method disclosed in this specification, a step of increasing the thermal resistance of the region by introducing a dopant or a different material different from the compound semiconductor into the region may be further provided so that the region has a higher thermal resistance than the surrounding regions.

[0021] In such a configuration, by introducing a dopant or a different material into the region where current flows, the thermal resistance of the region where current flows becomes higher than that of the surrounding regions. Therefore, when current flows, heat is likely to stagnate in this region, and the temperature is more likely to rise than that of the surrounding regions. Therefore, a large thermal stress can be applied to this region.

[0022] In an example of the manufacturing method disclosed in this specification, the compound semiconductor may be an oxide semiconductor, and the first element may be oxygen. Further, the compound semiconductor may be composed of β-Ga2O3. The cleavage plane may be the (100) plane and / or the (001) plane of β-Ga2O3.

[0023] Cleavage is likely to occur along the (100) plane or the (001) plane of β-Ga2O3. Therefore, when the substrate is divided along the (100) plane or the (001) plane of β-Ga2O3, the substrate can be easily divided.

[0024] In an example of the manufacturing method disclosed in this specification, a step of introducing a dopant or a different material different from the compound semiconductor onto the surface of the first substrate may be further provided before the step of laminating the first substrate and the second substrate. In the step of laminating the first substrate and the second substrate, the second substrate may be laminated on the surface of the first substrate.

[0025] In such a configuration, by introducing a dopant or a different material, the resistance of the surface of the first substrate increases. Then, a second substrate is laminated on the surface of the first substrate with increased resistance. Therefore, when an electric current is passed between the first substrate and the second substrate, the temperature of the contact surface of the first substrate with the second substrate is likely to rise. Accordingly, at the interface between the first substrate and the second substrate, the semiconductor material is likely to melt, and the first substrate and the second substrate can be efficiently bonded together.

[0026] In an example of the manufacturing method disclosed in this specification, before the step of bonding the first substrate and the second substrate, a step of increasing the resistance of at least one of the surface layer portion of the first substrate and the surface layer portion of the second substrate by annealing the first substrate or the second substrate may be further provided.

[0027] In such a configuration, by bringing the first substrate and the second substrate into contact with each other such that the surface layer portion with increased resistance is located at the interface between the first substrate and the second substrate, the resistance of this interface can be increased. Therefore, when an electric current is passed between the first substrate and the second substrate, the temperature of the interface between the first substrate and the second substrate (i.e., the contact surface between the first substrate and the second substrate) is likely to rise. Accordingly, at the interface, the semiconductor material is likely to melt, and the first substrate and the second substrate can be efficiently bonded together.

[0028] In an example of the manufacturing method disclosed in this specification, before the step of bonding the first substrate or the second substrate, a step of increasing the thermal resistance of at least one of the surface layer portion of the first substrate and the surface layer portion of the second substrate by annealing the first substrate and the second substrate may be further provided.

[0029] In such a configuration, by bringing the first substrate and the second substrate into contact with each other such that the surface layer portion with increased thermal resistance is located at the interface between the first substrate and the second substrate, the thermal resistance of this interface can be increased. Therefore, when an electric current flows between the first substrate and the second substrate, heat tends to stagnate at the interface between the first substrate and the second substrate (i.e., the contact surface between the first substrate and the second substrate), and the temperature of this interface tends to rise. Accordingly, the semiconductor material is likely to melt at this interface, and the first substrate and the second substrate can be efficiently bonded together.

[0030] In an example of the manufacturing method disclosed in this specification, the compound semiconductor may be an oxide semiconductor, and the first element may be oxygen. Further, the compound semiconductor may be composed of β-Ga2O3.

[0031] (Example 1) With reference to the drawings, a method for manufacturing the semiconductor device 10 of Example 1 will be described. In the manufacturing method of Example 1, the semiconductor device 10 is manufactured using the wafer-shaped semiconductor substrate 12 shown in FIG. 1. The manufacturing method of Example 1 is characterized by a step of dividing the semiconductor substrate 12 composed of a specific material to be described later. This manufacturing method can be adopted for various semiconductor devices and their semi-finished products that employ the specific material. Hereinafter, the step of dividing the semiconductor substrate 12 will be mainly described, and the description of other manufacturing steps will be omitted.

[0032] The semiconductor substrate 12 shown in FIG. 1 is composed of a compound semiconductor. Specifically, the semiconductor substrate 12 is composed of β-Ga2O3. However, the material of the semiconductor substrate 12 is not limited to β-Ga2O3. As the material of the semiconductor substrate 12, a compound semiconductor containing a first element and a second element that bond to each other, and having a difference in electronegativity between the first element and the second element of 1.5 or more can be used. Generally speaking, the semiconductor substrate 12 may be composed of a material having ionic bonding properties. In β-Ga2O3, O is the first element (electronegativity = 3.44), and Ga is the second element (electronegativity = 1.81). Note that the compound semiconductor constituting the semiconductor substrate 12 may further contain an element different from the first element and the second element. For example, other compound semiconductors constituting the semiconductor substrate 12 include gallium oxide-based semiconductors such as (Ga,Rh)2O3, (Ga,Ir)2O3, (Ga,Bi)2O3, ZnGa2O4, and other oxide semiconductors.

[0033] The plane along the X direction and the Z direction in FIG. 1 is the (100) plane of β-Ga2O3, the plane along the Y direction and the Z direction is the (001) plane of β-Ga2O3, and the plane along the paper surface of FIG. 1 (the plane along the surface 12a) is the (010) plane of β-Ga2O3. That is, the Y direction is the

[0100] direction, the X direction is the

[0001] direction, and the Z direction is the

[0010] direction.

[0034] As shown in FIG. 1, the semiconductor substrate 12 has a plurality of element regions 30 in which semiconductor devices 10 are respectively formed, and a division planned region 32 (a region to be cut later) provided around each element region 30. Each element region 30 is arranged in a lattice pattern along the X direction and the Y direction.

[0035] In this manufacturing method, first, dopants are introduced into the semiconductor substrate 12 by ion implantation. Here, as shown in FIG. 2, the dopants are selectively introduced along the planned division region 32. The dopants to be introduced are not particularly limited, and for example, Fe or V can be adopted. As a result, as shown in FIG. 2, a high-resistance region 34 into which dopants are introduced is formed inside the semiconductor substrate 12. The high-resistance region 34 has a higher resistance than the surrounding region (i.e., the element region 30) due to the introduction of dopants. In the cross-sectional views after FIG. 2, the illustration of the internal structure of the semiconductor substrate 12 is omitted.

[0036] Next, as shown in FIG. 3, the probes 16 are brought into contact with the front surface 12a and the back surface 12b of the semiconductor substrate 12, respectively. Here, each probe 16 is brought into contact with the semiconductor substrate 12 within the planned division region 32. In this step, as shown in FIG. 2, within the planned division region 32, the probe 16 may be brought into contact with only one location on the front surface 12a and the back surface 12b of the semiconductor substrate 12, or the probe 16 may be brought into contact at a plurality of locations within the planned division region 32. Also, the probe 16 may be brought into contact with the front surface 12a and the back surface 12b outside the planned division region 32.

[0037] Next, a current is passed through the semiconductor substrate 12 via each probe 16 in contact with the semiconductor substrate 12. Since dopants are introduced into the high-resistance region 34 within the planned division region 32, the high-resistance region 34 has a higher resistance compared to its surroundings. Therefore, when a current is passed through the semiconductor substrate 12, the temperature of the high-resistance region 34 rises to a higher temperature than the surrounding region. Thus, when a current is passed through the semiconductor substrate 12, a large thermal stress is applied to the high-resistance region 34. Also, since the semiconductor substrate 12 is composed of a compound semiconductor showing ionic bonding properties, when a current flows through the semiconductor substrate 12, the polarity inside the crystal is easily disturbed. Furthermore, since the planned division region 32 is provided along the (100) plane and the (001) plane of β-Ga2O3, cleavage is likely to occur. For the above reasons, in this step, for example, about 800 W / cm is applied to the semiconductor substrate 12 2When power exceeding this is applied, as shown in FIG. 4, the semiconductor substrate 12 can be divided along the division planned region 32. Thereby, a plurality of semiconductor devices 10 can be separated from the semiconductor substrate 12.

[0038] (Example 2) In the manufacturing method of Example 2, compared with Example 1, the method of passing a current through the semiconductor substrate 12 is different. The manufacturing method of Example 2 is the same as that of Example 1 up to the process shown in FIG. 2. In Example 2, after the process shown in FIG. 2, as shown in FIG. 5, an electrode 18 is formed on the surface 12a of the semiconductor substrate 12. Here, the electrode 18 is formed along the surface 12a of the division planned region 32 of the semiconductor substrate 12. The electrode 18 can be, for example, an electrode that makes a Schottky contact with the semiconductor substrate 12. Note that the electrode 18 may be formed so as to cover the entire surface 12a of the division planned region 32 of the semiconductor substrate 12, or may be formed intermittently along the surface 12a of the division planned region 32.

[0039] Next, a current is passed through the semiconductor substrate 12 via the electrode 18 disposed on the surface 12a of the semiconductor substrate 12. For example, a current can be passed between the electrode 18 and the back surface 12b of the semiconductor substrate 12. Then, by applying power exceeding about 800 W / cm 2 to the semiconductor substrate 12, as shown in FIG. 6, similar to Example 1, the semiconductor substrate 12 can be divided along the division planned region 32. Thereby, a plurality of semiconductor devices 10 can be separated from the semiconductor substrate 12.

[0040] As described above, in the manufacturing methods of Examples 1 and 2, the semiconductor substrate 12 can be easily divided by passing a current through the semiconductor substrate 12. Therefore, for example, compared with the dicing mode using a dicing blade conventionally employed for dividing a semiconductor substrate, the semiconductor substrate 12 can be divided in a short time. Furthermore, in the above-described examples, neither a dicing blade nor a dicing tape for protecting the surface of the semiconductor substrate during dicing is required, and the semiconductor substrate 12 can be divided at low cost.

[0041] In the above-described Examples 1 and 2, by passing a current through the semiconductor substrate 12 and using the cleavage of the compound semiconductor to divide the semiconductor substrate 12, damage is less likely to remain on the cut surface. Therefore, the cut surface becomes substantially uniform, and the semiconductor device 10 can be manufactured with a high yield.

[0042] In the above-described Examples 1 and 2, the entire semiconductor substrate 12 was made of β-Ga2O3, but only the planned division region 32 may be made of β-Ga2O3. That is, regions other than the planned division region 32 (for example, the element region 30, etc.) may contain elements other than O and Ga.

[0043] In the above-described examples, a current was passed between the front surface 12a and the back surface 12b of the semiconductor substrate 12. However, for example, using two or more probes or two or more electrodes 18 arranged at arbitrary positions on the front surface 12a of the semiconductor substrate 12, a current may be passed only in the vicinity of the front surface 12a of the semiconductor substrate 12 (that is, the surface layer portion of the front surface 12a). Similarly, a current may be passed only in the vicinity of the back surface 12 of the semiconductor substrate 12.

[0044] In the above-described Examples 1 and 2, the high-resistance region 34 was formed by ion-implanting a dopant. The high-resistance region 34 is not limited to the mode of being formed by ion-implanting a dopant, and may be formed by introducing a dopant by epitaxial growth. Alternatively, by introducing a different material different from the material constituting the semiconductor substrate 12 into a part of the planned division region 32, the resistance of the region may be increased. For example, instead of the process shown in FIG. 2, a groove may be formed by etching from the front surface 12a along the planned division region 32, and the groove may be filled with a different material (for example, SiO2, etc.). In such a configuration, a high-resistance region 34 reaching a predetermined depth (that is, the depth of the groove) from the front surface 12a of the semiconductor substrate 12 can be formed.

[0045] Also, in Examples 1 and 2, a high-resistance region 34 was formed by introducing a dopant. However, a high thermal-resistance region having a higher thermal resistance than its surroundings may be formed by introducing a dopant. Note that the high thermal-resistance region may be formed of the above-described different materials. When an electric current flows through the high thermal-resistance region, heat is more likely to stagnate and the temperature is more likely to rise than in the surrounding regions. Therefore, a large thermal stress can also be applied by forming the high thermal-resistance region. Note that the above-described high-resistance region 34 and high thermal-resistance region may not be formed. That is, in the technology disclosed in this specification, the step of introducing a dopant or different materials may not be provided. Even with such a configuration, the semiconductor substrate 12 can be split along the cleavage plane by flowing an electric current through the semiconductor substrate 12.

[0046] Also, in Examples 1 and 2, the steps for singulating the semiconductor device 10 from the semiconductor substrate 12 were mainly described. However, the technology disclosed in Examples 1 and 2 may be applied to, for example, the step of thinning the semiconductor substrate 12. For example, as shown in FIG. 7, a high-resistance region 40 is formed by selectively ion-implanting a dopant to a desired depth from the surface 12a of the semiconductor substrate 12. Then, the probes 16 are brought into contact with the surface 12a and the back surface 12b of the semiconductor substrate 12, and an electric current is passed through the semiconductor substrate 12 via the probes 16, whereby the semiconductor substrate 12 can be separated along the high-resistance region 40. Note that the surface along the high-resistance region 40 (that is, the surface to be separated) is set to the (100) plane or the (001) plane of β-Ga2O3, whereby the semiconductor substrate 12 can be separated more easily. Thereby, the semiconductor substrate 12 can be thinned. Note that the formation of the high-resistance region 40 is not limited to the mode of ion-implanting a dopant. For example, when the semiconductor substrate 12 is manufactured by epitaxial growth in the step of preparing the semiconductor substrate 12, a semiconductor material containing a dopant may be epitaxially grown at the depth where the high-resistance region 40 is to be formed. Alternatively, a semiconductor substrate 12 including the high-resistance region 40 may be manufactured using different materials.

[0047] In Examples 1 and 2, the semiconductor substrate 12 was divided along the planned division region 32 by applying power exceeding about 800 W / cm 2 to the semiconductor substrate 12. In this process, in the process of increasing the power applied to the semiconductor substrate 12, grooves are formed from the surface 12a of the semiconductor substrate 12 toward the thickness direction of the semiconductor substrate 12 along the planned division region 32 of the semiconductor substrate 12. That is, the technology disclosed in this specification is also useful as a technology for forming grooves on the surface 12a of the semiconductor substrate 12.

[0048] (Example 3) Next, the manufacturing method of Example 3 will be described. The manufacturing method of Example 3 is characterized by a step of bonding two semiconductor substrates 52 and 54 made of a specific material described later. The manufacturing method of Example 3 can be adopted for various semiconductor devices and their semi-finished products that adopt the specific material. Hereinafter, the step of bonding the semiconductor substrates 52 and 54 will be mainly described, and the description of other manufacturing steps will be omitted. Note that the semiconductor substrate 52 and the semiconductor substrate 54 are examples of the "first substrate" and the "second substrate", respectively.

[0049] The semiconductor substrates 52 and 54 are composed of a compound semiconductor similar to those in Examples 1 and 2. That is, the semiconductor substrates 52 and 54 are composed of β-Ga2O3. However, the materials of the semiconductor substrates 52 and 54 are not limited to β-Ga2O3. As the materials of the semiconductor substrates 52 and 54, a compound semiconductor containing a first element and a second element that bond to each other, and having a difference in electronegativity between the first element and the second element of 1.5 or more can be used. Generally speaking, the semiconductor substrate 12 may be composed of a material having ionic bonding properties. In β-Ga2O3, O is the first element (electronegativity = 3.44), and Ga is the second element (electronegativity = 1.81). Note that the compound semiconductor constituting the semiconductor substrate 12 may further contain an element different from the first element and the second element. For example, other compound semiconductors constituting the semiconductor substrate 12 include gallium oxide-based semiconductors such as (Ga, Rh)2O3, (Ga, Ir)2O3, (Ga, Bi)2O3, ZnGa2O4, and other oxide semiconductors.

[0050] First, as shown in FIG. 8, a dopant is introduced into the surface 52a of the semiconductor substrate 52 by ion implantation. Here, the dopant is introduced over the entire surface 52a of the semiconductor substrate 52. Thereby, a high-resistance region 56 in which ions are implanted is formed in a region (surface layer portion) facing the surface 52a of the semiconductor substrate 52. The dopant to be introduced is not particularly limited, and for example, Fe or V can be employed. Next, as shown in FIG. 9, the semiconductor substrate 54 is laminated on the surface 52a of the semiconductor substrate 52.

[0051] Next, the laminated semiconductor substrates 52 and 54 are annealed in an atmosphere containing oxygen. The atmosphere containing oxygen means an atmosphere containing oxygen as an element. For example, the semiconductor substrates 52 and 54 are annealed in an atmosphere such as oxygen (O2) gas. Thereby, the interface 55 between the semiconductor substrate 52 and the semiconductor substrate 54 is made to have a higher resistance. That is, in this step, the resistance of the region near the interface 55 of the semiconductor substrates 52 and 54 including the high-resistance region 56 is made higher.

[0052] Thereafter, a current is passed between the semiconductor substrate 52 and the semiconductor substrate 54. Specifically, as shown in FIG. 9, the probe 59 is brought into contact with the surface 54a of the semiconductor substrate 54 and the back surface 52b of the semiconductor substrate 52, respectively. Then, a current is passed through the semiconductor substrates 52 and 54 via the probe 59. A high-resistance region 56 is formed on the surface 52a of the semiconductor substrate 52. Further, the resistance in the vicinity of the interface 55 between the semiconductor substrate 52 and the semiconductor substrate 54 is increased by annealing. Therefore, when a current is passed through the laminate of the semiconductor substrates 52 and 54, the temperature in the vicinity of the interface 55 rises to a higher temperature than the surrounding region. Then, in the vicinity of the interface 55, a molten layer 60 in which the semiconductor material is melted is generated, and the crystal structure in the molten layer 60 is disturbed. Thereafter, when the current is stopped, in the process of solidification of the molten layer 60, the disturbed crystal structure is aligned again, and the semiconductor substrate 52 and the semiconductor substrate 54 can be bonded. As described above, in the manufacturing method of Example 3, the semiconductor substrates 52 and 54 can be easily bonded by passing a current through the laminated semiconductor substrates 52 and 54.

[0053] In addition, in Example 3, the entire semiconductor substrates 52 and 54 were made of β-Ga2O3, but only the region near the surface 52a of the semiconductor substrate 52 and the region near the back surface 54b of the semiconductor substrate 54 (that is, the range facing the bonding surface) may be made of β-Ga2O3.

[0054] Also, in Example 3, the high-resistance region 56 was formed by ion implantation of a dopant. However, for example, the high-resistance region 56 may be formed by epitaxially growing a semiconductor material containing a dopant on the surface 52a of the semiconductor substrate 52. Further, the high-resistance region 56 may be formed by forming a different material (for example, SiO2 or the like) different from the material constituting the semiconductor substrate 52 on the surface 52a.

[0055] In Example 3, the high-resistance region 56 was formed in the surface layer portion near the surface 52a of the semiconductor substrate 52. However, a high-resistance region may be formed in the surface layer portion near the back surface 54a of the semiconductor substrate 54. Further, the high-resistance region 56 may be formed in both the surface layer portion near the surface 52a of the semiconductor substrate 52 and the surface layer portion near the back surface 54a of the semiconductor substrate 54.

[0056] In Example 3, the high-resistance region 56 was formed by ion implantation. However, instead of or in addition to this, a high thermal-resistance region having a higher thermal resistance than its surroundings may be formed by ion implantation. Note that the high thermal-resistance region may be formed by the above-described dopant or different material. When a current flows through the high thermal-resistance region, heat is more likely to stagnate and the temperature is more likely to rise than in the surrounding regions. Therefore, a large thermal stress can also be applied by forming the high thermal-resistance region. The high thermal-resistance region may be formed in the surface layer portion near the surface 52a of the semiconductor substrate 52, in the surface layer portion near the back surface 54a of the semiconductor substrate 54, or in both of these surface layer portions. Similarly, instead of or in addition to the step of increasing the resistance of the interface 55 by annealing, the interface 55 between the semiconductor substrate 52 and the semiconductor substrate 54 may be made to have a high thermal resistance by annealing. Note that the above-described high-resistance region 56 and high thermal-resistance region may not be formed. That is, in the technology disclosed in this specification, the step of introducing a dopant or different material may not be provided. Also, the annealing step may not be provided. Even with such a configuration, the semiconductor substrates 52 and 54 can be bonded by flowing a current between the semiconductor substrates 52 and 54.

[0057] Although the embodiments have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above. The technical elements described in this specification or the drawings exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Also, the technology illustrated in this specification or the drawings achieves multiple purposes simultaneously, and achieving one of those purposes itself has technical utility.

Explanation of Signs

[0058] 10: Semiconductor device, 12: Semiconductor substrate, 12a: Front surface, 12b: Back surface, 16: Probe, 18: Electrode, 30: Element region, 32: Region to be divided, 34, 40: High-resistance region, 52, 54: Semiconductor substrate, 56: High-resistance region, 59: Probe

Claims

1. A method for manufacturing a semiconductor device, comprising: laminating a first substrate (52) and a second substrate (54); bonding the first substrate and the second substrate together by passing a current between the first substrate and the second substrate; Equipped with the first substrate and the second substrate are made of a compound semiconductor, the compound semiconductor contains a first element and a second element that is bonded to the first element and has an electronegativity 1.5 or more lower than that of the first element; Manufacturing method.

2. The method further includes a step of introducing a dopant or a different material different from the compound semiconductor into a surface (52a) of the first substrate prior to the step of stacking the first substrate and the second substrate, In the step of stacking the first substrate and the second substrate, the second substrate is stacked on the surface of the first substrate. The method of claim 1 .

3. 3. The manufacturing method according to claim 1, further comprising a step of increasing the resistance of at least one of a surface layer portion of the first substrate and a surface layer portion of the second substrate by annealing the first substrate or the second substrate prior to the step of bonding the first substrate and the second substrate.

4. The manufacturing method according to any one of claims 1 to 3, further comprising a step of increasing the thermal resistance of at least one of a surface layer portion of the first substrate and a surface layer portion of the second substrate by annealing the first substrate or the second substrate prior to the step of bonding the first substrate and the second substrate.

5. the compound semiconductor is an oxide semiconductor, The method according to any one of claims 1 to 4, wherein the first element is oxygen.

6. The compound semiconductor is β-Ga ２ O ３ The method of claim 5, comprising:

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