Bandwidth Boost Bidirectional Serial Bus Buffer Circuit

Abstract

The serial bus buffer circuit includes a master input / output terminal (104A), a slave input / output terminal (104B), a switched resistor circuit (202), and a switch control circuit (208). The switched resistor circuit (202) is configured to provide a low impedance connection between the master input / output terminal (104A) and the slave input / output terminal (104B). The switch control circuit (208) is coupled to the switched resistor circuit (202) and configured to enable the low impedance connection based on the voltage at the master input / output terminal (104A) and the voltage at the slave input / output terminal (104B).

Description

Technical Field

[0001] Universal serial buses such as the inter-integrated circuit (I 2 C) bus are widely used to connect the systems of devices. For example, the I 2 C bus is used to provide communication between a master device and one or more slave devices. In such applications, the capacitance added to the serial bus by the slave device can be large enough to significantly degrade the signal transition time and cause violations of the serial bus timing specifications.

Summary of the Invention

[0002] In this specification, a serial bus buffer circuit including a switchable low-impedance path is described for reducing transients (glitches) on a bus signal. In one example, the serial bus buffer circuit includes a master input / output terminal, a slave input / output terminal, a first switch, a second switch, a resistor, and a switch control circuit. The first switch includes a first terminal, a second terminal, and a control terminal. The first terminal is coupled to the master input / output terminal. The resistor includes a first terminal and a second terminal. The first terminal of the resistor is coupled to the second terminal of the first switch. The second switch includes a first terminal, a second terminal, and a control terminal. The first terminal of the second switch is coupled to the second terminal of the resistor. The second terminal of the second switch is coupled to the slave input / output terminal. The switch control circuit is coupled to the master input / output terminal, the slave input / output terminal, the control terminal of the first switch, and the control terminal of the second switch.

[0003] In another example, a serial bus buffer circuit includes a master input / output terminal, a slave input / output terminal, a switched resistor circuit, and a switch control circuit. The switched resistor circuit is configured to provide a low impedance connection between the master input / output terminal and the slave input / output terminal. The switch control circuit is coupled to the switched resistor circuit and is configured to enable the low impedance connection based on the voltage of the master input / output terminal and the voltage of the slave input / output terminal.

[0004] In a further example, a method includes monitoring a first voltage at a master input / output terminal of a serial bus buffer circuit and monitoring a second voltage at a slave input / output terminal of the serial bus buffer circuit. The first voltage and the second voltage are compared to a low logic level threshold. The low impedance connection between the master input / output terminal and the slave input / output terminal is enabled in response to the first voltage or the second voltage falling below the low logic threshold.

[0005] For a detailed description of the various examples, reference is now made to the accompanying drawings.

Brief Description of the Drawings

[0006]

Figure 1

[0007]

Figure 2

[0008]

Figure 3

[0009]

Figure 4

[0010]

Figure 5

[0011] A serial bus buffer circuit is used to reduce the capacitive load of a serial bus system (such as an I 2 C bus system) and improve signal integrity. Serial bus buffers with not very wide bandwidth generate glitches (such as positive responses, clock stretching, etc.) during handoff transitions. Implementations of some serial bus buffer circuits provide good glitch elimination but have insufficient isolation between serial bus devices. Other serial bus circuit implementations provide good isolation between serial bus devices but are too slow to provide good glitch elimination.

[0012] The described serial bus buffer circuit includes a compensation circuit that dynamically switches a low-impedance compensation path between the master and slave terminals of the serial bus buffer circuit when a handoff condition is detected. The low-impedance compensation path increases the bandwidth of the serial bus buffer circuit and reduces the amplitude and duration of handoff glitches. The serial bus buffer circuit also provides good master-slave isolation when the low-impedance compensation path is disabled.

[0013] FIG. 1 shows a block diagram for an exemplary serial bus system 100 that includes a serial bus buffer circuit. Serial bus system 100 includes a master device 102, a serial bus buffer circuit 104, and a slave device 106. In some implementations of serial bus system 100, master device 102 is an I 2 C master, slave device 106 is an I 2 C slave, and serial bus buffer circuit 104 is an I 2It is a C serial bus buffer circuit. The master device 102 is coupled to the master input / output terminal 104A of the serial bus buffer circuit 104, and the slave device 106 is coupled to the slave input / output terminal 104B of the serial bus buffer circuit 104. The serial bus buffer circuit 104 provides isolation and increased drive between the master device 102 and the slave device 106. The serial bus buffer circuit 104 includes a low-impedance compensation path between the master input / output terminal 104A and the slave input / output terminal 104B. The serial bus buffer circuit 104 detects a potential handoff and enables the low-impedance compensation path to reduce glitch amplitude and duration when a potential handoff is detected. When no handoff condition exists, the serial bus buffer circuit 104 disables the low-impedance compensation path to provide increased isolation between the master input / output terminal 104A and the slave input / output terminal 104B.

[0014] FIG. 2 shows a block diagram for an exemplary serial bus buffer circuit 200 that includes a transient reduction circuit element. The serial bus buffer circuit 200 is an implementation of the serial bus buffer circuit 104. The serial bus buffer circuit 200 includes a switched resistor circuit 202, a drive circuit 204, a drive circuit 206, a switch control circuit 208, a resistor 210, a switch 212, a resistor 214, and a switch 216. The switched resistor circuit 202 is an implementation of the low-impedance compensation path of the serial bus buffer circuit 104. The switched resistor circuit 202 includes a resistor 218, a switch 220, and a switch 222. The switches 220 and 222 are closed to connect the resistor 218 to the master input / output terminal 104A and the slave input / output terminal 104B and enable a low-impedance connection between the master input / output terminal 104A and the slave input / output terminal 104B. The switches 220 and 222 are opened to isolate the master input / output terminal 104A from the slave input / output terminal 104B.

[0015] The terminal 220A of the switch 220 is coupled to the master input / output terminal 104A. The terminal 220B of the switch 220 is coupled to the terminal 218A of the resistor 218. The terminal 218B of the resistor 218 is coupled to the terminal 222B of the switch 222. The terminal 222A of the switch 222 is coupled to the slave input / output terminal 104B.

[0016] The switch control circuit 208 monitors the voltages of the master input / output terminal 104A and the slave input / output terminal 104B, and controls the switched resistor circuit 202 based on those voltages. The switch control circuit 208 includes a terminal 208A coupled to the master input / output terminal 104A and a terminal 208B coupled to the slave input / output terminal 104B. Also, the switch control circuit 208 includes a terminal 208D coupled to the control terminal 220C of the switch 220 and a terminal 208E coupled to the control terminal 222C of the switch 222. The switch control circuit 208 includes an analog circuit such as an analog comparator that compares the voltages on the master input / output terminal 104A and the slave input / output terminal 104B with the logic low voltage (e.g., 30% of the power supply voltage at the power supply terminal 232) of the serial bus buffer circuit 200. When the switch control circuit 208 detects a logic low voltage at the master input / output terminal 104A or the slave input / output terminal 104B, the switch control circuit 208 closes the switch 220 and the switch 222 to enable a low-impedance connection between the master input / output terminal 104A and the slave input / output terminal 104B.

[0017] Also, the switch control circuit 208 includes an analog circuit such as an analog comparator that compares the voltages on the master input / output terminal 104A and the slave input / output terminal 104B with a predetermined voltage (e.g., 700 millivolts (mv)), and includes a slew rate detection circuit that measures the slew rate of the voltages at the master input / output terminal 104A and the slave input / output terminal 104B. When the voltage at the master input / output terminal 104A and the voltage at the slave input / output terminal 104B exceed the predetermined voltage and the slew rate of the voltage at the master input / output terminal 104A and the voltage at the slave input / output terminal 104B exceeds a predetermined slew rate (e.g., 1.2 volts per microsecond), the switch control circuit 208 opens the switches 220 and 222 to disable the low-impedance connection between the master input / output terminal 104A and the slave input / output terminal 104B.

[0018] Also, the switch control circuit 208 includes a digital circuit such as a state machine circuit that controls (opens and closes as described above) the switches 220 and 222 based on the output of the analog circuit elements and the current states of the switches 220 and 222.

[0019] The drive circuit 204 includes an amplifier 224 and a transistor 226. The transistor 226 is an N-channel metal-oxide-semiconductor field-effect transistor in some implementations of the drive circuit 204. The non-inverting input terminal 224A of the amplifier 224 is coupled to the master input / output terminal 104A, and the inverting input terminal 224B of the amplifier 224 is coupled to the slave input / output terminal 104B. The output terminal 224C of the amplifier 224 is coupled to the gate terminal 226G of the transistor 226. The source terminal 226S of the transistor 226 is coupled to the ground terminal 234. The drain terminal 226D of the transistor 226 is coupled to the master input / output terminal 104A. The amplifier 224 turns on the transistor 226 to pull down the master input / output terminal 104A when the voltage at the master input / output terminal 104A is greater than the voltage at the slave input / output terminal 104B.

[0020] The drive circuit 206 includes an amplifier 228 and a transistor 230. The transistor 230 is an N-channel MOSFET in some implementations of the drive circuit 206. The non-inverting input terminal 228A of the amplifier 228 is coupled to the slave input / output terminal 104B, and the inverting input terminal 228B of the amplifier 228 is coupled to the master input / output terminal 104A. The output terminal 228C of the amplifier 228 is coupled to the gate terminal 230G of the transistor 230. The source terminal 230S of the transistor 230 is coupled to the ground terminal 234. The drain terminal 230D of the transistor 230 is coupled to the slave input / output terminal 104B. The amplifier 228 turns on the transistor 230 to pull down the slave input / output terminal 104B when the voltage at the slave input / output terminal 104B is higher than the voltage at the master input / output terminal 104A.

[0021] The switch 212 couples the resistor 210 to the master input / output terminal 104A to pull up the master input / output terminal 104A under the control of the switch control circuit 208. The resistor 210 includes a terminal 210A coupled to the power supply terminal 232 and a terminal 210B coupled to the terminal 212A of the switch 212. The terminal 212B of the switch 212 is coupled to the master input / output terminal 104A, and the control terminal 212C of the switch 212 is coupled to the terminal 208C of the switch control circuit 208. The switch control circuit 208 closes the switch 212 based on the voltage at the master input / output terminal 104A exceeding a threshold value (e.g., 30% of the voltage of the power supply terminal 232) to reduce the rising time of the voltage at the master input / output terminal 104A.

[0022] Switch 216 couples resistor 214 to slave input / output terminal 104B to pull up master input / output terminal 104A under the control of switch control circuit 208. Resistor 214 includes a terminal 214A coupled to power supply terminal 232 and a terminal 214B coupled to terminal 216A of switch 216. Terminal 216B of switch 216 is coupled to slave input / output terminal 104B, and control terminal 216C of switch 216 is coupled to terminal 208F of switch control circuit 208. Switch control circuit 208 closes switch 216 based on the voltage of slave input / output terminal 104B exceeding a threshold value (e.g., 30% of the voltage of power supply terminal 232) to reduce the rise time of the voltage of slave input / output terminal 104B.

[0023] FIG. 3 shows glitches that occur at handoff in a serial bus buffer circuit without transient reduction circuit elements. Glitch 300 has a maximum amplitude of about 965 mV and an amplitude greater than about 300 mV for about 350 nanoseconds (ns).

[0024] FIG. 4 shows glitches generated at handoff by the implementation of serial bus buffer circuit 104. Glitch 400 has a maximum amplitude of less than 830 mV and an amplitude exceeding about 300 mV for less than about 140 nanoseconds (ns). Thus, serial bus buffer circuit 104 substantially reduces the amplitude and duration of transient glitches on the serial bus with respect to a serial bus buffer circuit without transient reduction circuit elements.

[0025] FIG. 5 shows a flowchart for an exemplary method 500 for reducing transients in a serial bus buffer circuit. For convenience, they are shown sequentially, but at least some of the acts shown may be performed in a different order and / or in parallel. Also, some implementations may perform only some of the acts shown. The operations of method 500 are performed by the implementation of serial bus buffer circuit 200.

[0026] In block 502, the switch control circuit 208 monitors the voltage at the master input / output terminal 104A and the voltage at the slave input / output terminal 104B.

[0027] In block 504, the switch control circuit 208 compares the voltage at the master input / output terminal 104A with a low logic level threshold (e.g., 30% of the voltage at the power supply terminal 232), and compares the voltage at the slave input / output terminal 104B with the low logic level threshold.

[0028] In block 506, if the voltage at the master input / output terminal 104A is less than the low logic level threshold, or if the voltage at the slave input / output terminal 104B is less than the low logic level threshold, the method continues in block 508. If the voltage at the master input / output terminal 104A does not fall below the low logic level threshold and the voltage at the slave input / output terminal 104B does not fall below the low logic level threshold, this method continues in block 502.

[0029] In block 508, the switch control circuit 208 enables a low impedance path between the master input / output terminal 104A and the slave input / output terminal 104B. Enabling the low impedance path includes closing switches 220 and 222. While the low impedance path is enabled, the handoff transient current decreases.

[0030] In block 510, the switch control circuit 208 monitors the voltage at the master input / output terminal 104A and the voltage at the slave input / output terminal 104B, and monitors the slew rate of the voltage at the master input / output terminal 104A and the slew rate of the voltage at the slave input / output terminal 104B.

[0031] In block 512, the switch control circuit 208 compares the voltage at the master input / output terminal 104A with a predetermined threshold (disable threshold, e.g., 700 mv), compares the voltage at the slave input / output terminal 104B with a predetermined threshold, compares the slew rate of the voltage at the master input / output terminal 104A with a threshold slew rate (e.g., 1.2 v / us), and compares the slew rate of the voltage at the slave input / output terminal 104B with the threshold slew rate.

[0032] In block 514, if the voltage at the master input / output terminal 104A is greater than a predetermined threshold, the slew rate of the voltage at the master input / output terminal 104A is greater than the threshold slew rate, the voltage at the slave input / output terminal 104B is greater than a predetermined threshold, and the slew rate of the voltage at the slave input / output terminal 104B is greater than the threshold slew rate, method 500 continues in block 516. If the voltage at the master input / output terminal 104A is not greater than the predetermined threshold, the slew rate of the voltage at the master input / output terminal 104A is less than or equal to the threshold slew rate, the voltage at the slave input / output terminal 104B is not greater than the predetermined threshold, or the slew rate of the voltage at the slave input / output terminal 104B is not greater than the threshold slew rate, method 500 continues to block 510.

[0033] In block 516, the switch control circuit 208 disables the low-impedance path between the master input / output terminal 104A and the slave input / output terminal 104B. Disabling the low-impedance path includes opening switches 220 and 222.

[0034] The term "coupled" is used throughout this specification. This term can encompass connections, communications, or signal paths that enable a functional relationship consistent with the description in this specification. For example, when device A generates a signal to control device B to perform a certain action, in a first example, device A is coupled to device B, or in a second example, when intervening component C does not substantially change the functional relationship between device A and device B, device A is coupled to device B via intervening component C such that device B is controlled by device A via the control signal generated by device A.

[0035] Within the scope of the claims of the present invention, modifications may be made to the described exemplary embodiments, and other embodiments are possible.

Claims

1. A serial bus buffer circuit, a master input / output data terminal, a slave input / output data terminal, a switched resistor circuit configured to provide a low-impedance connection between the master input / output data terminal and the slave input / output data terminal, a first switch having a first terminal coupled to the master input / output data terminal, a second terminal, and a control terminal, a first resistor having a first terminal coupled to the second terminal of the first switch and a second terminal, a second switch having a first terminal coupled to the second terminal of the first resistor, a second terminal coupled to the slave input / output data terminal, and a control terminal, including the switched resistor circuit, and a switch control circuit coupled to the master input / output data terminal, the slave input / output data terminal, the control terminal of the first switch, and the control terminal of the second switch. A serial bus buffer circuit including the above.

2. The serial bus buffer circuit according to Claim 1, further including an amplifier having a non-inverting input terminal coupled to the first terminal of the first switch, an inverting input terminal coupled to the second terminal of the second switch, and an output terminal.

3. The serial bus buffer circuit according to Claim 2, further including a transistor having a first terminal coupled to the master input / output data terminal, a second terminal coupled to a ground terminal, and a third terminal coupled to the output terminal of the amplifier.

4. The serial bus buffer circuit according to Claim 1, further including an amplifier having a non-inverting input terminal coupled to the second terminal of the second switch, an inverting input terminal coupled to the first terminal of the first switch, and an output terminal.

5. The serial bus buffer circuit according to Claim 4, further including a transistor having a first terminal coupled to the slave input / output data terminal, a second terminal coupled to a ground terminal, and a third terminal coupled to the output terminal of the amplifier.

6. The serial bus buffer circuit according to Claim 1, a second resistor having a first terminal coupled to a power supply terminal and a second terminal. A first terminal coupled to a second terminal of the second resistor, a second terminal coupled to the master input / output data terminal, and a control terminal coupled to the switch control circuit, a third switch; A serial bus buffer circuit further comprising.

7. The serial bus buffer circuit according to claim 1, A second resistor having a first terminal coupled to a power supply terminal and a second terminal; A first terminal coupled to a second terminal of the second resistor, a second terminal coupled to the slave input / output data terminal, and a control terminal coupled to the switch control circuit, a third switch; A serial bus buffer circuit further comprising.

8. A serial bus buffer circuit, A master input / output data terminal, A slave input / output data terminal, A switched resistor circuit configured to provide a low-impedance connection between the master input / output data terminal and the slave input / output data terminal, A switch control circuit coupled to the switched resistor circuit, the switch control circuit being configured to enable the low-impedance connection based on a voltage of the master input / output data terminal and a voltage of the slave input / output data terminal, A serial bus buffer circuit comprising.

9. The serial bus buffer circuit according to claim 8, The serial bus buffer circuit, wherein the switch control circuit is further configured to enable the low-impedance connection based on detection of a low logic voltage level at the master input / output data terminal or detection of a low logic voltage level at the slave input / output data terminal.

10. The serial bus buffer circuit according to claim 8, The serial bus buffer circuit, wherein the switch control circuit is further configured to disable the low-impedance connection based on detection of a first voltage exceeding a threshold at the master input / output data terminal and a second voltage exceeding the threshold at the slave input / output data terminal.

11. The serial bus buffer circuit according to claim 10, The serial bus buffer circuit is further configured such that the switch control circuit disables the low-impedance connection based on that the slew rate of the first voltage at the master input / output data terminal exceeds a predetermined slew rate and that the slew rate of the second voltage at the slave input / output data terminal exceeds the predetermined slew rate.

12. The serial bus buffer circuit according to claim 8, wherein the switched resistor circuit includes a first switch, a resistor coupled to the first switch, and a second switch coupled to the resistor, and the switch control circuit is further configured to close the first switch and the second switch to enable the low-impedance connection.

13. The serial bus buffer circuit according to claim 12, wherein the switch control circuit is further configured to open the first switch and the second switch to disable the low-impedance connection.

14. The serial bus buffer circuit according to claim 8, further comprising a drive circuit configured to drive the master input / output data terminal based on the voltage at the master input / output data terminal and the voltage at the slave input / output data terminal.

15. The serial bus buffer circuit according to claim 8, further comprising a drive circuit configured to drive the slave input / output data terminal based on the voltage at the master input / output data terminal and the voltage at the slave input / output data terminal.

16. A method comprising: monitoring a first voltage at a master input / output terminal of a serial bus buffer circuit; monitoring a second voltage at a slave input / output terminal of the serial bus buffer circuit; comparing the first voltage and the second voltage with a low logic level threshold; enabling a low-impedance connection between the master input / output terminal and the slave input / output terminal in response to the first voltage and the second voltage being below the low logic level threshold; comparing the first voltage and the second voltage with a disable threshold; disabling the low-impedance connection between the master input / output terminal and the slave input / output terminal in response to the first voltage and the second voltage exceeding the disable threshold; monitoring the slew rate of the first voltage; monitoring the slew rate of the second voltage; comparing the slew rate of the first voltage and the slew rate of the second voltage with a threshold slew rate; disabling the low-impedance connection between the master input / output terminal and the slave input / output terminal in response to the slew rate of the first voltage and the slew rate of the second voltage exceeding the threshold slew rate; A method comprising the above. **Claim 17** The method according to claim 16, wherein said enabling comprises closing a first switch to connect a resistor to the master input / output terminal; closing a second switch to connect the resistor to the slave input / output terminal; A method comprising the above. **Claim 18** The method according to claim 16, wherein said disabling comprises opening a first switch to disconnect a resistor from the master input / output terminal; opening a second switch to disconnect the resistor from the slave input / output terminal; A method comprising the above.

Images