Semiconductor device

Abstract

To improve the reliability of a semiconductor device.SOLUTION: A plurality of trenches TR1 are formed in a cell region, and a trench TR2 is formed in a peripheral region. A plurality of gate electrodes GE and a plurality of field plate electrodes FP1 are respectively formed inside the plurality of trenches TR1, and a field plate electrode FP2 is formed inside the trench TR2. For example, in a drift region formed in the peripheral region OR, a p-type column region PC is formed in a portion sandwiched in the Y direction by the trench TR2 and the portion between two trenches TR1 adjacent to each other among the plurality of trenches TR1.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device having a gate electrode inside a trench and a method for manufacturing the same.

Background Art

[0002] In semiconductor devices including semiconductor elements such as power MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), various structures are used to improve the breakdown voltage of the outer peripheral region. As such a structure, for example, a structure in which a trench gate electrically connected to a source wiring is disposed in the outer peripheral region, or a structure in which a p-type impurity region is disposed in the outer peripheral region is applied.

[0003] For example, Patent Document 1 discloses a multi-trench super-junction structure in which a pair of trench gates are provided in one unit cell. In the outer peripheral region surrounding each unit cell, a plurality of p-type impurity regions are arranged in a dot shape so that a region where the extension of the depletion layer becomes incomplete does not occur.

[0004] Patent Document 2 discloses a power MOSFET in which two electrodes are formed inside a trench. A dummy gate electrode electrically connected to a source wiring is provided below the trench, and a gate electrode electrically connected to a gate wiring is provided above the trench. In the outer peripheral region surrounding each power MOSFET, a p-type impurity region is arranged in a ring shape.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0006] In a structure in which trench gates electrically connected to source wirings are arranged in an outer peripheral region, it is necessary to consider the distance between the trench gates in the outer peripheral region and the trench gates in the cell region. At turn-off, the periphery of each trench gate is depleted. However, if the above distance is too wide, there is a risk that a portion where the depletion is not sufficient may occur locally, and the breakdown voltage assumed may not be maintained. On the other hand, if the above distance is set too narrow in order to perform sufficient depletion, it becomes easy to cause resolution failure in the exposure process, and there is a risk that the trench gates in the outer peripheral region and the trench gates in the cell region may be connected.

[0007] The main object of the present application is to provide a technique capable of sufficiently depleting the outer peripheral region without narrowing the distance between the trench gate in the outer peripheral region and the trench gate in the cell region more than necessary, thereby improving the reliability of the semiconductor device.

[0008] Other problems and novel features will become apparent from the description of this specification and the attached drawings.

Means for Solving the Problems

[0009] Among the embodiments disclosed in the present application, the outline of typical ones will be briefly described as follows.

[0010] A semiconductor device according to an embodiment includes a cell region in which a plurality of MOSFETs are formed, and an outer peripheral region surrounding the cell region in a plan view. The semiconductor device also includes a semiconductor substrate having a drift region of a first conductivity type, a body region of a second conductivity type, which is formed in the drift regions of the cell region and the outer peripheral region and is opposite to the first conductivity type, a source region of the first conductivity type, which is formed in the body region of the cell region, a plurality of first trenches, which are formed in the drift region of the cell region such that their bottoms reach a position deeper than the body region, a second trench, which is formed in the drift region of the outer peripheral region such that its bottom reaches a position deeper than the body region, a plurality of gate electrodes, which are formed in the plurality of first trenches via a gate insulating film respectively, and a second electrode, which is formed in the second trench via a second insulating film. Here, the plurality of first trenches extend in a first direction in a plan view, the second trench extends in a second direction that intersects at least the first direction in a plan view, and in the drift region of the outer peripheral region, a column region of the second conductivity type is formed at a position sandwiched in the first direction by a portion between two adjacent first trenches among the plurality of first trenches and the second trench, and the column region is formed to a position deeper than the body region.

[0011] A semiconductor device according to an embodiment includes a cell region in which a plurality of MOSFETs are formed, and an outer peripheral region surrounding the cell region in a plan view. The semiconductor device also includes a semiconductor substrate having a drift region of a first conductivity type, a body region of a second conductivity type formed in the drift regions of the cell region and the outer peripheral region and opposite to the first conductivity type, a source region of the first conductivity type formed in the body region of the cell region, a plurality of first trenches formed in the drift region of the cell region such that their bottoms reach a position deeper than the body region, a second trench formed in the drift region of the outer peripheral region such that its bottom reaches a position deeper than the body region, a plurality of gate electrodes formed in each of the plurality of first trenches via a gate insulating film, and a second electrode formed in the second trench via a second insulating film. Here, the plurality of first trenches extend in a first direction in a plan view, the second trench extends in a second direction intersecting at least the first direction in a plan view, and the second trench has a plurality of protruding portions protruding in the first direction toward a location between each of the plurality of first trenches.

Effect of the Invention

[0012] According to one embodiment, the reliability of the semiconductor device can be ensured.

Brief Description of the Drawings

[0013]

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Embodiments for Carrying Out the Invention

[0014] Hereinafter, embodiments will be described in detail with reference to the drawings. In all the drawings for explaining the embodiments, members having the same function are denoted by the same reference numerals, and repeated explanations thereof are omitted. Further, in the following embodiments, explanations of the same or similar parts are not repeated in principle unless particularly necessary.

[0015] In addition, the X direction, Y direction, and Z direction described in the present application intersect and are orthogonal to each other. In the present application, the Z direction is described as the vertical direction, height direction, or thickness direction of a certain structure. Further, expressions such as "plan view" or "plan view" used in the present application mean that the plane constituted by the X direction and the Y direction is the "plane", and this "plane" is viewed from the Z direction.

[0016] (Embodiment 1) <Structure of Semiconductor Device> FIGS. 1 and 2 are plan views of a semiconductor chip which is a semiconductor device 100. FIG. 1 mainly shows wirings formed on a semiconductor substrate SUB, and FIG. 2 shows a structure below the above wirings and shows the structure of a trench gate formed inside the semiconductor substrate SUB.

[0017] As shown in FIG. 1, most of the semiconductor device 100 is covered with a source wiring SW, and a gate wiring GW is formed on the outer periphery of the source wiring SW. Although not shown here, the source wiring SW and the gate wiring GW are covered with a protective film. An opening is provided in a part of the protective film, and the source wiring SW and the gate wiring GW exposed at the opening become a source pad and a gate pad. By connecting external connection terminals such as wire bonding or clips (copper plates) on the source pad and the gate pad, the semiconductor device 100 is electrically connected to other semiconductor chips or wiring boards.

[0018] In addition, the semiconductor device 100 includes a cell region CR and an outer peripheral region OR surrounding the cell region CR in plan view. The cell region CR is a region where main semiconductor elements such as a plurality of power MOSFETs are formed.

[0019] As shown in FIG. 2, in the cell region CR, a plurality of gate electrodes GE extend in the Y direction. In the outer peripheral region OR, a field plate electrode FP2 extending in the X and Y directions is provided so as to surround the plurality of gate electrodes GE. Here, the case where two field plate electrodes FP2 are provided in the outer peripheral region OR is exemplified, but the number of the field plate electrodes FP2 may be at least one or three or more.

[0020] FIG. 3 is a plan view corresponding to the portion surrounded by the broken line shown in FIGS. 1 and 2. FIGS. 4 to 6 are cross-sectional views taken along lines A-A, B-B, and C-C shown in FIG. 4, respectively.

[0021] First, the structure of the power MOSFET formed in the cell region CR will be described with reference to FIGS. 3 and 4.

[0022] The semiconductor substrate SUB is made of, for example, n-type silicon and has an n-type drift region NV. A p-type body region PB is formed in the drift region NV. An n-type source region NS is formed in the body region PB. The source region NS has a higher impurity concentration than the drift region NV.

[0023] In the drift region NV, a plurality of trenches TR1 are formed such that their bottoms reach a position deeper than the body region PB. The plurality of trenches TR extend in the Y direction and are adjacent to each other in the X direction.

[0024] Inside each of the plurality of trenches TR1, a plurality of gate electrodes GE are formed via gate insulating films GF, respectively. Also, inside the plurality of trenches TR1, and below the gate insulating films GF and the plurality of gate electrodes GE, a plurality of field plate electrodes FP1 are formed via insulating films IF1, respectively. The gate insulating films GF and the insulating films IF1 are, for example, silicon oxide films. The gate electrodes GE and the field plate electrodes FP1 are, for example, n-type polycrystalline silicon films. Also, the thickness of the insulating film IF1 is thicker than the thickness of the gate insulating film GF.

[0025] Note that the gate insulating film GF is also formed on the semiconductor substrate SUB outside the plurality of trenches TR1, but this gate insulating film GF may be left as it is or removed.

[0026] Next, the structure of the outer peripheral region OR will be described with reference to FIGS. 3, 5, and 6.

[0027] The body region PB is also formed in the drift region NV of the outer peripheral region OR. Trenches TR2 are formed in the drift region NV of the outer peripheral region OR such that their bottoms reach a position deeper than the body region PB. The trenches TR2 extend in the X direction and the Y direction so as to surround the plurality of trenches TR1.

[0028] Inside the trenches TR2, field plate electrodes FP2 are formed via insulating films IF2. The insulating films IF2 are films of the same layer as the insulating films IF1 and are, for example, silicon oxide films. The field plate electrodes FP2 are conductive films of the same layer as the field plate electrodes FP1 and are, for example, n-type polycrystalline silicon films. Also, in the present embodiment, as shown in FIG. 6, the bottom of the field plate electrode FP2 reaches the same position as the bottom of the field plate electrode FP1. Also, the bottom of the insulating film IF2 reaches the same position as the bottom of the insulating film IF1. That is, the thickness of the field plate electrode FP2 is the same as the sum of the thickness of the gate electrode GE, the thickness of the gate insulating film GF, and the thickness of the field plate electrode FP1.

[0029] Further, in the drift region NV of the outer peripheral region OR, a p-type column region PC is formed. The column region PC is formed to a position deeper than the body region PB. The impurity concentration of the column region PC is equal to or higher than the impurity concentration of the body region PB. The main feature of Embodiment 1 relates to the column region PC, and the detailed effects of the column region PC will be described in detail later.

[0030] As shown in FIGS. 4 to 6, an n-type drain region ND and a drain electrode DE are formed on the back surface of the semiconductor substrate SUB. The n-type drain region ND has an impurity concentration higher than that of the drift region NV. The drain electrode DE is composed of, for example, a single-layer metal film such as an aluminum film, a titanium film, a nickel film, a gold film or a silver film, or a laminated film in which these metal films are laminated as appropriate.

[0031] An interlayer insulating film IL is formed on the semiconductor substrate SUB so as to cover the gate electrode GE and the field plate electrode FP2. The interlayer insulating film IL is, for example, a silicon oxide film. A plurality of holes CH1 are formed in the interlayer insulating film IL in the cell region CR. The plurality of holes CH1 penetrate the interlayer insulating film IL and the source region NS so that their bottoms are located in the body region PB. In the body region PB at the bottom of each of the plurality of holes CH1, a high-concentration region PR having an impurity concentration higher than that of the body region PB is formed. Further, a plurality of holes CH2 are also formed in the interlayer insulating film IL in the outer peripheral region OR. The hole CH2 is formed above the gate electrode GE.

[0032] A source wiring SW is formed on the interlayer insulating film IL so as to fill the inside of the hole CH1. The source wiring SW is electrically connected to the source region NS, the body region PB, and the high-concentration region PR, and supplies a source potential to these. Also, a gate wiring GW is formed on the interlayer insulating film IL so as to fill the inside of the hole CH2. The gate wiring GW is electrically connected to the gate electrode GE. A gate potential is applied to the gate electrode GE from the gate wiring GW.

[0033] Although not shown here, other holes are also formed in the interlayer insulating film IL, and through these other holes, the field plate electrodes FP1 and FP2 are also electrically connected to the source wiring SW.

[0034] Further, the source wiring SW and the gate wiring GW are composed of, for example, a barrier metal film and a conductive film formed on the barrier metal film. The barrier metal film is, for example, a titanium nitride film, and the conductive film is, for example, an aluminum film.

[0035] Note that the source wiring SW and the gate wiring GW may be composed of a plug layer that fills the inside of the hole CH1 or the hole CH2, and the barrier metal film and the conductive film formed on the interlayer insulating film IL. In that case, the plug layer is composed of a barrier metal film such as a titanium nitride film and a conductive film such as a tungsten film.

[0036] <Matters Studied by the Inventors of the Present Application and Main Features of Embodiment 1> Hereinafter, with reference to FIGS. 7 to 10, first, a semiconductor device of an examination example studied by the inventors of the present application and its problems will be described, and then the main features of Embodiment 1 will be described. The semiconductor device of the examination example is the same as the semiconductor device 100 of Embodiment 1 except that the column region PC is not provided.

[0037] As shown in FIGS. 7 to 9, in the examination example, at the time of turn-off, the depletion layer 10 spreads overall from the cell region CR to the outer peripheral region OR. For this reason, the breakdown voltage of the semiconductor device 100 is maintained. However, since the depletion layer 10 spreads around the field plate electrodes FP1 and FP2, partial depletion occurs at locations away from the field plate electrodes FP1 and FP2, but complete depletion becomes difficult. In FIGS. 7 to 9, the location where complete depletion has occurred is shown as the complete depletion region 10A, and the location where partial depletion has occurred is shown as the partial depletion region 10B.

[0038] In order to achieve sufficient depletion, for example, it is conceivable to bring trench TR2 closer to the end of each trench TR1 to narrow the distance between trench TR1 and trench TR2. However, in that case, if the distance is set to a narrow distance such as 0.25 μm or less, for example, defective resolution in the exposure process is likely to occur, and there is a risk that trench TR1 and trench TR2 will be connected.

[0039] As can be seen by comparing FIGS. 9 and 10, in Embodiment 1, a p-type column region PC is provided in a location where the spread of the depletion layer 10 is insufficient (partial depletion region 10B). For example, as shown in FIGS. 3 and 5, a certain column region PC is formed in a location sandwiched in the Y direction by a location between two adjacent trenches TR among a plurality of trenches TR1 and trench TR2 in the drift region NV of the outer peripheral region OR. And this column region PC is formed at a position away from trench TR2 in the Y direction.

[0040] Since the column region PC is electrically connected to the source wiring SW via the body region PB, the source potential is also supplied to the column region PC. And the column region PC is formed to a position deeper than the body region PB. By this column region PC, a location where partial depletion has occurred can be completely depleted. Therefore, the breakdown voltage in the outer peripheral region OR of the semiconductor device 100 can be improved, and thus the reliability of the semiconductor device 100 can be improved.

[0041] Also, the column region PC is formed not in the cell region CR where the power MOSFET is configured, but in the outer peripheral region OR closer to trench TR2 than the end of trench TR1. For this reason, the column region PC does not cause an increase in on-resistance.

[0042] Also, as shown in FIG. 7, there are also portions near the corner where the trench TR2 extending in the X direction and the trench TR2 extending in the Y direction intersect that are prone to partial depletion. It is preferable to provide the column region PC also in such portions. That is, the column region PC is located between the trench TR1 closest to the trench TR2 extending in the Y direction among the plurality of trenches TR1 and the trench TR2 extending in the Y direction, and also in the drift region NV of the outer peripheral region OR located in the portion sandwiched in the Y direction by the trench TR2 extending in the X direction. And this column region PC is formed at positions away from the trench TR2 in each of the X direction and the Y direction. Thereby, the breakdown voltage in the outer peripheral region OR of the semiconductor device 100 can be improved.

[0043] Note that it is also conceivable to form the column region PC along the trench TR2 over the entire outer peripheral region OR. However, in that case, the column region PC would also be formed in portions that are originally prone to depletion. Then, in that portion, the depletion layer would spread completely at a low voltage, and if the voltage is further increased, there is a risk of breakdown due to electric field concentration. Therefore, as in Embodiment 1, it is preferable that each mutually separated column region PC is locally provided in the outer peripheral region OR.

[0044] <Method of manufacturing a semiconductor device> Hereinafter, with reference to FIGS. 11 to 20, a method of manufacturing the semiconductor device 100 will be described. In the following description, mainly a cross-sectional view taken along the line A-A of FIG. 3 will be used, but a cross-sectional view taken along the line B-B of FIG. 3 will also be used as necessary.

[0045] First, as shown in FIGS. 11 and 12, a semiconductor substrate SUB having an n-type drift region NV is prepared. The drift region NV may be the semiconductor substrate SUB itself made of n-type silicon, or may be a semiconductor layer grown on an n-type silicon substrate while introducing phosphorus (P) by an epitaxial growth method.

[0046] Next, a plurality of trenches TR1 are formed in the drift region NV of the cell region CR, and a trench TR2 is formed in the drift region NV of the outer peripheral region OR. To form the trenches TR1 and TR2, first, a silicon oxide film, for example, is formed on the semiconductor substrate SUB by, for example, the CVD method. Next, a resist pattern having an opening is formed on the silicon oxide film by photolithography. Next, a dry etching process is performed on the silicon oxide film and the drift region NV exposed from the opening using the resist pattern as a mask, thereby forming the trenches TR1 and TR2 in the drift region NV. Thereafter, the resist pattern is removed by an ashing process, and the silicon oxide film is removed by a wet etching process using, for example, hydrofluoric acid.

[0047] Next, as shown in FIG. 13, an insulating film IF1 made of, for example, a silicon oxide film is formed inside the plurality of trenches TR1 by, for example, thermal oxidation. Next, a conductive film CF made of, for example, an n-type polycrystalline silicon film is formed on the insulating film IF1 so as to fill the inside of the plurality of trenches TR1. Note that an insulating film IF1 and a conductive film CF are also formed inside the trench TR2 in the outer peripheral region OR by the same process.

[0048] Next, as shown in FIGS. 14 and 15, the conductive film CF and the insulating film IF1 formed outside the plurality of trenches TR1 and the trench TR2 are sequentially removed by, for example, dry etching and wet etching. In this way, a field plate electrode FP2 is formed inside the trench TR2 via an insulating film IF2, and a plurality of field plate electrodes FP1 are formed inside the plurality of trenches TR1 via the insulating film IF1, respectively. Here, for easy understanding of the configuration, the insulating film IF1 remaining inside the trench TR2 is described as the insulating film IF2.

[0049] Next, a resist pattern is formed to cover the outer peripheral region OR and open the cell region CR, and dry etching treatment and wet etching treatment are performed using the resist pattern as a mask. As a result, as shown in FIG. 15, inside the plurality of trenches TR1, the insulating film IF1 and the plurality of field plate electrodes FP1 are selectively recessed.

[0050] Next, as shown in FIG. 16, inside the plurality of trenches TR1, a gate insulating film GF made of, for example, a silicon oxide film is formed by, for example, thermal oxidation. Next, an n-type polycrystalline silicon film is formed on the gate insulating film GF by, for example, CVD method so as to fill the inside of the plurality of trenches TR1. Next, the polycrystalline silicon film formed outside the plurality of trenches TR1 is removed by, for example, dry etching treatment.

[0051] As a result, a plurality of gate electrodes GE are formed inside the plurality of trenches TR1 via the gate insulating film GF, respectively. The gate insulating film GF and the gate electrode GE are formed above the insulating film IF1 and the field plate electrode FP1. Thereafter, the gate insulating film GF formed outside the trench TR1 may be removed by wet etching treatment or the like.

[0052] Next, as shown in FIGS. 17 and 18, a p-type body region PB is formed by introducing, for example, boron (B) into the cell region CR and the drift region NV of the outer peripheral region OR by photolithography and ion implantation. Next, an n-type source region NS is formed by introducing, for example, arsenic (As) into the body region PB of the cell region CR by photolithography and ion implantation. Next, a p-type column region PC is formed by introducing, for example, arsenic (As) into the drift region NV of the outer peripheral region OR by photolithography and ion implantation.

[0053] Note that, as shown in FIG. 18, the column region PC is formed to a position deeper than the body region PB. Also, the impurity concentration of the column region PC may be the same as that of the body region PB, or may be higher than that of the body region PB. Further, as shown in FIGS. 3 and 5, the column region PC is formed in the drift region NV of the outer peripheral region OR located at a position sandwiched in the Y direction by the trenches TR2 and at a position between each of the plurality of trenches TR1.

[0054] Next, as shown in FIG. 19, an interlayer insulating film IL made of, for example, a silicon oxide film is formed on the semiconductor substrate SUB by, for example, the CVD method so as to cover the plurality of gate electrodes GE and the field plate electrode FP2.

[0055] Next, as shown in FIG. 20, a hole CH1 penetrating the interlayer insulating film IL and the source region NS in the cell region CR is formed by photolithography and dry etching processes. Note that, in the process of forming the hole CH1, a hole CH2 is also formed in the interlayer insulating film IL in the outer peripheral region OR. The bottom of the hole CH1 is located within the body region PB. Next, for example, boron (B) is introduced into the body region PB at the bottom of the hole CH1 by photolithography and ion implantation methods, thereby forming a p-type high concentration region PR.

[0056] Next, as shown in FIG. 21, a source wiring SW is formed on the interlayer insulating film IL. First, in order to fill the inside of the hole CH1, a laminated film of a barrier metal film made of, for example, a titanium nitride film and a conductive film made of, for example, an aluminum film is formed on the interlayer insulating film IL by a sputtering method or a CVD method. Next, the source wiring SW is formed by patterning the laminated film. Although not shown here, a gate wiring GW is also formed on the interlayer insulating film IL so as to fill the inside of the hole CH2 by the same process as the process of forming the source wiring SW. Next, a protective film made of, for example, a polyimide film is formed on the source wiring SW and the gate wiring GW by, for example, a coating method. Thereafter, although not shown, a part of the protective film is opened to expose regions that will become source pads and gate pads on the source wiring SW and the gate wiring GW.

[0057] Thereafter, through the following processes, the semiconductor device 100 is manufactured. First, the back surface of the semiconductor substrate SUB is polished as necessary. Next, an n-type drain region ND is formed by introducing, for example, arsenic (As) or the like into the back surface of the semiconductor substrate SUB by an ion implantation method. Next, a drain electrode DE is formed on the drain region ND by a sputtering method. Thus, the structures shown in FIGS. 3 to 5 are obtained.

[0058] (Embodiment 2) Hereinafter, the semiconductor device 100 in Embodiment 2 will be described with reference to FIG. 22. In the following description, the differences from Embodiment 1 will be mainly described, and the description of the points overlapping with Embodiment 1 will be omitted.

[0059] In Embodiment 1, a p-type column region PC was provided at a location where the spread of the depletion layer 10 was not sufficient, but in Embodiment 2, the column region PC is not provided. Instead, in Embodiment 2, as shown in FIG. 22, the trench TR2 extending in the X direction has a plurality of protrusions 20. The plurality of protrusions 20 protrude in the Y direction toward the locations between each of the plurality of trenches TR1.

[0060] Inside the protrusion 20, a field plate electrode FP2 electrically connected to the source wiring SW is also formed. Therefore, the protrusion 20 can completely deplete a portion that was partially depleted. Also in Embodiment 2, since the breakdown voltage in the outer peripheral region OR of the semiconductor device 100 can be improved, the reliability of the semiconductor device 100 can be improved.

[0061] Also in Embodiment 2, at the corner where the trench TR2 extending in the X direction and the trench TR2 extending in the Y direction intersect, there is a portion where partial depletion is likely to occur. It is preferable to provide the protrusion 20 also at such a portion. That is, one of the plurality of protrusions 20 protrudes in the Y direction toward a portion between the trench TR1 closest to the trench TR2 extending in the Y direction among the plurality of trenches TR1 and the trench TR2 extending in the Y direction.

[0062] Also, the width of each of the plurality of protrusions 20 in the X direction becomes narrower as it goes toward the portion between each of the plurality of trenches TR. By processing the protrusion 20 into such a shape, when forming the trench TR1 and the trench TR2, it becomes easier to bring the trench TR2 closer to the trench R1 while suppressing the possibility of the trench TR1 and the trench TR2 being connected.

[0063] Note that the manufacturing method of Embodiment 2 is substantially the same as the manufacturing method of Embodiment 1. The protrusion 20 can be formed simply by changing the mask for forming the trench TR2 to a mask with another layout shape. Therefore, since it is not necessary to form the column region PC of Embodiment 1, the manufacturing process can be simplified.

[0064] (Modification 1) Hereinafter, Modification 1 of Embodiment 2 will be described with reference to FIG. 23.

[0065] In Embodiment 2, the protruding portion 20 had a shape that gradually narrowed. In Modification 1, as shown in FIG. 23, not only the protruding portion 20 but also the end portion 30 of the trench TR1 has a shape that gradually narrows. That is, the width of each end portion 30 of the plurality of trenches TR1 in the X direction becomes narrower as it approaches the trench TR2. And the plurality of protruding portions 20 and the end portions 30 of each of the plurality of trenches TR1 are alternately adjacent to each other.

[0066] By processing the end portion 30 into such a shape, it becomes easier to bring the trench TR2 closer to the trench R1 than in Embodiment 2. Therefore, the breakdown voltage in the outer peripheral region OR of the semiconductor device 100 can be further improved.

[0067] (Modification 2) Hereinafter, Modification 2 of Embodiment 1 will be described with reference to FIG. 24.

[0068] In Embodiment 1, the plurality of trenches TR1 each extended in the Y direction and had a stripe shape. In Modification 2, there are portions where the plurality of trenches TR1 extend in the X direction, and the plurality of trenches TR1 are connected to each other and form a mesh shape. Also in Modification 2, the breakdown voltage in the outer peripheral region OR of the semiconductor device 100 can be improved.

[0069] Note that the mesh-shaped plurality of trenches TR1 disclosed in Modification 2 can also be applied to Embodiment 2 or Modification 1.

[0070] Although the present invention has been specifically described based on the above embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the gist thereof.

Explanation of Reference Numerals

[0071] 10 depletion layer 10A fully depleted region 10B partially depleted region 20 protruding portion 30 end portion 100 Semiconductor device CF Conductive film CH Hole CR Cell region DE Drain electrode FP1, FP2 Electrodes (Field plate electrodes) GE Gate electrode GF Gate insulating film GW Gate wiring IF1, IF2 Insulating films IL Interlayer insulating film ND Drain region NS Source region NV Drift region OR Peripheral region PB Body region PC Column region PR High-concentration region SUB Semiconductor substrate SW Source wiring TR1, TR2 Trenches

Claims

1. A semiconductor device having a cell region in which a plurality of MOSFETs are formed and an outer peripheral region surrounding the cell region in a plan view, a semiconductor substrate having a drift region of a first conductivity type, a body region of a second conductivity type, which is formed in the drift regions of the cell region and the outer peripheral region and is opposite to the first conductivity type, a source region of the first conductivity type, which is formed in the body region of the cell region, a plurality of first trenches, which are formed in the drift region of the cell region such that their bottoms reach a position deeper than the body region, a second trench, which is formed in the drift region of the outer peripheral region such that its bottom reaches a position deeper than the body region, a plurality of gate electrodes, which are respectively formed inside the plurality of first trenches via a gate insulating film, a second electrode, which is formed inside the second trench via a second insulating film, comprising: each of the plurality of first trenches extends in a first direction in a plan view and is adjacent to each other in a second direction intersecting the first direction in a plan view, the second trench extends at least in the second direction in a plan view, in the drift region of the outer peripheral region, a plurality of column regions of the second conductivity type are respectively formed at a plurality of positions each located between the plurality of first trenches and at a plurality of positions sandwiched in the first direction by the second trench, each of the plurality of column regions is formed to a position deeper than the body region, is formed at a position away from the second trench in the first direction, and is separated from each other in the second direction. A semiconductor device.

2. In the semiconductor device according to claim 1, an interlayer insulating film formed on the semiconductor substrate so as to cover the plurality of gate electrodes and the second electrode, gate wirings and source wirings formed on the interlayer insulating film, further comprising: the plurality of gate electrodes are electrically connected to the gate wirings, the plurality of column regions, the body region, the source region and the second electrode are electrically connected to the source wirings. A semiconductor device.

3. In the semiconductor device according to claim 2, inside the plurality of first trenches and below the gate insulating film and the plurality of gate electrodes, a plurality of first electrodes are respectively formed via a first insulating film, A semiconductor device, wherein the plurality of first electrodes are electrically connected to the source wiring.

4. In the semiconductor device according to claim 1, A semiconductor device, wherein the impurity concentration in each of the plurality of column regions is equal to or higher than the impurity concentration in the body region.

5. In the semiconductor device according to claim 1, The second trench extends also in the first direction, A semiconductor device, wherein the column region is located between the first trench closest to the second trench extending in the first direction among the plurality of first trenches and the second trench extending in the first direction, and is also formed in the drift region of the outer peripheral region located at a position sandwiched in the first direction by the second trench extending in the second direction.

6. A semiconductor device having a cell region in which a plurality of MOSFETs are formed and an outer peripheral region surrounding the cell region in a plan view, A semiconductor substrate having a drift region of a first conductivity type, A body region of a second conductivity type, which is formed in the drift regions of the cell region and the outer peripheral region and is opposite to the first conductivity type, A source region of the first conductivity type formed in the body region of the cell region, A plurality of first trenches formed in the drift region of the cell region such that their bottoms reach a position deeper than the body region, A second trench formed in the drift region of the outer peripheral region such that its bottom reaches a position deeper than the body region, A plurality of gate electrodes formed inside the plurality of first trenches via a gate insulating film, respectively, A second electrode formed inside the second trench via a second insulating film, Comprising: The plurality of first trenches extend in a first direction in a plan view, The second trench extends in a second direction that intersects at least the first direction in a plan view, The second trench has a plurality of protrusions protruding in the first direction respectively toward a location between each of the plurality of first trenches, The width of each of the plurality of protrusions in the second direction becomes narrower as it goes toward the location between each of the plurality of first trenches, A semiconductor device, wherein the width of each end of the plurality of first trenches in the second direction becomes narrower as it goes toward the second trench.

7. In the semiconductor device according to claim 6, An interlayer insulating film formed on the semiconductor substrate so as to cover the plurality of gate electrodes and the second electrode; A gate wiring and a source wiring formed on the interlayer insulating film; Further comprising: The plurality of gate electrodes are electrically connected to the gate wiring; A semiconductor device in which the body region, the source region, and the second electrode are electrically connected to the source wiring.

8. In the semiconductor device according to claim 7, Inside the plurality of first trenches and below the gate insulating film and the plurality of gate electrodes, a plurality of first electrodes are formed via first insulating films, respectively; A semiconductor device in which the plurality of first electrodes are electrically connected to the source wiring.

9. In the semiconductor device according to claim 6, The second trench also extends in the first direction; One of the plurality of protrusions protrudes in the first direction toward a location between the first trench that extends in the first direction and is closest to the second trench that extends in the first direction among the plurality of first trenches and the second trench that extends in the first direction. A semiconductor device.

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