Method for manufacturing semiconductor ultra-thin mounting structure

Abstract

A method for manufacturing a semiconductor ultra-thin stack structure includes the steps of: forming a stop layer structure in a semiconductor substrate by ion implantation, and providing an electric element and an internal connection layer on the active surface of the semiconductor substrate to form a semiconductor wafer; facing and bonding the internal connection layers of two semiconductor wafers one above the other; removing a part of the semiconductor substrate and the stop layer structure of the upper semiconductor wafer from the back surface of the upper semiconductor wafer in a back grinding and thinning process, so that the upper semiconductor wafer forms a thinned semiconductor wafer; then, bonding, back grinding and thinning processes are performed on each of the thinned semiconductor wafers, and another thinned semiconductor wafer is stacked one above the other; and finally, back grinding and thinning processes are performed on the bottom semiconductor wafer. This manufacturing method can stack multiple thinned semiconductor wafers to meet the requirement of high integration.

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a semiconductor structure, and particularly to a method for manufacturing a semiconductor ultra-thin stacked structure.

Background Art

[0002] With the booming development of the electronics industry, electronic products have gradually entered the research and development direction of multi-function and high performance. Among them, semiconductor science and technology has been widely applied to the manufacturing of chip sets such as memory and central processing units. In order to achieve goals such as high integration (Integration) and high speed, the dimensions of semiconductor integrated circuits have been continuously reduced. Currently, in order to achieve the above integration and speed requirements, multiple different materials and technologies have been developed. In order to improve the operating speed of the circuit, stacked structures including multiple substrates have also been studied. When the related technology of semiconductor planar packaging reaches its limit, miniaturization requirements can be met by integration, and wafer stacking technology will provide great assistance to future science and technology and is also an extremely improved goal in the current related fields.

Summary of the Invention

Problems to be Solved by the Invention

[0003] The present invention provides a method for manufacturing a semiconductor ultra-thin stacked structure, in which the semiconductor ultra-thin stacked structure can meet the requirements of high integration and speed and has better electrical characteristics and efficiency.

Means for Solving the Problems

[0004] The manufacturing method of the semiconductor ultra-thin mounting structure according to the present invention includes steps of manufacturing a plurality of semiconductor wafers, selecting one of the semiconductor wafers as the first semiconductor wafer of the bottom layer, and using some of the semiconductor wafers as the second semiconductor wafer and the third semiconductor wafer to be mounted. The step of manufacturing each of the semiconductor wafers includes providing a semiconductor substrate having opposing active surfaces and back surfaces, forming a stop layer structure in the semiconductor substrate, and dividing the semiconductor substrate into a first portion of the substrate and a second portion of the substrate. The first portion of the substrate is located between the stop layer structure and the active surface, and the second portion of the substrate is located between the stop layer structure and the back surface. The stop layer structure includes at least a silicon nitride layer. The manufacturing of the silicon nitride layer includes first performing a nitrogen ion implantation process at a first depth of the semiconductor substrate, and then performing a high-temperature treatment process to form a silicon nitride layer in the nitrogen ion implantation region. The step further includes installing a plurality of electrical elements and an internal connection layer including a plurality of interconnect points on the active surface, and installing a plurality of conductive structures on the first portion of the substrate so as to connect the internal connection layer and the stop layer structure. The step of flip-chip mounting the second semiconductor wafer on the first semiconductor wafer to oppose the internal connection layer of the first semiconductor wafer and the internal connection layer of the second semiconductor wafer and bonding them with a hybrid bonding technique. The step of performing a first back grinding process to grind from the back surface of the second semiconductor wafer to remove a part of the second portion of the substrate of the second semiconductor wafer. The step of performing a first thinning process to form a thinned second semiconductor wafer. The step of performing a second back grinding process to grind from the back surface of the first semiconductor wafer to remove a part of the second portion of the substrate of the first semiconductor wafer. The step of performing a second thinning process to form a thinned first semiconductor wafer. The first thinning process and the second thinning process include a substrate removal step of removing the remaining second portion of the substrate to expose the stop layer structure, and a stop layer removal step of removing the stop layer structure to expose the first portion of the substrate and the conductive structures.

[0005] In one embodiment of the present invention, before performing the second back grinding process, a plurality of thinned third semiconductor wafers can be sequentially stacked on the thinned second semiconductor wafer. The step of stacking each of the thinned third semiconductor wafers includes flip-chip mounting the third semiconductor wafer to the first semiconductor wafer flip chip, and facing and bonding the internal connection layer of the third semiconductor wafer to the first portion of the substrate of the thinned second semiconductor wafer; performing a third back grinding process to grind from the back surface of the third semiconductor wafer to remove a part of the second portion of the substrate of the third semiconductor wafer; and performing a third thinning process including a substrate removal step and a stop layer removal step.

[0006] In one embodiment of the present invention, the stop layer structure further includes a silicon dioxide layer disposed on the silicon nitride layer so as to be interposed between the silicon nitride layer and the active surface.

[0007] In one embodiment of the present invention, the step of forming the silicon dioxide layer includes, after the nitrogen ion implantation process, first performing an oxygen ion implantation process at a second depth of the semiconductor substrate smaller than the first depth, and then performing a high-temperature treatment process to form a silicon dioxide layer in the oxygen ion implantation region.

[0008] In one embodiment of the present invention, the stop layer removal step includes removing the silicon nitride layer and then removing the silicon dioxide layer.

[0009] In one embodiment of the present invention, the substrate removal step is selected from one of chemical mechanical polishing, wet etching, and plasma dry etching, and the selectivity ratio between silicon and silicon nitride is between 20 and 80.

[0010] In one embodiment of the present invention, the method of removing the silicon nitride layer and the silicon dioxide layer is selected from one of chemical mechanical polishing and plasma dry etching. The selectivity ratio between silicon nitride and silicon dioxide is between 10 and 20, and the selectivity ratio between silicon dioxide and silicon is about 5.

[0011] In one embodiment of the present invention, the distance between the above-mentioned stop layer structure and the active surface is between 1 micrometer and 5 micrometers, and the thickness of the thinned second semiconductor wafer is 12 micrometers or less.

[0012] In one embodiment of the present invention, after forming the thinned first semiconductor wafer, a plurality of solder balls are installed on the side of the thinned first semiconductor wafer away from the thinned second semiconductor wafer so as to be electrically connected to the conductive structure, respectively, and further includes steps of performing an electrical test and cutting.

[0013] The manufacturing method of the semiconductor ultra-thin mounting structure according to the present invention includes manufacturing a plurality of semiconductor wafers. The steps of manufacturing each semiconductor wafer include providing a semiconductor substrate having opposing active surfaces and back surfaces, forming a stop layer structure in the semiconductor substrate, and dividing the semiconductor substrate into a first portion of the substrate and a second portion of the substrate. The first portion of the substrate is located between the stop layer structure and the active surface, and the second portion of the substrate is located between the stop layer structure and the back surface. The stop layer structure includes at least a silicon nitride layer. The manufacturing of the silicon nitride layer first performs a nitrogen ion implantation process at a first depth of the semiconductor substrate and then performs a high-temperature treatment process to form the silicon nitride layer in the nitrogen ion implantation region. Installing a plurality of electrical elements and an internal connection layer including a plurality of interconnect points on the active surface, and installing a plurality of conductive structures on the first portion of the substrate so as to connect the internal connection layer and the stop layer structure. Selecting one of the semiconductor wafers as the first semiconductor wafer of the bottom layer, and cutting a part of the semiconductor wafers into the first lot of semiconductor chips to be mounted and at least one second lot of semiconductor chips. Flip-chip mounting the first lot of semiconductor chips on the first semiconductor wafer, opposing the internal connection layer of the first lot of semiconductor chips and the internal connection layer of the first semiconductor wafer, and bonding them with a hybrid bonding technique. Performing a first molding process to form a first packaging gel on the first semiconductor wafer so as to cover the first lot of semiconductor chips. Performing a first back grinding process to remove a part of the first packaging gel from the side away from the first semiconductor wafer of the first packaging gel and remove a part of the second portion of the substrate of the first lot of semiconductor chips. Performing a first thinning process to form a first semiconductor chip layer. Performing a second back grinding process to grind from the back surface of the first semiconductor wafer to remove a part of the second portion of the substrate of the first semiconductor wafer. Performing a second thinning process to form a thinned first semiconductor wafer. The first thinning process and the second thinning process are a substrate removal step of removing the remaining second portion of the substrate to expose the stop layer structure, and a step of removing the stop layer structure,including a step of exposing a first portion of the substrate and a conductive structure and a stop layer removal step.

[0014] In one embodiment of the present invention, before performing the second back grinding process, at least one second semiconductor chip layer can be sequentially stacked on the first semiconductor chip layer. The step of stacking each of the second semiconductor chip layers includes flip-chip mounting the second lot of semiconductor chips on the first semiconductor wafer, opposing and bonding the internal connection layer of the second lot of semiconductor chips and the first portion of the substrate of the first semiconductor chip layer; performing a second molding process to form a second packaging gel on the first semiconductor chip layer so as to cover the second lot of semiconductor chips; performing a third back grinding process to remove a part of the second packaging gel from the side away from the first semiconductor chip layer of the second packaging gel and remove a part of the second portion of the substrate of the second lot of semiconductor chips; and performing a third thinning process including a substrate removal step and a stop layer removal step.

[0015] The manufacturing method of the semiconductor ultra-thin mounting structure according to the present invention includes the steps of providing a carrier plate and forming a plurality of first conductive pillars on the carrier plate, and providing a plurality of semiconductor chips. The steps of manufacturing each of the semiconductor chips include providing a semiconductor substrate having opposing active surfaces and back surfaces, forming a stop layer structure in the semiconductor substrate, and dividing the semiconductor substrate into a first portion of the substrate and a second portion of the substrate. The first portion of the substrate is located between the stop layer structure and the active surface, and the second portion of the substrate is located between the stop layer structure and the back surface. The stop layer structure includes at least a silicon nitride layer. The manufacturing of the silicon nitride layer first includes performing a nitrogen ion implantation process at a first depth of the semiconductor substrate and then performing a high-temperature treatment process to form a silicon nitride layer in the nitrogen ion implantation region. Installing a plurality of electrical elements and an internal connection layer including a plurality of interconnect points on the active surface, and installing a plurality of conductive structures on the first portion of the substrate so as to connect the internal connection layer and the stop layer structure, and cutting. Selecting a first lot of semiconductor chips and at least one second lot of semiconductor chips from the semiconductor chips. The first lot of semiconductor chips includes a plurality of first semiconductor chips, and the second lot of semiconductor chips includes a plurality of second semiconductor chips. Flipping and mounting the first lot of semiconductor chips on the carrier plate so that the first conductive pillars are interposed between adjacent first semiconductor chips. The internal connection layer of the first lot of semiconductor chips is close to the carrier plate and the semiconductor substrate is away from the carrier plate. Performing a first molding process to form a first packaging gel on the carrier plate so as to cover the first lot of semiconductor chips and the first conductive pillars. Performing a first back grinding process to remove a part of the first packaging gel from the side of the first packaging gel away from the carrier plate and remove a part of the second portion of the substrate of the first lot of semiconductor chips. Performing a first thinning process to form a first semiconductor chip layer. The first thinning process includes sequentially removing the remaining second portion of the substrate and the stop layer structure of the first lot of semiconductor chips to expose the first portion of the substrate, the conductive structure, and the first conductive pillars. Installing a plurality of second conductive pillars so as to be electrically connected to a part of the conductive structure of the first semiconductor chip layer.The second semiconductor chips jumper between the adjacent first semiconductor chips respectively, the internal connection layer of the second semiconductor chips is electrically connected to a part of the conductive structure of the first conductive pillar and the first semiconductor chip layer that is exposed, and a part of the second conductive pillar is interposed between the adjacent second semiconductor chips. A step of flip-chip mounting and installing the second lot of semiconductor chips on the first semiconductor chip layer; a second molding step of forming a second packaging gel on the first semiconductor chip layer so as to cover the second lot of semiconductor chips and the second conductive pillar; A second back grinding step of removing a part of the second packaging gel from the side away from the first semiconductor chip layer of the second packaging gel and removing a part of the second part of the substrate of the second lot of semiconductor chips; a second thinning step of forming a second semiconductor chip layer, the second thinning step includes sequentially removing the second part of the remaining substrate of the second lot of semiconductor chips and the stop layer structure to expose the first part of the substrate, the conductive structure and the second conductive pillar; and removing the carrier plate to expose the internal connection layer and the first conductive pillar of the first semiconductor chip layer.

[0016] In one embodiment of the present invention, after removing the carrier plate, a step of installing a plurality of solder balls on the side of the first semiconductor chip layer away from the second semiconductor chip layer so as to electrically connect the internal connection layer and the first conductive pillar respectively, and a step of cutting are further included.

[0017] In one embodiment of the present invention, the plurality of first semiconductor chips of the first lot of semiconductor chips have different electrical functions.

[0018] In one embodiment of the present invention, the second semiconductor chips of the second lot of semiconductor chips have different electrical functions.

Effect of the Invention

[0019] In the present invention, when manufacturing a semiconductor wafer, first, a stop layer structure is formed in a semiconductor substrate in an ion implantation process, and then electrical elements and internal connection layers are installed on the active surface of the semiconductor substrate. Thereafter, two semiconductor wafers are joined together vertically, or the semiconductor wafer is cut to form a plurality of semiconductor chips, and then the lot of semiconductor chips is joined to the bottommost semiconductor wafer. Each time the semiconductor wafer / chip joining (and molding and formation of the packaging gel) is performed, in a back grinding and thinning process, a part of the semiconductor substrate and the stop layer structure of the upper semiconductor wafer / chip is removed from the back surface of the upper semiconductor wafer / chip, thereby forming a semiconductor wafer / semiconductor chip layer in which the upper semiconductor wafer / chip is thinned. Thereafter, for each of the thinned semiconductor wafers / chips, joining (and molding and formation of the packaging gel) of another semiconductor wafer / chip, a back grinding and thinning process are performed, another thinned semiconductor wafer / semiconductor chip layer is stacked thereon, and finally, a back grinding and thinning process is performed on the bottommost semiconductor wafer. When the thickness of each of the thinned semiconductor wafer / semiconductor chip layers is 12 micrometers or less and the total thickness of the chips is limited to 700 micrometers, 57 chip layers can be stacked, and higher integration and speed requirements can be satisfied.

[0020] The above description is only a summary of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention, it can be implemented according to the content of the specification. Also, in order to make the above and other objects, features, and advantages of the present invention more clearly and understandably, particularly preferred embodiments are given below and will be described in detail below in conjunction with the drawings.

Brief Description of the Drawings

[0021]

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Mode for Carrying Out the Invention

[0022] FIG. 1A to FIG. 1S are schematic cross-sectional views of a method for manufacturing a semiconductor ultra-thin stacked structure according to a first embodiment of the present invention. First, a plurality of semiconductor wafers 10 (shown in FIG. 1E) are manufactured. One of the semiconductor wafers 10 is selected as the first semiconductor wafer 10a (shown in FIG. 1F) of the stacked bottom layer, and the other semiconductor wafers 10 are selected as the second semiconductor wafer 10b (shown in FIG. 1F) and the third semiconductor wafer 10c (shown in FIG. 1L) to be stacked. The manufacturing processes of the plurality of semiconductor wafers 10 are the same or similar. FIGS. 1A to FIG. 1E show schematic cross-sectional views of the manufactured semiconductor wafers 10. As shown in FIG. 1A, a semiconductor substrate 12 is provided. The semiconductor substrate 12 is, for example, a silicon substrate, an epitaxial silicon substrate, a silicon germanium substrate, a silicon carbide substrate, or a silicon on insulation (SOI) substrate. In one embodiment, the thickness of the semiconductor substrate is, for example, 700 to 800 micrometers (um), preferably 775 micrometers. The semiconductor substrate 12 has an active surface 121 and a back surface 122 facing each other.

[0023] Then, a stop layer structure is formed in the semiconductor substrate 12. In one embodiment, the manufacturing of the stop layer structure includes performing at least one ion implantation process and a high-temperature treatment process. In one embodiment, the ion implantation process includes first performing nitrogen ion implantation and then performing oxygen ion implantation. As shown in FIGS. 1B and 1C, first, a nitrogen ion implantation process 14 is performed at a first depth D1 of the semiconductor substrate 12, and then an oxygen ion implantation process 16 is performed at a second depth D2 of the semiconductor substrate 12. In one embodiment, the first depth D1 of the nitrogen ion implantation region 14' is, for example, a depth of about 1 to 5 micrometers from the active surface 121, and the second depth D2 of the oxygen ion implantation region 16' is smaller than the first depth D1 of the nitrogen ion implantation region 14, that is, the oxygen ion implantation region 16' is closer to the active surface 121.

[0024] Thereafter, a high-temperature treatment is performed. As shown in FIG. 1D, a silicon nitride (Si3N4) layer 14a is formed in the nitrogen ion implantation region 14', and a silicon dioxide (SiO2) layer 16a is formed in the oxygen ion implantation region 16'. The silicon dioxide layer 16a is close to the active surface 121, and the silicon nitride layer 14a is close to the back surface 122. In this embodiment, the silicon nitride layer 14a and the silicon dioxide layer 16a constitute the above-mentioned stop layer structure 18. The silicon dioxide layer 16a is located on the silicon nitride layer 14 and is interposed between the silicon nitride layer 14a and the active surface 121. In one embodiment, the thicknesses of the silicon nitride layer 14a and the silicon dioxide layer 16a are, for example, 500 nanometers (nm). For convenience of explanation, the semiconductor substrate 12 between the silicon dioxide layer 16a of the stop layer structure 18 and the active surface 121 is also referred to as the first portion 123 of the substrate, and the semiconductor substrate 12 between the silicon nitride layer 14a of the stop layer structure 18 and the back surface 122 is also referred to as the second portion 124 of the substrate. In one embodiment, when the semiconductor wafer 10 is subsequently used for the fabrication of a metal-oxide-semiconductor field-effect transistor (MOSFET), since the depth of the N well generally used in combination is about 2 micrometers, the thickness of the first portion 123 of the substrate must be 2 micrometers or more. That is, when performing the above nitrogen ion implantation step 14 and oxygen ion implantation step 16, the first depth D1 of the nitrogen ion implantation region 14' and the second depth of the oxygen ion implantation region 16' must both be slightly larger than 2 micrometers.

[0025] Continuing with the above description, as shown in FIG. 1E, an internal connection layer 22 having a plurality of electrical elements 20 and connection points 221 is provided on the active surface 121. The electrical elements 20 include, for example, metal oxide semiconductors (MOS). A plurality of conductive structures are provided on the first portion 123 of the substrate. In one embodiment, the conductive structure includes, for example, a through-silicon via (TSV) 24, and the through-silicon via 24 is vertically connected to the internal connection layer 22 and the silicon dioxide layer 16a of the stop layer structure 18. The manufacturing processes of the electrical elements 20, the internal connection layer 22, and the through-silicon via 24 include the front-end-of-line (FEOL) and back-end-of-line (BEOL) processes of general semiconductor processes. The front-end process is, for example, manufacturing elements such as resistors, capacitors, diodes, and transistors on the semiconductor substrate 12, and the back-end process is, for example, manufacturing metal wiring for connection and connection points 221 between the elements. In one embodiment, the connection point 221 is, for example, a copper contact. FIG. 1E shows a schematic diagram of a semiconductor wafer 10 according to an embodiment of the present invention. The first semiconductor wafer 10a, the second semiconductor wafer 10b, and the third semiconductor wafer 10c described below continue to use the element symbols used in the description of the semiconductor wafer 10. The position of the through-silicon via 24 of the first semiconductor wafer 10a corresponds to, for example, the mounting position of the solder ball in subsequent processes, and the position of the through-silicon via 24 of the second semiconductor wafer 10b corresponds to, for example, the connection point 221 of the internal connection layer 22 of the third semiconductor wafer 10c.

[0026] As shown in FIG. 1F, by flip-chip mounting the second semiconductor wafer 10b on the first semiconductor wafer 10a, the internal connection layers 22 of the first semiconductor wafer 10a and the second semiconductor wafer 10b are opposed to each other and the connection points 221 are made to correspond to each other. Then, as shown in FIG. 1G, the first semiconductor wafer 10a and the second semiconductor wafer 10b are stacked on top of each other using hybrid bonding technology, and the hybrid bonding technology includes processes such as copper-to-copper bonding and annealing.

[0027] Then, using the first back grinding (Grind) process, grind from the back surface 122 of the second semiconductor wafer 10b to remove a part of the second portion 124 of the substrate of the second semiconductor wafer 10b. As shown in FIG. 1H, a very thin second portion 124 of the substrate remains. In one embodiment, the thickness of the remaining second portion 124 of the substrate is about 20.

[0028] Thereafter, a first thinning process is performed to form a thinned second semiconductor wafer. The first thinning process includes a substrate removal step and a stop layer removal step. FIGS. 1I to 1K show schematic diagrams of the first thinning process. As shown in FIG. 1I, the substrate removal step is used to remove the remaining second portion 124 of the substrate to expose the stop layer structure 18, for example, to expose the silicon nitride layer 14a. In one embodiment, the substrate removal step is the first chemical mechanical polishing (CMP) process, and the selectivity between silicon and silicon nitride is, for example, 20, that is, Si / Si3N4 is 20. The stop layer removal step is used to remove the stop layer structure 18, that is, to sequentially remove the silicon nitride layer 14a and the silicon dioxide layer 16a to expose the first portion 123 of the substrate and the silicon through electrode 24. In one embodiment, as shown in FIG. 1J, first, the silicon nitride layer 14a is removed by the second chemical mechanical polishing process to expose the silicon dioxide layer 16a, and the selectivity between silicon nitride and silicon dioxide is, for example, 10, that is, Si3N4 / SiO2 is 10. Then, as shown in FIG. 1K, the silicon dioxide layer 16a is removed by the third chemical mechanical polishing process to expose the first portion 123 of the substrate and the silicon through electrode 24, and the selectivity between silicon dioxide and silicon is, for example, 5, that is, SiO2 / Si is 5. The exposure of the first portion 123 of the substrate and the silicon through electrode 24 forms a thinned second semiconductor wafer 10b'.

[0029] Continuing with the above description, the stacking of the first semiconductor wafer 10a and the thinned second semiconductor wafer 10b' has already been completed. And, as shown in FIG. 1L, by flip-chip mounting the third semiconductor wafer 10c onto the first semiconductor wafer 10a, the internal connection layer 22 of the third semiconductor wafer 10c is directed towards the first portion 123 of the substrate of the thinned second semiconductor wafer 10b'. In one embodiment, the interconnect points 221 of the internal connection layer 22 of the third semiconductor wafer 10c respectively correspond to the silicon through electrodes 24 of the thinned second semiconductor wafer 10b'. Thereafter, the above-described first back grinding process and first thinning process are repeated to complete the stacking of the thinned third semiconductor wafer 10c' and the thinned second semiconductor wafer 10b'. In one embodiment, the thickness of the thinned second semiconductor wafer 10b' or the thinned third semiconductor wafer 10c' is, for example, 12 micrometers. Thus, on the premise of having a plurality of semiconductor wafers 10 as shown in FIG. 1M, when the bonding process, the first back grinding process, and the first thinning process of the semiconductor wafers 10 are repeated one by one, the stacking of the multilayer thinned semiconductor wafers 10' and the first semiconductor wafer 10a can be completed. In one embodiment, the first portion 123 of the substrate may not have the silicon through electrode 24 formed thereon as the uppermost stacked thinned semiconductor wafer 10'.

[0030] As shown in FIG. 1N, after stacking a predetermined number of the plurality of thinned semiconductor wafers 10', the second back grinding process is used to grind from the back surface 122 of the first semiconductor wafer 10a to remove a part of the second portion 124 of the substrate of the first semiconductor wafer 10a, leaving the second portion 124 of the extremely thin substrate remaining. Then, as shown in FIGS. 1O to 1Q, the second thinning process is performed, and using the above-described substrate removal step and stop layer removal step, the second portion 124 of the substrate, the silicon nitride layer 14a, and the silicon dioxide layer 16a remaining on the first semiconductor wafer 10a are removed in sequence, exposing the first portion 123 of the substrate and the silicon through electrode 24 of the further thinned first semiconductor wafer 10a'. Thus, the stacking of the plurality of thinned semiconductor wafers 10' such as the further thinned first semiconductor wafer 10a', the thinned second semiconductor wafer 10b', the thinned third semiconductor wafer 10c'... is completed.

[0031] Thereafter, as shown in FIG. 1R, a plurality of solder balls 26 are installed on the side of the thinned first semiconductor wafer 10a' away from the thinned second semiconductor wafer 10b', and are electrically connected to the exposed silicon through electrodes 24 respectively. After performing chip probing (CP) and testing the electrical functions, die sawing is performed to form the semiconductor ultra-thin stacked structure 28 shown in FIG. 1S. The thinned semiconductor wafers 10' of each layer are cut as semiconductor chip layers 10". The thickness of each of the thinned semiconductor wafers 10' may be, for example, 12 micrometers. In the semiconductor ultra-thin stacked structure 28 according to the embodiment of the present invention, when the total thickness of the chips is limited to 700 micrometers, 57 layers of thinned semiconductor chip layers 10" can be stacked, meeting the requirements of high integration and speed, and having better electrical characteristics and efficiency.

[0032] Furthermore, taking the example that the substrate removal step and the stop layer removal step in the first thinning step and the second thinning step together include a total of three chemical mechanical polishing steps, the present invention is not limited thereto. In other embodiments, the first / second thinning step includes one wet etching step and two chemical mechanical polishing steps. That is, in the substrate removal step, a wet etching step is used instead of the first chemical mechanical polishing step. For a schematic cross-sectional view of the thinning step, reference may be made to FIGS. 1H to 1K or FIGS. 1N to 1Q. First, the second portion 124 of the remaining substrate is removed by a wet etching step to expose the silicon nitride layer 14a. The selectivity ratio of silicon to silicon nitride in the wet etching step is, for example, 40, that is, Si / Si3N4 is 40. Further, the second chemical mechanical polishing step and the third chemical mechanical polishing step are sequentially performed to remove the silicon nitride layer 14a and the silicon dioxide layer 16a in sequence.

[0033] In another embodiment, in the first / second thinning process, three plasma dry etching processes may be used instead of the above three chemical mechanical polishing processes. For a schematic cross-sectional view of the thinning process, reference may continue to be made to FIGS. 1H to 1K or FIGS. 1N to 1Q. First, the second portion 124 of the remaining substrate is removed in the first plasma dry etching process to expose the silicon nitride layer 14a. In one embodiment, the selectivity between silicon and silicon nitride during the first plasma dry etching is, for example, 80, that is, Si / Si3N4 is 80. Then, the silicon nitride layer 14a is removed in the second plasma dry etching process to expose the silicon dioxide layer 16a. In one embodiment, the selectivity between silicon nitride and silicon dioxide in the second plasma dry etching process is, for example, 20, that is, Si3N4 / SiO2 is 20. Then, the silicon dioxide layer 16a is removed in the third plasma dry etching process to expose the first portion 123 of the substrate and the silicon through electrode 24. In one embodiment, the selectivity between silicon dioxide and silicon in the third plasma dry etching process is, for example, 5, that is, SiO2 / Si is 5.

[0034] In the first embodiment described above, a Wafer on Wafer (WoW) method is used, but it is not limited to this. Figures 2A to 2K show schematic cross-sectional views of a method for manufacturing a semiconductor ultra-thin stacked structure according to a second embodiment of the present invention. In this second embodiment, first, a plurality of semiconductor wafers 10 are provided. Since the manufacturing steps are disclosed in Figures 1A to 1E above, no further description will be given here. Then, as shown in Figure 2A, some of the semiconductor wafers 10 are selected as the bottom first semiconductor wafer 10a (shown in Figure 2B), and an electrical function test is performed on another part of the semiconductor wafers 10. The wafers with good electrical functions are selected and cut to obtain a plurality of semiconductor chips 30. Each semiconductor chip 30 includes an electrical element 20, an internal connection layer 22, and a semiconductor substrate 12. A stop layer structure 18 is formed on the semiconductor substrate 12. The stop layer structure 18 divides the semiconductor substrate 12 into a first part 123 and a second part 124 of the substrate. A silicon through electrode 24 is formed on the first part 123 of the substrate so as to connect the stop layer structure 18 and the internal connection layer 22. Hereinafter, for the convenience of explanation, the plurality of semiconductor chips 30 are divided into the first lot of semiconductor chips 30a and the second lot of semiconductor chips 30b in the time series of subsequent processes. Each lot includes a plurality of semiconductor chips 30.

[0035] As shown in Figure 2B, the first lot of semiconductor chips 30a are flip-chip mounted on the first semiconductor wafer 10a, with the internal connection layer 22 of the first lot of semiconductor chips 30a facing the internal connection layer 22 of the first semiconductor wafer 10a and the mutual connection points 221 corresponding to each other. Then, as shown in Figure 2C, using a hybrid bonding technology, the first semiconductor wafer 10a and the first lot of semiconductor chips 30a are joined vertically.

[0036] Then, as shown in FIG. 2D, a first molding process is performed to form a first packaging gel 32a on the first semiconductor wafer 10a so as to cover the first lot of semiconductor chips 30a. Thereafter, using a first back grinding process, a part of the first packaging gel 32a and a part of the second portion 124 of the substrate of the first lot of semiconductor chips 30a are removed from the side of the first packaging gel 32a away from the first semiconductor wafer 10a. As shown in FIG. 2E, a second portion 124 of the substrate with an extremely thin thickness and the first packaging gel 32a flush with the second portion 124 of the substrate remain on the first lot of semiconductor chips 30a.

[0037] Thereafter, performing the first thinning process includes the substrate removal step and the stop layer removal step described in the first embodiment, thereby removing the remaining second portion 124 of the substrate, the stop layer structure 18, and a part of the packaging gel 32 of the first lot of semiconductor chips 30a. As shown in FIG. 2F, the first portion 123 of the substrate and the silicon through electrodes 24 of the first lot of semiconductor chips 30a are exposed, and the first semiconductor chip layer 30a' thinned in this way is formed, and the first semiconductor chip layer 30a' is loaded on the first semiconductor wafer 10a.

[0038] Then, still flip-chip mount the second lot of semiconductor chips 30b onto the first semiconductor wafer 10a, align the internal connection layers 22 of the second lot of semiconductor chips 30b with the first part 123 of the substrate of the first semiconductor chip layer 30a' respectively, and bond the second lot of semiconductor chips 30b and the first semiconductor chip layer 30a'. Perform a second molding process to form a second packaging gel 32b on the first semiconductor chip layer 30a' so as to cover the second lot of semiconductor chips 30b. Perform a back grinding process and a thinning process to remove a part of the second packaging gel 32b, a second part (not shown) of the substrate of the second lot of semiconductor chips 30b, and a stop layer structure (not shown) from the side of the second packaging gel 32b away from the first semiconductor chip layer 30a', and expose the first part 123 of the substrate of the second lot of semiconductor chips 30b and the silicon through electrodes 24, thereby forming a thinned second semiconductor chip layer 30b'. In this way, as shown in FIG. 2H, when the bonding process, molding process, back grinding process, and first thinning process of the semiconductor chips 30 of the above lot are repeated one lot at a time, the loading of the first semiconductor chip layer 30a', the multilayer second semiconductor chip layers 30b', and the first semiconductor wafer 10a can be completed. In one embodiment, as the second semiconductor chip layer 30b' loaded on the top, a silicon through electrode 24 may not be formed on the first part 123 of its substrate.

[0039] Then, similar to the first embodiment, after loading a predetermined number of second semiconductor chip layers 30b', as shown in FIG. 2I, use a second back grinding process and a second thinning process to sequentially remove the second part 124 of the substrate of the first semiconductor wafer 10a and the stop layer structure 18 from the back surface 122 of the first semiconductor wafer 10a, expose the first part 123 of the substrate and the silicon through electrodes 24, and thus complete the loading of the thinned first semiconductor wafer 10a' and the plurality of semiconductor chips 30.

[0040] The above first and second thinning steps include the substrate removal step and the stop layer removal step described in the first embodiment. The selection of the steps of the substrate removal step and the stop layer removal step may be, for example, three chemical mechanical polishing steps, or a combination of a wet etching step and a chemical mechanical polishing step, or both may be plasma dry etching steps. And the selection ratios of materials such as silicon, silicon nitride, and silicon dioxide are as described in the first embodiment, so they will not be described further here. Thereafter, as shown in FIG. 2J, a solder ball was placed on the exposed silicon through electrode 24 of the thinned first semiconductor wafer 10a', and after performing an electrical function test, it was cut along the cutting path 321 of the first packaging gel 32a and the second packaging gel 32b to form a semiconductor ultra-thin stacked structure 34 shown in FIG. 2K. In the semiconductor ultra-thin stacked structure 34 according to this embodiment, since the electrical function test and sorting have already been performed on the semiconductor chip 30 that has already been stacked, the yield of the semiconductor ultra-thin stacked structure 34 is high.

[0041] FIGS. 3A to 3L show schematic cross-sectional views of a method for manufacturing a semiconductor ultra-thin stacked structure according to a third embodiment of the present invention. In the third embodiment, as shown in FIG. 3A, first, a carrier plate 40 is provided, and a plurality of first conductive pillars 42 are formed on the carrier plate 40. The carrier plate 40 is, for example, glass with a thickness of 500 micrometers and a length of 301 millimeters (mm), and the first conductive pillar 42 is, for example, a copper pillar.

[0042] Then, a plurality of semiconductor chips 44 (shown in FIG. 3B) that have undergone an electrical function test are sorted. The semiconductor chips 44 may have the same or different electrical functions. The plurality of types of semiconductor chips 44 are each obtained by cutting a plurality of types of semiconductor wafers 10. The manufacturing steps of the various semiconductor wafers 10 are disclosed in FIGS. 1A to 1E above and will not be described further here. Each semiconductor chip 44 still includes an electrical element 20, an internal connection layer 22, and a semiconductor substrate 12. A stop layer structure 18 is formed on the semiconductor substrate 12. The stop layer structure 18 divides the semiconductor substrate 12 into a first portion 123 of the substrate and a second portion 124 of the substrate. A silicon through electrode 24 is formed on the first portion 123 of the substrate so as to connect the stop layer structure 18 and the internal connection layer 22. In one embodiment, the thickness of the semiconductor substrate 12 is, for example, 775 micrometers, and the thickness of the internal connection layer 22 is, for example, 10 micrometers.

[0043] As shown in FIG. 3B, the selected first lot of semiconductor chips are flip-chip mounted and bonded onto a carrier plate 40. Taking as an example that the first lot of semiconductor chips 44 includes three first semiconductor chips 44a, the three first semiconductor chips 44a may have the same or different electrical functions, and the first conductive pillars 42 are interposed between adjacent first semiconductor chips 44a. In one embodiment, when flip-chip mounting and bonding the first semiconductor chips 44a, they are bonded in a flip-chip mounting manner in which the internal connection layer 22 is close to the carrier plate 40 and the semiconductor substrate 12 is away from the carrier plate 10.

[0044] Thereafter, as shown in FIG. 3C, a first forming step is performed to form a first packaging gel 46a on the carrier plate 40 so as to cover the three first semiconductor chips 44a and the first conductive pillars 42. Then, as shown in FIG. 3D, using the first back grinding step and the first thinning step, a second portion 124 of the substrate of the first packaging gel 46a and a part of the stop layer structure 18 are removed from the side away from the carrier plate 40 of the first packaging gel 46a, and the first portion 123 of the substrate, the silicon through electrode 24, and the first conductive pillar 44 are exposed, thus forming the thinned first semiconductor chip layer 44a'.

[0045] Thereafter, by installing the second conductive pillar 48, the second conductive pillar 48 is installed perpendicular to, for example, a part of the silicon through electrode 24. As shown in FIG. 3E, at least one silicon through electrode 24 of each thinned first semiconductor chip 44a is provided with the second conductive pillar 48, and the second conductive pillar 48 is, for example, a copper pillar. Thereafter, the selected second lot of semiconductor chips are flip-chip mounted and jumpered between two adjacent thinned first semiconductor chips 44a. Taking the example that the second lot of semiconductor chips includes two second semiconductor chips 44b as shown in FIG. 3F, the two semiconductor chips 44b may have the same or different electrical functions. In one embodiment, the internal connection layer 22 of the second semiconductor chip 44b and the first portion 123 of the substrate of the first semiconductor chip layer 44a' face each other, and the interconnecting point 221 of the second semiconductor chip 44b, a part of the silicon through electrode 24, and the first conductive pillar 42 form an electrical connection, and a part of the second conductive pillar 48 is interposed between the adjacent second semiconductor chips 44b.

[0046] Then, the second forming process, the second back grinding process, and the second thinning process are sequentially performed. After forming the second packaging gel 46b on the first semiconductor chip layer 44a' so as to cover the second semiconductor chip 44b and the second conductive pillar 48, in the second back grinding process and the second thinning process, the second portion 124 of the substrate of the second semiconductor chip 44b, the stop structure layer 18, and a part of the second packaging gel 46b are removed. As shown in FIG. 3G, the first portion 123 of the substrate, the silicon through electrode 124, and the second conductive pillar 48 are exposed, and the thinned second semiconductor chip layer 44b' is formed in this way.

[0047] In this way, as shown in FIG. 3H, the installation of the third conductive pillar 50, the flip chip mounting installation of the third semiconductor chip 44c on the second semiconductor chip layer 44b', the potting forming process, the back grinding process, and the thinning process are repeatedly performed to complete the stacking of the third semiconductor chip layer 44c', and, as shown in FIG. 3I, the stacking of more semiconductor chip layers is continued.

[0048] Thereafter, as shown in FIG. 3J, the carrier plate 40 is removed to expose the internal connection layer 22 and the first conductive pillar 42 of the first semiconductor chip layer, and, as shown in FIG. 3K, a solder ball 26 is installed on a circuit contact (not shown) provided in advance in the internal connection layer 22 and the first conductive pillar, and then cut to complete the semiconductor ultra-thin stacked structure 52 shown in FIG. 3L.

[0049] In the method for manufacturing a semiconductor ultra-thin stacked structure according to the above first / second / third embodiments, the nitrogen ion and oxygen ion implantation are sequentially performed, and the high-temperature treatment is performed to form a stop layer structure of a silicon nitride layer and a silicon dioxide layer as an example for explanation, but it is not limited thereto. In one embodiment, the stop layer structure may include only a silicon nitride layer so as to form a silicon nitride layer at a depth of 1 to 5 micrometers from the active surface, that is, the high-temperature treatment process may be performed after the nitrogen ion implantation process in the semiconductor substrate. Accordingly, in the stop layer removal step of the subsequent first / second thinning process, only the silicon nitride layer may be removed, and the other subsequent processes are the same, and will not be described further here.

[0050] In an embodiment of the present invention, a stop layer structure is formed at a certain depth of the semiconductor substrate, and in a subsequent thinning process, the substrate removal step and the formation of the stop layer structure are gradually carried out, so that only the first part of the substrate, that is, only the thickness of the substrate of 1 to 5 micrometers is left, and the semiconductor substrate can be reliably polished or etched. Thereby, the overall thickness of each semiconductor chip layer is made 12 micrometers or less, and the total thickness of the chip is limited to 700 micrometers. In the semiconductor ultra-thin stacked structure 28 according to the embodiment of the present invention, dozens of thinned semiconductor chip layers can be stacked, meeting the requirements of high integration and speed, and having better electrical characteristics and efficiency.

[0051] What has been described above are only preferred embodiments of the present invention and do not limit the present invention in any form. Although the present invention has been described above with preferred embodiments, it is not used to limit the present invention. Any person skilled in the art can, without departing from the scope of the technical solution of the present invention, make some changes or modifications using the methods and technical contents disclosed above as equivalent embodiments of equivalent changes. However, without departing from the content of the technical solution of the present invention, any simple modifications, equivalent changes or modifications substantially made to the above embodiments based on the technology of the present invention all belong to the scope of the technical solution of the present invention.

Claims

1. A step of manufacturing a plurality of semiconductor wafers, selecting one of the semiconductor wafers as a first semiconductor wafer of the bottom layer, and using the other semiconductor wafers as a second semiconductor wafer to be loaded and at least one third semiconductor wafer, wherein the step of manufacturing each of the semiconductor wafers includes: providing a semiconductor substrate having opposing active surfaces and back surfaces; forming a stop layer structure in the semiconductor substrate and dividing the semiconductor substrate into a first portion of the substrate and a second portion of the substrate, wherein the first portion of the substrate is located between the stop layer structure and the active surface, the second portion of the substrate is located between the stop layer structure and the back surface, the stop layer structure includes at least a silicon nitride layer, and the manufacturing of the silicon nitride layer includes first performing a nitrogen ion implantation process at a first depth of the semiconductor substrate and then performing a high-temperature treatment process to form the silicon nitride layer in the nitrogen ion implantation region formed by the nitrogen ion implantation process; installing a plurality of electrical elements and an internal connection layer including a plurality of interconnect points on the active surface, and installing a plurality of conductive structures on the first portion of the substrate so as to connect the internal connection layer and the stop layer structure; flip-chip mounting the second semiconductor wafer on the first semiconductor wafer, opposing the internal connection layer of the first semiconductor wafer and the internal connection layer of the second semiconductor wafer, and bonding them using a hybrid bonding technique; performing a first back grinding process to grind from the back surface of the second semiconductor wafer to remove a part of the second portion of the substrate of the second semiconductor wafer; performing a first thinning process to form a thinned second semiconductor wafer; performing a second back grinding process to grind from the back surface of the first semiconductor wafer to remove a part of the second portion of the substrate of the first semiconductor wafer; performing a second thinning process to form a thinned first semiconductor wafer, wherein the first thinning process and the second thinning process include a substrate removal step of removing the remaining second portion of the substrate to expose the stop layer structure, and a stop layer removal step of removing the stop layer structure to expose the first portion of the substrate and the conductive structure; The method for manufacturing a semiconductor ultra-thin stacked structure is characterized in that the stop layer structure further includes a silicon dioxide layer disposed on the silicon nitride layer so as to be interposed between the silicon nitride layer and the active surface.

2. Before performing the second back grinding process, a plurality of thinned third semiconductor wafers can be sequentially stacked on the thinned second semiconductor wafer. The step of stacking each of the thinned third semiconductor wafers includes: a step of flip-chip mounting the third semiconductor wafer on the first semiconductor wafer so that the internal connection layer of the third semiconductor wafer faces and is bonded to a first portion of the substrate of the thinned second semiconductor wafer; a step of performing a third back grinding process to grind from the back surface of the third semiconductor wafer to remove a part of a second portion of the substrate of the third semiconductor wafer; and a step of performing a third thinning process including the substrate removing step and the stop layer removing step. The method for manufacturing a semiconductor ultra-thin stacked structure according to claim 1 is characterized by the above.

3. The step of forming the silicon dioxide layer includes, after the nitrogen ion implantation process, first performing an oxygen ion implantation process at a second depth of the semiconductor substrate smaller than the first depth, and then performing the high-temperature treatment process to form the silicon dioxide layer in the oxygen ion implantation region formed by the oxygen ion implantation process. The method for manufacturing a semiconductor ultra-thin stacked structure according to claim 1 is characterized by the above.

4. The stop layer removing step includes a step of removing the silicon dioxide layer after removing the silicon nitride layer. The method for manufacturing a semiconductor ultra-thin stacked structure according to claim 3 is characterized by the above.

5. The substrate removing step is selected from one of chemical mechanical polishing, wet etching, and plasma dry etching, and the selectivity ratio between silicon and silicon nitride is between 20 and 80. The method for manufacturing a semiconductor ultra-thin stacked structure according to claim 4 is characterized by the above.

6. The method for removing the silicon nitride layer and the silicon dioxide layer is selected from one of chemical mechanical polishing and plasma dry etching. The selectivity ratio between silicon nitride and silicon dioxide is between 10 and 20, and the selectivity ratio between silicon dioxide and silicon is 5. The method for manufacturing a semiconductor ultra-thin stacked structure according to claim 4 is characterized by the above.

7. The distance between the stop layer structure and the active surface is between 1 micrometer and 5 micrometers, and the thickness of the thinned second semiconductor wafer is 12 micrometers or less. A method for manufacturing a semiconductor ultra-thin stacked structure according to claim 1, characterized in that.

8. After forming the thinned first semiconductor wafer, A step of installing a plurality of solder balls on a side of the thinned first semiconductor wafer away from the thinned second semiconductor wafer so as to be electrically connected to each of the conductive structures; A method for manufacturing a semiconductor ultra-thin stacked structure according to claim 1, further comprising a step of performing an electrical test and a cutting step.

9. A step of manufacturing a plurality of semiconductor wafers, wherein the step of manufacturing each of the semiconductor wafers comprises: Providing a semiconductor substrate having opposing active and back surfaces; Forming a stop layer structure in the semiconductor substrate to divide the semiconductor substrate into a first portion of the substrate and a second portion of the substrate, wherein the first portion of the substrate is located between the stop layer structure and the active surface, and the second portion of the substrate is located between the stop layer structure and the back surface, and the stop layer structure includes at least a silicon nitride layer, and the manufacturing of the silicon nitride layer first performs a nitrogen ion implantation process at a first depth of the semiconductor substrate, and then performs a high-temperature treatment process to form the silicon nitride layer in the nitrogen ion implantation region formed by the nitrogen ion implantation process; Installing a plurality of electrical elements and an internal connection layer including a plurality of interconnect points on the active surface, and installing a plurality of conductive structures on the first portion of the substrate so as to connect the internal connection layer and the stop layer structure; Selecting one of the semiconductor wafers as a first semiconductor wafer of the bottom layer, and cutting the other semiconductor wafers into a first lot of semiconductor chips to be stacked and at least one second lot of semiconductor chips; Flip-chip mounting the first lot of semiconductor chips on the first semiconductor wafer, opposing the internal connection layer of the first lot of semiconductor chips and the internal connection layer of the first semiconductor wafer, and bonding them by a hybrid bonding technique; Performing a first molding step of forming a first packaging gel on the first semiconductor wafer so as to cover the first lot of semiconductor chips; Performing a first back grinding process to remove a part of the first packaging gel from the side away from the first semiconductor wafer of the first packaging gel and to remove a part of the second portion of the substrate of the semiconductor chip of the first lot; Performing a first thinning process to form a first semiconductor chip layer; Performing a second back grinding process to grind from the back surface of the first semiconductor wafer to remove a part of the second portion of the substrate of the first semiconductor wafer; Performing a second thinning process to form a thinned first semiconductor wafer, wherein the first thinning process and the second thinning process include a substrate removing step of removing the remaining second portion of the substrate to expose the stop layer structure, and a stop layer removing step of removing the stop layer structure to expose the first portion of the substrate and the conductive structure. A method for manufacturing a semiconductor ultra-thin stacked structure, characterized by including the above steps.

10. Before performing the second back grinding process, at least one second semiconductor chip layer can be sequentially stacked on the first semiconductor chip layer, and the step of stacking each of the second semiconductor chip layers includes: Flip-chip mounting at least one of the semiconductor chips of the second lot on the first semiconductor wafer so that the internal connection layer of at least one semiconductor chip of the second lot faces and is bonded to the first portion of the substrate of the first semiconductor chip layer; Performing a second molding process to form a second packaging gel on the first semiconductor chip layer so as to cover the semiconductor chips of the second lot; Performing a third back grinding process to remove a part of the second packaging gel from the side away from the first semiconductor chip layer of the second packaging gel and to remove a part of the second portion of the substrate of the semiconductor chips of the second lot; Including the step of performing a third thinning process including the substrate removing step and the stop layer removing step. A method for manufacturing a semiconductor ultra-thin stacked structure according to claim 9, characterized by including the above steps.

11. After forming the thinned first semiconductor wafer, A method for manufacturing a semiconductor ultra-thin stacked structure according to claim 9, further comprising the steps of installing a plurality of solder balls on a side of the thinned first semiconductor wafer away from the first semiconductor chip layer so as to be electrically connected to each of the conductive structures, and performing an electrical test and cutting.

12. A method for manufacturing a semiconductor ultra-thin stacked structure, comprising: providing a carrier plate and forming a plurality of first conductive pillars on the carrier plate; providing a plurality of semiconductor chips, wherein the step of manufacturing each of the plurality of semiconductor chips includes providing a semiconductor substrate having opposing active surfaces and a back surface, forming a stop layer structure in the semiconductor substrate to divide the semiconductor substrate into a first portion of the substrate and a second portion of the substrate, the first portion of the substrate being located between the stop layer structure and the active surface, the second portion of the substrate being located between the stop layer structure and the back surface, the stop layer structure including at least a silicon nitride layer, and manufacturing the silicon nitride layer by first performing a nitrogen ion implantation process at a first depth of the semiconductor substrate and then performing a high-temperature treatment process to form the silicon nitride layer in a nitrogen ion implantation region formed by the nitrogen ion implantation process; installing a plurality of electrical elements and an internal connection layer including a plurality of interconnection points on the active surface, and installing a plurality of conductive structures on the first portion of the substrate so as to connect the internal connection layer and the stop layer structure; and cutting. selecting a first lot of semiconductor chips and at least one second lot of semiconductor chips from the semiconductor chips, wherein the first lot of semiconductor chips includes a plurality of first semiconductor chips and the at least one second lot of semiconductor chips includes a plurality of second semiconductor chips; flip-chip mounting and installing the first lot of semiconductor chips on the carrier plate such that the first conductive pillars are interposed between adjacent first semiconductor chips, wherein the internal connection layer of the first lot of semiconductor chips is close to the carrier plate and the semiconductor substrate is away from the carrier plate; performing a first molding process to form a first packaging gel on the carrier plate so as to cover the first lot of semiconductor chips and the first conductive pillars. Performing a first back grinding process to remove a part of the first packaging gel from the side away from the carrier plate of the first packaging gel and a part of the second portion of the substrate of the first lot of semiconductor chips. Performing a first thinning process to form a first semiconductor chip layer, wherein the first thinning process includes sequentially removing the remaining second portion of the substrate of the first lot of semiconductor chips and the stop layer structure to expose the first portion of the substrate, the conductive structure, and the first conductive pillars. Installing a plurality of second conductive pillars so as to be electrically connected to a part of the conductive structure of the first semiconductor chip layer. Flip-chip mounting and installing the second lot of semiconductor chips on the first semiconductor chip layer such that the second semiconductor chips jump between the adjacent first semiconductor chips, the internal connection layer of the second semiconductor chips is electrically connected to the exposed first conductive pillars and a part of the conductive structure of the first semiconductor chip layer, and a part of the second conductive pillars is interposed between the adjacent second semiconductor chips. Performing a second molding process to form a second packaging gel on the first semiconductor chip layer so as to cover the second lot of semiconductor chips and the second conductive pillars. Performing a second back grinding process to remove a part of the second packaging gel from the side away from the first semiconductor chip layer of the second packaging gel and a part of the second portion of the substrate of the second lot of semiconductor chips. Performing a second thinning process to form a second semiconductor chip layer, wherein the second thinning process includes sequentially removing the remaining second portion of the substrate of the second lot of semiconductor chips and the stop layer structure to expose the first portion of the substrate, the conductive structure, and the second conductive pillars. Removing the carrier plate to expose the internal connection layer and the first conductive pillars of the first semiconductor chip layer, characterized by a method for manufacturing a semiconductor ultra-thin stacked structure.

13. After removing the carrier plate, A step of installing a plurality of solder balls on a side of the first semiconductor chip layer away from the second semiconductor chip layer so as to electrically connect the internal connection layer and the first conductive pillar, respectively, and a step of cutting, further comprising a method for manufacturing a semiconductor ultra-thin mounting structure according to claim 12, characterized in that.

14. The first semiconductor chip in the first lot of semiconductor chips has different electrical functions, and a method for manufacturing a semiconductor ultra-thin mounting structure according to claim 12, characterized in that.

15. The second semiconductor chip in the second lot of semiconductor chips has different electrical functions, and a method for manufacturing a semiconductor ultra-thin mounting structure according to claim 12, characterized in that.

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