Memory system

Abstract

To provide a comparison system comprising at least one comparison circuit for improving operation speed.SOLUTION: A comparison system includes a comparison circuit 1 comprising: a common module that is connected to a power supply signal Vcc and a ground signal Vss and outputs the power supply signal or the ground signal on the basis of a first signal B and a second signal BN which are inverted; a first logical unit that is connected to the common module, receives a third signal A and a fourth signal AN which are inverted, and outputs a first operation signal Y which is an exclusive OR of the first signal and the third signal; and a second logical unit that is connected to the common module, receives the third signal and the fourth signal, and outputs a second operation signal YN which is a not exclusive OR of the first signal and the third signal.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] (Cross - reference to related applications) This application is filed based on a Chinese patent application with an application number of 202110049123.4 and an application date of January 14, 2021, claims the priority of the Chinese patent application, and all of the Chinese patent application is incorporated herein by reference.

[0002] The embodiments of this application relate to, but are not limited to, a comparison system.

Background Art

[0003] Semiconductor memories can be divided into non - volatile memories and volatile memories. Dynamic Random Access Memory (abbreviated as DRAM) is a volatile memory, which has advantages such as high recording density and fast read - write speed, and is widely used in various electronic systems.

[0004] As the manufacturing process of DRAM progresses and the recording density becomes higher and higher, the stored data in DRAM may have errors, which may seriously affect the performance of DRAM. Therefore, in DRAM, error correction code (ECC: Error Checking and Correction or Error correction Coding) technology is usually adopted to detect or correct errors in stored data.

Summary of the Invention

[0005] Embodiments of the present application provide a comparison system comprising at least one comparison circuit. The comparison circuit is connected to a power supply signal and a ground signal, and includes a shared module configured to control output of the power supply signal or the ground signal based on a first signal and a second signal that are in opposite phases to each other; a first logic unit connected to the shared module, configured to receive a third signal and a fourth signal that are in opposite phases to each other, and output a first operation signal that is an exclusive OR of the first signal and the third signal; and a second logic unit connected to the shared module, configured to receive the third signal and the fourth signal, and output a second operation signal that is a negative exclusive OR of the first signal and the third signal.

Brief Description of the Drawings

[0006]

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Best Mode for Carrying Out the Invention

[0007] One or more embodiments will be exemplarily described with reference to the figures in the corresponding drawings. These exemplary descriptions do not limit the embodiments. Elements with the same reference numerals in the drawings indicate similar elements, and unless otherwise specified, the figures in the drawings do not limit the scale.

[0008] Embodiments of the present application provide a comparison system. A first logic unit configured to implement an exclusive OR and a second logic unit configured to implement a negative exclusive OR share the same shared module. This contributes to a reduction in circuit area, increases the areas of the first logic unit and the second logic unit, and can further improve the driving capabilities of the first logic unit and the second logic unit, as well as the operation speeds of the exclusive OR operation and the negative exclusive OR operation, contributing to an improvement in the speed at which the memory system performs error detection and error correction.

[0009] To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, each embodiment of the present application will be described in detail below with reference to the drawings. However, in each embodiment of the present application, many technical details are shown to enable readers (persons skilled in the art) to clearly understand the present application. It should be understood by persons skilled in the art that the technical solutions claimed by the present application can be implemented even without these technical details and various changes and modifications based on the following embodiments.

[0010] FIG. 1 is a functional block diagram of a comparison circuit in a comparison system provided by an embodiment of the present application, FIG. 2 is a schematic circuit structure diagram of the comparison circuit in the comparison system provided by an embodiment of the present application, and FIG. 3 is a schematic circuit structure diagram of the comparison system provided by an embodiment of the present application.

[0011] Referring to FIG. 1, in the embodiment of the present application, the comparison system includes at least one comparison circuit 1. The comparison circuit 1 is connected to a power supply signal Vcc and a ground signal Vss, and a shared module 10 that is controlled to output the power supply signal Vcc or the ground signal Vss based on a first signal B and a second signal BN that are in opposite phases to each other. A first logic unit 11 that is connected to the shared module 10, receives a third signal A and a fourth signal AN that are in opposite phases to each other, and is configured to output a first operation signal Y that is an exclusive OR of the first signal B and the third signal A. A second logic unit 12 that is connected to the shared module 10, receives the third signal A and the fourth signal AN, and is configured to output a second operation signal YN that is a negative exclusive OR of the first signal B and the third signal A.

[0012] It should be noted that the connection lines between the shared module 10, the first logic unit 11, and the second logic unit 12 indicate the signal transmission relationship between them. It is not necessarily only one signal line. The signal line may be one or multiple.

[0013] In the following, the comparison system provided in the embodiment of the present application will be described in detail with reference to the drawings.

[0014] In the embodiment of the present application, referring to FIG. 2, the shared module 10 (refer to FIG. 1) includes a first shared unit 21 that is connected to the power supply signal Vcc and is controlled to output the power supply signal Vcc based on the first signal B and the second signal BN, and a second shared unit 22 that is connected to the ground signal Vss and is controlled to output the ground signal Vss based on the first signal B and the second signal BN. The first logic unit 11 (refer to FIG. 1) is connected between the first shared unit 21 and the second shared unit 22, and the second logic unit 12 (refer to FIG. 1) is connected between the first shared unit 21 and the second shared unit 22.

[0015] In an embodiment of the present application, referring to FIG. 2, the first sharing unit 21 includes a first PMOS transistor MP0 whose gate receives a first signal B and whose source is connected to a power supply signal Vcc, and a seventh PMOS transistor MP7 whose gate receives a second signal BN and whose source is connected to the power supply signal Vcc. When the first signal B is at a high level and the second signal BN is at a low level, the first PMOS transistor MP0 is cut off and the seventh PMOS transistor MP7 is turned on. When the first signal B is at a low level and the second signal BN is at a high level, the first PMOS transistor MP0 is turned on and the seventh PMOS transistor MP7 is cut off.

[0016] The second sharing unit 22 includes a first NMOS transistor MN0 whose gate receives the first signal B and whose source is connected to a ground signal Vss, and a seventh NMOS transistor MN7 whose gate receives the second signal BN and whose source is connected to the ground signal Vss. When the first signal B is at a high level and the second signal BN is at a low level, the first NMOS transistor MN0 is turned on and the seventh NMOS transistor MN7 is cut off. When the first signal B is at a low level and the second signal BN is at a high level, the first NMOS transistor MN0 is cut off and the seventh NMOS transistor MN7 is turned on.

[0017] In an embodiment of the present application, the first logic unit 11 includes a first PMOS transistor MP1 whose gate receives a fourth signal AN and whose source is connected to the drain of the first PMOS transistor MP0, a first NMOS transistor MN1 whose gate receives a third signal A, whose drain is connected to the drain of the first PMOS transistor MP1, and whose source is connected to the drain of the first NMOS transistor MN0, a fourth PMOS transistor MP4 whose gate receives the third signal A and whose source is connected to the drain of the seventh PMOS transistor MP7, and a fourth NMOS transistor MN4 whose gate receives the fourth signal AN, whose drain is connected to the drain of the fourth PMOS transistor MP4, and whose source is connected to the drain of the seventh NMOS transistor MN7.

[0018] The second logic unit 12 includes a second PMOS transistor MP2 whose gate receives the third signal A and whose source is connected to the drain of the 0th PMOS transistor MP0, a second NMOS transistor MN2 whose gate receives the fourth signal AN, whose drain is connected to the drain of the second PMOS transistor MP2, and whose source is connected to the drain of the 0th NMOS transistor MN0, a fifth PMOS transistor MP5 whose gate receives the fourth signal AN and whose source is connected to the drain of the seventh PMOS transistor MP7, and a fifth NMOS transistor MN5 whose gate receives the third signal A, whose drain is connected to the drain of the fifth PMOS transistor MP5, and whose source is connected to the drain of the seventh NMOS transistor MN7.

[0019] Also, the drain of the first PMOS transistor MP1 is connected to the drain of the fourth PMOS transistor MP4 to output the first arithmetic signal Y, and the drain of the second PMOS transistor MP2 is connected to the drain of the fifth PMOS transistor MP5 to output the second arithmetic signal YN.

[0020] Also, as shown in FIG. 3, the comparison system may include a plurality of comparison circuits 1, and the outputs of some of the comparison circuits 1 may be used as the inputs of other comparison circuits 1. The comparison system can be applied to a memory system, for example, it can be applied to the technology of error correction coding for a memory system.

[0021] In the comparison system provided in the embodiments of the present application, the first logic unit 11 configured to implement exclusive OR logic and the second logic unit 12 configured to implement exclusive NOR logic are connected to the same shared module 10. Therefore, the area occupied by the circuit structure of the shared module 10 can be reduced. Furthermore, by increasing the circuit areas corresponding to the first logic unit 11 and the second logic unit 12 to enhance the driving capabilities of the first logic unit 11 and the second logic unit 12, the operation speed at which the comparison system performs exclusive NOR operations and exclusive OR operations can be increased.

[0022] In some embodiments of the present application, a comparison system that is substantially the same as the foregoing embodiments is further provided, which is different in that the comparison system can also be applied to a memory system. Hereinafter, the comparison system will be described in detail with reference to the drawings. It should be noted that for parts that are the same as or equivalent to those in the above embodiments, reference may be made to the detailed description of the foregoing embodiments, and details will not be described herein.

[0023] FIG. 4 is a schematic diagram of a comparison system and a memory system provided in an embodiment of the present application.

[0024] In some embodiments of the present application, the comparison system 20 includes at least one comparison circuit including a shared module, a first logic unit, and a second logic unit. For the specific structure of the comparison circuit, reference may be made to the detailed description of the foregoing embodiments.

[0025] In an embodiment of the present application, as shown in FIG. 4, the comparison system 20 is applied to a memory system 101 that writes or reads a plurality of data during a read / write operation. The plurality of data are divided into M bytes, each byte has N data, and both M and N are positive natural numbers.

[0026] The comparison system 20 receives a plurality of data, each data is used as a first signal or a third signal, and a first encoding operation is performed based on some data in each byte to generate X first check codes. Some data corresponding to the same first check code have the same bits in different bytes Position and is configured to perform a second encoding operation based on all data in some bytes to generate Y second check codes. The X first check codes are for error detection and / or error correction for the N data in each byte, and the Y second check codes are for error detection and / or error correction for the M bytes. Both X and Y are positive natural numbers.

[0027] In an embodiment of the present application, the memory system 101 may be DRAM, for example, DDR4, LPDDR4, DDR5, or LPDDR5. The memory system 101 may also be other types of memory systems, for example, non-volatile memories such as NAND, NOR, FeRAM, PcRAM, etc. In the memory system 101, data is divided into different bytes, and the first check code is for error detection and / or error correction for N data within each byte, and the second check code is for error detection and / or error correction for M bytes. Such an encoding method by error detection and error correction can not only implement ECC, but also implement ECC with fewer hardware circuits, contributing to reducing the power consumption of the memory system and optimizing the speed and result of ECC.

[0028] It should be noted that the first check code described in the embodiment of the present application is for error detection and / or error correction for N data within each byte, and the second check code is for error detection and / or error correction for M bytes. It should be understood that all the first check codes and the second check codes are both used for error detection and / or error correction for all the data of M bytes. The second check code is used to identify which byte among the M bytes the incorrect data is in, and the first check code is used to identify which bit in the byte the incorrect data is in.

[0029] Normally, a byte is the basic unit of data processing. There is a regulation that information is stored and interpreted in byte units, and 1 byte consists of 8 binary bits, that is, 1 byte is equal to 8 bits, and each bit among the 8 bits has a corresponding bit Position and, that is, 1Byte = 8bit. Based on this, in an embodiment of the present application, N is 8, whereby the bits in each byte Position are maximized, contributing to improving the utilization rate of the circuits required for the comparison system 20. It is understandable that in other embodiments, N may be other appropriate positive integers.

[0030] Taking the example that the data transmitted by the memory system 101 in one read / write operation is 128 bits (i.e., 128 bits), M is 16 and N is 8. It should be noted that in other embodiments, depending on the number of bits of the data transmitted by the memory system during the read / write operation, M may be other appropriate positive integers, as long as M*N is equal to the number of bits of the data transmitted during the read / write operation.

[0031] FIG. 5 is a classification schematic diagram of multiple data provided in an embodiment of the present application, and a schematic diagram of the relationship between the first check code and the second check code. Each bit of the N data Position is different. In the embodiment of the present application, as shown in FIG. 5, for each byte, the N data have bits from bit 0 to bit 7 that increase as natural numbers Position All M bytes are divided into 16 bytes that increase from 0 to 15 as natural numbers for all bytes. Also, for different bytes, the N data within the byte all have 8 bits Position that increase from 0 to 7.

[0032] It should be noted that due to position limitations, the table that should actually be in the same row in FIG. 5 is decomposed into three tables, but it is actually one complete table. For the convenience of illustration, FIG. 6 schematically shows an enlarged view of the first check code corresponding to byte 0.

[0033] FIG. 7 is a functional block diagram of a comparison system provided in an embodiment of the present application. As shown in FIG. 7, the comparison system 20 (see FIG. 4) includes a first comparison module 102 composed of a plurality of the comparison circuits. The first comparison module 102 is configured to receive a plurality of data and perform a comparison process during the write operation of the memory system 101 (see FIG. 4), and generate X first check codes and Y second check codes.

[0034] Since the first comparison module 102 includes a plurality of comparison circuits, exclusive NOR operations or exclusive OR operations can be performed on some of the plurality of data to generate a first check code and a second check code.

[0035] In an embodiment of the present application, as shown in FIG. 7, the first comparison module 102 includes a plurality of first comparison units 112 and a plurality of second comparison units 122. Each first comparison unit 112 is configured to receive some data within each byte during the write operation of the memory system 101, perform comparison processing, and output one first check code. Each first comparison unit 112 correspondingly receives some data combined with different bits in a byte. Each second comparison unit 122 is configured to receive all data within some bytes during the write operation of the memory system 101, perform comparison processing, and output one second check code. Each second comparison unit 122 correspondingly receives all data combined with different bytes.

[0036] The first comparison unit 112 consists of some of the comparison circuits, and the second comparison unit 122 consists of some of the comparison circuits. Hereinafter, the first comparison unit 112 and the second comparison unit 122 will be described in detail.

[0037] 2 X is ≧ N, and each first check code is obtained by performing a first encoding operation on some data within all bytes, and some data corresponding to each first check code corresponds to different bit combinations in a byte. That is, each first check code is obtained by selecting a plurality of bits of data within each byte and performing a first encoding operation. For the same first check code, the bit combinations selected in all bytes are the same. For different first check codes, the bit combinations selected in N data are different.

[0038] In an embodiment of the present application, different first check codes are obtained by performing a first encoding operation based on different target data within all bytes. As a result, for different first check codes, the bits Position of affecting the result of the first check code are different. Also, since 2 X ≥ N, the first check codes obtained by each bit being selected for the first encoding operation are not completely the same, so that it is possible to obtain which bit Position the data corresponding to is incorrect through analysis. The first encoding operation is performed by the first comparison unit 112, that is, the first comparison unit 112 performs an exclusive OR operation or a negative exclusive OR operation.

[0039] In an embodiment of the present application, M is 16, N is 8, and X is 3. The number of first comparison units 112 is 3, and the number of second comparison units 122 is 5. If X is 3, it satisfies the requirement that errors in data of different bits Position can all be detected, and the complexity of the hardware circuit of the first comparison unit 112 can be reduced.

[0040] In some embodiments of the present application, the three first check codes include the first check code of the 0th bit, the first check code of the 1st bit, and the first check code of the 2nd bit in ascending order of bits Position with low values, and the N data are bits that increase from 0 to N - 1 in natural numbers PositionIt has. For example, the 0th bit is not involved in any of the first encoding operations corresponding to the first check codes, the 1st bit is involved in the first encoding operation corresponding to the first check code of the 0th bit, the 2nd bit is involved in the first encoding operation corresponding to the first check code of the 1st bit, the 3rd bit is involved in the first encoding operation corresponding to the first check codes of the 0th bit and the 1st bit, the 4th bit is involved in the first encoding operation corresponding to the first check code of the 2nd bit, the 5th bit is involved in the first encoding operation corresponding to the first check codes of the 0th bit and the 2nd bit, the 6th bit is involved in the first encoding operation corresponding to the first check codes of the 1st and 2nd bits, and the 7th bit is involved in the first encoding operation corresponding to the first check codes of the 0th, 1st, and 2nd bits. It should be understood that a person skilled in the art can set the number of the first check codes and other encoding operation relationships as necessary, as long as it satisfies that the first check codes obtained by each bit being selected for the first encoding operation are not exactly the same.

[0041] Taking the first encoding operation as an exclusive OR as an example, the three first comparison units 112 are respectively configured as follows. One first comparison unit 112 is configured to perform an exclusive OR operation on the data of the 1st, 3rd, 5th, and 7th bits in all bytes to generate a first check code at the least significant bit. Another first comparison unit 112 is configured to perform an exclusive OR operation on the data of the 4th, 5th, 6th, and 7th bits in all bytes to generate a first check code at the most significant bit. Still another first comparison unit 112 is configured to perform an exclusive OR operation on the data of the 2nd, 3rd, 6th, and 7th bits in all bytes to generate a first check code at the middle bit.

[0042] It should be noted that in other embodiments, the first encoding operation may be an exclusive NOR operation. Accordingly, one first comparison unit is configured to perform an exclusive NOR operation on the data of the first, third, fifth, and seventh bits in all bytes to generate one first check code, and another first comparison unit is configured to perform an exclusive NOR operation on the data of the fourth, fifth, sixth, and seventh bits in all bytes to generate another first check code. Still another first comparison unit is configured to perform an exclusive NOR operation on the data of the second, third, sixth, and seventh bits in all bytes to generate still another first check code.

[0043] Each second comparison unit 122 is configured to generate one second check code, and Y second check codes constitute a Y-bit second binary number. 2 Y ≧M, and each second check code is obtained by performing a second encoding operation on several bytes. In the embodiments of the present application, the second encoding operation is realized by the second comparison unit 122 and may be an exclusive NOR operation or an exclusive OR operation.

[0044] 2 YSince it is ≧M, the second check codes obtained by each byte participating in the second encoding operation are not exactly the same. In the embodiments of the present application, different second check codes are obtained by performing the second encoding operation based on several different bytes, so that for different second check codes, the bytes affecting the result of the second check code are different. Furthermore, it is possible to comprehensively analyze and obtain which data in which byte is incorrect. Finally, based on which bit in the byte is incorrect, it is determined which bit data in which byte is incorrect. It should be noted that the influence on the result of the second check code described here means that if the data in a specific byte is incorrect, the specific second check code obtained by performing the second encoding operation again is different from the second check code formed before the data is incorrect. In the embodiments of the present application, Y is 5, which satisfies that errors in data of different bytes can all be detected, and at the same time, the complexity of the hardware circuit of the second comparison unit 122 can be reduced.

[0045] In the embodiments of the present application, the M bytes are divided into bytes from 0 to 15 so as to increase as natural numbers, and the Y second check codes are divided into second check codes from 3 to 7 so as to increase as natural numbers. The acquisition methods of the five second check codes are as follows respectively.

[0046] The third second check code (corresponding to p13 in FIG. 5) is the exclusive logical sum or the exclusive logical sum of negation of all data of bytes 0, 2, 3, 4, 5, 6, and 8. The fourth second check code (corresponding to p14 in FIG. 5) is the exclusive logical sum or the exclusive logical sum of negation of all data of bytes 0, 1, 4, 5, 7, 9, 10, and 12. The fifth second check code (corresponding to p15 in FIG. 5) is the exclusive logical sum or the exclusive logical sum of negation of all data of bytes 1, 2, 4, 6, 9, 11, 13, and 14. The sixth second check code (corresponding to p16 in FIG. 5) is the exclusive logical sum or the exclusive logical sum of negation of all data of bytes 3, 5, 6, 7, 10, 11, 14, and 15. The seventh second check code (corresponding to p17 in FIG. 5) is the exclusive logical sum or the exclusive logical sum of negation of all data of bytes 8, 9, 10, 11, 12, 13, and 15.

[0047] It should be noted that each second check code is obtained by exclusive logical sum operation or each second check code is obtained by exclusive logical sum of negation operation.

[0048] Accordingly, the circuit corresponding to the second comparison unit 122 is designed as follows.

[0049] An exclusive logical sum is performed on the exclusive logical sum result of byte 0 and byte 4 to obtain result 0_4. An exclusive logical sum is performed on the result of byte 2 and byte 6 to obtain result 2_6. An exclusive logical sum is performed on the result of byte 3 and byte 5 to obtain result 3_5. An exclusive logical sum is performed on the result of byte 1 and byte 5 to obtain result 1_5. An exclusive logical sum is performed on the result of byte 1 and byte 4 to obtain result 1_4.

[0050] As shown in FIG. 8, FIG. 8 schematically shows a principle diagram of performing a second encoding operation on all bytes. As is clear from the figure, compared with bytes 0 to 7, the operations of bytes 8 to 15 can be completed using the same circuit set, that is, by only changing the input, the same operations can be performed on bytes 8 to 15, and results 9_13, result 10_12, result 11_15, result 10_14, and result 11_14 can be obtained. In addition to these operations that can use the same circuit, an exclusive OR operation is performed on bytes 6 and 7 to obtain result 6_7, and an exclusive OR operation is also required to be performed on the results of bytes 7 and 9 to obtain result 7_9.

[0051] An exclusive OR operation is performed according to the expression requirements of pc3 to pc7. For example, according to the expression pc3, an exclusive OR operation is performed on the exclusive OR results of result 0_4, result 2_6, result 3_5, and byte 8 to obtain the second check code p13 (see FIG. 5). According to the expression pc4, an exclusive OR operation is performed on result 0_4, result 1_5, result 7_9, and result 10_12 to obtain the second check code p14 (see FIG. 5). The method of obtaining the second check codes p15, p16, and p17 (see FIG. 5) will not be specifically described. Understandably, result 0_4, result 2_6, etc. can all be reused, thereby saving circuit resources.

[0052] In addition, in the embodiment of the present application, the second comparison unit 122 may further be configured such that the number of times each byte participates in the second encoding operation is a, where a satisfies (Y - 1) / 2 ≤ a ≤ (Y + 1) / 2 and a is a positive integer. Such a setting can reduce the wiring and area of the decoding circuit required in the subsequent decoding stage and contribute to improving the decoding speed.

[0053] Hereinafter, the generation principle of the first check code will be described with reference to FIGS. 5 and 6.

[0054] As shown in FIGS. 5 and 6, "×" indicates that it is currently involved in the encoding operation of this row, that is, it indicates performing an exclusive NOR or exclusive OR operation, and 128-bit data is divided into a total of 16 bytes from byte 0 to byte 15, and each byte has 8 bits. p10, p11, and p12 represent three first check codes, p13, p14, p15, p16, and p17 represent five second check codes, and pc0 to pc7 represent eight arithmetic expressions adopted corresponding to p10 to p17 during the encoding operation. In each row, all the places marked with "×" indicate that the data corresponding to this column needs to be involved in the exclusive OR or exclusive NOR operation within this arithmetic expression. The first check code and the second check code correspond to pb.

[0055] During the first encoding operation or the second encoding operation in the encoding stage, the first encoding operation or the second encoding operation is performed by the eight arithmetic expressions of pc0 to pc7, and the results of the operations are stored in p10 to p17 respectively, and p10 to p17 are not involved in the first encoding operation or the second encoding operation. In the decoding stage, the arithmetic expressions corresponding to each row remain unchanged, and since p10 to p17 stored need to be involved in the operation, p10 to p17 in the table of FIG. 5 are marked with "×" accordingly, and this will be described in detail later.

[0056] In the embodiment of the present application, in the encoding stage, for each byte, an exclusive OR or exclusive NOR is performed on the data of the 1st, 3rd, 5th, and 7th bits within this byte, and further an exclusive OR or exclusive NOR is performed on all the exclusive OR results or exclusive NOR results of 16 bytes, that is, the calculation formula of pc0 is adopted, and the calculation result is given to p10. For each byte, an exclusive OR or exclusive NOR is performed on the data of the 2nd, 3rd, 6th, and 7th bits within this byte, and further an exclusive OR or exclusive NOR is performed on all the exclusive OR results or exclusive NOR results of 16 bytes, the pc1 calculation formula is adopted, and the calculation result is given to p11. For each byte, an exclusive OR or exclusive NOR is performed on the data of the 4th, 5th, 6th, and 7th bits within this byte, and further an exclusive OR or exclusive NOR is performed on all the exclusive OR results or exclusive NOR results of 16 bytes, that is, the pc2 calculation formula is adopted, and the calculation result is given to p12.

[0057] p10, p11, and p12 constitute the first binary number, and p10 is the least significant bit and p12 is the most significant bit. When only 1-bit data among the multiple data of the memory system 101 (see FIG. 4) is incorrect, the following is clear.

[0058] If the data of the 0th bit is incorrect, since the 0th bit is not involved in the three calculation formulas of pc0, pc3, and pc3, none of the first check codes p10, p11, and p12 are affected.

[0059] If the data of the 1st bit is incorrect, since the 1st bit is not involved in the two calculation formulas of pc1 and pc2 and is involved in the calculation formula of pc0, the first check code p10 is affected, and the first check codes p11 and p12 are not affected.

[0060] If the data of the 2nd bit is incorrect, since the 2nd bit is involved in the calculation formula of pc1, the first check codes p10 and p12 are not affected, and the first check code p11 is affected.

[0061] If the data of the third bit is incorrect, since the third bit is involved in the two arithmetic expressions of pc0 and pc1, both the first check codes p10 and p11 are affected, and the first check code p12 is not affected.

[0062] Similarly, if the data of the seventh bit is incorrect, since the seventh bit is involved in the three arithmetic expressions of pc0, pc1, and pc2, all the first check codes p10, p11, and p12 are affected.

[0063] It should be noted that the fact that a specific first check code is affected when a specific piece of data here is incorrect means that when a specific piece of data is incorrect, the specific first check code obtained by performing the first encoding operation again is different from the first check code formed before the data was incorrect.

[0064] Understandably, for each arithmetic expression, the bits Position in different bytes involved in the first encoding operation Position are the same. Therefore, it is possible to obtain which bit Position of the data is incorrect by the first check code, but it is impossible to detect which corresponding bit Position in which byte of the data is incorrect. Therefore, it is necessary to further obtain which corresponding bit

[0065] in which byte of the data is incorrect by the second check code.

[0066] In addition, in the embodiments of the present application, the comparison system 20 may include a second comparison module 202 (see FIG. 7) composed of a plurality of comparison circuits, and is configured to receive a plurality of data, X first check codes, and Y second check codes during the read operation of the memory system 101, and the first check code, the second check code, or the data is used as the first signal or the third signal. The second comparison module 202 performs a third encoding operation on some data and X first check codes in each byte to generate X first operation codes corresponding to each one first check code, and performs a fourth encoding operation on all data and Y second check codes in some bytes to generate Y second operation codes corresponding to each one second check code. The third encoding operation is an exclusive NOR or an exclusive OR, and the fourth encoding operation is an exclusive NOR or an exclusive OR.

[0067] In the embodiments of the present application, the third encoding operation and the first encoding operation involve the same number of bits of the data involved in the operation Position However, they are different in that the first check code is also involved in the operation in the third encoding operation. The fourth encoding operation and the second encoding operation involve the same number of bytes of the data involved in the operation, and they are different in that the second check code is also involved in the operation in the fourth encoding operation.

[0068] Generally, the decoding stage is performed in the data reading process during the read operation. In the embodiments of the present application, according to the above description of FIG. 5 and the generation principles of the first check code and the second check code, the encoding operation in the decoding stage is based on the encoding operation in the aforementioned encoding stage, and an exclusive OR operation is respectively performed on the first check codes p10, p11, or p12 to obtain the corresponding first operation codes p20, p21, or p22 accordingly. That is, for the first operation code p20, using the arithmetic formula of pc0, different bits Position of the data in each received byte and the first check code p10 are subjected to a third encoding operation to obtain the first operation code p20, and using the pc1 arithmetic formula, different bits PositionPerform a third encoding operation on the data of Position and the first check code p11 to obtain a first operation code p21. Using the pc2 arithmetic formula, different bits within each received byte

[0069] Similarly, for the second check code and the second operation code, the encoding operation in the decoding stage needs to perform an exclusive OR on the second check codes p13, p14, p15, p16, or p17 respectively based on the encoding operation in the aforementioned encoding stage, and correspondingly obtain the second operation codes p23, p24, p25, p26, or p27.

[0070] p20, p21, and p22 form a second binary number, with p20 being the least significant bit and p22 being the most significant bit. If only 1-bit data among multiple data in the memory is incorrect, if the third encoding operation is an exclusive OR (it may be a negative exclusive OR in other embodiments), the following is clear.

[0071] If the data of the 0th bit is incorrect, since the 0th bit is not involved in the three arithmetic formulas of pc0, pc1, and pc2, all of the first operation codes p20, p21, and p22 are 0. To detect that the data of the 0th bit is incorrect, the second binary number is 000, and the corresponding decimal number is 0.

[0072] If the data of the 1st bit is incorrect, since the 1st bit is not involved in the two arithmetic formulas of pc1 and pc2 and is involved in the arithmetic formula of pc0, the first operation code p20 is 1, and the first operation codes p21 and p22 are 0. To detect that the data of the 1st bit is incorrect, the second binary number is 001, and the corresponding decimal number is 1.

[0073] If the data of the second bit is incorrect, since the second bit is involved in the arithmetic formula of pc1, the first arithmetic code p20 is 0, the first arithmetic code p21 is 1, p12 is 0, and so that the incorrect data of the second bit can be detected, the second binary number is 010, and the corresponding decimal number is 2.

[0074] If the data of the third bit is incorrect, since the third bit is involved in the two arithmetic formulas of pc0 and pc1, both the first arithmetic codes p20 and p21 are 1, p12 is 0, and so that the incorrect data of the third bit can be detected, the second binary number is 011, and the corresponding decimal number is 3.

[0075] Similarly hereinafter, if the data of the seventh bit is incorrect, since the seventh bit is involved in the three arithmetic formulas of pc0, pc1 and pc2, all the first arithmetic codes p20, p21 and p22 are 1, and so that the incorrect data of the seventh bit can be detected, the second binary number is 111, and the corresponding decimal number is 7.

[0076] Referring to FIG. 7, as can be seen from the acquisition principles of the above first arithmetic formula and second arithmetic formula, the second comparison module 202 includes one or more third comparison units 212, one or more fourth comparison units 222, one or more fifth comparison units 232, and one or more sixth comparison units 242.

[0077] The third comparison unit 212 includes the at least one comparison circuit, and each third comparison unit is configured to receive some data in each byte and perform comparison processing during the read operation of the memory system, and output one first update check code, and each third comparison unit 212 correspondingly receives some data combined with different bits in the byte.

[0078] The fourth comparison unit 222 includes the at least one comparison circuit. Each fourth comparison unit 222 is configured to receive all data within several bytes during a read operation of the memory system, perform comparison processing, and output one second update check code. Each fourth comparison unit 222 correspondingly receives all data combined with different bytes.

[0079] The fifth comparison unit 232 includes the at least one comparison circuit. Each first check code and one first update check code are used as a first signal and a third signal corresponding to one fifth comparison unit 232. Each fifth comparison unit 232 outputs one first operation code.

[0080] The sixth comparison unit 242 includes the at least one comparison circuit. Each second check code and the second update check code are used as a first signal and a third signal corresponding to one sixth comparison unit 242. Each sixth comparison unit 242 outputs one second operation code.

[0081] In an embodiment of the present application, the number of the third comparison units 212 may be the same as the number of the first comparison units 112, and the number of the fourth comparison units 222 may be the same as the number of the second comparison units 122. Understandably, in an embodiment of the present application, the third comparison unit 212 and the first comparison unit 112 may share a comparison circuit, and the fourth comparison unit 222 and the second comparison unit 122 may share a comparison circuit.

[0082] In an embodiment of the present application, according to FIGS. 7 and 9, the memory system 20 may further include a decoding module 203 configured to receive X first operation codes and Y second operation codes and identify an incorrect data position. In an embodiment of the present application, the X first operation codes are used to identify incorrect bits, and the Y second operation codes are used to identify incorrect bytes. For the specific principles and explanations of using the first operation codes and the second operation codes to identify incorrect data, reference may be made to the related explanations of the first check code and the second check code above, which will not be elaborated here.

[0083] FIG. 9 is a specific configuration diagram of a decoding module in the memory system provided in the embodiment of the present application. Referring to FIG. 9, the decoding module 203 includes M decoding units 31 each corresponding to 1 byte, which are configured to perform decoding processing on X first operation codes and Y second operation codes, obtain whether there is incorrect data in the byte, and identify the bits of the incorrect data, and includes the decoding unit 31. In FIG. 9, p20, p21, and p22 indicate the first operation codes, and p23, p24, p25, p26, and p27 indicate the second operation codes. In an embodiment of the present application, each decoding unit 31 performs decoding processing on the X first operation codes and the Y second operation codes corresponding to the byte.

[0084] That is, the number of decoding units 31 is the same as the number of bytes.

[0085] FIG. 10 is an enlarged configuration diagram of the decoding unit corresponding to byte 5 in the decoding module provided in the embodiment of the present application.

[0086] Referring to FIG. 10, in an embodiment of the present application, the decoding unit 31 (refer to FIG. 9) is a decoder 301 configured to receive X first operation codes and output N first decoding signals, and each first decoding signal is 1 bit of N data PositionA decoder corresponding thereto, and a first AND gate unit 302 configured to receive at least two selected operation codes and perform a logical AND operation, wherein the selected operation codes are second operation codes obtained after performing an encoding operation on the second check codes corresponding to the corresponding bytes among the Y second check codes; a first AND gate unit; a NOR gate unit 303 configured to receive at least two unselected operation codes and perform a negative logical sum operation, wherein the unselected operation codes are second operation codes among the Y second operation codes excluding the selected operation codes; a NOR gate unit; and N second AND gate units 304 each having an input terminal connected to the output terminal of the first AND gate unit 302, the output terminal of the NOR gate unit 303, and one first decoding signal, and configured to obtain an incorrect data position based on the output thereof.

[0087] It should be noted that FIG. 10 only shows the connection relationship between one first decoding signal and one second AND gate unit 304.

[0088] In the embodiment of the present application, the decoder 301 is a 3-8 decoder, with three input terminals respectively receiving three first operation codes, eight output terminals outputting eight first decoding signals, and each first decoding signal respectively representing the status of 8-bit data within the same byte.

[0089] In the embodiment of the present application, the first operation codes p20, p21, and p22 are 0 or 1, and the output terminals are represented by 0 to 7. When the 0th bit is incorrect and the 0th bit is not involved in the encoding operation of the first operation code, p20, p21, and p22 are all 0, and accordingly, the output terminal of "0" is 1, and the remaining output terminals are all 0. When the 1st bit is incorrect, p20 is 1, p21 and p22 are 0, and accordingly, the output terminal of "1" is 1, and the remaining output terminals are all 0. Similarly hereinafter, when the 7th bit is incorrect, p20, p21, and p22 are all 1, and accordingly, the output terminal of "7" is 1, and the remaining output terminals are all 0.

[0090] It should be noted that in other embodiments, the number of input terminals and output terminals of the decoder can also be reasonably set according to the first check code and the number of bits in each byte.

[0091] The first AND gate unit 302 has the characteristic that if all input terminals are 1, the output terminal is 1, and if one or more of the input terminals are 0, the output terminal is 0. In the embodiment of the present application, the first AND gate unit 302 has three input terminals. Further, when the number of selected operation codes is 2, one input terminal of the first AND gate unit 302 is connected to the power supply V DD is configured to be connected.

[0092] The NOR gate unit 303 has the characteristic that if all input terminals are 0, the output is 1, and if one or more of the input terminals are 1, the output terminal is 0. In the embodiment of the present application, the NOR gate unit has three input terminals. Further, when the number of unselected operation codes is 2, one input terminal of the NOR gate unit 303 is connected to the ground signal V ss is configured to be connected.

[0093] Accordingly, in the embodiment of the present application, the selected operation code is the second operation code obtained after performing a fourth encoding operation on the corresponding second check code for this byte, and the unselected operation code is the second operation code obtained after performing a fourth encoding operation on the other second check codes excluding the corresponding second check code for this byte.

[0094] For example, for byte 0, if the second operation codes p23 and p24 are the second operation codes obtained by performing a fourth encoding operation on the second check codes p13 and p14 corresponding to byte 0, the second operation codes p23 and p24 are input to the input ends of the first AND gate unit 302, and the remaining second operation codes p25, p26, and p27 are input to the input ends of the NOR gate unit 303. For byte 1, if the second operation codes p24 and p25 are the second operation codes obtained by performing a fourth encoding operation on the second check codes p14 and p15 corresponding to byte 1, the second operation codes p24 and p25 are input to the input ends of the first AND gate unit 302, and the remaining second operation codes p23, p26, and p27 are input to the input ends of the NOR gate unit 303. For byte 4, the second operation codes p23, p24, and p25 are input to the input ends of the first AND gate unit 302, and the remaining second operation codes p26 and p27 are input to the input ends of the NOR gate unit 303. For other bytes, they are not specifically enumerated.

[0095] The number of the second AND gate units 304 is the same as the number of bits in the same byte. In the embodiment of the present application, if N is 8, correspondingly, there are 8 second AND gate units 304, and based on the outputs of the 8 second AND gate units 304, it is determined whether there is incorrect data in the byte and which bit is incorrect.

[0096] As is obvious, in the embodiments of the present application, although the circuits of the decoding unit 31 for each byte are all the same, only the wiring of the input ends is different. Moreover, the wiring of the input ends of the first AND gate unit 302 and the NOR gate unit 303 corresponding to each byte is determined by five arithmetic expressions from pc3 to pc7 in FIG. 2. For each byte, after performing the fourth encoding operation on the corresponding second check code, the obtained second operation code is connected to the input end of the first AND gate unit 302. After performing the fourth encoding operation on the other second check codes except the corresponding second check code, the obtained second operation code is connected to the input end of the NOR gate unit 303. Also, the input end of the unused first AND gate unit 302 is connected to the power supply, the input end of the unused NOR gate unit 303 is grounded, and the first operation code is connected to the input end of the decoder 301. Therefore, only eight wirings are used for the connection to the input end of the decoding unit 301. Each wiring transmits one first operation code or one second operation code, thereby reducing the wiring path and area and contributing to the improvement of the decoding speed.

[0097] To easily understand the decoding circuit, taking the decoding unit corresponding to byte 5 as an example, the decoding circuit will be described in more detail below based on the operating principle of the decoding circuit.

[0098] If there is a 1 in the output of one of the eight second AND gate units 304, it indicates that 1 bit of data in the byte is incorrect. In the embodiments of the present application, the data of this byte is incorrect. The second operation codes p23, p24, and p26 are all 1. The output of the first AND gate unit 302 is 1. The unselected operation codes p25 and p27 are both 0. The output of the NOR gate unit 303 is 1. In this case, when identifying the first decoding signal corresponding to the second AND gate unit 304 whose output is 1 among the N second AND gate units 304, the bit Position of the data corresponding to this first decoding signal is incorrect.

[0099] As an understandable example, in the embodiments of the present application, if the first decoded signal is 1, it is exemplified that the data of the corresponding bit Position is incorrect, and if the first decoded signal is 0, the data of the corresponding bit Position is correct. In other embodiments, if the first decoded signal is 0, the data of the corresponding bit Position is incorrect, and if the first decoded signal is 1, the data of the corresponding bit Position is correct. Accordingly, those skilled in the art can design other parts as needed, for example, by connecting the first decoded signal to a NOT gate circuit and outputting it.

[0100] It should be noted that when all the data within M bytes are not incorrect and only 1 bit in the X first check codes is incorrect, one of the first operation codes becomes 1, and one output of the decoder 301 becomes 1. However, since all the Y second check codes are not incorrect, all the second operation codes are 0. Further, the output of the first AND gate unit 302 is 0, and the outputs of the second AND gate unit 304 are also all 0, indicating that all the data within M bytes are not incorrect. When all the data within M bytes are not incorrect and only 1 bit in the Y second check codes is incorrect, all the first operation codes become 0, and the 0 output terminal of the decoder 301 becomes 1. However, since the remaining Y - 1 second check codes are not incorrect, the corresponding Y - 1 second operation codes are 0. The output of the first AND gate unit 302 is 0, and further, the outputs of the second AND gate unit 304 are also all 0, indicating that all the data within M bytes are not incorrect.

[0101] Understandably, in the embodiments of the present application, a first operation code is generated based on a first check code, and the position of incorrect data in bytes is identified by the first operation code generated based on the first check code. Therefore, the first check code is for error detection and / or error correction for N data within each byte. A second operation code is generated based on a second check code, and the position of an incorrect byte is identified by the second operation code generated based on the second check code. Therefore, the second check code is for error detection and / or error correction for M bytes.

[0102] The embodiments of the present application provide a comparison system with excellent structural performance applicable to a memory system, which can detect and correct 1-bit errors, reduce the hardware circuit, further reduce the power consumption of the memory system, increase the encoding speed and decoding speed, and increase the speed at which the memory system performs error detection and error correction. Also, due to the special design of the first check code and the second check code, the difference in encoding time for all data combinations is reduced, and the difference in decoding time for all data combinations is also reduced, thereby reducing the requirements for the comparison system.

[0103] Each of the above embodiments is a specific example for implementing the present application. It is understood by those skilled in the art that various changes can be made to the form and details without departing from the spirit and scope of the present application in actual applications. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application. Therefore, the protection scope of the present application should conform to the scope limited by the claims.

Industrial Applicability

[0104] Embodiments of the present application provide a comparison system comprising at least one comparison circuit. The comparison circuit includes a shared module configured to be controlled to output a power signal or a ground signal based on a first signal and a second signal that are in inverse phase with each other, a first logic unit connected to the shared module, receiving a third signal and a fourth signal that are in inverse phase with each other, and configured to output a first operation signal that is an exclusive OR of the first signal and the third signal, and a second logic unit connected to the shared module, receiving the third signal and the fourth signal that are in inverse phase with each other, and configured to output a second operation signal that is a negative exclusive OR of the first signal and the third signal.

[0105] Since the first logic unit and the second logic unit share the same shared module, the circuit area can be reduced and the efficiency of error detection and error correction can be improved. Also, since the area occupied by the circuit of the shared module is small, it contributes to an increase in the circuit area of the first logic unit and the second logic unit, thereby increasing the speed at which the comparison system performs exclusive OR operations and negative exclusive OR operations. For example, when the comparison system is applied to error correction of a memory system, it contributes to an improvement in the speed of error detection and error correction for the memory system.

Claims

**Claim 1**: A memory system, a memory configured to write or read a plurality of data during read / write operations, wherein the plurality of data is divided into M bytes, and each of the bytes has N data; a comparison system configured to receive the plurality of data and perform a first encoding operation based on one or more data in each of the bytes to generate X first check codes during a write operation of the memory system, wherein the one or more data corresponding to the same first check code have the same bit positions in different bytes, and perform a second encoding operation based on all data in one or more of the bytes to generate Y second check codes during the write operation of the memory system, wherein the X first check codes are for error detection and / or error correction for the N data in each of the bytes, and the Y second check codes are for error detection and / or error correction for the M bytes, wherein the comparison system includes a second comparison module; the second comparison module is configured to receive the plurality of data, the X first check codes, and the Y second check codes during a read operation of the memory system; the second comparison module is further configured to perform a third encoding operation on one or more data in each of the bytes and the X first check codes to generate X first operation codes, each of the first operation codes corresponding to one of the first check codes, and perform a fourth encoding operation on all data in one or more of the bytes and the Y second check codes to generate Y second operation codes, each of the second operation codes corresponding to one of the second check codes; wherein M, N, X, and Y are all positive natural numbers; a memory system. **Claim 2**: The first encoding operation is an exclusive NOR or exclusive OR, the second encoding operation is an exclusive NOR or exclusive OR, the third encoding operation is an exclusive NOR or exclusive OR, and the fourth encoding operation is an exclusive NOR or exclusive OR. The memory system according to Claim 1. **Claim 3** The second comparison module includes one or more third comparison units, one or more fourth comparison units, one or more fifth comparison units, and one or more sixth comparison units. Each of the third comparison units is configured to receive one or more data within each byte during the read operation of the memory system, perform a comparison process, and output one first update check code. Each of the third comparison units correspondingly receives one or more data combined with different bits in the byte. Each of the fourth comparison units is configured to receive all the data within one or more of the bytes during the read operation of the memory system, perform a comparison process, and output one second update check code. Each of the fourth comparison units correspondingly receives all the data combined with different bytes. Each of the first check codes and one of the first update check codes are used as input signals corresponding to one of the fifth comparison units. Each of the fifth comparison units outputs one of the first operation codes. Each of the second check codes and the second update check code are used as input signals corresponding to one of the sixth comparison units. Each of the sixth comparison units outputs one of the second operation codes. The memory system according to claim 2.

4. The comparison system further includes a decoding module. The decoding module includes M decoding units, each of the decoding units corresponding to one of the bytes. The decoding module receives X of the first operation codes and Y of the second operation codes, decodes the X first operation codes and the Y second operation codes, thereby obtaining whether there is incorrect data within the byte and identifying the bits of the incorrect data. The memory system according to claim 1.

5. The decoding unit includes a decoder, a first AND gate unit, a NOR gate unit, and N second AND gate units. The decoder is configured to receive X of the first operation codes and output N first decoding signals. Each of the first decoding signals corresponds to one bit of the N data. The first AND gate unit is configured to receive at least two selected operation codes and perform a logical AND operation. The selected operation codes are the second operation codes obtained after performing the fourth encoding operation on the corresponding second check codes corresponding to the corresponding bytes among the Y second check codes. The NOR gate unit is configured to receive at least two unselected operation codes and perform a negative logical OR operation. The unselected operation codes are the second operation codes excluding the selected operation codes corresponding to the corresponding bytes. The input end of each second AND gate unit is connected to the output end of the first AND gate unit, the output end of the NOR gate unit, and one of the first decoding signals. Based on the outputs of the N second AND gate units, an incorrect data position is obtained. The storage system according to claim 4.

6. The first AND gate unit has three input ends. When the number of the selected operation codes is 2, the first AND gate unit is further configured such that one of the input ends of the first AND gate unit is connected to a power source. The NOR gate unit has three input ends. When the number of the unselected operation codes is 2, the NOR gate unit is further configured such that one of the input ends of the NOR gate unit is grounded. The storage system according to claim 5.

7. The comparison system further includes a first comparison module, and the first comparison module is configured to receive the plurality of data and perform a comparison process during a write operation of the storage system, and generate X first check codes and Y second check codes. The first comparison module includes a plurality of first comparison units and a plurality of second comparison units. Each first comparison unit is configured to receive one or more data within each byte and perform a comparison process during a write operation of the storage system, and output one first check code. Each first comparison unit correspondingly receives one or more data combined with different bits in the byte. Each of the second comparison units is configured to receive all data within one or more of the bytes during a write operation of the memory system, perform a comparison process, and output one of the second check codes. Each of the second comparison units correspondingly receives all data combined with different ones of the bytes. The memory system according to claim 1. **Claim 8**: M is 16, N is 8, X is 3, Y is 5, the number of the first comparison units is 3, and the number of the second comparison units is 5. The memory system according to claim 7.

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