Semiconductor device

Abstract

To provide a semiconductor device in which the number of processes during manufacturing can be reduced.SOLUTION: A semiconductor device of the embodiment has a first electrode, a first semiconductor region of the first conductive type, a second semiconductor region of the second conductive type, a third semiconductor region of the first conductive type, a first conductive portion, a first gate electrode, a second conductive portion, a second gate electrode, a first connection portion, and a second electrode. The first conductive portion is provided in the first semiconductor region through the first insulating portion. The first gate electrode faces the second semiconductor region in a second direction perpendicular to the first direction from the first electrode to the first semiconductor region. The second conductive portion is provided in the first semiconductor region through the second insulating portion. The second gate electrode faces the second semiconductor region in the second direction. The first connecting portion is provided above the second and third semiconductor regions and contacts the first and second gate electrodes. The second electrode is provided above the second semiconductor region and the third semiconductor region.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor devices.

Background Art

[0002] Semiconductor devices such as Metal Oxide Semiconductor Field Effect Transistor (MOSFET) are used for power conversion applications. When manufacturing a semiconductor device, it is desirable that the number of necessary processes be small.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] The problem to be solved by the present invention is to provide a semiconductor device capable of reducing the number of processes during manufacturing.

Means for Solving the Problems

[0005] The semiconductor device according to the embodiment includes a first electrode, a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type, a first conductive portion, a first gate electrode, a second conductive portion, a second gate electrode, a first connection portion, and a second electrode. The first semiconductor region is provided on the first electrode and is electrically connected to the first electrode. The second semiconductor region is provided on the first semiconductor region. The third semiconductor region is provided on a part of the second semiconductor region. The first conductive portion is provided in the first semiconductor region via a first insulating portion. The first gate electrode is provided in the first insulating portion and faces the second semiconductor region in a second direction perpendicular to a first direction from the first electrode toward the first semiconductor region. The second conductive portion is provided in the first semiconductor region via a second insulating portion and is separated from the first conductive portion in the second direction. The second gate electrode is provided in the second insulating portion and faces the second semiconductor region in the second direction. The first connection portion is provided above the second semiconductor region and the third semiconductor region, extends in the second direction, and contacts the first gate electrode and the second gate electrode. The second electrode is provided on the second semiconductor region and the third semiconductor region and is electrically connected to the second semiconductor region, the third semiconductor region, the first conductive portion, and the second conductive portion.

Brief Description of the Drawings

[0006]

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Best Mode for Carrying Out the Invention

[0007] Hereinafter, each embodiment of the present invention will be described with reference to the drawings. The drawings are schematic or conceptual, and the relationships between the thicknesses and widths of the respective parts, the ratios of the sizes between the parts, etc. are not necessarily the same as those in reality. Even when representing the same part, there are cases where the dimensions and ratios are represented differently in the drawings. In the present specification and each figure, the same elements as those already described are denoted by the same reference numerals, and detailed descriptions thereof are appropriately omitted. In the following description and drawings, n + , n - and p +, The notation of p represents the relative high or low of each impurity concentration. That is, the notation with a "+" indicates that the impurity concentration is relatively higher than the notation without either a "+" or a "-", and the notation with a "-" indicates that the impurity concentration is relatively lower than the notation without any. When both p-type impurities and n-type impurities are included in each region, these notations represent the relative high or low of the net impurity concentration after these impurities compensate each other. For each embodiment described below, each embodiment may be implemented by inverting the p-type and n-type of each semiconductor region.

[0008] FIG. 1 is a plan view showing a semiconductor device according to the first embodiment. FIG. 2 is an enlarged plan view of part A in FIG. 1. FIG. 3 is a cross-sectional view taken along line B1 - B2 in FIG. 2. FIG. 4 is a cross-sectional view taken along line C1 - C2 in FIG. 2. FIG. 2 corresponds to a cross-sectional view taken along line A1 - A2 in FIGS. 3 and 4. FIG. 5 is an enlarged plan view of part D in FIG. 1. FIG. 6 is a cross-sectional view taken along line E1 - E2 in FIG. 5. FIG. 5 corresponds to a cross-sectional view taken along line D1 - D2 in FIG. 6.

[0009] The semiconductor device according to the first embodiment is a MOSFET. As shown in FIGS. 1 to 6, the semiconductor device 100 according to the first embodiment includes an n - -type (first conductivity type) drift region 1 (first semiconductor region), a p-type (second conductivity type) base region 2 (second semiconductor region), an n + -type source region 3 (third semiconductor region), a p + -type contact region 4, an n + -type drain region 5, a p + -type contact region 6, an insulating portion 10, an insulating portion 15, a conductive portion 20, a gate electrode 30, a drain electrode 50 (first electrode), a source electrode 60 (second electrode), a gate pad 70, a gate wiring 71, an insulating portion 81, a conductive portion 82, and an electrode layer 83. Note that in FIGS. 2 and 5, the insulating portion 15 is omitted.

[0010] In the description of the embodiment, an XYZ orthogonal coordinate system is used. From the drain electrode 50 to the n -The direction toward the n-shaped drift region 1 is defined as the Z direction (the first direction). One direction orthogonal to the Z direction is defined as the X direction (the third direction). The direction orthogonal to the Z direction and intersecting the X direction is defined as the Y direction (the second direction). Here, the direction toward the n-shaped drift region 1 from the drain electrode 50 is called "up", and the opposite direction is called "down". These directions are based on the relative positional relationship between the drain electrode 50 and the n-shaped drift region 1 and are independent of the direction of gravity. - The direction toward the n-shaped drift region 1 is called "up", and the opposite direction is called "down". These directions are based on the relative positional relationship between the drain electrode 50 and the n-shaped drift region 1 and are independent of the direction of gravity. - These directions are based on the relative positional relationship between the drain electrode 50 and the n-shaped drift region 1 and are independent of the direction of gravity.

[0011] As shown in FIG. 1, on the upper surface of the semiconductor device 100, a source electrode 60, a gate pad 70, and a gate wiring 71 are provided. The gate pad 70 and the gate wiring 71 are separated from the source electrode 60 and are electrically isolated from the source electrode 60. The gate wiring 71 is provided around the source electrode 60 in the X-Y plane (the first plane). The gate wiring 71 is electrically connected to the gate pad 70.

[0012] As shown in FIGS. 3 and 4, the drain electrode 50 is provided on the lower surface of the semiconductor device 100. The n-shaped drain region 5 is provided above the drain electrode 50 and is electrically connected to the drain electrode 50. + The n-shaped drain region 5 is provided above the drain electrode 50 and is electrically connected to the drain electrode 50. - The n-shaped drift region 1 is provided above the n-shaped drain region 5. + The n-shaped drift region 1 is provided above the n-shaped drain region 5. - The n-type impurity concentration of the n-shaped drift region 1 is lower than that of the n-shaped drain region 5. + The n-type impurity concentration of the n-shaped drift region 1 is lower than that of the n-shaped drain region 5. - The n-shaped drift region 1 is electrically connected to the drain electrode 50 through the n-shaped drain region 5. + The n-shaped drift region 1 is electrically connected to the drain electrode 50 through the n-shaped drain region 5.

[0013] As shown in FIG. 3, the p-type base region 2 is provided above the n-shaped drift region 1. - The p-type base region 2 is provided above the n-shaped drift region 1. + The p-shaped source region 3 and the p-shaped contact region 4 are respectively provided above a part of the p-type base region 2. + The p-shaped source region 3 and the p-shaped contact region 4 are respectively provided above a part of the p-type base region 2. +The p-type impurity concentration in the shaped contact region 4 is higher than that in the p-type base region 2.

[0014] The conductive part 20 is provided in the n- - shaped drift region 1 via the insulating part 10. The conductive part 20 faces the n- - shaped drift region 1 in the X and Y directions. The gate electrode 30 is provided in the insulating part 10 and faces the p-type base region 2 in the X and Y directions. A part of the insulating part 10 is located between the p-type base region 2 and the gate electrode 30 and functions as a gate insulating layer.

[0015] The source electrode 60 is provided on the n- + shaped source region 3, p- + shaped contact region 4, and the gate electrode 30, and is electrically connected to the n- + shaped source region 3, p- + shaped contact region 4, and the conductive part 20. The p-type base region 2 is electrically connected to the source electrode 60 via the p- + shaped contact region 4. The gate electrode 30 is electrically separated from the source electrode 60 by the insulating part 15.

[0016] The source electrode 60 includes an extending part 61 and a contact part 62. The extending part 61 extends in the Z direction and is provided on the conductive part 20. The lower end of the extending part 61 contacts the upper end of the conductive part 20, so that the source electrode 60 is electrically connected to the conductive part 20. The contact part 62 is provided on the p- + shaped contact region 4. The lower part of the contact part 62 contacts the n- + shaped source region 3 and p- + shaped contact region 4, so that the source electrode 60 is electrically connected to these semiconductor regions.

[0017] As shown in FIG. 2, the gate electrode 30 is located around a part of the extending part 61 in the X-Y plane. The n- + shaped source region 3 is located around the gate electrode 30 in the X-Y plane.

[0018] As shown in FIGS. 2 to 4, n + A plurality of the rectangular source regions 3, the conductive portions 20, the gate electrodes 30, and the extending portions 61 are provided in the X direction and the Y direction, respectively. When viewed from the Z direction, the contact portion 62 is located between the rectangular source regions 3. + is located between the rectangular source regions 3.

[0019] The connection portion 40 electrically connects adjacent gate electrodes 30. Specifically, the connection portion 40 extends in the Y direction, and both ends of the connection portion 40 in the Y direction are in contact with the adjacent gate electrodes 30 in the Y direction, respectively. Thereby, the adjacent gate electrodes 30 in the Y direction are electrically connected. As shown in FIG. 2, the length of the connection portion 40 in the Y direction is longer than the length of the connection portion 40 in the direction perpendicular to the Y-Z plane. When viewed from the Z direction, the gate electrodes 30 and the connection portion 40 are alternately provided in the Y direction.

[0020] As shown in FIG. 3, the connection portion 40 is provided above the p-type base region 2, the n + rectangular source region 3, and the p + rectangular contact region 4. A part of the insulating portion 15 is provided between these semiconductor regions and the connection portion 40, and the connection portion 40 is electrically separated from these semiconductor regions. As shown in FIG. 4, the connection portion 40 is located between the adjacent extending portions 61 in the Y direction.

[0021] As a specific example, as shown in FIG. 2, the plurality of insulating portions 10 include an insulating portion 11 (first insulating portion) and an insulating portion 12 (second insulating portion). The plurality of conductive portions 20 include a conductive portion 21 (first conductive portion) and a conductive portion 22 (second conductive portion). The plurality of gate electrodes 30 include a gate electrode 31 (first gate electrode) and a gate electrode 32 (second gate electrode). The plurality of connection portions 40 include a connection portion 41 (first connection portion). The plurality of extending portions 61 include an extending portion 61a (first extending portion) and an extending portion 61b (second extending portion).

[0022] The conductive part 21 and the gate electrode 31 are provided in the insulating part 11. The conductive part 22 and the gate electrode 32 are provided in the insulating part 12. The conductive part 22 and the gate electrode 32 are adjacent to the conductive part 21 and the gate electrode 31 in the Y direction. The connection part 41 electrically connects the gate electrode 31 and the gate electrode 32. The extending part 61a is in contact with the conductive part 21. The extending part 61b is in contact with the conductive part 22. The connection part 41 is located between the extending part 61a and the extending part 61b.

[0023] As shown in FIG. 1, the semiconductor device 100 includes a cell region 101 and a termination region 102. The termination region 102 is provided around the cell region 101 in the X-Y plane. The source electrode 60 is provided in the cell region 101. The gate wiring 71 is provided in the termination region 102. The above-described p-type base region 2, n + type source region 3, p + type contact region 4, insulating part 10, conductive part 20, gate electrode 30, and connection part 40 are provided in the cell region 101.

[0024] As shown in FIGS. 5 and 6, in the vicinity of the termination region 102, the plurality of insulating parts 10 include an insulating part 14. The insulating part 14 is located at the ends of the plurality of insulating parts 10 arranged in the Y direction. Similarly, the plurality of conductive parts 20 include a conductive part 24. The conductive part 24 is located at the ends of the plurality of conductive parts 20 arranged in the Y direction. The plurality of gate electrodes 30 include a gate electrode 34. The gate electrode 34 is located at the ends of the plurality of gate electrodes 30 arranged in the Y direction. The conductive part 24 and the gate electrode 34 are provided in the insulating part 14.

[0025] The insulating part 81, the conductive part 82, and the electrode layer 83 are provided in the termination region 102. As shown in FIG. 6, the conductive part 82 is provided in the n - type drift region 1 through the insulating part 81. The conductive part 82 is electrically connected to the source electrode 60 by the contact part 63 of the source electrode 60. The electrode layer 83 is provided in the insulating part 81 and is located above the conductive part 82. The electrode layer 83 is electrically separated from the source electrode 60 and the conductive part 82.

[0026] The plurality of connection parts 40 further includes a connection part 44. The electrode layer 83 is electrically connected to the gate electrode 34 by the connection part 44. The gate wiring 71 is located above the electrode layer 83. The electrode layer 83 is electrically connected to the gate wiring 71 by the contact part 72. The gate electrode 30 is electrically connected to the gate pad 70 via the electrode layer 83 and the gate wiring 71. In FIG. 5, the insulating part 15 is omitted, and the source electrode 60, the gate wiring 71, and the contact part 72 are shown by broken lines.

[0027] p + The p-shaped contact region 6 is provided around the gate electrode 34 in the X-Y plane. p + The p-type impurity concentration of the p-shaped contact region 6 is higher than the p-type impurity concentration of the p-type base region 2. Around the gate electrode 34, an n + -type source region 3 is not provided. As shown in FIG. 5, in the X-Y plane, around the p + -shaped contact region 6, a contact part 62 is provided, and the p + -shaped contact region 6 is electrically connected to the contact part 62.

[0028] The operation of the semiconductor device 100 will be described. With a positive voltage applied to the drain electrode 50 with respect to the source electrode 60, a voltage equal to or higher than the threshold value is applied to the gate electrode 30. As a result, a channel (inversion layer) is formed in the p-type base region 2, and the semiconductor device 100 is turned on. Electrons flow from the source electrode 60 to the drain electrode 50 through the channel. When the voltage applied to the gate electrode 30 becomes lower than the threshold value, the channel in the p-type base region 2 disappears, and the semiconductor device 100 becomes off.

[0029] When the semiconductor device 100 switches to the off state, the positive voltage applied to the drain electrode 50 with respect to the source electrode 60 increases. At this time, from the interface between the insulating part 10 and the n - -type drift region 1 to the n -The depletion layer extends toward the n-type drift region 1. Due to the extension of this depletion layer, the breakdown voltage of the semiconductor device 100 can be increased. Or, while maintaining the breakdown voltage of the semiconductor device 100, the n - -type impurity concentration in the -type drift region 1 can be increased to reduce the on-resistance of the semiconductor device 100.

[0030] An example of the material of each component of the semiconductor device 100 will be described. n - -type drift region 1, p-type base region 2, n + -type source region 3, p + -type contact region 4, n + -type drain region 5, and p + -type contact region 6 contain a semiconductor material. As the semiconductor material, silicon, silicon carbide, gallium nitride, or gallium arsenide can be used. As the n-type impurity, arsenic, phosphorus, or antimony can be used. As the p-type impurity, boron can be used.

[0031] The insulating portions 10 and 15 contain an insulating material. For example, the insulating portions 10 and 15 contain silicon oxide, silicon nitride, or silicon oxynitride. The conductive portion 20, gate electrode 30, and connection portion 40 contain polysilicon. N-type or p-type impurities may be added to the conductive portion 20, gate electrode 30, and connection portion 40. The drain electrode 50, source electrode 60, and gate pad 70 contain a metal such as titanium, tungsten, or aluminum. The connection portion 40 may contain a metal like the drain electrode 50 instead of polysilicon.

[0032] Figs. 7(a) to 11(b) are cross-sectional views showing a method of manufacturing a semiconductor device according to the first embodiment. First, a semiconductor substrate including an n + -type semiconductor layer 5a is prepared. On the n + -type semiconductor layer 5a, an n - -type semiconductor layer 1a is formed by epitaxial growth of a semiconductor material. As shown in Fig. 7(a), by reactive ion etching (RIE), n -An opening OP1 is formed in the n-type semiconductor layer 1a. A plurality of openings OP1 are formed in the X direction and the Y direction.

[0033] Along the inner surface of the opening OP1 and the upper surface of the n - type semiconductor layer 1a, an insulating layer 10a is formed by thermal oxidation or chemical vapor deposition (CVD). By CVD, a conductive layer is formed on the insulating layer 10a. The upper surface of the conductive layer is recessed by chemical dry etching (CDE) or wet etching. As a result, as shown in FIG. 7(b), a conductive layer 20a is formed inside the opening OP1.

[0034] By CVD, an insulating layer 10b is formed on the insulating layer 10a and the conductive layer 20a. The upper surface of the insulating layer 10a and the upper surface of the insulating layer 10b are recessed by CDE or wet etching. By thermal oxidation, along the inner surface of the opening OP1 and the upper surface of the n - type semiconductor layer 1a, an insulating layer 10c is formed. By CVD, a conductive layer is formed on the insulating layer 10c. The upper surface of the conductive layer is recessed by chemical mechanical polishing (CMP). As a result, as shown in FIG. 8(a), a conductive layer 30a is formed inside the opening OP1.

[0035] n - type semiconductor layer 1a, p-type impurities and n-type impurities are sequentially ion-implanted to form a p-type semiconductor region 2a and an n + type semiconductor region 3a. By CVD, as shown in FIG. 8(b), a thin conductive layer 40a is formed on the insulating layer 10c and the conductive layer 30a. As shown in FIG. 9(a), the conductive layer 40a is patterned so that only a part of the conductive layer 40a remains.

[0036] By RIE, the center of the conductive layer 30a in the X-Y plane and the insulating layer 10b are removed. An insulating layer 15a covering the conductive layer 30a and the conductive layer 40a is formed. As shown in FIG. 9(b), by RIE, an opening OP2 is formed that penetrates the insulating layer 15a and the n + type semiconductor region 3a and reaches the p-type semiconductor region 2a.

[0037] Ion-implant p-type impurities into the p-type semiconductor region 2a through the opening OP2 to form a p + type semiconductor region 4a. As shown in FIG. 10(b), form an opening OP3 that penetrates the insulating layer 15a and reaches the conductive layer 20a by RIE. Form a barrier metal 60a that fills the openings OP2 and OP3 by CVD. The barrier metal 60a has, for example, a laminated structure of a titanium nitride layer, a titanium layer, and a tungsten layer. Form an aluminum layer 60b on the barrier metal 60a by sputtering as shown in FIG. 11(a).

[0038] Pattern the barrier metal 60a and the aluminum layer 60b so that a source electrode 60, a gate pad 70, and a gate wiring 71 are formed. Grind the lower surface of the n + type semiconductor layer 5a until it reaches a predetermined thickness. As shown in FIG. 11(b), form an aluminum layer 50a on the lower surface of the n + type semiconductor layer 5a by sputtering. Thus, the semiconductor device 100 is manufactured. + The n

[0039] type semiconductor layer 1a shown in FIG. 11(b) corresponds to the n - type drift region 1 of the semiconductor device 100 shown in FIGS. 1 to 6. The p-type semiconductor region 2a corresponds to the p-type base region 2. The n - type semiconductor region 3a corresponds to the n + type source region 3. The p + type semiconductor region 4a corresponds to the p + type contact region 4. The n + type semiconductor layer 5a corresponds to the n + type semiconductor layer 5a corresponds to the n +It corresponds to the V-shaped drain region 5. A part of the insulating layer 10a, the insulating layer 10c, and the insulating layer 15a corresponds to the insulating portion 10. Another part of the insulating layer 15a corresponds to the insulating portion 15. The conductive layer 20a corresponds to the conductive portion 20. The conductive layer 30a corresponds to the gate electrode 30. The conductive layer 40a corresponds to the connection portion 40. The aluminum layer 50a corresponds to the drain electrode 50. The patterned barrier metal 60a and the aluminum layer 60b correspond to the source electrode 60, the gate pad 70, and the gate wiring 71.

[0040] Explain the advantages of the first embodiment. FIG. 12 is a cross-sectional view showing a part of a semiconductor device according to a reference example. The semiconductor device 100r shown in FIG. 12 does not include the connection portion 40 and the gate wiring 71, and includes a gate wiring layer 75. The gate wiring layer 75 extends along the X-Y plane and is electrically connected to a gate pad 70 (not shown). Further, the gate wiring layer 75 is electrically connected to the gate electrode 30 via a contact portion 75a extending in the Z direction. The gate wiring layer 75 contains a metal such as aluminum.

[0041] In the semiconductor device 100r, similar to the semiconductor device 100, a plurality of each of the conductive portion 20 and the gate electrode 30 are provided in the X direction and the Y direction. According to this structure, compared with the case where the conductive portion 20 and the gate electrode 30 extend in one direction, - the volume of the V-shaped drift region 1 increases. The current path in the on state increases, and the on-resistance of the semiconductor devices 100 and 100r can be reduced.

[0042] On the one hand, the conductive part 20 and the gate electrode 30 need to be electrically connected to the source electrode 60 and the gate pad 70 while being electrically separated from each other. In the semiconductor device 100r, a gate wiring layer 75 is provided for the electrical connection between the gate electrode 30 and the gate pad 70. When providing the gate wiring layer 75, the manufacturing processes required, such as the formation of the contact part 75a, the patterning of the gate wiring layer 75, and the separation between the gate wiring layer 75 and the source electrode 60, increase. Also, the finer the insulating part 10, the conductive part 20, and the gate electrode 30 are, the larger the channel area (channel density) per unit area can be made. However, considering the misalignment of the contact part 75a and the like, it becomes difficult to miniaturize the gate electrode 30.

[0043] Regarding these problems, in the semiconductor device 100, the gate electrodes 30 are electrically connected to each other by the connection part 40. The connection part 40 extends in the Y direction and contacts the adjacent gate electrodes 30 in the Y direction. The gate electrode 30 is electrically connected to the gate pad 70 via the connection part 40. Therefore, in the semiconductor device 100, the gate wiring layer 75 for electrically connecting the gate electrode 30 and the gate pad 70 is unnecessary. According to the first embodiment, the number of manufacturing processes during the production of the semiconductor device 100 can be reduced. Also, since the contact part 75a for connecting the gate electrode 30 and the gate wiring layer 75 is unnecessary, the miniaturization of the gate electrode 30 becomes possible. As a result, the on-resistance of the semiconductor device 100 can be further reduced.

[0044] Also, when the connection part 40 contains polysilicon, the electrical resistance of the connection part 40 can be made larger compared to the case where the connection part 40 contains metal. By increasing the electrical resistance of the connection part 40, the change in voltage (dV / dt) with respect to time when the semiconductor device 100 is switched to the off state can be made smaller. Thereby, during turn-off, the voltage oscillation of the gate electrode 30 and the connection part 40 can be reduced, and the noise caused by the voltage oscillation can be reduced. Note that when the electrical resistance of the gate electrode 30 is sufficiently large and it is not necessary to increase the electrical resistance of the connection part 40, a metal such as tungsten may be used for the connection part 40.

[0045] In the vicinity of the terminal region 102, around the gate electrode 34, instead of the n + -type source region 3, a p + -type contact region 6 is provided. By providing the p + -type contact region 6, carriers generated in the terminal region 102 during avalanche breakdown can be easily discharged to the source electrode 60. For example, fluctuations in the potential of the p-type base region 2 in the vicinity of the terminal region 102 can be suppressed, and the operation of the parasitic bipolar transistor can be suppressed. That is, the avalanche withstand voltage can be improved. When more emphasis is placed on reducing the on-resistance of the semiconductor device 100, instead of the p + -type contact region 6, an n + -type source region 3 may be provided.

[0046] (Modification example) FIG. 13, FIG. 15, and FIG. 16 are plan views showing a part of a semiconductor device according to a modification example of the first embodiment. FIG. 14 is a cross-sectional view taken along line A1 - A2 of FIG. 13. Note that in FIGS. 13, 15, and 16, the insulating portion 15 is omitted. In the semiconductor device 110 shown in FIGS. 13 and 14 and the semiconductor device 120 shown in FIG. 15, a part of the plurality of connection portions 40 extends in the Y direction. Another part of the plurality of connection portions 40 extends in the X direction. Both ends of the connection portion 40 extending in the X direction are in contact with the gate electrodes 30 adjacent to each other in the X direction. As a result, the gate electrodes 30 adjacent to each other in the X direction are electrically connected.

[0047] As a specific example, as shown in FIGS. 13 and 14, the plurality of insulating portions 10 further includes an insulating portion 13 (third insulating portion). The plurality of conductive portions 20 further includes a conductive portion 23 (third conductive portion). The plurality of gate electrodes 30 further includes a gate electrode 33 (third gate electrode). The plurality of connection portions 40 further includes a connection portion 42 (second connection portion). The plurality of extending portions 61 further includes an extending portion 61c (third extending portion).

[0048] The conductive part 23 and the gate electrode 33 are provided inside the insulating part 13. The conductive part 23 and the gate electrode 33 are adjacent to the conductive part 21 and the gate electrode 31 in the X direction. The connection part 42 electrically connects the gate electrode 31 and the gate electrode 33. The extending part 61c is in contact with the conductive part 23. The connection part 42 is located between the extending part 61a and the extending part 61c.

[0049] In the semiconductor device 110, in the extending direction of some of the connection parts 40, the insulating part 14, the conductive part 24, and the gate electrode 34 are aligned with the insulating part 81, the conductive part 82, and the electrode layer 83.

[0050] In the semiconductor device 120, in the direction intersecting the extending direction of the connection part 40, the insulating part 14, the conductive part 24, and the gate electrode 34 are aligned with the insulating part 81, the conductive part 82, and the electrode layer 83.

[0051] In the semiconductor device 130 shown in FIG. 16, a plurality of connection parts 40 include a connection part 43 (third connection part). The connection part 43 extends in a direction intersecting the X direction and the Y direction. The connection part 43 electrically connects the adjacent gate electrodes 32 and 33 in its extending direction.

[0052] If the connection part 40 electrically connects adjacent gate electrodes 30 as in the semiconductor devices 110 to 130, the extending direction of the connection part 40 can be changed as appropriate. Also, if each gate electrode 30 is electrically connected to the gate pad 70, the number of connection parts 40 can also be changed as appropriate.

[0053] According to the semiconductor device 100, compared with the semiconductor devices 110 to 130, + the area of the n + -type source region 3 and the area of the p-type contact region 4 are large. Carriers generated at the time of avalanche breakdown are easily discharged to the source electrode 60. Therefore, the avalanche withstand voltage of the semiconductor device 100 can be improved.

[0054] On the other hand, according to semiconductor devices 110 to 130, the number of connection parts 40 is larger than that of semiconductor device 100. As the number of connection parts 40 increases, the gate resistance between the gate pad 70 and the gate electrode 30 becomes smaller. For example, the fluctuation period of the potential of the gate electrode 30 during switching can be shortened, and the operation of the semiconductor device can be stabilized. In particular, since semiconductor device 130 includes even more connection parts 40 than semiconductor devices 110 and 120, the gate resistance can be further reduced.

[0055] (Second Embodiment) FIG. 17 is a plan view showing a part of the semiconductor device according to the second embodiment. FIG. 18 is a cross-sectional view taken along line A1 - A2 of FIG. 17. FIG. 19 is a cross-sectional view taken along line B1 - B2 of FIG. 17. FIG. 17 corresponds to a cross-sectional view taken along line C1 - C2 of FIGS. 18 and 19. Note that in FIG. 17, the insulating part 15 is omitted. The semiconductor device 200 according to the second embodiment is different from the semiconductor devices 100 to 130 according to the first embodiment in that it includes a planar gate structure.

[0056] Specifically, as shown in FIG. 18, the n - -type drift region 1 includes a first part 1p that is aligned with the n + -type source region 3 in a direction perpendicular to the Y - Z plane. The first part 1p is located between the n + -type source regions 3. A part of the p-type base region 2 is provided between the first part 1p and the n + -type source region 3. As shown in FIG. 18, the connection part 40 faces, in the Z direction, the first part 1p, the said part of the p-type base region 2, and a part of the n + -type source region 3 through a part of the insulating part 15. The said part of the insulating part 15 functions as a gate insulating layer.

[0057] As shown in FIGS. 17 and 19, the n + -type source region 3 is located under both side parts of the connection part 40. The both side parts are the end parts of the connection part 40 in a direction orthogonal to the extending direction of the connection part 40. In the semiconductor device according to the first embodiment, the n +A plurality of V-shaped source regions 3 are provided in the Y direction. In contrast, in the semiconductor device 200, n + The V-shaped source regions 3 are connected to each other in the Y direction.

[0058] When the semiconductor device 200 is in the on state, in addition to a part of the p-type base region 2 facing the gate electrode 30, a channel is also formed in another part of the p-type base region 2 facing the connection portion 40. Electrons can move through the channel between the V + -shaped source region 3 and the first portion 1p. According to the second embodiment, compared with the first embodiment, the current path in the on state increases. Therefore, according to the second embodiment, the on-resistance of the semiconductor device 200 can be further reduced.

[0059] It is also possible to apply the structure according to any modification of the first embodiment to the semiconductor device 200. For example, the semiconductor device 200 includes insulating portions 11 to 13, conductive portions 21 to 23, gate electrodes 31 to 33, a connection portion 41, and extending portions 61a to 61c. Similar to the semiconductor device 110 or 120, the semiconductor device 200 may further include a connection portion 42. Similar to the semiconductor device 130, the semiconductor device 200 may further include a connection portion 43. Thereby, the gate resistance in the semiconductor device 200 can be reduced.

[0060] Regarding the relative levels of the impurity concentrations between the semiconductor regions in each of the embodiments described above, for example, it is possible to confirm using a scanning capacitance microscope (SCM). Note that the carrier concentration in each semiconductor region can be regarded as equal to the impurity concentration activated in each semiconductor region. Therefore, the relative levels of the carrier concentrations between the semiconductor regions can also be confirmed using the SCM. In addition, the impurity concentration in each semiconductor region can be measured, for example, by secondary ion mass spectrometry (SIMS).

[0061] As described above, several embodiments of the present invention have been illustrated. However, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, changes, etc. can be made without departing from the gist of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are also included in the invention described in the claims and the equivalent scope thereof. Further, the above-described embodiments can be implemented in combination with each other.

Explanation of Reference Numerals

[0062] 1:n - Shape drift region, 1a:n - Shape semiconductor layer, 1p: First part, 2: p-type base region, 2a: p-type semiconductor region, 3: n + Shape source region, 3a:n + Shape semiconductor region, 4:p + Shape contact region, 4a:p + Shape semiconductor region, 5:n + Shape drain region, 5a:n + Shape semiconductor layer, 6:p + Shape contact region, 10 - 15: Insulating part, 10a - 10c, 15a: Insulating layer, 20 - 24: Conductive part, 20a: Conductive layer, 30 - 34: Gate electrode, 30a: Conductive layer, 40 - 44: Connection part, 40a: Conductive layer, 50: Drain electrode, 50a: Aluminum layer, 60: Source electrode, 60a: Barrier metal, 60b: Aluminum layer, 61, 61a - 61c: Extending part, 62, 63: Contact part, 70: Gate pad, 71: Gate wiring, 72: Contact part, 75: Gate wiring layer, 75a: Contact part, 81: Insulating part, 82: Conductive part, 83: Electrode layer, 100, 100r, 110 - 130, 200: Semiconductor device, 101: Cell region, 102: Terminal region, OP1 - OP3: Opening

Claims

1. a first electrode, a first semiconductor region of a first conductivity type provided on the first electrode and electrically connected to the first electrode, a second semiconductor region of a second conductivity type provided on the first semiconductor region, a third semiconductor region of the first conductivity type provided on a part of the second semiconductor region, a first conductive portion provided in the first semiconductor region via a first insulating portion, a first gate electrode provided in the first insulating portion and facing the second semiconductor region in a second direction perpendicular to a first direction from the first electrode toward the first semiconductor region, a second conductive portion provided in the first semiconductor region via a second insulating portion and separated from the first conductive portion in the second direction, a second gate electrode provided in the second insulating portion and facing the second semiconductor region in the second direction, another conductive portion provided in the first semiconductor region via another insulating portion, separated from the first conductive portion and the second conductive portion in the second direction, and having the second conductive portion positioned therebetween and the first conductive portion, another gate electrode provided in the another insulating portion and facing the second semiconductor region in the second direction, a first connection portion provided above the second semiconductor region and the third semiconductor region, extending in the second direction, and contacting the first gate electrode and the second gate electrode, another connection portion provided above the second semiconductor region and the third semiconductor region, extending in the second direction, and contacting the second gate electrode and the another gate electrode, wherein the first gate electrode and the another gate electrode are electrically connected via the first connection portion, the second gate electrode, and the another connection portion, a second electrode provided on the second semiconductor region and the third semiconductor region and electrically connected to the second semiconductor region, the third semiconductor region, the first conductive portion, and the second conductive portion, a semiconductor device comprising the above components.

2. The second electrode includes a first extending portion extending in the first direction and contacting the first conductive portion, The first gate electrode is provided around a part of the first extending portion along a first plane perpendicular to the first direction, according to the semiconductor device of Claim 1.

3. The second electrode includes a second extending portion extending in the first direction and contacting the second conductive portion, The second gate electrode is provided around a part of the second extending portion along the first plane, The semiconductor device according to claim 2, wherein the first connection portion is located between the first extending portion and the second extending portion.

4. A first electrode, a first semiconductor region of a first conductivity type provided on the first electrode and electrically connected to the first electrode, a second semiconductor region of a second conductivity type provided on the first semiconductor region, a third semiconductor region of a first conductivity type provided on a part of the second semiconductor region, a first conductive portion provided in the first semiconductor region via a first insulating portion, a first gate electrode provided in the first insulating portion and facing the second semiconductor region in a second direction perpendicular to a first direction from the first electrode toward the first semiconductor region, a second conductive portion provided in the first semiconductor region via a second insulating portion and separated from the first conductive portion in the second direction, a second gate electrode provided in the second insulating portion and facing the second semiconductor region in the second direction, a first connection portion provided above the second semiconductor region and the third semiconductor region, extending in the second direction, and in contact with the first gate electrode and the second gate electrode, a second electrode provided on the second semiconductor region and the third semiconductor region, electrically connected to the second semiconductor region, the third semiconductor region, the first conductive portion, and the second conductive portion, the second electrode including a first extending portion extending in the first direction and in contact with the first conductive portion, and the first gate electrode being provided around a part of the first extending portion along a first plane perpendicular to the first direction, the second electrode, A semiconductor device comprising.

5. The semiconductor device according to any one of claims 1 to 4, wherein the first connection portion faces a part of the first semiconductor region, the second semiconductor region, and a part of the third semiconductor region via a gate insulating layer in the first direction.

6. A first electrode, a first semiconductor region of a first conductivity type provided on the first electrode and electrically connected to the first electrode, a second semiconductor region of a second conductivity type provided on the first semiconductor region, a third semiconductor region of a first conductivity type provided on a part of the second semiconductor region, a first conductive portion provided in the first semiconductor region via a first insulating portion, a first gate electrode provided in the first insulating portion and facing the second semiconductor region in a second direction perpendicular to a first direction from the first electrode toward the first semiconductor region, A second conductive portion provided in the first semiconductor region via a second insulating portion and separated from the first conductive portion in the second direction; A second gate electrode provided in the second insulating portion and facing the second semiconductor region in the second direction; A first connection portion provided above the second semiconductor region and the third semiconductor region, extending in the second direction, contacting the first gate electrode and the second gate electrode, and facing a part of the first semiconductor region, the second semiconductor region, and a part of the third semiconductor region via a gate insulating layer in the first direction; A second electrode provided on the second semiconductor region and the third semiconductor region and electrically connected to the second semiconductor region, the third semiconductor region, the first conductive portion, and the second conductive portion; A semiconductor device comprising the above.

7. A third conductive portion provided in the first semiconductor region via a third insulating portion and separated from the first conductive portion in a third direction perpendicular to the first direction and intersecting the second direction; A third gate electrode provided in the third insulating portion; The semiconductor device according to any one of claims 1 to 6, comprising the above.

8. The semiconductor device according to claim 7, further comprising a second connection portion provided above the second semiconductor region and the third semiconductor region, extending in the third direction, and contacting the first gate electrode and the third gate electrode.

9. The semiconductor device according to claim 8, wherein the second connection portion contains polysilicon.

10. A conductive portion provided in the first semiconductor region via an insulating portion, separated from the first conductive portion and the second conductive portion, and electrically connected to the second electrode; An electrode layer containing polysilicon, separated from the conductive portion in the first direction, and electrically connected to the first gate electrode, the second gate electrode, and the first connection portion; A wiring provided on the electrode layer, separated from the second electrode, and electrically connected to the electrode layer; The semiconductor device according to any one of claims 1 to 9, comprising the above.

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