Semiconductor device and method for manufacturing the same

Abstract

To provide a semiconductor device capable of reducing a leakage current and improving a withstanding voltage.SOLUTION: A semiconductor device comprises a semiconductor part that includes: a first semiconductor layer of a first conductivity type; and a second semiconductor layer of a second conductivity type provided in the first semiconductor layer. The semiconductor part includes a first interface between the first semiconductor layer and the second semiconductor part, and a second interface between the first semiconductor layer and the second semiconductor part, the second interface crossing the first interface. The second semiconductor layer includes a plurality of portions laminated in a direction perpendicular to the first interface. The second interface includes an interface between each of the plurality of portions of the second semiconductor layer and the first semiconductor layer. The second interface extends in a second direction inclined to a first direction perpendicular to the first interface.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] Embodiments relate to a semiconductor device and a method of manufacturing the same.

Background Art

[0002] For example, semiconductor devices used for power control and the like are required to reduce leakage current and improve breakdown voltage.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] Embodiments provide a semiconductor device capable of reducing leakage current and improving breakdown voltage.

Means for Solving the Problems

[0005] The semiconductor device according to an embodiment includes a semiconductor portion including a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type provided in the first semiconductor layer. The semiconductor portion includes a first interface between the first semiconductor layer and the second semiconductor portion, and a second interface between the first semiconductor layer and the second semiconductor portion that intersects the first interface. The second semiconductor layer includes a plurality of portions stacked in a direction orthogonal to the first interface, and the second interface includes an interface between the plurality of portions of the second semiconductor layer and the first semiconductor layer. The second interface extends in a second direction inclined with respect to a first direction orthogonal to the first interface.

Brief Description of the Drawings

[0006]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Embodiments for Carrying Out the Invention

[0007] Hereinafter, embodiments will be described with reference to the drawings. The same parts in the drawings are denoted by the same reference numerals, and detailed descriptions thereof will be omitted as appropriate, and different parts will be described. Note that the drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the ratio of the sizes between parts, etc. are not necessarily the same as those in reality. Also, even when representing the same part, the dimensions and ratios may be represented differently in the drawings.

[0008] Furthermore, the arrangement and configuration of each part will be described using the X-axis, Y-axis, and Z-axis shown in each figure. The X-axis, Y-axis, and Z-axis are perpendicular to each other and represent the X direction, Y direction, and Z direction, respectively. Also, there may be cases where the Z direction is described as upward and the opposite direction as downward.

[0009] Figs. 1(a) to (c) are schematic cross-sectional views showing a method of manufacturing a semiconductor device according to an embodiment. The semiconductor device according to the embodiment is formed using, for example, a first semiconductor layer 11 of a first conductivity type. The first semiconductor layer 11 is epitaxially grown, for example, on a semiconductor substrate 10. The semiconductor substrate 10 is, for example, a silicon carbide (SiC) substrate or a silicon substrate. The first semiconductor layer 11 is, for example, a SiC layer having a hexagonal crystal structure. Hereinafter, the first conductivity type will be described as n-type and the second conductivity type as p-type.

[0010] As shown in Fig. 1(a), a first semiconductor layer 11a is epitaxially grown on a semiconductor substrate 10. The first semiconductor layer 11a is formed, for example, using a CVD method (Chemical Vapor Deposition method). The first semiconductor layer 11a is epitaxially grown with a Si plane in the

[0001] direction of the hexagonal crystal as a growth plane. The upper surface of the semiconductor substrate 10 has an off-angle, for example, 4 degrees, with respect to the Si plane.

[0011] Subsequently, after forming an ion implantation mask HM1 on the first semiconductor layer 11a, a second conductivity type impurity, for example, aluminum (Al), is ion-implanted into the first semiconductor layer 11a through a first opening WP1 of the ion implantation mask HM1. Thereby, a second semiconductor layer 13a of the second conductivity type is formed in the first semiconductor layer 11a.

[0012] The second conductivity type impurity is implanted in a direction inclined with respect to the upper surface of the first semiconductor layer 11a. The implantation angle θ between the direction perpendicular to the upper surface of the first semiconductor layer 11a and the implantation direction is set to be the same as, for example, the off-angle of the semiconductor substrate 10. Thereby, the second conductivity type impurity is ion-implanted in a direction perpendicular to the C plane of the hexagonal crystal.

[0013] As shown in Fig. 1(b), a first semiconductor layer 11b is formed on the first semiconductor layer 11a. The first semiconductor layer 11b has, for example, the same composition as the first semiconductor layer 11a. The concentration of the first conductivity type impurity in the first semiconductor layer 11b may be the same as or different from the concentration of the first conductivity type impurity in the first semiconductor layer 11a. The second conductivity type impurity ion-implanted into the first semiconductor layer 11a is activated during a heat treatment after the ion implantation or during a temperature increase process during epitaxial growth.

[0014] Subsequently, after forming the ion implantation mask HM2 on the first semiconductor layer 11b, through the second opening WP2 of the ion implantation mask HM2, a second conductivity type impurity, for example, aluminum (Al), is ion implanted into the first semiconductor layer 11b. The second conductivity type impurity is ion implanted into the first semiconductor layer 11b with the same implantation angle θ as the second conductivity type impurity implanted into the first semiconductor layer 11a. Thereby, the second semiconductor layer 13b of the second conductivity type is formed in the first semiconductor layer 11b.

[0015] The second opening WP2 of the ion implantation mask HM2 has the same width as the first opening WP1 of the ion implantation mask HM1. The second opening WP2 is provided at a horizontal position shifted in the implantation direction side (-X direction) with respect to the horizontal position of the first opening WP1. Here, the horizontal position is the relative position in the horizontal direction along the upper surfaces of the first semiconductor layer 11a and the 1 first semiconductor layer 11b, respectively.

[0016] The amount of horizontal shift of the second opening WP2 with respect to the first opening WP1 is equal to, for example, the product of the layer thickness in the Z direction of the first semiconductor layer 11b and the tangent of the implantation angle θ (see Fig. 4(a)). Thereby, the second semiconductor layer 13a and the second semiconductor layer 13b are formed such that their respective side surfaces (that is, the interfaces between the first semiconductor layer 11 and the second semiconductor layer 13) are continuously connected.

[0017] As shown in Fig. 1(c), the first semiconductor layer 11c is formed on the first semiconductor layer 11b. The first semiconductor layer 11c has, for example, the same composition as the first semiconductor layers 11a and 11b. The concentration of the first conductivity type impurity in the first semiconductor layer 11c may be the same as or different from the concentration of the first conductivity type impurity in the first semiconductor layer 11b. The second conductivity type impurity ion implanted into the first semiconductor layer 11b is activated during the heat treatment after ion implantation or the temperature increase process during epitaxial growth.

[0018] Subsequently, after forming the ion implantation mask HM3 on the first semiconductor layer 11c, through the third opening WP3 of the ion implantation mask HM3, a second conductivity type impurity, for example, aluminum (Al), is ion implanted into the first semiconductor layer 11c. The second conductivity type impurity is ion implanted into the first semiconductor layer 11c with the same implantation angle θ as the second conductivity type impurity implanted into the first semiconductor layers 11a and 11b. Thereby, a second semiconductor layer 13c of the second conductivity type is formed in the first semiconductor layer 11c.

[0019] The third opening WP3 of the ion implantation mask HM3 has the same width as the second opening WP2 of the ion implantation mask HM2. The third opening WP3 is provided at a horizontal position shifted in the implantation direction side (-X direction) with respect to the horizontal position of the second opening WP2. The horizontal shift amount of the third opening WP3 with respect to the second opening WP2 is equal to, for example, the product of the layer thickness in the Z direction of the first semiconductor layer 11c and the tangent of the implantation angle θ. Thereby, the second semiconductor layers 13b and 13c are formed such that their respective side surfaces are continuously connected. Note that the ion implantation masks HM1 to HM3 may be, for example, a hard mask such as a silicon oxide film or a metal film, or may be a resin such as a resist.

[0020] Hereinafter, the laminate of the first semiconductor layers 11a to 11c will be described as the first semiconductor layer 11. Also, the laminate of the second semiconductor layers 13a to 13c will be described as the second semiconductor layer 13. Note that the above manufacturing method is an example and is not limited thereto. For example, the first semiconductor layer 11 and the second semiconductor layer 13 may each be a laminate of four or more layers.

[0021] Figs. 2(a) and (b) are schematic diagrams showing a manufacturing method of a semiconductor device according to an embodiment. Figs. 2(a) and (b) represent a wafer 100 used in the manufacture of a semiconductor device. The wafer 100 includes a semiconductor substrate 10 and a first semiconductor layer 11.

[0022] As shown in FIG. 2(a), the wafer 100 has, for example, an orifice parallel to the (10-10) plane (hereinafter, the M plane) of the hexagonal crystal. Further, the surface 100F of the wafer 100 has a predetermined off-angle θ with respect to the (0001) plane (hereinafter, the C plane) of the hexagonal crystal.

[0023] As shown in FIG. 2(b), when implanting the second conductivity type impurity (Al) by ion implantation, the wafer 100 is arranged such that its surface 100F is inclined with respect to the ion beam IB. The wafer 100 is arranged to be inclined by the implantation angle θ clockwise within a plane including, for example, the [11-20] direction and the

[0001] direction, that is, within the M plane, from a position orthogonal to the ion beam IB. When the surface 100F is inclined 4 degrees clockwise from the C plane within the M plane, that is, when the off-angle θ is 4 degrees, by setting the implantation angle θ to 4 degrees, the ion beam IB can be made to be incident perpendicularly to the C plane.

[0024] Also, the embodiment is not limited to this example. For example, the ion beam IB may be made to be incident perpendicularly to a crystal plane inclined 17 degrees clockwise from the C plane within the M plane. In such a crystal plane and the C plane, the interatomic distance becomes relatively wide, and so-called channeling of the implanted ions occurs. Therefore, the second conductivity type impurity implanted by ion implantation can be distributed more widely in the depth direction (Z direction). That is, in the manufacturing method according to the embodiment, the number of times of epitaxial growth carried out to obtain the second semiconductor layer 13 having a predetermined thickness can be reduced.

[0025] For example, when the off-angle θ of the wafer is 4 degrees, by inclining the surface 100F 21 degrees clockwise within the M plane, it becomes possible to make the ion beam IB incident in the channeling direction. Also, when the off-angle θ of the wafer 100 is -4 degrees, by inclining the surface 100F 13 degrees clockwise within the M plane, it is also possible to make the ion beam IB incident in the channeling direction. Thereby, the shielding effect due to the mask thickness of the ion implantation masks HM1 to HM3 can be reduced.

[0026] FIG. 3 is a schematic diagram showing the structure of a semiconductor device according to an embodiment. FIG. 3 is a schematic diagram illustrating the concentration profile of the second conductivity type impurity (Al) in the second semiconductor layer 13. The horizontal axis represents the depth from the surface. The vertical axis represents the Al concentration.

[0027] In this example, two ion implantations are performed on each of the first semiconductor layers 11a to 11c. Each ion implantation is performed such that Al ions are incident in a direction perpendicular to the C plane. Imp1 in FIG. 3 represents the distribution of Al introduced into the first semiconductor layer 11a by the first ion implantation. Also, Imp2 represents the distribution of Al introduced into the first semiconductor layer 11a by the second ion implantation. The distribution of Al in the first semiconductor layer 11a is the sum of the first Al distribution and the second Al distribution.

[0028] The first ion implantation is performed, for example, at room temperature under the conditions of an implantation energy of 900 keV and a dose of 1×10 13 cm -2 . The second ion implantation is performed, for example, at room temperature under the conditions of an implantation energy of 200 keV and a dose of 6×10 12 cm -3 . Also, the embodiment is not limited to this example. For example, the high-acceleration ion implantation may be 600 to 1200 keV, and the low-acceleration ion implantation may be 100 to 400 keV.

[0029] In the first semiconductor layers 11b and 11c as well, two ion implantations are performed under the above conditions respectively. The Al distributions in the first semiconductor layers 11b and 11c represent the distributions of Al introduced by the two ion implantations. Also, the layer thickness (thickness in the Z direction) of each of the first semiconductor layers 11b and 11c is, for example, 1.5 micrometers (μm).

[0030] As shown in FIG. 3, in the Al distribution of each of the first semiconductor layers 11a to 11c, two concentration peaks corresponding to two ion implantations appear. That is, the distribution of the second conductivity type impurities in the second semiconductor layers 13a to 13c formed in the first semiconductor layers 11a to 11c has concentration peaks corresponding to the number of ion implantations. In other words, the second semiconductor layers 13a to 13c are each formed by at least one ion implantation, and the distribution of the second conductivity type impurities in each contains at least one concentration peak.

[0031] FIGS. 4(a) and (b) are schematic cross-sectional views showing the structure of a semiconductor device according to an embodiment. FIG. 4(a) is a cross-sectional view showing the second semiconductor layer 13 of the semiconductor device 1 according to the embodiment. FIG. 4(b) is a cross-sectional view showing the second semiconductor layer 13 of the semiconductor device 2 according to the comparative example.

[0032] In the semiconductor device 1 shown in FIG. 4(a), the second semiconductor layers 13a to 13d are stacked with their respective horizontal positions shifted. For example, impurities ion-implanted into a semiconductor layer made of SiC do not diffuse by subsequent heat treatment. Therefore, the impurity distribution in the ion-implanted state is maintained within each semiconductor layer.

[0033] The amount of mutual shift in the horizontal direction in the second semiconductor layers 13a to 13d reflects the horizontal positional relationship between the first openings WP1 to the third openings WP3 of the ion implantation masks HM1 to HM3 (see FIGS. 1(a) to (c)). The amount of shift between adjacent layers among the second semiconductor layers 13a to 13d is, for example, the product of the layer thickness TL of each layer and the tangent (tanθ) of the implantation angle θ.

[0034] Also, as shown in FIG. 4(a), a first interface IF1 and a second interface IF2 occur between the first semiconductor layer 11 and the second semiconductor layer 13. The first interface IF1 is the boundary between the first semiconductor layer 11 and the bottom surface of the second semiconductor layer 13. The second interface IF2 intersects the first interface IF1.

[0035] The second interface IF2 extends, for example, along a second plane PL2 that is inclined with respect to a first plane PL1 orthogonal to the first interface IF1. In other words, in the X-Z plane, the second interface IF2 extends in a second direction that is inclined with respect to a first direction orthogonal to the first interface IF1. The inclination angle of the second plane PL2 with respect to the first plane PL1 is equal to the implantation angle θ of the second conductive-type impurity. Also, the straight line connecting the center 13BC of the first interface IF1 and the center 13TC of the surface 13TS on the side opposite to the first interface IF1 is parallel to the second plane PL2.

[0036] In the semiconductor device 2 shown in FIG. 4(b), the second semiconductor layer 13 is formed, for example, without relatively shifting the horizontal positions of the first openings WP1 to the third openings WP3 of the ion implantation masks HM1 to HM3. Therefore, the second semiconductor layers 13b to 13d are provided directly above the respective second semiconductor layers 13a to 13c. For this reason, the straight line connecting the center 13BC of the first interface IF1 and the center 13TC of the surface 13TS on the opposite side thereof is orthogonal to the first interface IF1.

[0037] As shown by the region surrounded by the circle in FIG. 4(b), at the mutual boundaries of the second semiconductor layers 13a to 13d, the second interface IF2 has a step. Such a step causes non-uniformity of the electric field or local electric field concentration between the first semiconductor layer 11 and the second semiconductor layer 13. For this reason, in the semiconductor device 2, there is a risk of an increase in leakage current or a decrease in breakdown voltage.

[0038] On the other hand, in the semiconductor device 1 according to the embodiment, the second interface IF2 between the first semiconductor layer 11 and the second semiconductor layer 13 extends flatly along the second plane PL2. Therefore, in the semiconductor device 1, it is possible to suppress the leakage current caused by the step of the second interface IF2 and avoid a decrease in breakdown voltage.

[0039] Figs. 5(a) to 5(c) are schematic diagrams showing the structure of the semiconductor device 3 according to the embodiment. Figs. 5(a) to 5(c) are schematic diagrams showing the SJ (Super Junction) structure of the semiconductor device 3. Fig. 5(a) is a plan view showing the surface 13TS of the second semiconductor layer 13. Fig. 5(b) is a cross-sectional view taken along the line A-A shown in Fig. 5(a). Fig. 5(c) is a cross-sectional view taken along the line B-B shown in Fig. 5(a).

[0040] As shown in Fig. 5(a), the second semiconductor layer 13 includes a plurality of pillar portions 13PP and a terminal portion 13TP. The pillar portions 13PP are provided in the active region AR. The terminal portion 13TP is located in the terminal region TR and surrounds the active region AR. The plurality of pillar portions 13PP are each provided in a stripe shape extending in the X direction. The plurality of pillar portions 13PP are arranged in the Y direction.

[0041] As shown in Fig. 5(b), the terminal portion 13TP of the second semiconductor layer 13 has a bottom surface 13BS and a side surface 13SS. The side surface 13SS is inclined with respect to a plane perpendicular to the bottom surface 13BS. Here, the X-Z plane is the M plane of the hexagonal crystal. The inclination angle of the side surface 13SS is the same as the implantation angle θ of the ion implantation.

[0042] As shown in Fig. 5(c), in the Y-Z plane, the side surface 13SS of the terminal portion 13TP is orthogonal to its bottom surface 13BS. Also, the side surface 13PS of the pillar portion 13PP is orthogonal to its bottom surface 13PB.

[0043] In the semiconductor device 3, in the terminal region TR where electric field concentration is likely to occur, it is possible to suppress the step (see Fig. 4(b)) on the inclined side surface 13SS of the second semiconductor layer 13. Thereby, an increase in leakage current and a decrease in breakdown voltage can be avoided.

[0044] Fig. 6 is a schematic cross-sectional view showing the semiconductor device 3 according to the embodiment. Fig. 6 is a cross-sectional view of the active region AR taken along the line B-B in Fig. 5(a). The semiconductor device 3 is, for example, a MOS transistor.

[0045] As shown in FIG. 6, the semiconductor device 3 includes a semiconductor part SP, a first electrode 20, a second electrode 30, and a control electrode 40. The first electrode 20 is, for example, a drain electrode. The second electrode 30 is, for example, a source electrode. The control electrode 40 is, for example, a gate electrode.

[0046] The semiconductor part SP is located between the first electrode 20 and the second electrode 30. The first electrode 20 is provided on the back surface of the semiconductor part SP. The second electrode 30 is provided on the front surface of the semiconductor part SP.

[0047] The control electrode 40 is disposed inside a trench GT provided on the front surface side of the semiconductor part SP. That is, the semiconductor device 3 has a trench gate structure. The control electrode 40 is, for example, located between the first electrode 20 and the second electrode 30. The control electrode 40 is electrically insulated from the semiconductor part SP by a first insulating film 43. Also, the control electrode 40 is electrically insulated from the second electrode 30 by a second insulating film 45. The first insulating film 43 is, for example, a gate insulating film. The second insulating film 45 is, for example, an interlayer insulating film.

[0048] The semiconductor part SP includes a first semiconductor layer 11, a second semiconductor layer 13, a third semiconductor layer 15 of a second conductivity type, a fourth semiconductor layer 17 of a first conductivity type, a fifth semiconductor layer 19 of a second conductivity type, and a sixth semiconductor layer 21 of a first conductivity type.

[0049] The first semiconductor layer 11 extends between the first electrode 20 and the second electrode 30. A plurality of second semiconductor layers 13 are provided in the first semiconductor layer 11 and are arranged in the Y direction. The first semiconductor layer 11 and the second semiconductor layers 13 constitute a so-called SJ structure. In this example, the control electrode 40 is located between each of the second semiconductor layers 13 and the second electrode 30.

[0050] The third semiconductor layer 15 is provided between the first semiconductor layer 11 and the second electrode 30. The third semiconductor layer 15 is located between adjacent control electrodes 40 and faces the control electrodes 40 via the first insulating film 43.

[0051] The fourth semiconductor layer 17 is partially provided on the third semiconductor layer 15 between the third semiconductor layer 15 and the second electrode 30. The fourth semiconductor layer 17 is provided at a position in contact with the first insulating film 43.

[0052] The fifth semiconductor layer 19 is partially provided on the third semiconductor layer 15 between the third semiconductor layer 15 and the second electrode 30. The fourth semiconductor layer 17 and the fifth semiconductor layer 19 are arranged side by side on the third semiconductor layer 15.

[0053] The second electrode 30 is connected to the fourth semiconductor layer 17 and the fifth semiconductor layer 19 on the surface of the semiconductor portion SP. The second electrode 30 is, for example, ohmically connected to the fourth semiconductor layer 17 and the fifth semiconductor layer 19.

[0054] The sixth semiconductor layer 21 is provided between the first semiconductor layer 11 and the first electrode 20. The sixth semiconductor layer 21 is formed, for example, by grinding and thinning the back surface of the semiconductor substrate 10. The first electrode 20 is, for example, ohmically connected to the sixth semiconductor layer 21.

[0055] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the gist of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are also included in the invention described in the claims and its equivalent scope.

Explanation of Reference Numerals

[0056] 1, 2, 3... semiconductor device, 10... semiconductor substrate, 11, 11a, 11b, 11c... first semiconductor layer, 13, 13a, 13b, 13c... second semiconductor layer, 13BS, 13PB... bottom surface, 13PP... pillar portion, 13PS, 13SS... side surface, 13TP... end portion, 13TS... surface, 15... third semiconductor layer, 17... fourth semiconductor layer, 19... fifth semiconductor layer, 20... first electrode, 21... sixth semiconductor layer, 30... second electrode, 40... control electrode, 43... first insulating film, 45... second insulating film, 100... wafer, 100F... surface, AR... active region, HM1, HM2, HM3... ion implantation mask, IB... ion beam, IF1... first interface, IF2... second interface, PL1... first plane, PL2... second plane, SP... semiconductor portion, GT... trench, TR... terminal region, WP1... first opening, WP2... second opening, WP3... third opening

Claims

1. A semiconductor part including a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type provided in the first semiconductor layer, wherein the semiconductor part includes a first interface between the first semiconductor layer and the second semiconductor layer and a second interface between the first semiconductor layer and the second semiconductor layer that intersects the first interface, the second semiconductor layer includes a plurality of portions laminated in a direction orthogonal to the first interface, the second interface includes an interface between the plurality of portions of the second semiconductor layer and the first semiconductor layer, the second interface extends in a second direction inclined with respect to a first direction orthogonal to the first interface, the crystal structure of the semiconductor part is hexagonal, the first direction and the second direction are included in the M plane of the hexagonal crystal, an inclination angle of the second direction with respect to the first direction is the same as an inclination angle of the first interface with respect to the C plane of the hexagonal crystal, the second semiconductor layer includes a plurality of extending portions extending in a direction along the first interface and arranged in a direction orthogonal to the direction along the first interface, and a terminating portion surrounding the plurality of extending portions, a semiconductor device.

2. A semiconductor part including a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type provided in the first semiconductor layer, wherein the semiconductor part includes a first interface between the first semiconductor layer and the second semiconductor layer and a second interface between the first semiconductor layer and the second semiconductor layer that intersects the first interface, the second semiconductor layer includes a plurality of portions laminated in a direction orthogonal to the first interface, the second interface includes an interface between the plurality of portions of the second semiconductor layer and the first semiconductor layer, the second interface extends in a second direction inclined with respect to a first direction orthogonal to the first interface, the crystal structure of the semiconductor part is hexagonal, the first direction and the second direction are included in the M plane of the hexagonal crystal, an inclination angle of the second direction with respect to the first direction in the M plane is a value obtained by adding 17 degrees to an inclination angle of the first interface with respect to the C plane of the hexagonal crystal or subtracting the inclination angle of the first interface from 17 degrees, the second semiconductor layer includes a plurality of extending portions extending in a direction along the first interface and arranged in a direction orthogonal to the direction along the first interface, and a terminating portion surrounding the plurality of extending portions, a semiconductor device.

3. ​ ​ The semiconductor device according to claim 1 or 2, wherein the concentration distribution of the second conductivity type impurity in the second semiconductor layer has a concentration peak of the second conductivity type impurity in each of the plurality of portions of the second semiconductor layer.

4. The semiconductor device according to any one of claims 1 to 3, wherein the direction from the center of the first interface to the center of the surface of the second semiconductor layer on the side opposite to the first interface is parallel to the second direction.

5. A first semiconductor layer of a first conductivity type, having a hexagonal crystal structure, forms a first ion implantation mask on the surface of the first semiconductor layer, By ion-implanting an impurity of a second conductivity type through the first opening of the first ion implantation mask in a channeling direction perpendicular to either the C plane of the hexagonal crystal or a crystal plane inclined 17 degrees with respect to the C plane and inclined with respect to the surface of the first semiconductor layer, the impurity of the second conductivity type is introduced into the first semiconductor layer, A second first semiconductor layer is formed on the first semiconductor layer, On the second first semiconductor layer, a second ion implantation mask having a second opening of the same size as the first opening of the first ion implantation mask is formed in a direction along the surface of the second first semiconductor layer and in a direction opposite to the direction in which the channeling direction is projected onto the surface of the second first semiconductor layer, such that the second opening is displaced with respect to the first opening, A method of manufacturing a semiconductor device, wherein the impurity of the second conductivity type is introduced into the second first semiconductor layer by ion-implanting the impurity of the second conductivity type in the channeling direction through the second opening of the second ion implantation mask.

6. The method of manufacturing a semiconductor device according to claim 5, wherein the amount of displacement of the second opening with respect to the first opening is the product of the thickness in the direction perpendicular to the surface of the second first semiconductor layer and the tangent of the inclination angle of the channeling direction with respect to the direction perpendicular to the surface of the second first semiconductor layer.

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