Method for manufacturing a silicon carbide semiconductor device

Abstract

To provide a manufacturing method for a silicon carbide semiconductor device that can reduce a charge imbalance.SOLUTION: A manufacturing method for a silicon carbide semiconductor device includes: a step (a) to form a drift layer of an n type on a silicon carbide semiconductor substrate of the n type through epitaxial growth; a step (b) to measure impurity concentration of the drift layer; a step (c) to form an ion implantation mask on the drift layer, the ion implantation mask including a plurality of first openings being periodically provided; a step (d) to implant impurity ions of a p type through the plurality of first openings, form a plurality of second pillar regions of the p type in the drift layer, and turn the drift layer between the second pillar regions into a first pillar region of the n type; a step (e) to form an epitaxial layer of the n-type on the drift layer through epitaxial growth; and a step (f) to form a plurality of unit cells of a transistor in the epitaxial layer. The step (d) includes a step to perform feedforward control on an ion implantation amount so that there is a positive correlation with measurement results of the step (b).SELECTED DRAWING: Figure 6

Description

Technical Field

[0001] The present disclosure relates to a method for manufacturing a silicon carbide semiconductor device, and more particularly, to a method for manufacturing a silicon carbide semiconductor device capable of improving the trade-off between breakdown voltage and on-resistance.

Background Art

[0002] As a semiconductor device used in power electronics, a vertical semiconductor element having electrodes on both surfaces of a semiconductor substrate is the mainstream. For example, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) or an IGBT (Insulated Gate Bipolar Transistor) is typical. In a normal vertical MOSFET, when it is in the off state, a depletion layer extends in the drift layer, which functions as a breakdown voltage holding layer. If the thickness of the drift layer is small or the impurity concentration of the drift layer is high, only a thin depletion layer can be formed, so the breakdown voltage of the element decreases. On the other hand, when the MOSFET is in the on state, a main current flows through the semiconductor substrate and the drift layer, and the resistance that this main current receives is called the on-resistance. The resistance of the drift layer, that is, the drift resistance, is high compared to the resistance of the semiconductor substrate, so it is one of the main resistance components of the MOSFET. Therefore, the on-resistance can be substantially reduced by reducing the drift resistance. Typical methods for this are to reduce the thickness of the drift layer or increase the impurity concentration of the drift layer. For this reason, there is a trade-off between high breakdown voltage and low on-resistance.

[0003] As a structure capable of improving this trade-off between breakdown voltage and on-resistance, for example, a super junction structure (SJ structure) as disclosed in Patent Document 1 has been proposed.

[0004] A super junction structure is a structure in which pillars of a second conductivity type and pillars of a first conductivity type are alternately arranged along a direction orthogonal to the direction in which the main current flows in the drift layer. According to this structure, in addition to the depletion layer spreading from the pn junction surface or the metal junction surface existing near the surface of the semiconductor element, a depletion layer also spreads from the pn junction surface between the pillars of the second conductivity type and the pillars of the first conductivity type. In the SJ structure, generally, both these pillars of the first conductivity type and the pillars of the second conductivity type are depleted during breakdown voltage retention, but at that time, it is designed so that the average value of the space charge per depth direction is near 0. This means that the termination of the electric field lines due to the space charge per depth direction can be ignored, and this state is called a charge-balanced state. Therefore, ideally, the impurity concentration of the SJ structure can be increased to a high concentration without reducing the breakdown voltage within the range where the pillars of the first conductivity type are depleted, so it is possible to significantly improve the trade-off between the on-resistance and the breakdown voltage, which was an issue in MOSFETs.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0006] In a silicon carbide semiconductor device as well, reduction of the resistance of the drift layer by the SJ structure is expected in the same way as in a silicon semiconductor device. On the other hand, when using silicon carbide, control of variations in impurity concentration becomes an issue. In particular, the drift layer that requires a low impurity concentration is generally formed by an epitaxial growth method (hereinafter referred to as epitaxial growth) by chemical vapor deposition (CVD method: Chemical Vaper Deposition). However, for epitaxial growth of silicon carbide, high temperature and precise control of the ratio of source gases of silicon and carbon are required, so variations in impurity concentration are relatively large. Therefore, even for epitaxial wafers of the same specifications, the drift layer concentration varies from wafer to wafer, for example, varying by about ±10 to 30% with respect to the central condition. Therefore, even if a pillar of the second conductivity type can be created without variation assuming that the conductivity type of the impurity in the drift layer is the first conductivity type, a deviation from the charge balance of ±10 to 30%, that is, charge imbalance occurs due to variations in the impurity concentration of the drift layer. As a result, the breakdown voltage in the SJ structure decreases.

[0007] Also, regarding the film thickness, although not as much as the carrier concentration, variations are relatively large in a silicon carbide semiconductor substrate, varying by about ±5 to 20% with respect to the central condition. Variations in film thickness cause charge imbalance in the region of the boundary between each epitaxial layer when adopting epitaxial growth in a multi-epitaxial method (hereinafter referred to as multi-epi method) that repeatedly performs epitaxial growth and ion implantation to form a pillar region, which can cause a decrease in breakdown voltage.

[0008] As described above, in realizing a silicon carbide MOSFET (SJ-SiC-MOSFET) having an SJ structure, since a decrease in breakdown voltage due to charge imbalance caused by variations in the impurity concentration (hereinafter referred to as epi concentration) of the epitaxial layer occurs, in order to achieve the same breakdown voltage, it is necessary to increase the film thickness of the epitaxial layer accordingly, resulting in a problem that the on-resistance decreases.

[0009] The present disclosure has been made to solve the above problems, and an object thereof is to provide a method for manufacturing a silicon carbide semiconductor device capable of reducing charge imbalance even when there are large variations in the epitaxial concentration and film thickness of a drift layer among a plurality of wafers.

Means for Solving the Problems

[0010] A method for manufacturing a semiconductor device according to the present disclosure includes: a step (a) of forming a drift layer of a first conductivity type by epitaxial growth on a silicon carbide semiconductor substrate of the first conductivity type; a step (b) of measuring the impurity concentration of the drift layer; a step (c) of forming an ion implantation mask having a plurality of first openings periodically provided on the drift layer; a step (d) of injecting impurity ions of a second conductivity type through the plurality of first openings to form a plurality of second pillar regions of the second conductivity type in the drift layer, and making the drift layer between the second pillar regions into a first pillar region of the first conductivity type; a step (e) of forming an epitaxial layer of the first conductivity type by epitaxial growth on the drift layer; and a step (f) of forming a plurality of unit cells of a transistor in the epitaxial layer. The step (d) includes a step of performing feedforward control on the ion implantation amount of the impurity ions so as to have a positive correlation with the measurement result in the step (b).

Advantages of the Invention

[0011] According to the method for manufacturing a semiconductor device according to the present disclosure, since the impurity concentration of the drift layer is measured and the ion implantation process for forming the second pillar region is feedforward controlled so as to have a positive correlation with the measurement result, a semiconductor device with reduced charge imbalance can be obtained.

Brief Description of the Drawings

[0012]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

Figure 15

Figure 16

Figure 17

Figure 18

Figure 19

Figure 20

Figure 21

Figure 22

Figure 23

Figure 24

Figure 25

Figure 26

Figure 27

Figure 28

Figure 29

Best Mode for Carrying Out the Invention

[0013] <First> Hereinafter, embodiments according to the present disclosure will be described with reference to the drawings. Note that the drawings are schematically shown, and the horizontal and vertical dimensions of each component in the drawings do not accurately represent the actual dimensions, and the dimensional ratios are not accurate. Further, in the following description, the same reference numerals are used to illustrate the same components, and their names and functions are also the same. Therefore, detailed descriptions thereof may be omitted.

[0014] In the following description, terms such as "upper", "lower", "side", "front" or "back" may be used to mean specific positions and directions. However, these terms are used for convenience in order to facilitate understanding of the content of the embodiments and have nothing to do with the directions in actual implementation.

[0015] In the following, "outer side" means the direction toward the outer periphery of the semiconductor substrate, and "inner side" means the direction opposite to the "outer side".

[0016] In the present disclosure, as a semiconductor device, a silicon carbide (SiC) semiconductor device is exemplified. In particular, an n-channel silicon carbide MOSFET with the first conductivity type being n-type and the second conductivity type being p-type will be described as an example. The description of the high and low potentials is for the case where the n-type is the first conductivity type and the p-type is the second conductivity type. When the n-type is the second conductivity type and the p-type is the first conductivity type, the description of the high and low potentials is reversed. Further, in the entire semiconductor device, a region where unit cells are periodically arranged is called an active region, and a region outside the active region is called an outer peripheral region.

[0017] <Embodiment 1> <Device Configuration> FIG. 1 is a plan view of an SJ-SiC-MOSFET 1000, which is a silicon carbide semiconductor device according to Embodiment 1 of the present disclosure, as viewed from the source electrode side, which is the upper surface. Note that FIG. 1 is also used as a plan view of an SJ-SiC-MOSFET 2000 according to Embodiment 2 to be described later.

[0018] As shown in FIG. 1, the SJ-SiC-MOSFET 1000 is a semiconductor chip having a rectangular shape in plan view, and a gate wiring 82 is provided so as to surround the outer periphery of a source electrode 80 that occupies most of the semiconductor chip. The gate wiring 82 extends from a gate pad 81 provided at a corner of the semiconductor chip. The gate pad 81 and the gate wiring 82 can be formed of the same conductor.

[0019] Note that the arrangement and shape of the source electrode 80, the gate pad 81, and the gate wiring 82 are merely examples and are not limited to FIG. 1.

[0020] FIG. 2 is a cross-sectional view taken along line A-A in FIG. 1 and shows the configuration of unit cells periodically and repeatedly arranged in the region below the source electrode 80. In the present embodiment, as an example, a trench-type MOSFET structure that is common in SJ-SiC-MOSFETs will be described.

[0021] In the SJ-SiC-MOSFET 1000 of Embodiment 1, a p-type field protection region 31 is provided below a trench gate TR, and a p-type pillar region 30 (second pillar region) is further provided therebelow, which is a feature.

[0022] That is, as shown in FIG. 2, in the SJ-SiC-MOSFET 1000, an n-type drift layer 20 is provided on a first main surface of an n-type silicon carbide semiconductor substrate 10. A p-type pillar region 30 formed by an ion implantation method and activation annealing is provided in the drift layer 20. Also, an n-type region in the drift layer 20 where the pillar region 30 is not formed is referred to as a pillar region 21 (first pillar region). The impurity concentration of the pillar region 21 can be the same as that of the drift layer 20, but in order to maximize the effect of the SJ structure, it can also be set to a higher impurity concentration by an additional epitaxial growth process or ion implantation process, etc.

[0023] As shown in FIG. 2, a region where the pillar region 21 and the pillar region 30 are repeatedly arranged in a repetition period d1 in the lateral direction of the paper surface, that is, the arrangement direction (x direction) of the trench gate TR, is referred to as an SJ region 100. The repetition period d1 can be referred to as a pillar pitch d1. In this SJ region 100, the pillar region 21 and the pillar region 30 are formed along the depth direction of the paper surface in a plan view, that is, the extending direction (y direction) of the trench gate TR, and the planar shape is formed in a stripe shape.

[0024] Also, a region above the SJ region 100 is referred to as a MOSFET region 200, and the pillar region 30 is connected to a p-type impurity region in the MOSFET region 200. In the case of a trench structure, it can be formed so as to be connected to a p-type field protection region 31.

[0025] In the MOSFET region 200, a trench gate TR is provided so as to reach from the outermost surface of the drift layer 20 into the drift layer 20. The trench gate TR is formed with a gate insulating film 50 made of silicon oxide or the like with a thickness of 25 to 150 nm so as to cover the inner surface of a trench formed by digging into the drift layer 20, and a gate electrode 60 made of polycrystalline silicon or the like is formed so as to fill the region surrounded by the gate insulating film 50. The trench gates TR are provided repeatedly with a repetition period d2, and the upper parts of the gate electrodes 60 are each covered by an interlayer insulating film 51 made of silicon oxide or the like.

[0026] An n-type source region 23 provided between the trench gates TR is selectively provided in the upper layer part of the drift layer 20, and a p-type body region 32 is provided under the source region 23. A p-type body contact region 33 is provided inside the source region 23 and the body region 32. The body contact region 33 is provided so as to penetrate the source region 23 but not penetrate the body region 32.

[0027] An ohmic electrode 70 is provided on the upper part of the body contact region 33, and the ohmic electrode 70 is connected to a source electrode 80 through an opening provided between the interlayer insulating films 51.

[0028] A pillar region 21, which is between the trench gate TR and the field protection region 31 at the lower part of the body region 32, is called a JFET region 22. Since the impurity concentration of the JFET region 22 is different from that of the SJ region 100 and charge balance is not required, it can be made higher than the pillar region 21 to reduce the JFET resistance. On the other hand, in order to reduce the manufacturing process, the same concentration as the pillar region 21, that is, the drift layer 20 which is an epitaxial layer can be used as it is.

[0029] The electric field protection region 31 provided at the bottom of the trench gate TR is connected to the body region 32 at a portion not shown in the depth direction in plan view, and has the source potential. Thereby, since the potential of the pillar region 30 connected to the electric field protection region 31 is fixed, the potential of the pillar region 30 can be stabilized.

[0030] Although it is preferable that the impurity concentration of the electric field protection region 31 is higher than that of the pillar region 30, it can be the same as that of the pillar region 30, or can be lower than that.

[0031] The impurity concentrations of the pillar region 21 and the pillar region 30 can vary due to process variations or the like, but in principle, they are designed to be generally charge-balanced. Charge balance means a condition in which the sum of the space charge densities when the pillar region 21 and the pillar region 30 are completely depleted at the same depth (constant in the z direction) cancels out positive and negative charges and becomes close to zero. Specifically, it can be realized by designing the SJ region 100 so that the product of the pillar width of the pillar region 21 and the impurity concentration of the pillar region 21 is approximately equal to the product of the pillar width of the pillar region 30 and the impurity concentration of the pillar region 30.

[0032] Of course, as a design range, the ratio of the total depletion layer charge at complete depletion at a certain depth, that is, the degree of charge balance, can be changed. For example, when the total number of depleted layer charges ionized in the pillar region 21 is Nntot and the total number of depleted layer charges ionized in the pillar region 30 is Nptot, the value of the ratio of the total depletion layer charges defined by Nntot / Nptot can be changed by about 0.5 to 2.0. The case where the value of Nntot / Nptot is 1 is a charge-balanced state, the case where it is greater than 1 and 2.0 or less is referred to as the "positive side", and the case where it is 0.5 or more and less than 1 is referred to as the "negative side".

[0033] If the ratio of the total depletion layer charge is on the positive side, the characteristics will be closer to those of an n-type MOSFET, making it possible to reduce the amount of minority carriers that cause the reverse recovery current of the body diode of the MOSFET. On the other hand, if it is on the negative side, the location where breakdown occurs can be shifted inside from the substrate surface, and by extending the conduction path of the avalanche current, the avalanche current can be suppressed and the avalanche withstand voltage can be increased.

[0034] In the SJ-SiC-MOSFET 1000 shown in FIG. 2, a configuration was shown in which the repetition period d1 of the pillar regions 21 and 30 in the SJ region 100 and the repetition period d2 of the trench gate TR in the MOSFET region 200 match, but they do not necessarily have to match. For example, as shown in FIG. 3, the repetition period d1 can be set to an integer multiple of the repetition period d2. In this case, the width of the pillar region 21 expands, and the spreading resistance caused by the main current path not spreading smoothly due to the depletion layer extending from the pillar region 30 can be reduced.

[0035] That is, even in the on state, a potential difference between the diffusion potential and the voltage drop in the pillar region 21 is added between the pn junctions of the pillar region 30 and the pillar region 21, and thus the depletion layer expands according to that value. The expanded depletion layer inhibits the main current path, so the main current path does not spread smoothly and the resistance of the main current path increases. On the other hand, when the width of the pillar region 21 expands, the main current path at the bottom of the trench gate TR expands, and the resistance of the main current path in the SJ region 100 decreases.

[0036] Similarly, the repetition period d2 does not necessarily have to match the repetition period d1. For example, as shown in FIG. 4, by adopting a configuration in which trench sources TS are arranged between the trench gates TR in the MOSFET region 200, the number of trench gates TR can be thinned and the input capacitance can be reduced.

[0037] The trench source TS has the same configuration as the trench gate TR. A gate insulating film 50 is formed to cover the inner surface of the trench formed by digging into the drift layer 20, and a trench source electrode 61 made of polycrystalline silicon or the like is formed so as to fill the region surrounded by the gate insulating film 50. Since the trench source electrode 61 is connected to the source electrode 80 at a portion not shown in the depth direction in the plane view, it does not function as a gate electrode.

[0038] Also, as shown in FIG. 5, by adopting a configuration in which a trench-type Schottky electrode 84 is arranged between the trench gates TR, a MOSFET incorporating an SBD (Schottky Barrier Diode) can be obtained. The trench-type Schottky electrode 84 is provided so as to fill the trench formed by digging into the drift layer 20 and is in contact with the source electrode 80. With this configuration, the conduction of the bipolar current during the reverse operation can be suppressed, and the increase in the on-voltage and the increase in the leakage current due to the crystal defects peculiar to SiC can be suppressed.

[0039] <Manufacturing Method> Next, the manufacturing method of the SJ-SiC-MOSFET1000 of Embodiment 1 will be described. In the manufacturing method of the silicon carbide semiconductor device according to the present disclosure, it is essential to apply a multi-epi method in which the formation of the n-type drift layer 20 by epitaxial growth and the formation of the p-type pillar region 30 by ion implantation are repeated one or more times to form the SJ structure. Hereinafter, the method of forming the SJ region 100 using the multi-epi method will be described with reference to the flowchart shown in FIG. 6.

[0040] FIG. 6 is a flowchart showing a manufacturing process including an ion implantation process in which feedforward is performed, which is a feature of the manufacturing method of the silicon carbide semiconductor device according to the present disclosure. Note that FIG. 6 shows only the important processes for explaining the effect of the implantation process by feedforward, and various processes, that is, cleaning and appearance inspection, etc. are performed between the respective processes.

[0041] As shown in FIG. 6, first, a silicon carbide semiconductor substrate 10 in a wafer state is obtained (step S10). Then, substrate cleaning or the like is performed to make the silicon carbide semiconductor substrate 10 in a clean state. This state is shown in FIG. 7. Then, an n-type epitaxial layer is formed to a thickness of several hundred nm to several tens of μm on the upper part of the silicon carbide semiconductor substrate 10 by epitaxial growth using the CVD method to form a drift layer 20 (step S20).

[0042] Thereafter, the average impurity concentration per wafer is quantified by CV measurement or the like to evaluate the concentration of the epitaxial layer (step S30). FIG. 8 schematically shows a state in which a voltmeter VM is connected to the back surface of the silicon carbide semiconductor substrate 10, a probe DT of a CV measurement device is arranged on the upper surface of the drift layer 20, and the carrier concentration of the depletion layer VC in the surface of the drift layer 20 is measured.

[0043] The carrier concentration of the epitaxial layer of a general silicon carbide semiconductor substrate is obtained, for example, by measuring the capacitances at a plurality of points in the plane of the silicon carbide semiconductor substrate using a CV measurement device having a mercury probe and calculating the carrier concentration for each measurement point from the capacitance values. The carrier concentrations for each measurement point are averaged to evaluate the average carrier concentration in the plane of the silicon carbide semiconductor substrate 10.

[0044] When the repetition of epitaxial growth and ion implantation is only once, a commercially available silicon carbide semiconductor substrate on which an epitaxial layer of a known concentration has been grown can also be used. In that case, since the epitaxial growth process can be omitted, the production equipment can be simplified.

[0045] Thereafter, a silicon oxide (SiO2) film is formed on the drift layer 20, a resist material is applied thereon, and the resist material is patterned by photolithography to form a resist mask RM as shown in FIG. 9. The silicon oxide film is patterned by dry etching using the resist mask RM to form an implantation mask SM for ion implantation (step S40). Note that since the implantation mask SM of silicon oxide has a high selectivity ratio with respect to silicon carbide, it can be etched without removing the drift layer 20. Note that it is not necessarily limited to SiO2 as long as it has a high selectivity ratio with respect to silicon carbide and is a chemically stable material.

[0046] After forming the implantation mask SM, the implantation amount of impurity ions is determined (step S60), and ion implantation of p-type impurities is performed using the implantation mask SM for ion implantation (step S70) to form a pillar region 30 in the drift layer 20 as shown in FIG. 10. After forming the pillar region 30, the SJ-SiC-MOSFET 1000 is completed through a conventional MOSFET manufacturing process (step S80).

[0047] (Feedforward to the implantation amount) Hereinafter, the determination of the implantation amount of impurity ions in step S60 will be further described. First, since the average impurity concentration per wafer of the drift layer 20 has been acquired in step S30, the implantation amount of impurity ions is determined based on this value. Specifically, it is determined so as to minimize the total charge imbalance formed in the plane of the drift layer 20.

[0048] For example, when the average impurity concentration per wafer of the drift layer 20 fluctuates by about ±15% with respect to the design center, if the ion implantation amount is similarly changed by about ±15%, the charge imbalance can be reduced within the range excluding the variations in the ion implantation process, the variations in the implantation mask, and the variations in the epi concentration within the wafer. That is, the implantation amount and the concentration of the epitaxial layer are controlled so as to have a positive correlation. Generally, the ion implantation process has little variation. In addition, since SiC has a very small thermal diffusion coefficient of the implanted ions, the implantation process in SiC has very little variation. By feeding forward the results of the epitaxial growth process with large variations to the implantation process, it becomes possible to significantly reduce the charge imbalance within the wafer.

[0049] Regarding the change in the implantation amount, in addition to changing the value each time within the specified range, for example, a work recipe stipulating simplified implantation conditions of two levels or more can be prepared in advance, and the work efficiency can also be improved by selecting the work recipe according to the average epi concentration of the wafer.

[0050] That is, the essential point of the present disclosure is that when an n-type transistor is assumed, the acceptor ion implantation amount is adjusted in proportion to the variation in the epi concentration, and the charge balance amount is kept as constant as possible. For example, when the epi concentration increases by 10% due to variations, the dose amount of the acceptor ions is also increased by 10% to have a positive correlation.

[0051] Therefore, simplifying this to two levels means preparing two-level implantation conditions for the control range of epi concentration that can vary in the production process. Specifically, in the case of an epitaxial layer production method with a ±20% variation from the central condition, a 20% region from the center to the high-concentration side, i.e., a region with a 20% higher concentration than the average, is provided, and a 20% region from the center to the low-concentration side, i.e., a region with a 20% lower concentration than the average, is provided. For the center of each region, the implantation amount of acceptor ions is determined so that the charge balance amount is constant. In this case, when the epi concentration finishes higher than the process center, the implantation amount of acceptor ions will increase by 10%, and when it finishes lower, it will decrease by 10%.

[0052] Note that instead of setting the implantation conditions individually for each wafer, by reducing the arbitrariness of the implantation conditions and processing them in a simplified process, such as setting condition A for wafers with a high concentration and condition B for wafers with a low concentration, the manufacturing process can be simplified. The specific feedforward method for the implantation amount will be described later.

[0053] (Feedforward by the opening width of the implantation mask) As a parameter for feedforward to the impurity implantation amount, not only the epi concentration but also the opening width of the implantation mask can be feedforwarded. For example, when the opening width increases, even with the same implantation amount, the amount of impurities supplied to a certain depth increases, so adjustment of the implantation amount is required to maintain the optimal charge balance.

[0054] Figure 11 is a flowchart showing a manufacturing process incorporating the step of evaluating the opening width of the implantation mask before determining the implantation amount of impurity ions. In Figure 11, before step S60 of determining the implantation amount of impurity ions, an evaluation of the finished shape of the implantation mask (step S50) for evaluating the opening width of the implantation mask is introduced.

[0055] In this case, the injection amount can be determined to have a negative correlation with respect to the average value within the wafer surface of the measured aperture width. Also, for improving work efficiency, the injection conditions can be prepared in advance as discrete conditions of two levels or more.

[0056] Here, the discrete injection conditions of two levels or more mean that if the resist aperture width varies by ±20% with respect to the design center, when the aperture width is larger than the design value, the dose amount is decreased by 10%, and when the aperture width is smaller than the design value, the dose amount is increased by 10%, and so on for the injection conditions.

[0057] The set value of the dose amount can also be set to have a negative correlation with respect to the aperture width, similar to the feedforward for the variation in the epi concentration. For example, when the aperture width is wider than the design center, the dose amount can be decreased by 7%, and conversely, it can be increased by 7%. Note that the absolute value of the feedforward amount when the aperture width is shifted up and down with respect to the design center does not necessarily have to be the same. For example, when the aperture width is wider than the design center, the dose amount can be decreased by 9%, but conversely, it can be increased by 5%.

[0058] Such settings can be changed according to how the finish of the aperture width is distributed with respect to the design center, that is, whether it is a normal distribution, uniformly distributed with a certain probability, symmetric with respect to the design center, etc. The specific feedforward method for the injection amount will be described later.

[0059] (Pillar injection) Ion implantation into the pillar region, that is, p-type pillar implantation (step S70) in FIGS. 6 and 11, is performed at an implantation energy that does not penetrate the photoresist and the ion implantation mask, that is, an implantation energy of several 100 keV to several MeV or less depending on the thickness of the ion implantation mask. While changing the implantation energy and the dose amount, the pillar region 30 is formed so as to have a uniform depth direction profile. A specific example thereof is shown in FIG. 12.

[0060] FIG. 12 shows an implantation profile in which the impurity concentration is shown on a logarithmic scale on the horizontal axis and the depth from the substrate surface is shown on a linear scale on the vertical axis.

[0061] As shown in FIG. 12, for example, by setting the implantation energy to three levels: low, medium, and high, a pillar region 30 with a uniform concentration is formed. In this specification, the ion implantation with feedforward is all of these implantations, and the purpose is to control the impurity concentration in the pillar region 30 that results from multiple-stage ion implantation. As the implanted element to be ion implanted, boron (B) or aluminum (Al) is used for the p-type.

[0062] (Multi-epi method) The epitaxial layer formation process shown in FIGS. 7 to 10 shows the case where the repetition of epitaxial growth and ion implantation is only once. In the multi-epi method where the repetition of epitaxial growth and ion implantation is repeated multiple times, after forming the pillar region 30, the resist mask RM and the implantation mask SM are removed, an n-type epitaxial layer is formed again, the epi concentration is evaluated, and through the steps below step S40 in FIG. 6 or FIG. 11, the pillar region 30 is extended in the vertical direction. These steps are repeated multiple times to form the SJ region 100 having the pillar region 21 and the pillar region 30. By performing the feedforward implantation for each repeated step, an SJ structure with minimized charge imbalance can be realized.

[0063] In the multi-epi method, it is also possible to add feedforward of the implantation energy with respect to the thickness of the epitaxial layer (hereinafter referred to as the epi film thickness).

[0064] FIG. 13 is a flowchart in which a step of evaluating the epitaxial film thickness is added after evaluating the concentration of the epitaxial layer, and a step of determining the implantation energy of impurity ions is added after determining the implantation amount of impurity ions. In FIG. 13, after step S30 of evaluating the concentration of the epitaxial layer, step S31 of evaluating the epitaxial film thickness is introduced, and after step S60 of determining the implantation amount of impurity ions, step S61 of determining the implantation energy of impurity ions is inserted.

[0065] To evaluate the epitaxial film thickness, as an example, it is carried out by measuring the epitaxial film thickness at a plurality of points in the wafer plane using a Fourier transform infrared spectrometer (FTIR) or the like and obtaining the average film thickness.

[0066] In this case, the energy of each implantation during multi-step implantation can be adjusted so as to have a positive correlation with the epitaxial film thickness. When the film thickness becomes unintentionally thick, by increasing the implantation energy of each step by a predetermined multiple, it is possible to prevent the connection of the pillar region 30 from weakening between each epitaxial layer. This specific example is shown in FIG. 14.

[0067] FIG. 14 shows implantation profiles with the impurity concentration shown on the horizontal axis in a logarithmic scale and the depth from the substrate surface shown on the vertical axis in a linear scale, in the case of "finished at design center" where the film thickness is finished as designed, the case of "finished film thickness" where the epitaxial film thickness becomes an unintended thickness, and the case of "finished film thickness + feedforward" where the implantation energy is feedforwarded when the epitaxial film thickness becomes an unintended thickness.

[0068] In FIG. 14, each implantation profile shows the case where epitaxial growth is performed twice and ion implantation is performed with three-step implantation energy for each epitaxial layer, and the boundary between the first epitaxial growth and the second epitaxial growth is shown by a dashed line.

[0069] When the film thickness finishes 10% higher than the design center, as shown in the implantation profile of "film thickness finish", a region where the concentration of the pillar region 30 locally decreases occurs near the boundary of epitaxial growth. Therefore, charge imbalance locally occurs in this region, or the resistance of the pillar region 21 increases, resulting in a decrease in breakdown voltage and switching speed. On the other hand, when the implantation energy is increased by 10% respectively in response to the increase in film thickness, the central implantation depth also increases by approximately 10%. As shown in the implantation profile of "film thickness finish + feed forward" in Fig. 14, the profile of the pillar region 30 can be made uniform, and the above-mentioned problems can be alleviated.

[0070] Conversely, when the film thickness becomes thinner, a region with a locally high impurity concentration occurs in the pillar region 30, resulting in a decrease in breakdown voltage due to the occurrence of charge imbalance. Similarly, in this case, the decrease in breakdown voltage can be eliminated by reducing the implantation energy below the design center.

[0071] In summary, by controlling the implantation energy so as to have a positive correlation with the epi film thickness, it is possible to suppress the occurrence of problems associated with the increase and decrease of the epi film thickness. The method of changing the implantation energy can be continuously changed, or it can be selected from discrete two-level or more conditions set in advance similar to the implantation amount.

[0072] So far, the multi-epi method of ion-implanting p-type impurities into an n-type epitaxial layer has been described, but n-type and p-type can be interchanged. Also, an epitaxial layer can be made into a region with a low impurity concentration, and an n-type region can be formed by full-surface ion implantation. When forming an n-type region, implantation of nitrogen (N) or phosphorus (P) is generally used as the impurity.

[0073] (Cost and device performance of the multi-epi method) In the multi-epi method, the manufacturing cost mainly depends on the number of multi-epi. On the other hand, when trying to reduce the number of multi-epi, special processes such as MeV ion implantation are required. Therefore, for example, due to the increase in implantation defects caused by the increase in implantation energy and the expansion of processing dimensions due to the thickening of the implantation mask, the performance of the semiconductor device tends to decrease. Although details will be described later, generally, in SJ-MOSFETs, as the miniaturization progresses, the higher the aspect ratio, the higher the concentration, and the shorter the repetition period, the higher the performance, that is, the lower the on-resistance at the same breakdown voltage. Therefore, in the multi-epi method, there is a trade-off between manufacturing cost and device performance, and the balance is mainly determined by the number of multi-epi.

[0074] (Concentration relationship in the SJ region) In the multi-epi method, the relationship between the impurity concentrations of the SJ region 100, the silicon carbide semiconductor substrate 10, and the drift layer 20 is as follows. First, for the n-type region, the silicon carbide semiconductor substrate 10 has the highest concentration. The drift layer 20 is designed to have the same concentration as or lower than the pillar region 21. Next, for the p-type region, the magnitude relationship of the concentrations varies depending on the design of the charge balance in the SJ region 100. Basically, within a certain plane in the depth direction in the SJ region 100, this is only for the active region, but if the total donor amount / total acceptor amount is in the range of 0.5 to 2, that is, in a state of being balanced in a half-and-a-half relationship, it can generally be regarded as having a charge balance.

[0075] (Depth direction concentration distribution in the SJ region) As a specific example of the first embodiment, FIG. 15 shows the cross-sectional structure of the SJ region 100 when the multi-epi method is repeated four times, and FIG. 16 shows the profiles of the average impurity concentrations in the depth direction of acceptor ions and donor ions in the SJ region 100. In the first embodiment, it is assumed that acceptor impurities by ion implantation are activated in the activation annealing process described later, and FIG. 16 shows only the profiles of activated donors and acceptors. Also, in this specification, basically, all quantitative discussions about impurity concentrations when discussing charge balance are performed only for activated impurities.

[0076] As shown in FIG. 15, in the cross-sectional structure of the SJ region 100 when the multi-epi method is repeated four times, a first-stage n-type pillar region 211, a second-stage n-type pillar region 212, a third-stage n-type pillar region 213, and a fourth-stage n-type pillar region 214, and a first-stage p-type pillar region 310, a second-stage p-type pillar region 302, a third-stage p-type pillar region 303, and a fourth-stage p-type pillar region 304 are formed.

[0077] In FIG. 16, the horizontal axis represents the depth from the surface of the SJ region 100 on a linear scale, the vertical axis represents the average impurity concentration in the depth direction on a linear scale, the profile of the impurity concentration of acceptor ions along the line A-A in FIG. 15 is shown by a broken line, and the profile of the impurity concentration of donor ions along the line B-B in FIG. 15 is shown by a solid line.

[0078] As shown in FIG. 16, for example, when the donor concentration of the epitaxial layer increases as in the second-stage n-type pillar region 212, the ion implantation amount is increased, and the acceptor concentration is increased as in the second-stage p-type pillar region 302 to maintain charge balance in a certain depth direction.

[0079] Also, when the epitaxial film thickness increases as shown in the third-stage n-type pillar region 213, the implantation energy and dose are adjusted according to the increase amount of the epitaxial film thickness, the implantation peak is dispersed as in the third-stage p-type pillar region 303, and the process is finished so as to minimize the generated charge imbalance.

[0080] (Method for forming MOSFET region) Next, a method for forming the MOSFET region 200 will be described with reference to FIG. 2. First, to form the MOSFET region 200, an n-type epitaxial layer is formed on the upper part of the SJ region 100. At this time, the number of processes can be reduced by controlling the epitaxial conditions so that the impurity concentration becomes equal to that of the JFET region 22.

[0081] Also, after forming the epitaxial layer with a low n-type impurity concentration, for example, 1×10 14 cm -3 , it can also be increased to the same concentration as the JFET region 22 by ion implantation. In this case, the variation in impurity concentration can be made smaller than that when forming an n-type epitaxial layer by epitaxial growth, and the variation reduction of the product and the increase in yield can be realized.

[0082] The impurity concentration of the JFET region 22 can be formed with an impurity concentration higher than that of the drift layer 20 and the pillar region 21, or can also be formed with the same impurity concentration. When the impurity concentration of the JFET region 22 is higher than that of the drift layer 20 or the like, the JFET resistance can be made low resistance, and when it is the same as that of the drift layer 20 or the like, the implantation process can be reduced and the cost can be reduced. The impurity concentration of the JFET region 22 can be, for example, 5×10 16 ~1×10 18 cm -3 . Also, the impurity concentrations of the drift layer 20 and the pillar region 21 are 1×10 15 ~1×10 17 cm -3If it is within the range, it can operate as a MOSFET. Although the impurity concentration of the drift layer 20 and the pillar region 21 is generally lower than that of the JFET region 22, if the pillar pitch is miniaturized in the SJ-SiC-MOSFET, the concentration can be increased. In that case, it is also possible to increase the concentration to the same level as the JFET region 22. The thickness of the n-type epitaxial layer formed on the upper part of the SJ region 100 is about 1 to 4 μm.

[0083] Next, acceptor ions such as Al are implanted into the n-type epitaxial layer by ion implantation to form the n-type body region 32. The impurity concentration of the body region 32 can be, for example, 5×10 17 ~1×10 19 cm ―3 . The impurity concentration of the body region 32 is made higher than that of the JFET region 22. The depth of the body region 32 can be about 0.5 to 1.5 μm. If the body region 32 is deeper, the channel length can be made longer, and the short-circuit withstand capacity can be increased. Also, the body region 32 can be formed by providing a p-type epitaxial layer.

[0084] Next, the source region 23 and the body contact region 33 are formed by ion implantation and photolithography. The n-type source region is formed by implanting impurities such as nitrogen (N) or phosphorus (P), and the impurity concentration is 1×10 18 ~1×10 21 cm -3 , which is a value exceeding the p-type impurity concentration of the body region 32. The body contact region 33 is obtained by forming p-type impurities such as Al or B at an impurity concentration of 5×10 18 ~1×10 22 cm ―3 exceeding the body region 32. The depths of the source region 23 and the body contact region 33 are about 200 nm to 1.0 μm.

[0085] Next, after the source region 23 and the body contact region 33 are formed, an SiO2 film is formed on the substrate, a resist material is applied thereon, the resist material is patterned by photolithography to form a resist mask, the SiO2 film is patterned by dry etching using the resist mask, and a mask for trench etching is prepared. Thereafter, a trench is formed that penetrates the body region 32 from the substrate surface and reaches the JFET region 22 by reactive ion etching (RIE) or the like. The depth of the trench is set to about 0.8 to 3.0 μm, and further, a p-type impurity is introduced by ion implantation at the lower part thereof to form an electric field protection region 31. The impurity concentration of the electric field protection region 31 can be, for example, 1×10 17 ~5×10 18 cm ―3 , and the depth thereof can be set to about 0.2 to 1.0 μm. At this time, by using the implantation mask for forming the electric field protection region 31 in combination with the mask for trench etching, the number of steps can be reduced.

[0086] Next, annealing is performed at a temperature of 1300 to 1900°C for 30 seconds to 1 hour in an inert gas atmosphere such as argon (Ar) gas by a heat treatment apparatus. By this annealing, the ion-implanted N and Al are electrically activated.

[0087] Next, the surface of the silicon carbide layer is thermally oxidized to form a silicon oxide film with a desired thickness, and the gate insulating film 50 is formed. The gate insulating film 50 covers the inner surface of the trench and also covers the surfaces of the source region 23 and the body contact region 33.

[0088] Next, a polycrystalline silicon film having conductivity is formed on the gate insulating film 50 by a reduced-pressure CVD method, and the gate electrode 60 is formed by patterning this. The polycrystalline silicon film fills the trench surrounded by the gate insulating film 50 and also covers the upper parts of the source region 23 and the body contact region 33, but the polycrystalline silicon film other than that in the trench is removed by patterning by etching or the like.

[0089] Next, a silicon oxide film is formed by a reduced-pressure CVD method to form the interlayer insulating film 51. At this time, the gate insulating film 50 remaining on the substrate becomes integral with the interlayer insulating film 51.

[0090] Next, openings are formed that penetrate the interlayer insulating film 51 and the gate insulating film 50 and reach the body contact region 33 and the source region 23 within the active region.

[0091] Next, for example, a metal film mainly composed of nickel (Ni) is formed by a sputtering method or the like, and then heat treatment is performed at a temperature of 600 to 1100 °C to react the metal film mainly composed of Ni with the silicon carbide layer within the opening, thereby forming a metal silicide between the silicon carbide layer and the metal film. Next, the metal film other than the metal silicide formed by the reaction is removed by wet etching. As a result, the remaining metal silicide becomes the ohmic electrode 70.

[0092] Next, a metal film mainly composed of Ni is formed on the back surface, which is the second main surface of the silicon carbide semiconductor substrate 10, and heat treatment is performed at a temperature of 600 to 1100 °C to form an ohmic electrode (not shown).

[0093] Next, a wiring metal such as Al is formed on the surface side of the silicon carbide semiconductor substrate 10 by a sputtering method or a vapor deposition method, and is processed into a predetermined shape by photolithography technology, so that, as shown in FIG. 1, a source electrode 80, a gate pad 81, and a gate wiring 82 are formed. The source electrode 80 is in contact with the ohmic electrode 70, and the gate pad 81 is in contact with the gate electrode 60.

[0094] Finally, by forming a drain electrode 83, which is a metal film, on the surface of the ohmic electrode (not shown) formed on the back surface of the silicon carbide semiconductor substrate 10, the SJ-SiC-MOSFET shown in FIGS. 1 to 5 is completed.

[0095] <Operation> Next, the operation of the SJ-SiC-MOSFET 1000 will be described. Hereinafter, the SJ-SiC-MOSFET with a 4H-type silicon carbide semiconductor material will be described as an example. Power devices perform various operations in power conversion devices such as inverters. As the operations and states in which the present disclosure exhibits effects, the off state and the on state will be described. Descriptions of other operation modes will be omitted.

[0096] <Off state> (Fully depleted) First, a general off state common to the n-channel SJ-SiC-MOSFET 1000 will be described. In the off state, the gate voltage is below the threshold value, generally 0 V or a few negative volts, and no n-channel is formed, resulting in a high-resistance state. In an inverter, a high voltage is applied to the drain of the element in this off state. In the case of an SJ-SiC-MOSFET, first, when a positive voltage starts to be applied to the drain, a reverse bias is applied to the pn junction between the pillars in the SJ region 100. Therefore, a depletion layer extends in the lateral direction of the SJ region 100. When a certain voltage is exceeded, the n-type pillar region 21 and the p-type pillar region 30 are completely depleted. As a result, the drain-source interval becomes significantly highly resistive, and the off state can be maintained. At this time, if the charge balance is not perfect, even if one side is completely depleted, the other side will not be completely depleted, resulting in an extra electric field.

[0097] (Avalanche) In the off state, when the drain voltage is further increased, the longitudinal electric field increases. Depending on the design, the location where the electric field is maximized is mainly the pn junction between the bottom or top body region 32 of the SJ region 100 and the JFET region 22, where the maximum electric field is applied. When the maximum electric field at this time exceeds the breakdown electric field of SiC (about 3 MV / cm), breakdown due to avalanche current occurs.

[0098] (Optimal design) Thus, it can be seen that adjusting the charge balance of the pillars is very important in the design of SJ-SiC-MOSFETs. As a direction for optimizing the design of these pillars, for example, the theory of Fujihira (T. Fujihira, "Theory of semiconductor superjunction devices" (Jpn. J. Appl. Phys., Vol. 36 (1997), pp6254-6262)) is well-known. Also in the present disclosure, the realization of an SJ region optimized based on the theory of Fujihira is assumed.

[0099] As an example, the result of the optimal design of the SJ region 100 is shown. Here, for the sake of simplicity, the case where the widths of the p-type pillars and the n-type pillars are equal and a simple pn diode structure as shown in Fig. 17 is described.

[0100] In Fig. 17, an anode A containing p-type impurities at a concentration Na and a cathode K containing n-type impurities at a concentration Nd are provided such that their pillar layers are interlaced with each other, and half of the width of the pillar layer is shown as d. Note that the portion where the p-type pillars and the n-type pillars are formed is referred to as the SJ layer.

[0101] When an optimal design based on the theory of Fujihira is carried out, the on-resistance of the characteristics of the SJ layer and the breakdown voltage of the semiconductor device are determined by the following mathematical formula (1).

[0102]

Equation

[0103] In the above mathematical formula (1), R on.sp. is the on-resistance of the characteristics, d is half of the pillar width, V B is the breakdown voltage, μ is the mobility, ε s is the dielectric constant of the semiconductor, and E c is the breakdown electric field.

[0104] Under the conditions of the optimal design for which the mathematical formula (1) holds, the maximum electric field when a breakdown voltage V B is applied to the cathode K is exactly the breakdown electric field Ec However, the breakdown is shown by the following mathematical formulas (2) and (3).

[0105]

Number

[0106]

Number

[0107] In the above mathematical formulas (2) and (3), E zmax is the maximum electric field in the longitudinal direction at the center of the SJ layer, and E xmax is also the maximum electric field in the transverse direction at the center of the SJ layer.

[0108] In the case of the pn diode structure shown in Fig. 17, the widths and impurity concentrations of the p-type pillars and n-type pillars are equal. When the cathode voltage rises to a certain voltage, depletion layers spread by a width d from the pn junction surfaces in the p-type pillars and n-type pillars, respectively. At this time, the n-type pillars and p-type pillars are completely depleted, and at the center of the SJ layer, the maximum electric field E xmax is applied in the transverse direction, and at the upper and lower ends of the pillar center of the SJ layer, the maximum electric field E zmax is applied in the longitudinal direction. When breakdown occurs, at the center of the SJ layer, the maximum electric field E xmax +E zmax is applied in the longitudinal direction at the upper and lower ends of the pillar center of the SJ layer. When this value reaches the breakdown electric field, breakdown occurs. In the case of this structure, as shown in mathematical formula (3), by designing the maximum electric fields in the longitudinal and transverse directions to be equal, the breakdown voltage and on-resistance can be maximized.

[0109] The impurity concentration N of the n-type pillars and p-type pillars in this optimal design is obtained by the following mathematical formula (4) from mathematical formulas (2) and (3) and Gauss's law.

[0110]

Number

[0111] The relationship between the pillar repeat period (pillar pitch), on-resistance, and impurity concentration N was calculated based on the above formula (4) and formula (1), and the results are shown in Figure 18. In Figure 18, the horizontal axis shows the pillar pitch 4d (μm), and the left vertical axis shows the characteristic on-resistance R on.sp。 (mΩcm 2 ) and the right vertical axis shows the impurity concentration N (cm -3 ) is shown.

[0112] In FIG. 18, the pillar pitch vs. on-resistance characteristic is B are plotted for 600V, 1200V, 3300V, 6500V and 13000V.

[0113] From Figure 18, it can be seen that the on-resistance tends to decrease as the pillar pitch (4d) decreases. It can also be seen that the impurity concentration increases as the pillar pitch (4d) decreases. Therefore, it can be said that if the pillar pitch is reduced and the on-resistance is reduced, the total amount of charge required for charging and discharging the pillars also tends to increase.

[0114] (While maintaining pressure) Next, the characteristics of the silicon carbide semiconductor device produced by the manufacturing method of the present disclosure, which are exhibited when the breakdown voltage is maintained, i.e., in the off state, will be described. When the breakdown voltage is maintained, the charge balance state of the SJ region 100 becomes a very important parameter, and the effect of the manufacturing method of the present disclosure is most prominent. First, the electric field distribution when the breakdown voltage is maintained in an ideal charge balance will be described, and then the behavior when the charge balance is lost will be described, followed by the specific feedforward injection control method and effect of the present disclosure.

[0115] (Ideal case) In the case of the pn diode structure shown in FIG. 17, the acceptor concentration and donor concentration are optimally designed, and charge balance is established, and the state when the withstand voltage is maintained, that is, the state when a voltage is applied just before dielectric breakdown occurs, is shown in FIG. 19.

[0116] In FIG. 19, the p-type pillars and the n-type pillars are completely depleted. FIG. 20 shows the electric field distribution obtained by plotting the absolute value of the electric field strength along the C-C line and the D-D line of the n-type pillars and the p-type pillars in this case with respect to the depth direction (z-axis). In FIG. 19, the surface of the anode A is set to z = 0, the tip of the n-type pillar is set to z t and the base of the n-type pillar is set to z b for representation.

[0117] In FIG. 20, the horizontal axis represents the position in the depth direction, and the vertical axis represents the absolute value of the electric field strength. In an ideal state, since the SJ layer is completely charge-balanced, the electric field distribution within the SJ layer becomes uniform, and the electric field distributions along the C-C line and the D-D line are line-symmetric distributions. This means that when viewed from a macroscopic perspective, no space charge appears to exist in the drift layer, that is, it appears like an insulator. In this case, the SJ layer attains the maximum breakdown voltage.

[0118] (When only the epi concentration varies) Next, consider the case where only the impurity concentration in the p-type region varies in the pn diode structure shown in FIG. 17. First, when the p-type region becomes highly concentrated, as shown in FIG. 21, the electric field distributions along the C-C line and the D-D line become asymmetric electric field distributions. The mechanism is as follows: As the voltage increases and the depletion layer expands, first, the p-type pillars are completely depleted. Thereafter, for the depletion of the remaining n-type pillars, depletion of the p-region above the p-type pillars is necessary. Therefore, the electric field lines emitted by the donor ions of the newly depleted n-type pillars are terminated by the acceptor ions in the p-region. Consequently, as the region where z is low, that is, the region closer to the p-region, the electric field of the SJ layer increases. This can be considered that, when viewed from a macroscopic perspective, the SJ layer becomes a thin n-type region by the amount of charge imbalance. Since the applied voltage is the value obtained by integrating the electric field strength along the path from the anode A to the cathode K, the breakdown voltage (dielectric breakdown voltage) decreases in proportion to the reduction in the area of the electric field distribution graph in FIG. 21 due to the charge imbalance.

[0119] On the other hand, when the impurity concentration of the n-type pillar is low, as shown in FIG. 22, contrary to FIG. 21, the electric field distribution at the C-C line and the electric field distribution at the D-D line are interchanged. That is, from a macroscopic perspective, it can be considered that the SJ layer is a p-type region that is thinner by the amount of charge imbalance. The breakdown voltage decreases in proportion to the decrease in the area of the electric field distribution graph in FIG. 22 due to charge imbalance.

[0120] (When only the concentration is fed forward) Next, a specific method of feeding forward the carrier concentration of the drift layer 20 to the ion implantation process and its effects will be described. FIG. 23 is a diagram showing the impurity concentration profile at a certain depth in the SJ region 100 in the cross section of FIG. 2. First, as a premise, a quantity indicating the degree of charge balance, that is, the charge balance amount, is defined, and on this basis, a method of keeping the charge balance amount at a constant value is presented.

[0121] In FIG. 23, the horizontal axis corresponds to the x-axis in FIG. 2, and the impurity concentration is shown on the vertical axis in a logarithmic scale. In FIG. 23, the acceptor ion concentration N A (x) is distributed in the x-axis direction with a period of the pillar pitch d1 corresponding to the pillar region 30. Regarding the distribution N D of the donor concentration N D , assuming that the epi concentration is uniform, it can be regarded as N D (x)=N D =constant. Here, the average donor concentration N Dave per pillar pitch d1 in the SJ region 100 is N Dave =N D ·d1 / d1=N D as shown. Also, the average number of acceptors N Aave per pillar pitch d1 is represented by the following mathematical formula (5).

[0122] [Number]

[0123] Using the above values, the charge balance amount α is defined by the following formula (6).

[0124]

Equation

[0125] The charge balance amount α means the excess or deficiency amount of the average concentrations of donors and acceptors when donors per pillar pitch d1 are positive and acceptors are negative.

[0126] When α = 0, N Dave = N Aave and it becomes a completely charge-balanced state. When α is a positive value, there is a donor excess, and when α is a negative value, there is an acceptor excess. Note that, as described above, only the activated concentrations of acceptors and donors are handled.

[0127] For example, when designing with α = 0 at the center design, that is, N Dave = N Aave = N mid If N Dave becomes 10% higher than the design center value N mid , the total donor amount N Dtot is N Dtot = 1.1·N mid and the total acceptor amount N Atot is N Atot = N mid Therefore, substituting this into formula (6), α = (1.1 - 1) / 1.1 ≒ 0.091.

[0128] This means that the net depletion layer impurity concentration at a certain depth in the SJ region 100 at complete depletion is +N mid ·0.091. Generally, the closer α is to 0, the greater the effect of improving the breakdown voltage by the SJ structure. However, for a structure that is not an SJ structure, that is, N AtotWhen =0 and α = 1, if it is designed so that the absolute value of α is smaller than this, that is, |α| < 1, it is possible to obtain the effect of improving the breakdown voltage due to flattening of the electric field distribution in the depth direction by the SJ structure, that is, neutralization of the drift layer from a macroscopic perspective.

[0129] In the present disclosure, the concentration of the drift layer 20 averaged within the wafer surface is set as a known concentration by performing an evaluation process such as CV measurement. Therefore, the average donor concentration N within the wafer surface in the mathematical formula (6) Dave becomes known.

[0130] First, the variation in the average donor concentration N Dave within the wafer surface is ignored for simplification. In this case, let the finished opening width of the implantation mask for implanting acceptor ions be Lp, and assume that a pillar region 30 having the same width as the finished opening width Lp of the implantation mask is formed. In this case, when the average donor concentration within the wafer surface varies by ±β%, the average donor concentration N Dave will deviate by ±β% from the design center value. Here, β is a positive real number of 50 or less. Therefore, by changing the change amount of the total donor amount N Dtot by ±β% with the acceptor dose amount D a by feedforward, the SJ region 100 can be finished without changing the charge balance amount α, and the effects according to the present disclosure can be fully enjoyed.

[0131] When enjoying the effects of the present disclosure by a simpler method, the conditions for the dose amount implemented by feedforward can be selected according to the impurity concentration of the drift layer 20 from a previously prepared specified value. For example, assuming a process in which the donor concentration varies by ±β% with respect to the donor concentration N D that is the design center. Here, β is, for example, 30. The acceptor dose amount D a is used as the donor concentration N DWhen it is divided into cases where it is larger and smaller than the design center, it can be determined to be (+β / 2)% when it is larger and (-β / 2)% when it is smaller. In this case, compared with the case where feed-forward injection is not performed, the variation in the charge balance amount can be halved. Similarly, the acceptor dose amount, the donor concentration N D The value of can also be divided into n regions within the range of ±β% with respect to the design center, and representative values can be prepared for each region. In this case, the variation in the charge balance amount can be reduced to 1 / n.

[0132] (When the aperture width is also feed-forwarded) Next, consider the case where the aperture width Lp of the resist for forming the injection mask for injecting acceptor ions is also feed-forwarded. The donor concentration N D is deviated by ±β% with respect to the design center, and the aperture width Lp of the resist is deviated by ±γ% with respect to the design center. Here, γ is a positive real number of 30 or less. For simplicity, ±β is denoted as β1 and ±γ is denoted as γ1. Note that β and γ are real numbers with an absolute value of 30 or less. When feed-forward is not performed, the total acceptor amount N Atot is represented by the following formula (7) with the design center as N Atot0 .

[0133]

Equation

[0134] Here, the charge balance amount α0 at the design center is represented by the following formula (8) with the design center of the total donor amount N Dtot as N Dtot0 .

[0135]

Equation

[0136] Here, when feed-forwarding the variation in the aperture width Lp of the resist and the donor concentration N D , the acceptor dose amount D a is the design center Da0 It is set to a value changed as represented by the following mathematical formula (9) with respect to

[0137]

Equation

[0138] In this case, the total amount of acceptors N per pillar pitch Atot1 is multiplied by the coefficient of the mathematical formula (9) representing the total amount of acceptors N when no feedforward is performed, so it is represented by the following mathematical formula (10). Atot Therefore, the charge balance amount α when feedforward injection of the mathematical formula (10) is performed is represented by the following mathematical formula (11).

[0139]

Equation

[0140] Therefore, by performing the feedforward injection of the mathematical formula (10), the coefficient due to the variation of the drift layer 20 and the coefficient due to the variation of the opening width of the resist can be offset, the charge balance amount α0 at the design center can be maintained, and the effects of the present disclosure can be fully enjoyed.

[0141]

Equation

[0142] From the above mathematical formula (11), by performing the feedforward injection shown in the mathematical formula (9), the coefficient due to the variation of the drift layer 20 and the coefficient due to the variation of the opening width of the resist can be offset, the charge balance amount α0 at the design center can be maintained, and the effects of the present disclosure can be fully enjoyed.

[0143] As described above, when performing feedforward injection including the opening width of the resist, the process can be simplified by selecting from a set of predefined conditions prepared in advance, similar to the case of feedforwarding only the carrier concentration. In this case, for the variation of the epi concentration ±β% and the variation of the resist opening width ±γ%, a certain control width is provided, and each of β and γ is divided into a finite number of intervals within the control width to form a matrix, and table data of the injection amount for it can be formed.

[0144] An example of this table data is shown in FIG. 24. In FIG. 24, an example is shown in which the variation γ of the resist opening width is divided into ranges of -15% to -5%, -5% to +5%, and +5% to +15%, and the variation β of the epi concentration is divided into ranges of -20% to -8%, -8% to +8%, and +8% to +20%. Then, with the resist opening width at the design center being x1 and the dose amount at the design center being Dref, for each variation range of the resist opening width and each variation range of the epi concentration, prescribed values prepared in advance are set.

[0145] For example, when only the epi concentration varies in the range of -20% to -8%, the dose amount is set to -14%, and when the epi concentration varies in the range of +8% to +20% and the resist opening width varies in the range of +5% to +15%, the dose amount is set to Dref·1.14 / 1.1.

[0146] The dose amount for feed-forward injection can be set to have a positive correlation with the variation of the epi concentration and a negative correlation with the variation of the resist opening width, as shown in Equation (9).

[0147] Finally, a method of feed-forwarding the film thickness of the drift layer 20 to the acceptor injection amount and injection energy will be described. As a basic concept, with the number of injections being constant, the interval between the peaks of the injection energy is increased or decreased according to the increase or decrease in the film thickness. The outline is shown in FIG. 25.

[0148] FIG. 25 is an injection profile showing the impurity concentration injected per depth on the horizontal axis on a logarithmic scale and the depth from the substrate surface on the vertical axis on a linear scale. First, an example of feed-forwarding the variation in the average film thickness within the wafer plane that occurs when performing epi growth for the second and subsequent times in a multi-epi structure to the injection energy will be described.

[0149] Specifically, when the average film thickness varies by ±δ%, for example, the implantation energy at each stage in multi-stage implantation is changed by ±δ% with the n-th stage as a representative. At this time, the implantation depth from the surface of the epitaxial layer at the peak concentration in the n-th stage implantation to the design center is t an is defined as, and the film thickness at the design center of each epi-layer is L mepi is defined as. FIG. 25 shows the case where the epi-layer formed at the k-th time is finished at the design center, and the case where the average film thickness of the epi-layer formed at the (k + 1)-th time is finished at +δ%.

[0150] By implementing such a feed-forward, since the implantation energy is proportional to the implantation depth, as shown in FIG. 25, it becomes possible to uniformly expand and contract the distribution of the peak positions of the multi-stage implantation of acceptors, and the depth-direction variation of charge imbalance can be suppressed.

[0151] Specifically, by changing the interval between implantation peaks, that is, the difference t an+1 -t an between the implantation depths of the n-th stage and the (n + 1)-th stage, by ±δ% in proportion to the variation in film thickness, the implantation depth of each stage can be uniformly increased or decreased. For simplicity, in this specification, it is assumed that the implantation depth t an and the implantation energy E an are proportional. However, for example, when a method such as implantation through a through-film such as SiO2 is used for the purpose of increasing the concentration on the surface of the epitaxial layer, the implantation energy E an is set as the energy E0 required for passing through the through-film, and the net energy E an implanted into SiC, which is obtained by subtracting the energy E0 from the implantation energy E an ', is controlled to vary by ±δ%.

[0152] As described above, when the film thickness of the drift layer 20 is fed forward to determine the implantation energy in the multi-step implantation process for forming the pillar region 30, if the implantation dose amount is not changed, the concentration with respect to the film thickness of the peak of the distribution formed by the acceptor ion implantation increases or decreases in inverse proportion to the film thickness variation δ%. That is, for example, when the film thickness increases by δ%, it is necessary to widen the energy interval of the multi-step implantation, whereby the average acceptor concentration in the pillar region 30 decreases by δ%. Therefore, when feeding forward the implantation energy based on the film thickness, it is desirable to perform a feed forward of the dose amount corresponding to the coarsening of the multi-step implantation profile separately from the feed forward for the epi concentration.

[0153] Specifically, when the film thickness increases or decreases by δ%, after setting the implantation energy by the method as described above, the implantation dose amount D a is set to the design center D a0 and changed to D a0 / (1 ± δ / 100), a desired acceptor concentration can be achieved and the charge balance amount can be optimally maintained.

[0154] Regarding the film thickness feed forward method in the first embodiment described above, it has been described for the second and subsequent epi growths, but it can also be applied to the first epi growth. In the case of the first epi growth, since there is no pillar region 30 formed in the previous epi growth, the above-described effects cannot be enjoyed. On the other hand, since the change in the distance between the lower end of the pillar region 30 and the silicon carbide semiconductor substrate 10 due to the film thickness can be alleviated, the electric field distribution can be alleviated and a certain effect on improving the breakdown voltage can be obtained.

[0155] <On state> The on-state of the SJ-SiC-MOSFET1000 will be described with reference to FIG. 2. When a positive voltage equal to or higher than the threshold value, for example, a voltage of about 15 V, is applied as the gate voltage, an n-type inversion layer channel is induced at the interface between the gate insulating film 50 and the channel region immediately below the gate insulating film 50, that is, the body region 32 sandwiched between the n-type pillar region 21 and the source region 23. As a result, the source region 23 and the JFET region 22 are connected with low resistance, and the drain electrode 83 and the source electrode 80 are connected with low resistance, resulting in an on-state.

[0156] The on-resistance of the SJ-SiC-MOSFET1000 is represented by the following mathematical formula (12).

[0157] [Number]

[0158] In the above mathematical formula (12), if the on-resistance is R on.sp. then the substrate resistance R SUB , the resistance R driftSJ of the drift layer 20 and the pillar region 21, the resistance R JFET of the JFET region 22, and the channel resistance R ch together determine the on-resistance R on.sp. . Among these, the component that most effectively achieves the effects of the present disclosure is the resistance R driftSJ .

[0159] (Comparison with Conventional SJMOSFET) Consider the comparison with a conventional SJ-SiC-MOSFET. In the case of a conventional multi-epi type SJ-SiC-MOSFET, since the impurity concentration in the pillar region 21 remains the same even when the epi concentration varies, charge imbalance occurs according to the variation in the epi concentration, resulting in a decrease in breakdown voltage. Therefore, in anticipation of a decrease in breakdown voltage, the thickness of the drift layer must be increased to ensure the breakdown voltage. As a result, the drift layer resistance increases in inverse proportion to the increase in thickness. Particularly when the epi concentration varies towards the lower side, in addition to this, the drift layer resistance increases in inverse proportion to the decrease in carrier concentration, and the conduction loss in the on-state significantly increases.

[0160] On the other hand, in the SJ-SiC-MOSFET 1000, since acceptor ion implantation can be performed under the conditions of feeding forward the film thickness, epi concentration, and injection resist opening width of the drift layer 20, charge imbalance caused by variations in epi concentration, injection resist opening width, and film thickness can be significantly suppressed, and variations in breakdown voltage can be remarkably suppressed. Therefore, compared with the conventional SJ-SiC-MOSFET, even if the film thickness of the drift layer is reduced, the breakdown voltage can be maintained, and the on-resistance can be reduced in proportion to the reduction in the film thickness of the drift layer. For this reason, the effect of increasing the breakdown voltage without increasing the on-resistance can be obtained.

[0161] In the first embodiment described above, the main focus is on measuring the variation in the impurity concentration of the drift layer 20 and feeding forward to the dose amount of the ion implantation process with less variation in principle. Further, by measuring the injection resist opening width, the amount of ions effectively implanted into the drift layer 20 is also fed forward. In addition, the variation in the film thickness of the epitaxial layer is measured, and by feeding forward to the ion implantation energy and dose amount, the effect of the present disclosure can be further enhanced. On the other hand, these feedforwards to the ion implantation energy and dose amount do not necessarily need to be applied to all parameters simultaneously. It is also possible to perform only the feedforward for the epi concentration, only the feedforward for the resist opening width, only the feedforward for the film thickness, or a combination of several of these. In that case, while enjoying the effect of the present disclosure to a certain extent, reduction of production load due to simplification of the number of processes can be achieved.

[0162] In order to maximize the effect of the present disclosure, it is desirable to perform feedforward so that the charge balance amount α defined by Equation (6) maintains a design center value α0 with an absolute value less than 1 regardless of the variation in the impurity concentration of the drift layer 20, the finish variation of the injection mask, and the variation in the film thickness of the multi-epi layer, and to determine the injection amount and injection energy.

[0163] However, in order to obtain the minimum effect, the variation in the charge balance amount α should be made less than the wafer-to-wafer variation in the in-wafer average of the impurity concentration in the drift layer 20, which is the main variation factor. This can reduce the breakdown voltage drop caused by the variation in the charge balance amount α due to the variation in the impurity concentration in the drift layer 20 compared to the case without feedforward, and the effect of the present disclosure can be minimally enjoyed.

[0164] <Embodiment 2> FIG. 26 is a plan view of the SJ-SiC-MOSFET 2000 according to Embodiment 2 in a state where the source electrode 80, the gate pad 81, and the gate wiring 82 are removed from the plan view shown in FIG. 1.

[0165] In the present Embodiment 2, it is characterized in that the breakdown voltage termination structure of the outer peripheral portion is formed under the same conditions as the implantation conditions of the pillar region 30.

[0166] First, the structure of a guard ring (GR), which is a breakdown voltage termination structure used in SiC power devices, and a field limiting ring (FLR) formed by combining a plurality of them will be described.

[0167] FIG. 26 shows the active region AR and the termination region TER provided on the outer periphery thereof. In the active region AR, the body region 32, the gate insulating film 50, the gate electrode 60, and the body contact region 33 are shown. In the termination region TER, the FLR region 400 is shown. Note that these are plan views of a general trench-type MOSFET, and the description thereof is omitted.

[0168] Also, a plurality of GRs 37 are provided concentrically in the FLR region 400. The GR 37 shown in FIG. 26 is a p-type region having an impurity concentration lower than that of the body region 32, and is formed with a gap from each other in the FLR region 400. The FLR region 400 is characterized in that the area ratio occupied by the GR 37 is provided so as to decrease toward the outer peripheral direction.

[0169] A plurality of GR37s arranged in this way form an FLR structure. The FLR structure has a structure in which, when viewed from a macroscopic perspective, the average impurity concentration of the p-type impurity region decreases as it goes in the outer peripheral direction. In the terminal region TER where the electric field is concentrated, it has the effect of smoothing the electric field distribution and maintaining the breakdown voltage with a small terminal region width.

[0170] On the other hand, if the epi concentration varies in the design of the FLR, the distribution of the impurity concentration in the terminal region TER when viewed from a macroscopic perspective changes. For example, when the epi concentration becomes high, the ratio of n-type impurities in the region outside the FLR increases, so the position where the electric field strength is maximum shifts toward the chip center side. Conversely, when the epi concentration becomes low, the point with the maximum electric field strength shifts toward the chip outer peripheral side. Considering these, it is common to design a wider FLR width compared to the case where there is no variation in the epi concentration.

[0171] In the second embodiment, the manufacturing process of this FLR is formed in the same process as the pillar region 30. That is, by feeding forward the information on the epi concentration and the film thickness of the epi layer to the implantation process of GR37, it is possible to minimize the variation in the epi concentration even in the terminal region TER. In addition to improving the breakdown voltage of the active region AR, the width of the FLR region 400 in the terminal region TER can be reduced, and the effect of suppressing the chip cost can be enjoyed.

[0172] This is because the mechanism of electric field relaxation in the FLR region 400 strongly depends on the relative relationship between the impurity concentration of the drift layer 20 and the implantation region, similar to the pillar region 30. Also, the process of creating the FLR region 400 and the process of forming the pillar region 30 can be shared, reducing the number of processes and suppressing the process cost.

[0173] The arrow cross-sectional view along line B-B shown in FIG. 26, that is, line B-B shown in FIG. 1, is shown in FIG. 27. Basically, the unit cell shown in FIG. 2 is periodically repeated for the active region AR. In the outer peripheral region 500 between the active region AR and the FLR region 400, the body region 32 extends to form, protecting the gate electrode 60 in the outer peripheral region 500 and the gate wiring 82 above it from the electric field of the drift layer 20.

[0174] Also, a field insulating film 52 is provided under the gate electrode 60 made of polycrystalline silicon. If only a thin gate insulating film is provided under the gate electrode 60 with a large area in the outer peripheral region 500, the gate insulating film may be subjected to electric field stress due to fluctuations in the drain voltage during the switching operation. Therefore, the reliability is enhanced by providing a thick field insulating film 52 in addition to the gate insulating film.

[0175] Also, in the lower part of the outer peripheral region 500, the pillar region 30 and the pillar region 21 are provided with the same period as the active region AR to form the SJ region 100, realizing the electric field distribution and breakdown voltage in the vertical direction.

[0176] In the FLR region 400, a plurality of GR37s formed by the same implantation mask and the same implantation process used for forming the pillar region 30 are formed such that the arrangement interval becomes wider toward the outside.

[0177] <Embodiment 3> In Embodiment 1 and Embodiment 2, the trench-type MOSFET has been described. However, the manufacturing method of the present disclosure can also be applied to a planar-type MOSFET.

[0178] FIG. 28 is a cross-sectional view showing the configuration of a unit cell of the planar SJ-SiC-MOSFET 3000 according to Embodiment 3. As shown in FIG. 28, in the SJ-SiC-MOSFET 3000, an n-type drift layer 20 is provided on the first main surface of an n-type silicon carbide semiconductor substrate 10. A p-type pillar region 30 formed by ion implantation and activation annealing is provided in the drift layer 20. Also, an n-type region in the drift layer 20 where the pillar region 30 is not formed is referred to as a pillar region 21.

[0179] As shown in FIG. 28, a region where the pillar region 21 and the pillar region 30 are repeatedly arranged in the lateral direction of the paper surface, that is, in the arrangement direction (x direction) of the gate electrodes 60, is referred to as an SJ region 100, which is the same as in Embodiment 1. In this SJ region 100, the pillar region 21 and the pillar region 30 are formed along the depth direction of the paper surface in a plan view, that is, in the extending direction (y direction) of the gate electrodes 60, and the planar shape is formed in a stripe shape.

[0180] Also, a region above the SJ region 100 is referred to as a MOSFET region 200, and the pillar region 30 is connected to a p-type impurity region in the MOSFET region 200.

[0181] In the MOSFET region 200, a p-type body region 32 is selectively provided in the upper layer portion of the drift layer 20, and an n-type source region 23 is provided in the surface of the body region 3. A p-type body contact region 33 is provided inside the source region 23 and the body region 32. The body contact region 33 is provided so as to penetrate the source region 23 but not penetrate the body region 32.

[0182] On the drift layer 20, a gate insulating film 50 made of silicon oxide or the like is provided so as to span between adjacent source regions 23, and a gate electrode 60 made of polycrystalline silicon or the like is provided on the gate insulating film 50. The gate electrodes 60 are each covered by an interlayer insulating film 51 made of silicon oxide.

[0183] An ohmic electrode 70 is provided above the body contact region 33, and the ohmic electrode 70 is connected to the source electrode 80 through an opening provided between the interlayer insulating films 51.

[0184] Below the gate insulating film 50, the n-type region between adjacent body regions 32 becomes the JFET region 22. Since the impurity concentration of the JFET region 22 is different from that of the SJ region 100 and charge balance is not required, it can be made higher than that of the pillar region 21 to reduce the JFET resistance.

[0185] When a planar MOSFET is adopted, the trench etching process and the process of forming the electric field protection region 31 at the bottom of the trench can be omitted, and the number of processes can be reduced. The process of forming the SJ region 100 is basically the same as that in the first embodiment. In addition, as an additional component, there is a JFET region 22 formed between adjacent body regions 32.

[0186] The on-resistance of the JFET region 22 can be further reduced by increasing the impurity concentration higher than that of the drift layer 20 and the pillar region 21 by an epitaxial process or an ion implantation process. On the other hand, in order to reduce the cleaning process, the same impurity concentration as that of the drift layer 20 or the pillar region 21 can also be adopted.

[0187] Note that the pillar region 30 is preferably provided below the center of the body region 32 that is periodically and repeatedly arranged. It is difficult to inhibit the current path in the on state, that is, the main current path flowing from the drain electrode 83 through the silicon carbide semiconductor substrate 10, the drift layer 20, the pillar region 21, the JFET region 22, and the source region 23 to the source electrode 80, and the effect of the SJ structure can be maximally enjoyed.

[0188] <Modification Example> As a modification example of the third embodiment, in the planar SJ-SiC-MOSFET 3000 as well, the breakdown voltage termination structure of the outer peripheral portion can be formed under the same conditions as the implantation conditions of the pillar region 30, similar to the second embodiment.

[0189] Fig. 29 shows a cross-sectional view corresponding to Fig. 27 of Embodiment 2. Basically, for the active region AR, the unit cells shown in Fig. 28 are periodically repeated. In the outer peripheral region 500 between the active region AR and the FLR region 400, the body region 32 extends to form, protecting the gate electrode 60 in the outer peripheral region 500 and the gate wiring 82 above it from the electric field of the drift layer 20.

[0190] In the FLR region 400, a plurality of GR37s formed by the same implantation mask and the same implantation process as those used for forming the pillar region 30 are formed such that the arrangement intervals become wider toward the outside.

[0191] By forming the manufacturing process of the FLR in the same process as that of the pillar region 30, information on the epi concentration and the film thickness of the epi layer can be fed forward to the implantation process of GR37, and variations in the epi concentration can also be minimized in the terminal region TER. As a result, while enjoying the effect of optimizing the charge imbalance in the active region AR, it is possible to enjoy the effect of reducing variations in the electric field distribution in the terminal region TER and reducing the width of the FLR region 400. Note that an SJ region 100 is formed at the lower part of the outer peripheral region 500 in the same manner as the lower part of the active region AR.

[0192] Note that within the scope of the present disclosure, the respective embodiments can be freely combined, or each embodiment can be appropriately modified or omitted.

[0193] The present disclosure described above is summarized as an appended note.

[0194] (Appended Note 1) (a) A step of forming a drift layer of a first conductivity type by epitaxial growth on a silicon carbide semiconductor substrate of the first conductivity type; (b) A step of measuring the impurity concentration of the drift layer; (c) A step of forming an ion implantation mask having a plurality of first openings periodically provided on the drift layer; (d) Injecting impurity ions of the second conductivity type through the plurality of first openings to form a plurality of second pillar regions of the second conductivity type in the drift layer, and making the drift layer between the second pillar regions into a first pillar region of the first conductivity type; (e) Forming an epitaxial layer of the first conductivity type by epitaxial growth on the drift layer; (f) Forming a plurality of unit cells of a transistor in the epitaxial layer, comprising: The step (d) includes a step of feedforward controlling the ion implantation amount of the impurity ions so as to have a positive correlation with the measurement result in the step (b), a method for manufacturing a silicon carbide semiconductor device.

[0195] (Appendix 2) Between the step (b) and the step (c), (g) Further comprising a step of measuring the film thickness of the drift layer; The step (d) Further includes a step of feedforward controlling the ion implantation energy of the impurity ions so as to have a positive correlation with the measurement result in the step (g), a method for manufacturing a silicon carbide semiconductor device according to Appendix 1.

[0196] (Appendix 3) (a) Forming a drift layer of the first conductivity type by epitaxial growth on a silicon carbide semiconductor substrate of the first conductivity type; (b) Measuring the film thickness of the drift layer; (c) Forming an ion implantation mask having a plurality of first openings periodically provided on the drift layer; (d) Injecting impurity ions of the second conductivity type through the plurality of first openings to form a plurality of second pillar regions of the second conductivity type in the drift layer, and making the drift layer between the second pillar regions into a first pillar region of the first conductivity type; (e) Forming an epitaxial layer of the first conductivity type by epitaxial growth on the drift layer; (f) Forming a plurality of unit cells of a transistor in the epitaxial layer, comprising: The method for manufacturing a silicon carbide semiconductor device, wherein the step (d) includes a step of performing feedforward control on the ion implantation energy of the impurity ions so as to have a positive correlation with the measurement result in the step (b).

[0197] (Appendix 4) Between the step (b) and the step (c), (g) Further comprising a step of measuring the impurity concentration of the drift layer, The step (d) is, The method for manufacturing a silicon carbide semiconductor device according to Appendix 3, further comprising a step of performing feedforward control on the ion implantation amount of the impurity ions so as to have a positive correlation with the measurement result in the step (g).

[0198] (Appendix 5) Between the step (c) and the step (d), (h) Further comprising a step of measuring the average opening width of the plurality of first openings of the ion implantation mask, The step (d) is, The method for manufacturing a silicon carbide semiconductor device according to Appendix 1 or Appendix 4, further comprising a step of performing feedforward control on the ion implantation amount so as to have a negative correlation with the measurement result in the step (h).

[0199] (Appendix 6) The step (d) is to set at least two levels of implantation conditions for the impurity ions to perform ion implantation with respect to the width of the variation in the impurity concentration of the drift layer, in the method for manufacturing a silicon carbide semiconductor device according to Appendix 1 or Appendix 4.

[0200] (Appendix 7) The step (c) is, Forming the ion implantation mask so as to have a plurality of second openings for forming a plurality of guard rings on the outer peripheral portion of the silicon carbide semiconductor substrate, The step (d) is, Inject the impurity ions of the second conductivity type through the plurality of second openings, and form the plurality of guard rings in the outer peripheral portion with the same implantation profile as that of the second pillar region, the method for manufacturing a silicon carbide semiconductor device according to Appendix 1 or Appendix 3.

[0201] (Appendix 8) The transistor is a trench-type transistor having a trench gate provided in an epitaxial layer, The step (f) is a step of forming an electric field protection region of the second conductivity type with a higher concentration than that of the second pillar region at the bottom of the trench gate, the method for manufacturing a silicon carbide semiconductor device according to Appendix 1 or Appendix 3, wherein the electric field protection region is connected to the second pillar region.

[0202] (Appendix 9) The transistor is a planar-type transistor having a gate provided on an epitaxial layer, The step (f) is a step of forming a body region of the second conductivity type with a higher concentration than that of the second pillar region in the upper layer portion of the epitaxial layer, the method for manufacturing a silicon carbide semiconductor device according to Appendix 1 or Appendix 3, wherein the body region is connected to the second pillar region.

Explanation of Reference Numerals

[0203] 10 Silicon carbide semiconductor substrate, 20 Drift layer, 21, 30 Pillar region, 31 Electric field protection region, 32 Body region, 37 Guard ring.

Claims

1. (a) A step of forming a drift layer of a first conductivity type by epitaxial growth on a silicon carbide semiconductor substrate of the first conductivity type; (b) A step of measuring the impurity concentration of the drift layer; (c) A step of forming an ion implantation mask having a plurality of first openings periodically provided on the drift layer; (d) Injecting impurity ions of a second conductivity type through the plurality of first openings to form a plurality of second pillar regions of the second conductivity type in the drift layer, and making the drift layer between the second pillar regions a first pillar region of the first conductivity type; (e) A step of forming an epitaxial layer of the first conductivity type by epitaxial growth on the drift layer; (f) A step of forming a plurality of unit cells of a transistor in the epitaxial layer, and The step (d) includes a step of feed-forward controlling the ion implantation amount of the impurity ions so as to have a positive correlation with the measurement result in the step (b). A method for manufacturing a silicon carbide semiconductor device.

2. Between the step (b) and the step (c), (g) Further comprising a step of measuring the film thickness of the drift layer, The step (d) Further includes a step of feed-forward controlling the ion implantation energy of the impurity ions so as to have a positive correlation with the measurement result in the step (g). The method for manufacturing a silicon carbide semiconductor device according to claim 1.

3. (a) A step of forming a drift layer of a first conductivity type by epitaxial growth on a silicon carbide semiconductor substrate of the first conductivity type; (b) A step of measuring the film thickness of the drift layer; (c) A step of forming an ion implantation mask having a plurality of first openings periodically provided on the drift layer; (d) Injecting impurity ions of a second conductivity type through the plurality of first openings to form a plurality of second pillar regions of the second conductivity type in the drift layer, and making the drift layer between the second pillar regions a first pillar region of the first conductivity type; (e) A step of forming an epitaxial layer of the first conductivity type by epitaxial growth on the drift layer; (f) A step of forming a plurality of unit cells of a transistor in the epitaxial layer, and The step (d) includes a step of feed-forward controlling the ion implantation energy of the impurity ions so as to have a positive correlation with the measurement result in the step (b). A method for manufacturing a silicon carbide semiconductor device.

4. Between the step (b) and the step (c), (g) further comprising a step of measuring the impurity concentration of the drift layer, The step (d) is, The method for manufacturing a silicon carbide semiconductor device according to claim 3, further comprising a step of feed-forward controlling the ion implantation amount of the impurity ions so as to have a positive correlation with the measurement result in the step (g).

5. Between the step (c) and the step (d), (h) further comprising a step of measuring the average opening width of the plurality of first openings of the ion implantation mask, The step (d) is, The method for manufacturing a silicon carbide semiconductor device according to claim 1 or claim 4, further comprising a step of feed-forward controlling the ion implantation amount so as to have a negative correlation with the measurement result in the step (h).

6. The method for manufacturing a silicon carbide semiconductor device according to claim 1 or claim 4, wherein in the step (d), at least two levels of implantation conditions are set with respect to the width of the variation in the impurity concentration of the drift layer, and the impurity ions are ion-implanted.

7. The step (c) is, forming the ion implantation mask so as to have a plurality of second openings for forming a plurality of guard rings on the outer peripheral portion of the silicon carbide semiconductor substrate, The step (d) is, injecting the impurity ions of the second conductivity type through the plurality of second openings, and forming the plurality of guard rings with the same implantation profile as the second pillar region in the outer peripheral portion. The method for manufacturing a silicon carbide semiconductor device according to claim 1 or claim 3.

8. The transistor is, a trench-type transistor having a trench gate provided in an epitaxial layer, The step (f) is, having a step of forming a second-conductivity-type electric field protection region having a higher concentration than the second pillar region at the bottom of the trench gate, The method for manufacturing a silicon carbide semiconductor device according to claim 1 or claim 3, wherein the electric field protection region is connected to the second pillar region.

9. The transistor is, a planar-type transistor having a gate provided on an epitaxial layer, The step (f) is, having a step of forming a second-conductivity-type body region having a higher concentration than the second pillar region in the upper layer portion of the epitaxial layer, The method for manufacturing a silicon carbide semiconductor device according to claim 1 or claim 3, wherein the body region is connected to the second pillar region.

Images