Solid-state imaging device

Abstract

This solid-state imaging device comprises a pixel array in which pixels (10) are arranged in a matrix form. The pixels (10) have a photoelectric conversion unit (24) that generates a signal charge on the basis of incident light, and light-shielding element separation layers (22, 23) that surround the periphery of the photoelectric conversion unit (24). In the row direction and the column direction, the element separation layers (22, 23) of adjacent pixels (10) are mutually separated. In the row direction and the column direction, in a region sandwiched by the element separation layers (22, 23) of adjacent pixels (10), a charge storage layer (13) and a charge capture layer (11) are provided. The charge storage layer (13) stores the signal charge, and the charge capture layer (11) suppresses the incidence of light on the charge storage layer (13).

Description

Technical Field

[0001] The present disclosure relates to a solid-state imaging device.

Background Art

[0002] In smartphones, digital cameras, etc., solid-state imaging devices are used to acquire images. As a method of the shutter of the solid-state imaging device, a method of providing a charge holding portion in a pixel and simultaneously reading out pixel signals from all pixels (global shutter method) is known. Further, in order to suppress the leakage of light into the charge holding portion, it is known to provide a light-shielding element isolation layer and a charge trapping region (Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] To realize a solid-state imaging device in which well separation does not deteriorate when a charge trapping layer is provided for a pixel array.

Means for Solving the Problems

[0005] The solid-state imaging device includes a pixel array in which pixels are arranged in a matrix. Each pixel has a photoelectric conversion portion that generates signal charges based on incident light, and an element isolation layer that surrounds the periphery of the photoelectric conversion portion. In both the row direction and the column direction, the element isolation layers of adjacent pixels are separated from each other. A charge storage layer that accumulates signal charges and a charge trapping layer that suppresses the incidence of light on the charge storage layer are provided in a region sandwiched between the element isolation layers of adjacent pixels.

Effects of the Invention

[0006] According to the solid-state imaging device of the present disclosure, even when pixels are arranged in a matrix and a charge trapping layer is provided, the separation of wells is good.

Brief Description of the Drawings

[0007]

Figure 1

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Figure 11

Embodiments for Carrying Out the Invention

[0008] (First Embodiment) Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. FIG. 1 is a diagram schematically showing a planar layout of an exemplary solid-state imaging device. FIGS. 2, 3, and 4 are schematic cross-sectional views taken along lines II-II', III-III', and IV-IV' in FIG. 1, respectively.

[0009] FIG. 1 shows three pixels 10 arranged vertically in the figure (one of the pixels 10 is shown surrounded by a broken line). The pixels 10 may be further arranged vertically or may be arranged horizontally to form a matrix-like pixel array.

[0010] The pixel 10 includes an N-type photoelectric conversion unit 24 (e.g., composed of a photodiode) that photoelectrically converts incident light to generate signal charges, an overflow drain 28 that can discharge the charges of the photoelectric conversion unit 24, and an overflow gate 27 that controls the movement of charges to the overflow drain 28. Further, a plurality of transistors 25 are arranged on the side opposite to the overflow drain 28 of the photoelectric conversion unit 24. The transistor 25 is a transistor used for controlling charge readout, reset, selection of readout pixels, etc. in the pixel 10.

[0011] As shown in FIG. 2, the photoelectric conversion unit 24 is formed as an N-type region on the substrate, and a surface passivation layer is provided as a thin P-type layer 14 above the photoelectric conversion unit 24 (substrate surface portion) in cross-section. Further, an N-type charge storage layer 13 (memory node) is provided near the substrate surface in the P-well 20 on the side of the photoelectric conversion unit 24. A thin P-type layer 14 is also provided above the charge storage layer 13. Note that the exemplary solid-state imaging device is a back-illuminated type, and light is incident from below in the figure (indicated by arrow 51).

[0012] A first transfer gate 16 for controlling the movement of signal charges from the photoelectric conversion unit 24 to the charge storage layer 13 is provided on the substrate.

[0013] Below the charge storage layer 13, a charge trapping layer 11 is provided via a P-well 20. On both sides of the charge trapping layer 11, a light-shielding device isolation layer (DTI: Deep Trench Isolation) is provided. More specifically, in one pixel 10, a non-penetrating DTI 23 that reaches the lower end of the substrate but not the upper end is provided between the charge storage layer 13 and the photoelectric conversion unit 24. In order to provide a path for moving charges from the photoelectric conversion unit 24 to the charge storage layer 13, the device isolation layer at this location is the non-penetrating DTI 23. Also, on the side opposite to the photoelectric conversion unit 24 (the end side of the pixel 10) with respect to the charge trapping layer 11, a penetrating DTI 22 that reaches both the upper and lower ends of the substrate is provided.

[0014] Also, a back surface light-shielding film 15 is provided so as to cover the back surface side of the substrate with respect to the charge trapping layer 11.

[0015] Such a penetrating DTI 22, non-penetrating DTI 23, and back surface light-shielding film 15 suppress the incidence of light on the charge storage layer 13, which is a memory node. Also, light incident from the back surface side may leak in from the portion of the non-penetrating DTI 23. However, since it becomes a path of reflection on the front surface side of the substrate (the back side of the first transfer gate 16 in the figure as an example) as indicated by the arrow 51, such light generally enters the charge trapping layer 11. As a result, the leaked light is photoelectrically converted in the charge trapping layer 11, and it is suppressed that the leaked light is mixed into the signal charges of the charge storage layer 13.

[0016] In this way, by providing the charge trapping layer 11, it is possible to suppress the leakage of light into the charge storage layer 13 (or the addition of charges derived from the leaked light to the signal charges), and reduce the deterioration of image quality.

[0017] The signal charges stored in the charge storage layer 13 are transferred to the floating diffusion 18. To control this, a second transfer gate 17 is provided. FIG. 3 shows a cross section taken along line III-III' passing over the floating diffusion 18. Also in the cross section of FIG. 3, through DTI 22 and non-through DTI 23 are provided on both sides of the charge trapping layer 11. The region on the opposite side of the charge trapping layer 11 via the non-through DTI 23 is provided with a P-type deep well region 26 for separating the photoelectric conversion units 24 for each pixel 10. A back surface light-shielding film 15 is also provided for the deep well region 26. On the surface side with respect to the deep well region 26, a transistor including an N+ layer 30 which is a source region or a drain region and a gate electrode 32 is formed.

[0018] The first transfer gate 16, the second transfer gate 17, the charge storage layer 13, the floating diffusion 18, etc. are also shown in FIG. 4 which is a cross section taken along line IV-IV' of FIG. 1. With respect to the floating diffusion 18, STI 19 (Shallow Trench Isolation) is provided as an element isolation region on the side opposite to the second transfer gate 17. Further, the charge trapping layer 11 includes an extension region 31 extended to a region outside the arranged region (pixel array) of the pixels 10 (see FIGS. 1 and 4). For the extension region 31, a terminal 21 for making an electrical connection to the charge trapping layer 11 is provided on the surface side of the substrate.

[0019] By providing the extension region 31 in this way, it becomes unnecessary to provide a terminal in the pixel array for the charge trapping layer 11, so the degree of freedom in layout increases and it contributes to reducing the area of the pixel array.

[0020] (Second Embodiment) Next, an example will be described in which the pixels 10 are arranged in a matrix (two-dimensionally), and charge trapping layers 11 etc. are provided between the pixels 10 in both the row direction and the column direction.

[0021] FIG. 5 is a plan view schematically showing four representative pixels 10 arranged in a matrix, specifically two rows and two columns. Here too, each pixel 10 is provided with a photoelectric conversion section 24, which is surrounded by a light-shielding element isolation layer. More specifically, through DTI 22 is provided on two adjacent sides (the upper and right sides in FIG. 5) of the substantially square photoelectric conversion section 24, and non-through DTI 23 is provided on the other two sides (the left and lower sides in FIG. 5). The two sides of the non-through DTI 23 are connected to form an L shape, but the two sides of the through DTI 22 are separated, and a non-through DTI 23a with a small occupation area is provided in the gap (the upper right corner portion of the photoelectric conversion section 24 in FIG. 5).

[0022] Also, FIG. 5 shows the charge trapping layer 11 provided between the pixels 10. As shown in FIG. 5, the element isolation layer surrounding the photoelectric conversion section 24 is provided individually for each pixel 10. That is, between adjacent pixels 10, the element isolation layers (through DTI 22, non-through DTI 23) are not connected to each other. The charge trapping layer 11 is provided in such an area between pixels (between the element isolation layers). The charge trapping layer 11 is provided between pixels in both the row direction and the column direction. Therefore, the charge trapping layer 11 can be provided as a grid-like area extending vertically and horizontally (row direction, column direction).

[0023] Next, FIG. 6 shows the configuration related to the transfer of the signal charge generated in the charge trapping layer 11. Further, FIG. 7 shows a cross section taken along line VII-VII' in FIG. 5.

[0024] Regarding the pixel 10 of the present embodiment, the cross-sectional structure is similar to that shown in FIGS. 2, 3, and 4. As shown in FIG. 7, the photoelectric conversion unit 24 is formed as an N-type region on the substrate, and a thin P+-type layer is provided above the photoelectric conversion unit 24 (substrate surface portion) in the cross section. An N-type charge storage layer 13 (memory node) is provided near the substrate surface in the P well 20 on the side of the photoelectric conversion unit 24 with the non-penetrating DTI 23 interposed therebetween. A thin P-type layer is also provided above the charge storage layer 13. On the substrate, a first transfer gate 16 for controlling the movement of signal charges from the photoelectric conversion unit 24 to the charge storage layer 13 is provided. Further, a floating diffusion 18 to which signal charges are transferred from the charge storage layer 13 and a second transfer gate 17 for controlling this transfer are provided. An STI 19 is provided as an element isolation region on the side opposite to the second transfer gate 17 with respect to the floating diffusion 18. Further, transistors 25, a VDD region 12, and yet another transistor 25 are sequentially configured. Each of the transistors 25 may include a plurality of transistors. A region 42 where a P well is not formed is disposed below the VDD region 12.

[0025] A charge trapping layer 11 is provided below the charge storage layer 13, the floating diffusion 18, etc., with the P well 20 interposed therebetween. A back surface light-shielding film 15 is provided below the charge storage layer 13 so as to cover the back surface of the substrate. The back surface light-shielding film 15 has an opening in the portion of the photoelectric conversion unit 24.

[0026] The above cross-sectional configuration is mainly the configuration of the region between pixels arranged in the row direction (left-right direction in FIG. 5) as shown by the VII-VII' line in FIG. 5. However, a similar configuration is also provided between the column directions (up-down direction in FIG. 5). That is, for one pixel 10, two each of the charge storage layer 13, the first transfer gate 16, the second transfer gate 17, the floating diffusion 18, etc. are provided. These arrangements are shown in FIG. 6. In FIG. 7, the charge trapping layer 11, the charge storage layer 13, etc. are also shown on the side opposite to the penetrating DTI 22 with respect to the photoelectric conversion unit 24 (corresponding to the upper side of the photoelectric conversion unit 24 in FIG. 6).

[0027] Further, with respect to the photoelectric conversion unit 24, in the portion between the through DTI 22 (upper right in FIG. 6), an overflow drain 28 capable of discharging the charges of the photoelectric conversion unit 24 and an overflow gate 27 for controlling the movement of the charges to the overflow drain 28 are provided.

[0028] According to the above configuration, in a solid-state imaging device having a pixel array in which pixels 10 are arranged in a matrix, a plurality (here, two) of charge accumulation layers 13 can be arranged for each pixel 10. Thereby, for example, it can be used to acquire distance information of an imaging target as a time-of-flight (TOF) sensor.

[0029] Further, with respect to the plurality of charge accumulation layers 13 provided for each pixel, the light leakage can be suppressed by the provided charge trapping layers 11 respectively, and the deterioration of the image quality can be suppressed.

[0030] However, when the configuration is a plan view as shown in FIG. 5, the following problems may occur.

[0031] In the configuration of FIG. 5, the charge accumulation layer 13 is provided in the region 41 between two adjacent pixels 10 in the row direction and the column direction. Therefore, the charge trapping layer 11 may be similarly provided in the region 41. However, in the case of FIG. 5, the charge trapping layer 11 is also formed in the intersection region 40 where the region extending between the columns of the pixels 10 and the region extending between the rows of the pixels 10 intersect (in other words, the central region of four 2×2 pixels).

[0032] The charge trapping layer 11 is formed, for example, by impurity implantation. Here, the light-shielding element isolation layer (through DTI 22, non-through DTI 23, etc.) induces negative charges to suppress the dark current of the photoelectric conversion unit 24. Therefore, in order to obtain a desired potential for the charge trapping layer 11, implantation of impurities at a predetermined concentration is necessary. For example, when considering the case of forming an N-type charge trapping layer 11 with respect to the P well 20, N-type impurities are implanted to sufficiently lower the potential.

[0033] When performing implantation into the region that extends continuously between the columns of pixels 10 and the region that extends continuously between pixels 10, respectively, to form the charge trapping layer 11, the intersection region 40 is implanted twice, and the implantation concentration becomes high. As a result, for the intersection region 40, the impurity concentration becomes high, the potential drops too much, and it is conceivable that the separation of the P-well 20 becomes weak (deteriorates).

[0034] Also, for the intersection region 40, there is no element isolation layer that induces negative charges around it. Therefore, even when implantation is performed simultaneously without dividing it into two times, it is conceivable that the potential in the intersection region 40 drops too much and the separation of the P-well 20 becomes weak.

[0035] The P-well 20 constitutes various transistors necessary for the operation of the pixel 10. Therefore, when the separation of the P-well 20 deteriorates, inconveniences such as the threshold voltage of the transistor fluctuating, each source / drain region shorting through the charge trapping layer 11, and the transistor not operating occur.

[0036] To avoid this, the position where the charge trapping layer 11 is formed, the concentration of impurities introduced for that purpose, etc. are set. FIG. 8 is a plan view showing an example thereof.

[0037] In the example of FIG. 8, a charge trapping layer 11d is disposed in the region 41 between two adjacent pixels 10 (the region sandwiched between the through DTI 22 and the non-through DTI 23 provided in each pixel), and no charge trapping layer is disposed in the intersection region 40. This is realized by setting the region where impurities are implanted.

[0038] By doing so, it is possible to avoid the potential from dropping too much in the intersection region 40 and ensure the separation of the P-well 20. Also, in this case, the charge trapping layer 11d between the pixels 10 is not continuous in the row direction and the column direction and is interrupted. Alternatively, it may be weakly continuous only at the four corners of the intersection region 40.

[0039] Further, FIG. 9 shows another example. In the example of FIG. 9, in addition to the configuration of FIG. 8, in the intersection region 40, a small charge trapping layer 11a is provided only in a part thereof. That is, the occupied area of the charge trapping layer 11a is smaller than the area of the intersection region 40. The charge trapping layer 11a is not connected to the charge trapping layer 11d between the pixels 10 in the row direction and the column direction. Thereby, in the intersection region 40, it is possible to adjust the potential to a desired level and also to exert a certain degree of effect of suppressing the leakage of light into the photoelectric conversion unit 24.

[0040] FIG. 10 shows still another example. Also in the example of FIG. 10, in the intersection region 40, a charge trapping layer 11b is provided only in a part thereof. However, the charge trapping layer 11b has a cross-shaped pattern and is connected to the charge trapping layer 11d provided between the light-shielding element isolation layers in the row direction and the column direction. Thereby, similar to the example of FIG. 9, in the intersection region 40, it is possible to adjust the potential to a desired level and also to exert a certain degree of effect of suppressing the leakage of light into the photoelectric conversion unit 24. Further, the charge trapping layers 11d can be connected to each other to be electrically continuous in the row direction and the column direction.

[0041] Also, when the charge trapping layer 11 is provided as shown in FIG. 5, it is also possible to lower the impurity concentration in the portion of the intersection region 40 to form a low-concentration charge trapping layer and adjust the potential.

[0042] (Electrical connection to the charge trapping layer) Next, in this embodiment, an example in which a terminal for making an electrical connection to the charge trapping layer 11 is arranged in a region outside the pixel array will be described. FIG. 11 shows a case where, in the layout of FIG. 5, extension regions 31 for extending the charge trapping layer 11 in the row direction and the column direction are provided. The cross-sectional view in the length direction of the extension region 31 is the same as that of FIG. 4. Also, a P-type deep well region 26 is provided around the extension region 31. A terminal 21 for making an electrical connection to the charge trapping layer 11 is provided on the surface side of the substrate with respect to the extension region 31.

[0043] By providing the extension region 31 in this way, it becomes unnecessary to provide a terminal in the pixel array with respect to the charge trapping layer 11, so the degree of freedom in layout increases, and it contributes to reducing the area of the pixel array.

[0044] (Method for manufacturing a solid-state imaging device) The solid-state imaging device of the present disclosure is manufactured, for example, as follows (see FIGS. 2, 3, 4, etc.).

[0045] To manufacture a solid-state imaging device, an N-type or P-type epitaxial substrate is used. A deep well region 26 for separating the photodiodes (photoelectric conversion portions 24) of the respective pixels 10 is formed on the epitaxial substrate. For this purpose, a mask is created by resist deposition and pattern formation by lithography on the substrate, and ion implantation is performed.

[0046] Next, STI (STI 19 in FIG. 4, etc.) filled with an insulating film is formed on the surface side of the substrate to separate regions such as the photoelectric conversion portion 24, the memory node (charge storage layer 13), and the transistor 25.

[0047] Subsequently, P-type impurities and N-type impurities are respectively implanted to form a P-well 20 and a charge storage layer 13. Also, implantation for adjusting the Vth (threshold voltage) of the transistor is performed as necessary. In each case, resist patterning is performed and ion implantation is performed on the necessary regions. However, in the regions that will become the charge trapping layers (11, 11a, 11b, 11d), a portion where implantation for P-well formation is not performed is left in order to take a terminal on the surface.

[0048] P-type impurities are ion-implanted on the surface side of the charge storage layer 13 to form a surface passivation layer (P-type layer 14).

[0049] Annealing is performed to activate the impurities injected so far, and then an oxide film is formed. Further, a gate structure is formed by depositing a polysilicon layer and patterning the polysilicon layer by etching. The gate structure includes various gates such as transistor 25, first transfer gate 16, second transfer gate 17, and overflow drain gate 27.

[0050] High-concentration P-type impurities are injected onto the surface side of the photodiode (photoelectric conversion section 24) to form a surface passivation layer.

[0051] A silicon nitride film and a silicon oxide film are sequentially deposited on the substrate including the gate to form a stacked film, and the stacked film is etched to form a sidewall structure covering the sidewalls of the gate structure.

[0052] To provide the source region / drain region (such as N+ layer 30) of each transistor, field diffusion 18, and terminal 21 of charge trapping layer 11, high-concentration N-type impurities are injected. At this time, resist patterning may also be performed and used as a mask.

[0053] Furthermore, for supplying potential to the P well 14, high-concentration P-type impurities are injected (this is not shown in the figure). Here too, for example, the region may be segmented by resist patterning and ion implantation may be performed.

[0054] Thereafter, annealing is performed again to activate the impurities.

[0055] Furthermore, an insulating film is deposited, contacts, vias are formed, metal is embedded, etc. to form a wiring layer (not shown in the figure).

[0056] Through the above processes, a pixel array is formed on the substrate (excluding light-shielding element isolation layers such as through DTI 22 and non-through DTI 23). The substrate is attached to another support substrate, for example, via an insulating film. Thereafter, the back surface side of the substrate (the side opposite to the charge storage layer 13, etc.) is thinned by etching or the like to make the substrate a predetermined thickness (for example, about 3 to 10 μm).

[0057] Subsequently, perform resist patterning, and form holes (or grooves) for forming the through DTI 22, non-through DTI 23, etc. by etching. Further, deposit an oxide film, hafnium oxide having negative fixed charges, aluminum oxide, etc., fill the formed grooves, and also form them as a layer on the back side of the substrate. A metal film can also be formed partially. In addition, in order to form DTIs with different depths (such as the through DTI 22 and the non-through DTI 23), grooves with different depths are formed by repeating the groove-forming process.

[0058] Furthermore, deposit a metal film such as tungsten on the back side of the substrate, and perform resist patterning and etching. Thereby, the backside light-shielding film 15 is formed in a predetermined region.

[0059] Thereafter, form a hole from the back side so as to reach the wiring layer on the front side of the substrate, and sequentially perform deposition of a metal such as aluminum, resist patterning, etching, etc., to form a metal pad connected to the wiring layer.

[0060] Through the above, the solid-state imaging device is manufactured.

Industrial Applicability

[0061] According to the configuration of the present disclosure, even when a charge trapping layer is provided, well separation can be performed well, which is useful for improving the image quality of the solid-state imaging device.

Explanation of Reference Numerals

[0062] 10 Pixel 11 Charge trapping layer 11a Charge trapping layer 11b Charge trapping layer 11d Charge trapping layer 12 VDD region 13 Charge storage layer 14 P-type layer 15 Backside light-shielding film 16 First transfer gate 17 Second transfer gate 18 Floating diffusion 19 STI 20 P-well 21 Terminal 22 Through DTI 23 Non-through DTI 23a Non-through DTI 24 Photoelectric conversion section 25 Transistor 26 Deep well region 27 Overflow gate 28 Overflow drain 30 N+ layer 31 Extension region 32 Gate electrode 40 Intersection region 41 Region 51 Arrow 42 Region where P-well is not formed

Claims

1. Comprising a pixel array in which pixels are arranged in a matrix, each of said pixels having a photoelectric conversion section for generating signal charges based on incident light, and a light-shielding element isolation layer surrounding the periphery of said photoelectric conversion section, in both the row direction and the column direction, the element isolation layers of adjacent pixels are separated from each other, in the row direction and the column direction, a charge storage layer and a charge trapping layer are provided in a region sandwiched between the element isolation layers of adjacent pixels, said charge trapping layer is also formed in an intersection region where a region between columns of said pixels and a region between rows of said pixels intersect, said charge storage layer stores said signal charges, said charge trapping layer is characterized in that it suppresses the incidence of light onto said charge storage layer. A solid-state imaging device.

2. Comprising a pixel array in which pixels are arranged in a matrix, each of said pixels having a photoelectric conversion section for generating signal charges based on incident light, and a light-shielding element isolation layer surrounding the periphery of said photoelectric conversion section, in both the row direction and the column direction, the element isolation layers of adjacent pixels are separated from each other, in the row direction and the column direction, a charge storage layer and a charge trapping layer are provided in a region sandwiched between the element isolation layers of adjacent pixels, said charge storage layer stores said signal charges, said charge trapping layer suppresses the incidence of light onto said charge storage layer, in an intersection region where a region between columns of said pixels and a region between rows of said pixels intersect, a solid-state imaging device, characterized in that an intersection region charge trapping layer that partially occupies said intersection region is provided.

3. In Claim 2, said intersection region charge trapping layer is provided so as to avoid contact with the charge trapping layer in the region sandwiched between the element isolation layers. A solid-state imaging device.

4. In Claim 2, said intersection region charge trapping layer is provided so as to connect the charge trapping layers in the region sandwiched between the element isolation layers in the row direction and the column direction. A solid-state imaging device.

5. Comprising a pixel array in which pixels are arranged in a matrix, each of said pixels having a photoelectric conversion section for generating signal charges based on incident light, and a light-shielding element isolation layer surrounding the periphery of said photoelectric conversion section, in both the row direction and the column direction, the element isolation layers of adjacent pixels are separated from each other, in the row direction and the column direction, a charge storage layer and a charge trapping layer are provided in a region sandwiched between the element isolation layers of adjacent pixels, The charge storage layer stores the signal charges, The charge trapping layer suppresses the incidence of light on the charge storage layer, A solid-state imaging device characterized in that a low-concentration charge trapping layer having a lower impurity concentration than the charge trapping layer in a region sandwiched between the element isolation layers is provided in an intersection region where a region between columns of the pixels and a region between rows of the pixels intersect. **Claim 6**: A pixel array in which pixels are arranged in a matrix, Each of the pixels has a photoelectric conversion section that generates signal charges based on incident light, and a light-shielding element isolation layer that surrounds the periphery of the photoelectric conversion section. In both the row direction and the column direction, the element isolation layers of adjacent pixels are separated from each other. In the row direction and the column direction, a charge storage layer and a charge trapping layer are provided in a region sandwiched between the element isolation layers of adjacent pixels. The charge storage layer stores the signal charges, The charge trapping layer suppresses the incidence of light on the charge storage layer, A solid-state imaging device characterized in that the charge trapping layer extends to the outside of the region of the pixel array, and a terminal for taking the potential of the charge trapping layer is formed in the extended region. **Claim 7** A pixel array in which pixels are arranged at least one-dimensionally, Each of the pixels includes a photoelectric conversion section that generates signal charges based on incident light, a charge storage layer that stores the signal charges, and a charge trapping layer that suppresses the incidence of light on the charge storage layer. A solid-state imaging device characterized in that the charge trapping layer extends to the outside of the region of the pixel array, and a terminal for taking the potential of the charge trapping layer is formed in the extended region.

Images