Silicon carbide semiconductor device and method for manufacturing the same

Abstract

To provide a SiC semiconductor device capable of reducing manufacturing costs and preventing deterioration in reliability, and a method of manufacturing the same.SOLUTION: A SiC semiconductor device includes an n-type current diffusion layer 3 provided on the upper surface of an n-type drift layer 2, a p-type base region 6 provided on the upper surface, a p-type gate bottom protection region 4b provided inside the current diffusion layer 3, p-type base bottom buried regions (4a, 5a) separated from the gate bottom protection region 4b inside the current diffusion layer 3 and in contact with the bottom surface of the base region 6, insulated gate electrode structures (11, 12a) provided inside a trench 9a that penetrates the base region 6 and reaches the gate bottom protection region 4b, and a lower recombination region 24 provided at the bottom of the drift layer 2 and recombining minority carriers by crystal defects.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present invention relates to a silicon carbide (SiC) semiconductor device and a method for manufacturing the same.

Background Art

[0002] Commercially available silicon carbide (SiC) single crystal substrates contain a large number of dislocations including basal plane dislocations (BPDs). Such dislocations are inherited by an epitaxial substrate obtained by epitaxially growing a SiC single crystal on the substrate. Therefore, it is known that the characteristics of semiconductor devices formed on the epitaxial substrate are adversely affected.

[0003] In SiC semiconductor devices such as MOS field effect transistors (FETs), a built-in diode having a pn junction is provided on the epitaxial substrate. The basal plane dislocation causes deterioration of the forward characteristics of the built-in diode that performs bipolar operation during turn-off. For example, minority carriers generated by forward conduction during bipolar operation, such as holes in an n-type semiconductor, diffuse through the epitaxial substrate. When the minority carriers recombine at the basal plane dislocation and give recombination energy to the basal plane dislocation, stacking faults expand in the epitaxial substrate starting from the basal plane dislocation. When the stacking faults expand, when a forward current flows through the built-in diode, the forward voltage increases and the forward resistance increases. Thus, when the element characteristics deteriorate, the generated losses increase over time and the amount of heat generation also increases, which causes a failure of the semiconductor device.

[0004] The stacking faults expand from the interface between an n-type substrate and a drift layer which is an n-type epitaxial growth layer. By disposing a high-concentration n + -type buffer layer between the substrate and the drift layer, holes injected from the surface electrode side can be recombined in the buffer layer. Since the recombination energy is released in the buffer layer, the expansion of the stacking faults can be prevented. However, in order to maintain a high breakdown voltage, the buffer layer is required to have a thickness of about 10 μm, which increases the manufacturing cost of the epitaxial substrate.

[0005] Patent Document 1 proposes a method of implanting hydrogen ions (protons) near the interface between a substrate and an n-type boundary layer to provide recombination centers (lifetime killers). In the method of Patent Document 1, since the recombination centers are introduced over the entire interface between the substrate and the n-type boundary layer, the on-resistance of the MOSFET deteriorates. Patent Document 2 proposes a method of implanting protons or helium ions at the pn junction interface at the bottom of the base region of a planar MOSFET to provide recombination centers and reduce the reverse recovery loss of the built-in diode. In the method of Patent Document 2, since the recombination centers are provided at the bottom of the base region, it is difficult to sufficiently reduce the holes injected into the drift layer.

Prior Art Documents

Patent Documents

[0006]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0007] In view of the above problems, an object of the present invention is to provide a SiC semiconductor device and a method for manufacturing the same that can reduce manufacturing costs and prevent a decrease in reliability.

Means for Solving the Problems

[0008] To achieve the above object, one aspect of the present invention is a SiC semiconductor device comprising: (a) a drift layer of a first conductivity type provided on a SiC substrate of the first conductivity type; (b) a current diffusion layer of the first conductivity type provided on the upper surface of the drift layer and having a higher impurity concentration than the drift layer; (c) a base region of a second conductivity type provided on the upper surface of the current diffusion layer; (d) a gate bottom protection region of the second conductivity type provided inside the current diffusion layer; (e) a base bottom buried region of the second conductivity type spaced apart from the gate bottom protection region inside the current diffusion layer and in contact with the lower surface of the base region; (f) an insulated gate electrode structure provided inside a trench that penetrates the base region and reaches the gate bottom protection region; and (g) a lower recombination region provided at the bottom of the drift layer for recombining minority carriers injected into the drift layer due to crystal defects.

[0009] Another aspect of the present invention is a method for manufacturing a SiC semiconductor device, comprising: (a) forming an element structure in an active part by polishing the lower surface of a substrate after forming, on the upper surface of a drift layer of a first conductivity type epitaxially grown on a substrate of the first conductivity type, a current diffusion layer of the first conductivity type having a higher impurity concentration than the drift layer, a base region of a second conductivity type on the upper surface of the current diffusion layer, a gate bottom protection region of the second conductivity type having a higher impurity concentration than the base region at the bottom of the current diffusion layer, a base bottom buried region of the second conductivity type spaced apart from the gate bottom protection region inside the current diffusion layer and having a higher impurity concentration than the base region in contact with the lower surface of the base region, and an insulated gate electrode structure provided inside a trench that penetrates the base region and reaches the gate bottom protection region; and (b) selectively ion-implanting protons or helium from the polished lower surface of the substrate into the bottom of the drift layer to form a lower recombination region at the bottom of the drift layer for recombining minority carriers due to crystal defects.

Advantages of the Invention

[0010] According to the present invention, it is possible to provide a SiC semiconductor device and a method for manufacturing the same that can reduce manufacturing costs and prevent a decrease in reliability.

Brief Description of the Drawings

[0011]

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BEST MODE FOR CARRYING OUT THE INVENTION

[0012] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the description of the drawings, the same or similar parts are denoted by the same or similar reference numerals, and redundant explanations are omitted. However, the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thicknesses of the respective layers, etc. may be different from the actual ones. Also, there may be portions where the dimensional relationships and ratios are different even between the drawings. Further, the embodiments shown below are examples of devices and methods for embodying the technical idea of the present invention, and the technical idea of the present invention does not specify the materials, shapes, structures, arrangements, etc. of the components as the following.

[0013] In this specification, the source region of a MOS transistor is the "one main region (first main region)" that can be selected as the emitter region of an insulated gate bipolar transistor (IGBT). Also, in a thyristor such as a MOS controlled static induction thyristor (SI thyristor), one main region can be selected as the cathode region. The drain region of a MOS transistor is the "other main region (second main region)" of a semiconductor device that can be selected as the collector region in an IGBT and as the anode region in a thyristor. When simply referred to as the "main region" in this specification, it means either the appropriate first main region or second main region based on the common general knowledge of those skilled in the art.

[0014] Also, the definitions of directions such as up and down in the following description are merely for convenience of explanation and do not limit the technical idea of the present invention. For example, if the object is rotated 90° for observation, up and down are read as left and right after conversion, and if rotated 180° for observation, up and down are read in reverse, which goes without saying. Also, in the following description, the case where the first conductivity type is n-type and the second conductivity type is p-type will be exemplified. However, the conductivity types may be selected in the reverse relationship, with the first conductivity type being p-type and the second conductivity type being n-type. Also, the + and - attached to n and p mean semiconductor regions with relatively higher or lower impurity densities compared to semiconductor regions without the attached + and -. However, even for semiconductor regions with the same n attached, it does not mean that the impurity densities of the respective semiconductor regions are exactly the same.

[0015] <Structure of SiC Semiconductor Device> Crystal polymorphs exist in SiC crystals, and the main ones are cubic 3C, and hexagonal 4H, 6H. The reported values of the bandgap at room temperature are 2.23 eV for 3C-SiC, 3.26 eV for 4H-SiC, and 3.02 eV for 6H-SiC. In the embodiments of the present invention, 4H-SiC will be used for explanation.

[0016] The SiC semiconductor substrate (substrate) 100 for manufacturing the SiC semiconductor device according to the embodiment of the present invention is composed of a plurality of chip regions 101 and dicing lines 102 as shown in FIG. 1. For example, the chip region 101 has a rectangular planar shape and is arranged on the substrate 100 in a matrix. The dicing lines 102 are arranged in a grid so as to surround each of the chip regions 101. As shown in FIG. 2, the chip region 101 is provided with an active part 101a containing active elements and an outer peripheral part 101b having a breakdown voltage structure. In FIG. 2, a MOSFET with a trench gate structure provided on the upper part of a drift layer 2 of the first conductivity type (n - -type) is exemplified as a case including electric field relaxation regions 20a and 20b as the breakdown voltage structure.

[0017] As shown in FIG. 2, a base region 6 of the second conductivity type (p-type) is arranged on the upper surface of the drift layer 2. The drift layer 2 and the base region 6 are each composed of an epitaxial growth layer made of SiC (hereinafter abbreviated as "epitaxial layer"). On the upper part of the base region 6, a p + -type base contact region 8 with a higher impurity concentration than that of the base region 6 is selectively provided. On the upper part of the base region 6, an n + -type first main region (source region) 7 with a higher impurity concentration than that of the drift layer 2 is selectively provided so as to be in contact with the base contact region 8.

[0018] A trench 9a with a width of 1 μm or less penetrates through the base region 6 from the upper surfaces of the source region 7 and the base region 6. That is, the source region 7 and the base region 6 are in contact with the side surfaces of the trench 9a. A gate insulating film 11 is provided on the bottom surface and the side surfaces of the trench 9a. A gate electrode 12a is embedded in the trench 9a via the gate insulating film 11 to form an insulated gate type electrode structure (11, 12a). As the gate insulating film 11, in addition to a silicon dioxide film (SiO2 film), a silicon oxynitride (SiON) film, a strontium oxide (SrO) film, a silicon nitride (Si3N4) film, an aluminum oxide (Al2O3) film, a magnesium oxide (MgO) film, a yttrium oxide (Y2O3) film, a hafnium oxide (HfO2) film, a zirconium oxide (ZrO2) film, a tantalum oxide (Ta2O5) film, a bismuth oxide (Bi2O3) film, any one of single-layer films or a composite film formed by laminating a plurality of these can be adopted. As the material of the gate electrode 12a, for example, a polysilicon layer (doped polysilicon layer) with impurities such as phosphorus (P) and boron (B) added at a high impurity concentration can be used.

[0019] An n-type current spreading layer (CSL) 3 with a higher impurity concentration than the drift layer 2 is selectively provided above the drift layer 2. The bottom of the trench 9a reaches the current spreading layer 3. The current spreading layer 3 is not necessarily provided. When the current spreading layer 3 is not provided, the bottom of the trench 9a reaches the drift layer 2. Inside the current spreading layer 3, a p + -type gate bottom protection region 4b is provided so as to be in contact with the bottom of the trench 9a. Inside the current spreading layer 3, below the base contact region 8, at a depth approximately the same as the gate bottom protection region 4b and spaced apart from the gate bottom protection region 4b, a p + -type first buried region 4a is provided. Above the current spreading layer 3, a p +A second embedded region 5a of the type is provided. The second embedded region 5a is also provided below the base contact region 8. The first embedded region 4a and the second embedded region 5a constitute a base bottom embedded region (4a, 5a). Also, selectively in the depth direction of the trench, a p + type connection portion 4d is provided. An upper recombination region 26 is provided so as to contact the bottom surface of the first embedded region 4a of the base bottom embedded region (4a, 5a). The upper recombination region 26 is preferably provided so as to cover the bottom surface and the bottom surface end portion of the first embedded region 4a.

[0020] An interlayer insulating film 13 is disposed on the upper surface of the gate electrode 12a. As the interlayer insulating film 13, a silicon oxide film (BPSG) added with boron (B) and phosphorus (P) is used. However, as the interlayer insulating film 13, a silicon oxide film (PSG) added with phosphorus (P), a non-doped SiO2 film called "NSG" that does not contain phosphorus (P) or boron (B), a silicon oxide film (BSG) added with boron (B), a Si3N4 film, etc. may also be used. Also, these laminated films may be used.

[0021] A source contact layer 14 is provided so as to physically contact the source region 7 and the base contact region 8 exposed between the interlayer insulating films 13. A barrier metal layer 15a is provided so as to cover the interlayer insulating film 13 and the source contact layer 14. The first main electrode (source electrode) 16a is electrically connected to the source region 7 and the base contact region 8 through the barrier metal layer 15a and the source contact layer 14. For example, the source contact layer 14 can be composed of a nickel silicide (NiSi x ) film, the barrier metal layer 15a can be composed of a titanium nitride (TiN) film or a titanium (Ti) film, and the source electrode 16a can be composed of an aluminum (Al) film or an aluminum-silicon (Al-Si) film. The source electrode 16a is disposed separately from the gate surface electrode (not shown).

[0022] On the outer peripheral portion 101b side of the active portion 101a, a base contact region 8a is provided on the upper portion of the base region 6. On the upper surface of the base contact region 8a, a wiring layer 12b is disposed via a field oxide film 10, and a gate electrode pad 16b is disposed on the upper surface of the wiring layer 12b via a barrier metal layer 15b. Although not shown, the gate electrode pad 16b is electrically connected to the gate electrode 12a via the wiring layer 12b. The interlayer insulating film 13 and the field oxide film 10 extend to the outer peripheral portion 101b side. Further, on the outer peripheral portion 101b side of the active portion 101a, a base bottom buried region (4c, 5b) composed of a second buried region 5b and a first buried region 4c extends so as to be in contact with the lower surface of the base region 6. An upper recombination region 26a is provided so as to be in contact with the bottom surface of the first buried region 4c of the base bottom buried region (4c, 5b).

[0023] Below the drift layer 2, an n + -type buffer layer 22 and an n + -type second main region (drain region) 1 are disposed. The drain region 1 is composed of a SiC semiconductor substrate (substrate). Below the base bottom buried region (4a, 5a), a lower recombination region 24 is selectively provided at the bottom of the drift layer 2. The gaps between adjacent lower recombination regions 24 are disposed so as to face the gate bottom protection region 4b. Further, at the bottom of the drift layer 2 below the base bottom buried region (4c, 5b), a lower recombination region 24a is provided so as to extend to the outer peripheral portion 101b.

[0024] A second main electrode (drain electrode) 17 is disposed on the lower surface of the drain region 1. As the drain electrode 17, for example, a single-layer film made of gold (Au) or a metal film laminated in the order of Ti, nickel (Ni), and Au can be used, and a metal film such as molybdenum (Mo) or tungsten (W) may be laminated on the lowermost layer thereof. Further, a drain contact layer may be provided between the drain region 1 and the drain electrode 17. The drain contact layer is, for example, a nickel silicide (NiSi x ) film.

[0025] As shown in FIG. 2, on the outer peripheral portion 101b, mesa grooves 9b are provided that penetrate the base region 6 from the upper surface of the base region 6 and reach the first embedded region 4c. The width of the mesa grooves 9b in one chip region 101 is, for example, in the range of 5 μm or more and 200 μm or less. On the outer peripheral portion 101b, electric field relaxation regions 20a and 20b are provided as terminal structures so as to be exposed on the bottom surface of the mesa grooves 9b. Each of the electric field relaxation regions 20a and 20b is, for example, a junction termination extension (JTE) structure, and a plurality of p-type spatially modulated portions are provided. Each of the electric field relaxation regions 20a and 20b is not limited to the JTE structure, and a plurality of p-type guard rings may be provided in a concentric ring shape. Also, at the outer end portion of the outer peripheral portion 101b, an n + -type channel stopper may be provided in a concentric ring shape. Note that instead of the n + -type channel stopper, a p + -type channel stopper may be provided.

[0026] For example, the drift layer 2 has an impurity concentration of 1×10 15 cm -3 or more and 2×10 16 cm -3 or less, and a thickness of 1 μm or more and several hundred μm or less. The optimum thickness and impurity density are selected according to the breakdown voltage specification of the built-in diode described later. The impurity concentration of the base region 6 is 1×10 17 cm -3 or more and 1×10 18 cm -3 or less. The impurity concentration of the base contact region 8 is 5×10 18 cm -3 or more and 5×10 20 cm -3 or less, the impurity concentration of the source region 7 is 5×10 18 cm -3 or more and 5×10 20 cm -3 or less. The impurity concentration of the current diffusion layer 3 is 5×10 16 cm -3 or more and 5×10 17 cm -3Hereinafter, the gate bottom protection region 4b, the first buried region 4a and the second buried region 5a of the base bottom buried region (4a, 5a) have impurity concentrations of the same order, 1×10 17 cm -3 or more and 1×10 19 cm -3 or less. The buffer layer 22 has an impurity concentration of 5×10 17 cm -3 or more and 1×10 18 cm -3 or less, and a thickness of 0.5 μm or more and 1 μm or less. The impurity concentration of the drain region 1 is 1×10 18 cm -3 or more and 1×10 19 cm -3 or less.

[0027] During the operation of the semiconductor device according to the embodiment, when a positive voltage is applied to the drain electrode 17 with the source electrode 16a at the ground potential and a positive voltage equal to or higher than the threshold value is applied to the gate electrode 12a, an inversion layer (channel) is formed on the side surface of the trench 9a in the base region 6, and the device is in the on state. The inversion layer is formed on the surface of the base region 6 exposed on the side surface of the trench 9a at the interface between the gate insulating film 11 and the base region 6, which is sandwiched between the positions where the base region 6 faces the gate electrode 12a. In the on state, current flows from the drain electrode 17 through the drain region 1, the drift layer 2, the current diffusion layer 3, the inversion layer in the base region 6, and the source region 7 to the source electrode 16a. On the other hand, when the voltage applied to the gate electrode 12a is less than the threshold value, no inversion layer is formed in the base region 6, so the device is in the off state and no current flows from the drain electrode 17 to the source electrode 16a.

[0028] Also, as shown in FIG. 2, a p-type base region 6 is formed on top of an n-type drift layer 2, thereby forming a built-in diode (body diode) of a pn junction. That is, the built-in diode is constituted by a base contact region 8, a base region 6, base bottom embedded regions (4a, 5a), a current diffusion layer 3, a drift layer 2, a buffer layer 22, and a drain region 1. The drain region 1 made of a semiconductor substrate functions as the “cathode region” of the built-in diode, and the drift layer 2 and the current diffusion layer 3 on the buffer layer 22 function as a “travel region” where carriers travel by drift. Also, the base contact region 8, the base region 6, and the base bottom embedded regions (4a, 5a) function as the “anode region” of the built-in diode. For this reason, the drain electrode 17 provided on the lower surface of the drain region 1 functions as a “cathode electrode” and supplies carriers supplied to the drain region 1 to an external circuit via the drain electrode 17. The source electrode 16a provided on the upper surface of the base contact region 8 functions as the “anode electrode” of the built-in diode and supplies carriers from an external circuit to the base contact region 8 and the base region 6 via the source electrode 16a. A large number of carriers (electrons) supplied from the drain region 1 travel through the drift layer 2 by a drift electric field. Then, minority carriers (holes) are injected from the base contact region 8 through the base region 6 into the drift layer 2.

[0029] In a normal SiC substrate, there are 1000 basal plane dislocations / cm 2 on the order. As shown in FIG. 3, an n + -type substrate 1s has an n + -type buffer layer 22s and an n -When an epitaxial layer 2s of a certain type is epitaxially grown, most of the basal plane dislocations 40t are converted into threading dislocations 42 within the buffer layer 22s. The buffer layer 22s functions as a transfer conversion layer and its thickness is set to about 1 μm or less. On the other hand, some of the basal plane dislocations 40s propagate from the substrate 1s through the buffer layer 22s to the epitaxial layer 3s. When a pn diode is formed using such an epitaxial substrate (1s, 2s, 3s), upon energization, the basal plane dislocations 40s near the interface between the substrate 1s and the buffer layer 22s can become the starting point for the expansion of stacking faults. That is, when holes are injected into the epitaxial layer 2s from the p-type anode region formed on the upper part of the epitaxial layer 2s, the basal plane dislocations 40s become the starting point for the expansion of stacking faults. Note that the threading dislocations 42 converted from the basal plane dislocations 40t do not expand into stacking faults.

[0030] For example, holes 44 are injected as "minority carriers" from the anode region of the pn diode into the n-type epitaxial layer 2s. Electrons, which are the majority carriers in the conduction band generated by forward biasing, recombine with the holes 44 at the electron energy levels of the stacking faults generated from the basal plane dislocations 40s, that is, at the recombination centers, causing the expansion of the stacking faults. Since the recombination energy by the recombination centers is small, the expansion of the stacking faults does not occur unless the hole density reaching the stacking faults becomes equal to or higher than the threshold value. The threshold hole density is said to be about 1×10 15 cm -3 or so. The epitaxial layer 2s has a low impurity density, and the diffusion depth of the holes injected into the epitaxial layer 2s is about 10 μm. Therefore, when using an epitaxial layer 2s with a thickness of about 10 μm as the operating region of the pn diode, the holes injected from the anode region can reach the substrate 1s from within the buffer layer 22s at a sufficiently high density. Starting from the basal plane dislocations 40s localized near the interface between the buffer layer 22s and the substrate 1s, stacking faults 46 expand within the epitaxial layer 2s. Since the stacking faults become high-resistance regions, the current flows through the regions without stacking faults. As a result, in the pn diode, it causes deterioration of forward characteristics such as an increase in the on-voltage (forward voltage) and an increase in the on-resistance.

[0031] In a conventional semiconductor device, as shown in FIG. 4, an n-type recombination promoting layer 34 of about several μm is provided between a buffer layer 22 and a drift layer 2. For example, the drift layer 2 is about 10 μm, and the recombination promoting layer 34 is 3 μm to 7 μm. FIG. 5 is an enlarged view showing an n-type laminated structure including a drain region 1, a buffer layer 22, a recombination promoting layer 34, and a drift layer 2 of the semiconductor device shown in FIG. 4. As shown in FIG. 5, holes 44 of minority carriers injected into the drift layer 2 from the anode region of the built-in diode in FIG. 2 recombine with electrons of majority carriers in the recombination promoting layer 34 and disappear. Therefore, basal plane dislocations 40t and 40s existing in the drain region 1 are both converted into through dislocations 42, and it is prevented from expanding into stacking defects. In order to sufficiently promote the recombination of the holes 44, it is necessary to epitaxially grow the recombination promoting layer 34 thick enough, which leads to an increase in manufacturing cost. + For sufficiently promoting the recombination of holes 44, it is necessary to epitaxially grow the recombination promoting layer 34 thick enough, which leads to an increase in manufacturing cost.

[0032] FIG. 6 is an enlarged view of part B of the semiconductor device shown in FIG. 2. As shown in FIG. 6, in the semiconductor device according to the embodiment, an upper recombination region 26 and a lower recombination region 24 having crystal defects as recombination centers for recombining holes of minority carriers are provided. The crystal defects are composed of ion-implanted light element ions, for example, protons (hydrogen ions) or helium ions. The upper recombination region 26 is selectively provided so as to cover the bottom surface and the bottom surface end portion of the first implanted region 4a of the base bottom implanted region (4a, 5a), and protrudes by a protrusion width Dc toward the opposing gate bottom protection region 4b side. The lower recombination region 24 is selectively provided in contact with the upper surface of the buffer layer 22 at the bottom of the drift layer 2 below the base bottom implanted region (4a, 5a) and spaced apart from each other by a spacing width Ds. Here, the lower recombination region 24 may be provided so as to stay inside the drift layer 2 and not cover the buffer layer 22. Thereby, the function of the buffer layer 22 of converting the dislocations of the substrate can be maintained. However, in order not to allow holes, which are minority carriers, to reach the buffer layer 22, it is preferable that the distance between the bottom of the lower recombination region 24 and the bottom of the buffer layer 22 is 3 μm or less.

[0033] In the upper recombination region 26, holes injected from the base region 6, particularly through the base bottom embedded regions (4a, 5a) into the drift layer 2, are recombined by crystal defects. The protrusion width Dc of the side surface of the upper recombination region 26 is desirably 1 / 2 or less of the current diffusion width Dp between the base bottom embedded regions (4a, 5a) and the gate bottom protection region 4b. When the protrusion width Dc is 0 or less, that is, smaller than the width of the base bottom embedded regions (4a, 5a), the holes injected into the drift layer 2 through the base bottom embedded regions (4a, 5a) cannot be sufficiently reduced. Further, since the upper recombination region 26 containing crystal defects has a high resistance, when the protrusion width Dc becomes larger than 1 / 2 of the current diffusion width Dp including the main current path of the semiconductor device, the on-resistance of the MOSFET and the forward voltage of the built-in diode increase. Further, the upper recombination region 26 has a crystal defect, that is, the surface density of the implanted protons or helium is in the range of 5×10 10 cm -2 or more and 2×10 11 cm -2 or less, and desirably the thickness is 0.2 μm or more and 0.5 μm or less. Within such a range of surface density and thickness, hole recombination can be sufficiently performed, and an increase in the on-resistance of the MOSFET and the forward voltage of the built-in diode can be suppressed.

[0034] In the lower recombination region 24, holes that are injected into the drift layer 2 without being recombined in the upper recombination region 26 from the base region 6 are recombined by crystal defects. A region between adjacent lower recombination regions 24 is provided at a position facing the gate bottom protection region 4b. That is, the lower recombination region 24 is provided at a position facing the base bottom buried region (4a, 5a) with a width wider than that of the base bottom buried region (4a, 5a). The separation width Ds between adjacent lower recombination regions 24 is desirably made larger than the width Dg of the gate bottom protection region 4b in order to suppress an increase in on-resistance, so as not to increase the resistance of the region of the drift layer 2 directly below the gate bottom protection region 4b. Further, in order to sufficiently recombine holes, the separation width Ds is set to be (Dg + Dp) or less, and it is desirable that the side surface of the lower recombination region 24 is positioned closer to the gate bottom protection region 4b than 1 / 2 between the first buried region 4a and the gate bottom protection region 4b. That is, the end of the lower recombination region 24 is positioned closer to the gate bottom protection region 4b between the base bottom buried region (4a, 5a) and the gate bottom protection region 4b in plan view. Further, the lower recombination region 24 has a crystal defect, that is, the surface density of implanted protons or helium is 5×10 11 cm -2 or more and 2×10 12 cm -2 or less, and desirably has a thickness of 0.5 μm or more and 1.0 μm or less. Within such a range of surface density and thickness, holes can be sufficiently recombined, and an increase in the on-resistance of the MOSFET and the forward voltage of the built-in diode can be suppressed.

[0035] <Method for manufacturing SiC semiconductor device> Next, with reference to the process cross-sectional views of FIGS. 7 to 17, a method for manufacturing an SiC semiconductor device according to an embodiment will be described by taking the case of a trench gate type MOSFET as an example. Note that the method for manufacturing a trench gate type MOSFET described below is an example, and it goes without saying that various other manufacturing methods including this modification can be realized within the scope of the gist described in the claims.

[0036] First, an n-type semiconductor substrate doped with an n-type impurity such as nitrogen (N) +Prepare a SiC semiconductor substrate (substrate) 1p of a certain type. On the upper surface of the substrate 1p, an n - type drift layer 2p is epitaxially grown. Next, a photoresist film is applied to the upper surface of the drift layer 2p, and the photoresist film is patterned using photolithography technology or the like. Using the patterned photoresist film 130 as a mask for ion implantation, n-type impurity ions such as nitrogen (N) are selectively implanted in multiple stages into the active portion 101a of the drift layer 2 from the upper surface side of the drift layer 2p. In this way, as shown in FIG. 7, an n-ion implantation layer 3p is formed in the active portion 101a of the drift layer 2p.

[0037] After removing the photoresist film 130, an oxide film made of SiO2 is deposited on the upper surfaces of the n-ion implantation layer 3p and the drift layer 2p by CVD technology or the like. A photoresist film is applied to the upper surface of the oxide film, and the oxide film is patterned using photolithography technology and dry etching technology or the like. Using the patterned oxide film 140 as a mask for ion implantation, p-type impurity ions such as aluminum (Al) are implanted in multiple stages into the n-ion implantation layer 3p. As a result, as shown in FIG. 8, a first buried region 4a, a gate bottom protection region 4b, and a first buried region 4c are selectively formed inside the n-ion implantation layer 3p. Although not shown, the connection portion 4d shown in FIG. 2 is also formed in this process.

[0038] After removing the oxide film 140, an n-type epitaxial layer 5e is grown on the upper surfaces of the first buried regions 4a and 4c, the gate bottom protection region 4b, and the drift layer 2p. A photoresist film is applied to the surface of the epitaxial layer 5e, and the photoresist film is patterned using photolithography technology or the like. Using the patterned photoresist film as a mask for ion implantation, n-type impurity ions such as nitrogen (N) are selectively implanted in multiple stages into the upper portion of the epitaxial layer 5e of the active portion 101a from the upper surface side of the epitaxial layer 5e to form an n-ion implantation layer 5p.

[0039] After removing the photoresist film used as a mask for ion implantation, an oxide film made of SiO2 is deposited on the upper surfaces of the n-ion implantation layer 5p and the epitaxial layer 5e shown in FIG. 9 by means of CVD technology or the like. A photoresist film is applied to the upper surface of the oxide film, and the oxide film is patterned using photolithography technology, dry etching technology, and the like. Using the patterned oxide film 150 as a mask for ion implantation, p-type impurity ions such as aluminum (Al) are selectively implanted into the n-ion implantation layer 5p in multiple stages. As a result, as shown in FIG. 9, second implanted regions 5a and 5b are selectively formed in the n-ion implantation layer 5p above the first implanted regions 4a and 4c, respectively.

[0040] After removing the oxide film 150, a p-type epitaxial layer 6p is epitaxially grown on the upper surfaces of the second implanted regions 5a and 5b, the n-ion implantation layer 5p, and the epitaxial layer 5e. An oxide film made of SiO2 is deposited on the surface of the grown epitaxial layer 6p by means of CVD technology or the like. A photoresist film is applied to the upper surface of this oxide film, and the oxide film is patterned using photolithography technology, dry etching technology, and the like. Using the patterned oxide film as an etching mask, the epitaxial layer 6p, a part of the second implanted region 5b, and the epitaxial layer 5e are selectively etched in the outer peripheral portion 101b by means of dry etching technology or the like. As a result, as shown in FIG. 10, a mesa groove 9b is formed. The epitaxial layer 6p, the second implanted region 5a, the n-ion implantation layer 5p, and the second implanted region 5b remain in the active portion 101a, and at the outer peripheral portion 101b, the end portion of the first implanted region 4c and the upper surface of the drift layer 2 are exposed on the bottom surface of the mesa groove 9b.

[0041] After removing the oxide film used as an etching mask, an oxide film made of SiO2 is deposited on the upper surface of the epitaxial layer 6p and the bottom surface of the mesa groove 9b by means of CVD technology or the like. A photoresist film is applied to the upper surface of this oxide film, and the oxide film is patterned using photolithography technology, dry etching technology, or the like. Using the patterned oxide film as a mask for ion implantation, n-type impurity ions such as phosphorus (P) are multi-step ion implanted into the epitaxial layer 6p from the upper surface side of the epitaxial layer 6p. As a result, in the active portion 101a, an n-ion implantation layer is formed on the upper portion of the epitaxial layer 6p.

[0042] After removing the oxide film used as a mask for ion implantation, an oxide film is deposited on the upper surface of the n-ion implantation layer and the bottom surface of the mesa groove 9b by means of CVD technology or the like. A photoresist film is applied to the upper surface of this oxide film, and the oxide film is patterned using photolithography technology, dry etching technology, or the like. Using the patterned oxide film as a mask for ion implantation, p-type impurity ions such as aluminum (Al) are selectively multi-step ion implanted into the n-ion implantation layer from the upper surface side of the n-ion implantation layer. As a result, the source region 7 and the base contact regions 8 and 8a shown in FIG. 11 are formed on the upper portion of the base region 6. The source region 7 is formed above the n-ion implantation layer 5p, and the base contact region 8 in contact with the source region 7 is formed above the second buried region 5a. Further, the base contact region 8a is formed above the second buried region 5b.

[0043] After removing the oxide film used as a mask for ion implantation, a photoresist film is applied to the upper surfaces of the source region 7, the base contact regions 8 and 8a, and the bottom surface of the mesa groove 9b, and the photoresist film is patterned using photolithography techniques or the like. Using the patterned photoresist film as a mask for ion implantation, p-type impurity ions such as aluminum (Al) are selectively implanted in multiple stages from the upper surface side of the mesa groove 9b to the bottom surface of the mesa groove 9b to form the electric field relaxation regions 20a and 20b. After removing the photoresist film used as a mask for ion implantation, as shown in FIG. 11, the electric field relaxation regions 20a and 20b are provided as a termination structure so as to be exposed on the bottom surface of the mesa groove 9b.

[0044] Subsequently, an oxide film is deposited on the upper surfaces of the source region 7, the base contact regions 8 and 8a, and the bottom surface of the mesa groove 9b by CVD techniques or the like. A photoresist film is applied to the upper surface of this oxide film, and the oxide film is patterned using photolithography techniques, dry etching techniques, or the like. Using the patterned oxide film as an etching mask, the trench 9a is selectively formed by dry etching techniques. As shown in FIG. 12, an n-type current diffusion layer 3 composed of an n-ion implantation layer 3p and an n-ion implantation layer 5p is formed on the upper surface of the drift layer 2, and the trench 9a penetrates the source region 7 and the base region 6 and reaches the gate bottom protection region 4b formed in the current diffusion layer 3.

[0045] After removing the oxide film, a carbon (C) film is formed by carbon sputtering techniques or the like so as to cover the trench 9a and the mesa groove 9b. Thereafter, heat treatment is performed to simultaneously activate the implanted n-type and p-type impurity ions. An oxide film made of SiO2 is deposited on the exposed surface after removing the carbon film by CVD techniques or the like. A photoresist film is applied to the upper surface of this oxide film, and the photoresist film is patterned using photolithography techniques or the like. Using the patterned photoresist film as an etching mask, the oxide film is selectively removed to form the field oxide film 10 shown in FIG. 13 so as to extend from the bottom surface of the mesa groove 9b to the upper surface of the base contact region 8a.

[0046] By means of a thermal oxidation method, chemical vapor deposition (CVD) technology, or the like, a gate insulating film such as an SiO2 film is formed on the bottom surface and side surfaces of the trench 9a, and on the upper surfaces of the source region 7 and the base contact region 8. Next, by means of CVD technology or the like, a polysilicon layer (doped polysilicon layer) with a high concentration of impurities such as phosphorus (P) or boron (B) is deposited so as to fill the trench 9a. Thereafter, by means of photolithography technology and dry etching, a part of the polysilicon layer and a part of the gate insulating film are selectively removed to form the insulated gate electrode structure (11, 12a) shown in FIG. 13. The insulated gate electrode structure (11, 12a) is composed of a gate insulating film 11 and a gate electrode 12a made of a polysilicon layer. Also, in the vicinity of the mesa groove 9b, a wiring layer 12b electrically connected to the gate electrode 12a is formed on the upper surface of the field oxide film 10. Next, by means of CVD technology or the like, an insulating film is deposited on the upper surface of the insulated gate electrode structure (11, 12a) composed of the gate electrode 12a and the gate insulating film 11. As this insulating film, boron phosphorus glass (BPSG), NSG, or the like is used. Then, by means of photolithography technology, dry etching technology, or the like, a part of the deposited insulating film is selectively removed. As a result, as shown in FIG. 13, a source electrode contact hole and a gate electrode pad contact hole are opened in the interlayer insulating film 13. Although not shown, a gate contact hole is also opened in the interlayer insulating film 13 so that a part of the gate surface electrode connected to the gate electrode 12a is exposed at a location different from the source electrode contact hole.

[0047] A metal layer such as a Ni film is deposited by a sputtering method, an evaporation method, or the like, and the metal layer is patterned using photolithography technology, RIE technology, or the like. Then, a source contact layer 14 is formed by performing high-speed heat treatment (RTA), for example, heat treatment at about 1000°C. Next, a metal layer such as a TiN film is deposited by a sputtering technique or the like, and the metal layer is patterned using photolithography technology, RIE technology, or the like to form barrier metal layers 15a and 15b. As a result, as shown in FIG. 14, the source contact layer 14 is formed on the upper surfaces of the source region 7 and the base contact region 8, and the barrier metal layer 15a is formed so as to cover the interlayer insulating film 13. Further, the barrier metal layer 15b is formed on the upper surface of the wiring layer 12b exposed from the interlayer insulating film 13. Next, a metal layer such as an Al film is deposited by a sputtering method or the like. The metal layer such as the Al film is patterned using photolithography technology, RIE technology, or the like to form patterns of the source electrode 16a, the gate electrode pad 16b, and the gate surface electrode (not shown). In this way, the patterns of the source electrode 16a and the gate surface electrode are separated, and the gate electrode pad 16b is electrically connected to the gate electrode 12a via the wiring layer 12b.

[0048] Next, as shown in FIG. 15, an adhesive 200 is applied to the upper surface side of the substrate 1p on which the element structure is formed and bonded to the glass plate 210. The lower surface of the substrate 1p is polished by chemical mechanical polishing (CMP) or the like to adjust the thickness to 100 μm or less, for example, about 50 μm, to form the drain region 1. Thereafter, a photoresist film is applied to the lower surface of the drain region 1, and the photoresist film is patterned using photolithography technology or the like. Using the patterned photoresist film 220 as a mask for ion implantation, protons (hydrogen (H) ions) or helium (He) ions are selectively implanted in multiple stages into the upper part of the drift layer 2. As a result, as shown in FIG. 16, the upper recombination region 26 is selectively formed on the upper part of the drift layer 2 so as to be in contact with the first implanted region 4a, and the upper recombination region 26a is in contact with the first implanted region 4b. The width of the upper recombination region 26 is made wider than the width of the bottom surface of the first implanted region 4a, and the bottom surface end portion of the first implanted region 4a is covered by the upper recombination region 26.

[0049] Subsequently, after removing the photoresist film 220, a photoresist film is applied to the lower surface of the drain region 1, and the photoresist film is patterned using photolithography technology or the like. Using the patterned photoresist film 230 as a mask for ion implantation, protons (hydrogen (H) ions) or helium (He) ions are selectively implanted in multiple stages into the upper part of the drift layer 2. As a result, as shown in FIG. 17, the lower recombination regions 24 and 24a are formed on the bottom of the drift layer 2 so as to be in contact with the upper surface of the buffer layer 22. The bottoms of the lower recombination regions 24 and 24a may be separated from the buffer layer 22 within a range of 3 μm or less. The lower recombination region 24 is selectively formed below the first implanted region 4a such that the position directly below the gate bottom protection region 4b corresponds to the position between the lower recombination regions 24. Further, the lower recombination region 24a is formed to extend from below the first implanted region 4c to the outer peripheral portion 101b.

[0050] After removing the photoresist film 230, the adhesive 200 is removed to separate the element structure from the glass plate 210. A drain electrode 17 made of Au or the like is formed on the entire lower surface of the drain region 1 by a sputtering method, a vapor deposition method, or the like. In this way, the trench gate type semiconductor device shown in FIG. 2 is completed.

[0051] In the method for manufacturing a semiconductor device according to the embodiment, the step of generating crystal defects that recombine holes is performed after a step including a high-temperature heat treatment such as activation of implanted impurity ions and electrode formation. Therefore, it is possible to suppress the generated crystal defects from disappearing due to the high-temperature heat treatment. Further, since the drain region 1 is formed by polishing the substrate 1p to a thickness of 100 μm or less, it is possible to reproducibly implant light element ions such as hydrogen and helium into the drift layer 2 at a high concentration from the lower surface of the drain region 1.

[0052] In the above description, in the semiconductor device according to the embodiment shown in FIG. 2, the lower recombination region 24 is selectively formed at the bottom of the drift layer 2 so as to be located below the first embedded region 4a. However, as shown in FIG. 18, a lower recombination region 24b in contact with the upper surface of the buffer layer 22 may be provided on the entire bottom surface of the drift layer 2. In this case, although it is possible to increase the recombination of holes in the lower recombination region 24b, it is likely to cause an increase in the on-resistance of the MOSFET and the forward voltage of the built-in diode. Therefore, it is desirable to reduce the surface density of crystal defects included in the lower recombination region 24b or to make the thickness of the lower recombination region 24b thinner. Note that the lower recombination region 24b may extend to the outer peripheral portion 101b.

[0053] Also, as shown in FIG. 19, an upper recombination region 26a may be provided so as to contact the bottom surface of the gate bottom protection region 4b. The upper recombination region 26a is provided separately from the upper recombination region 26. The width of the upper recombination region 26a is made wider than that of the gate bottom protection region 4b so that the bottom surface turning portion of the gate bottom protection region 4b is covered by the upper recombination region 26a. The gate bottom protection region 4b may be used in a floating manner, but generally it is connected to the first implantation region 4a of the base bottom implantation regions (4a, 5a). Also in this example, the gate bottom protection region 4b and the first implantation region 4a are connected by the connection portion 4d, but an upper recombination region 26c may also be provided at the bottom of the connection portion 4d to connect the upper recombination region 26 and the upper recombination region 26a. By providing the upper recombination regions 26a and 26c in this way, holes injected from the base region 6 through the gate bottom protection region 4b into the drift layer 2 can be recombined and reduced in the upper recombination region 26a. The protruding width Dt of the upper recombination region 26a protruding from the side surface of the gate bottom protection region 4b toward the first implantation region 4a side is preferably greater than 0 and not more than 1 / 2 of the current diffusion width Dp. Within such a range, it is possible to increase the recombination of holes and suppress an increase in the on-resistance of the MOSFET and the forward voltage of the built-in diode. Note that the thicknesses and the surface densities of the irradiated ions of the upper recombination regions 26a and 26c may be the same as those of the upper recombination region 26.

[0054] Also, as shown in FIG. 20, an n + -type partial current diffusion layer 28 may be provided on the upper part of the upper recombination region 26 so as to contact the bottom surface of the first implantation region 4a. For example, the impurity concentration of the partial current diffusion layer 28 is 5×10 17 cm -3 or more and 1×10 19 cm -3 or less. The partial current diffusion layer 28 has a current diffusion function, but it is possible to reduce the injection of holes from the first implantation region 4a.

[0055] (Other Embodiments) As described above, embodiments of the present invention have been described, but the discussions and drawings that form part of this disclosure should not be understood as limiting the present invention. Various alternative embodiments, examples, and operational techniques will become apparent to those skilled in the art from this disclosure.

[0056] As described above, in the embodiment, light element ions such as hydrogen (H) and helium (He) are used to generate crystal defects, but it is not limited thereto. For example, heavy metal ions such as titanium (Ti), vanadium (V), chromium (Cr), manganese (Mn), iron (Fe), platinum (Pt), and gold (Au) may be used. As shown in FIG. 21, the upper recombination region 26b using heavy metal ions is preferably provided such that crystal defects are localized at the bottom of the first implantation region 4a of the base bottom implantation region (4a, 5a). When using heavy metal ions, since the implantation depth of ion implantation becomes small, it is difficult to perform ion implantation from the lower surface of the drain region 1 as shown in FIG. 16. Therefore, as shown in FIG. 22, heavy metal ions are implanted before the step of implanting p-type impurity ions into the first implantation region 4a of FIG. 8 to form the upper recombination region 26b. As the mask for ion implantation, the oxide film 140 can be used. Since the implanted heavy metal itself constitutes crystal defects, the crystal defects remain even in a high-temperature process such as activation heat treatment. Note that the heavy metal ion implantation may be performed immediately after the p-type impurity ion implantation step of the first implantation region 4a.

[0057] Thus, the present invention naturally includes various embodiments and the like not described herein, such as configurations in which each configuration described in the above embodiments and each modification example is arbitrarily applied. Therefore, the technical scope of the present invention is defined only by the invention-specific matters according to the reasonable claims based on the above description.

Explanation of Reference Numerals

[0058] 1... Drain region (second main region) 1p, 100... SiC semiconductor substrate (substrate) 2, 2p... Drift layer 2s, 3s, 5e, 6p... Epitaxial layer 3... Current diffusion layer 3p, 5p…n ion implantation layer (4a, 5a)…base bottom buried region 4a, 4c…first buried region 4b…gate bottom protection region 4d…connection part 5a, 5b…second buried region 6…base region 7…source region (first main region) 8, 8a…base contact region 9a…trench 9b…mesa groove 10…field oxide film 11…gate insulating film (11, 12a)…insulated gate electrode structure 12a…gate electrode 12b…wiring layer 13…interlayer insulating film 14…source contact layer 15a, 15b…barrier metal layer 16a…source electrode (first main electrode) 16b…gate electrode pad 17…drain electrode (second main electrode) 20a, 20b…electric field relaxation region 22…buffer layer 24, 24a, 24b…lower recombination region 26, 26a, 26b, 26c…upper recombination region 28…partial current diffusion layer 34…recombination promotion layer 31a, 31b…mask 40s, 40t…base plane dislocation 42…through dislocation 44…minority carrier (hole) 46…stacking defect 101…chip region 101a…active part 101b…peripheral part 102…dicing line 130, 220, 230…photoresist film 140, 150…oxide film 200…adhesive 210…glass plate

Claims

1. A first-conductivity-type drift layer provided on a first-conductivity-type silicon carbide substrate, a first-conductivity-type current diffusion layer provided on the upper surface of the drift layer and having a higher impurity concentration than the drift layer, a second-conductivity-type base region provided on the upper surface of the current diffusion layer, a second-conductivity-type gate bottom protection region provided inside the current diffusion layer, a second-conductivity-type base bottom embedded region provided inside the current diffusion layer, spaced apart from the gate bottom protection region, and in contact with the lower surface of the base region, an insulated gate type electrode structure provided inside a trench that penetrates the base region and reaches the gate bottom protection region, a lower recombination region provided at the bottom of the drift layer for recombining minority carriers injected into the drift layer by crystal defects, an upper recombination region provided in contact with the bottom surface of the base bottom embedded region for recombining minority carriers injected from the base region by crystal defects, A silicon carbide semiconductor device comprising the above.

2. The upper recombination region has a recombination center composed of hydrogen or helium as the crystal defect, and is provided on the upper part of the drift layer so as to cover the bottom surface and the bottom end part of the base bottom embedded region. The silicon carbide semiconductor device according to Claim 1.

3. The side surface of the upper recombination region protrudes from the end of the bottom surface of the base bottom embedded region toward the gate bottom protection region side with a width of 1 / 2 or less of the width between the base bottom embedded region and the gate bottom protection region. The upper recombination region has a surface density of the crystal defects in the range of 5×10 １０ cm －２ or more and 2×10 １１ cm －２ or less, and has a thickness in the range of 0.2 μm or more and 0.5 μm or less. The silicon carbide semiconductor device according to claim 1, characterized in that.

4. A first-conductivity-type drift layer provided on a first-conductivity-type silicon carbide substrate, a first-conductivity-type current diffusion layer provided on the upper surface of the drift layer and having a higher impurity concentration than the drift layer, a second-conductivity-type base region provided on the upper surface of the current diffusion layer, a second-conductivity-type gate bottom protection region provided inside the current diffusion layer, a second-conductivity-type base bottom embedded region provided inside the current diffusion layer, spaced apart from the gate bottom protection region, and in contact with the lower surface of the base region, an insulated gate type electrode structure provided inside a trench that penetrates the base region and reaches the gate bottom protection region, a lower recombination region provided at the bottom of the drift layer for recombining minority carriers injected into the drift layer by crystal defects, Comprising The lower recombination region has a recombination center composed of hydrogen or helium that recombines minority carriers, and is selectively provided below the base bottom implantation region. The silicon carbide semiconductor device is characterized in that.

5. The region between adjacent lower recombination regions is provided at a position facing the gate bottom protection region. The width between adjacent lower recombination regions is made larger than the width of the gate bottom protection region. In plan view, the ends of the lower recombination regions are located on the gate bottom protection region side between the base bottom implantation region and the gate bottom protection region. The silicon carbide semiconductor device according to claim 4, characterized in that.

6. The silicon carbide semiconductor device according to any one of claims 1 to 3, characterized in that the lower recombination region is provided on the entire bottom surface of the drift layer.

7. A first conductivity type drift layer provided on a first conductivity type silicon carbide substrate, A first conductivity type current diffusion layer provided on the upper surface of the drift layer and having a higher impurity concentration than the drift layer. A second conductivity type base region provided on the upper surface of the current diffusion layer. A second conductivity type gate bottom protection region provided inside the current diffusion layer. A second conductivity type base bottom implantation region provided inside the current diffusion layer, separated from the gate bottom protection region, and in contact with the lower surface of the base region. An insulated gate type electrode structure provided inside a trench that penetrates the base region and reaches the gate bottom protection region. A lower recombination region provided at the bottom of the drift layer, which recombines minority carriers injected into the drift layer by crystal defects. Comprising The lower recombination region has a surface density of crystal defects in the range of 5×10 １１ cm －２ or more and 2×10 １２ cm －２ or less, and has a thickness in the range of 0.5 μm or more and 1.0 μm or less. A silicon carbide semiconductor device characterized by this.

8. A first conductivity type drift layer provided on a first conductivity type silicon carbide substrate, A first conductivity type current diffusion layer provided on the upper surface of the drift layer and having a higher impurity concentration than the drift layer. A second conductivity type base region provided on the upper surface of the current diffusion layer. A second conductivity type gate bottom protection region provided inside the current diffusion layer. A second conductivity type base bottom implantation region provided inside the current diffusion layer, separated from the gate bottom protection region, and in contact with the lower surface of the base region. An insulated gate type electrode structure provided inside a trench that penetrates the base region and reaches the gate bottom protection region. A lower recombination region provided at the bottom of the drift layer, which recombines minority carriers injected into the drift layer by crystal defects. A gate bottom recombination region that is provided so as to cover the bottom surface and the bottom surface end portion of the gate bottom protection region, and that recombines minority carriers due to crystal defects; A silicon carbide semiconductor device characterized by comprising the same. **Claim 9** The upper recombination region extends so as to be in contact with the entire bottom surface of the base bottom embedded region that extends from an end portion of the active portion provided with the insulated gate electrode structure to an outer peripheral portion disposed around the active portion. The silicon carbide semiconductor device according to any one of claims 1 to 3. **Claim 10** The silicon carbide semiconductor device according to any one of claims 1 to 3, further comprising, on an upper portion of the upper recombination region, a partial current diffusion layer of a first conductivity type that is in contact with the bottom surface of the base bottom embedded region. **Claim 11** The upper recombination region has, as the crystal defect, a recombination center composed of at least one heavy metal selected from titanium, vanadium, chromium, manganese, iron, platinum, and gold, and is provided so as to be localized at the bottom of the base bottom embedded region. The silicon carbide semiconductor device according to claim 1. **Claim 12** The silicon carbide semiconductor device according to any one of claims 1 to 11, further comprising, on an upper surface of the silicon carbide substrate, a buffer layer of a first conductivity type having a higher impurity concentration than the drift layer so as to be in contact with a lower surface of the drift layer. **Claim 13** A step of forming an element structure in an active portion by polishing a lower surface of the silicon carbide substrate after forming a first conductivity type current diffusion layer having a higher impurity concentration than the drift layer on an upper surface of a first conductivity type drift layer epitaxially grown on a first conductivity type silicon carbide substrate, a second conductivity type base region on an upper surface of the current diffusion layer, a second conductivity type gate bottom protection region having a higher impurity concentration than the base region at a bottom of the current diffusion layer, a second conductivity type base bottom embedded region having a higher impurity concentration than the base region and spaced apart from the gate bottom protection region inside the current diffusion layer and in contact with a lower surface of the base region, and an insulated gate electrode structure provided inside a trench that penetrates the base region and reaches the gate bottom protection region; A step of selectively ion-implanting hydrogen or helium from the lower surface of the polished silicon carbide substrate to a bottom of the drift layer to form a lower recombination region that recombines minority carriers due to crystal defects at the bottom of the drift layer; Selectively ion-implant hydrogen or helium into the upper part of the drift layer from the lower surface of the polished silicon carbide substrate to selectively form an upper recombination region where minority carriers recombine due to crystal defects so as to contact the bottom surface of the base bottom embedded region. A method for manufacturing a silicon carbide semiconductor device, characterized by including the above.

14. The method for manufacturing a silicon carbide semiconductor device according to claim 13, wherein the upper recombination region is formed so as to cover the bottom surface and the bottom surface end portion of the base bottom embedded region.

15. After forming a first conductivity type current diffusion layer having a higher impurity concentration than the drift layer on the upper surface of a first conductivity type drift layer epitaxially grown on a silicon carbide substrate of the first conductivity type, a second conductivity type base region on the upper surface of the current diffusion layer, a second conductivity type gate bottom protection region having a higher impurity concentration than the base region at the bottom of the current diffusion layer, a second conductivity type base bottom embedded region having a higher impurity concentration than the base region and spaced apart from the gate bottom protection region inside the current diffusion layer and contacting the lower surface of the base region, and an insulated gate type electrode structure provided inside a trench that penetrates the base region and reaches the gate bottom protection region, forming an element structure in the active part by polishing the lower surface of the silicon carbide substrate. Selectively ion-implant hydrogen or helium into the bottom of the drift layer from the lower surface of the polished silicon carbide substrate to form a lower recombination region where minority carriers recombine due to crystal defects at the bottom of the drift layer. including A method for manufacturing a silicon carbide semiconductor device, characterized in that the lower recombination region is selectively formed below the base bottom embedded region.

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