Silicon carbide semiconductor device and method of manufacturing the same

Abstract

To provide a silicon carbide semiconductor device capable of mitigating electric field concentration in the vicinity of a bottom face of a gate trench, and a manufacturing method of the silicon carbide semiconductor device.SOLUTION: In a silicon carbide semiconductor device 100, a gate trench 5 defined by a side face 3 penetrating a source region 13 and a body region 12 and reaching a first semiconductor region 11 and a bottom face 4 communicated with the side face is provided on a first principal surface 1 of a silicon carbide wafer 10, and the silicon carbide wafer further comprises an electric field mitigation region 16 which is provided between the bottom face and a second principal surface 2 and has a second conductivity type. Regarding the electric field mitigation region, a second width at a second position in contact with the bottom face is larger than a first width at a first position separated from the bottom face to the side of the second principal surface by 1.5 μm, and the first width is larger than a width of the bottom face.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present disclosure relates to a silicon carbide semiconductor device and a method for manufacturing a silicon carbide semiconductor device.

Background Art

[0002] In a trench gate type MOSFET (metal-oxide-semiconductor field effect transistor), a structure in which the bottom of the trench is exposed from a p-type shield region when viewed from the drain side, and a structure in which the bottom of the trench is covered with a p-type shield region having the same width as the trench width are known (see, for example, Patent Documents 1 to 3).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0004] In a structure in which the bottom of the trench is exposed from a p-type shield region when viewed from the drain side, and a structure in which the bottom of the trench is covered with a p-type shield region having the same width as the trench width, the electric field concentration on the gate insulating film during the off operation may increase.

[0005] An object of the present disclosure is to provide a silicon carbide semiconductor device and a method for manufacturing a silicon carbide semiconductor device that can mitigate the electric field concentration in the vicinity of the bottom surface of the gate trench.

Means for Solving the Problems

[0006] The silicon carbide semiconductor device of the present disclosure includes a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface. The silicon carbide substrate includes a first semiconductor region having a first conductivity type, a body region provided on the first semiconductor region and having a second conductivity type different from the first conductivity type, and a source region provided on the body region so as to be separated from the first semiconductor region and having the first conductivity type. On the first main surface, a gate trench defined by a side surface that penetrates the source region and the body region and reaches the first semiconductor region, and a bottom surface continuous with the side surface is provided. The silicon carbide substrate further includes an electric field relaxation region provided between the bottom surface and the second main surface and having the second conductivity type. The electric field relaxation region has a second width at a second position in contact with the bottom surface that is wider than a first width at a first position 1.5 μm away from the bottom surface toward the second main surface, and the first width is wider than the width of the bottom surface.

Advantages of the Invention

[0007] According to the present disclosure, it is possible to relieve the electric field concentration in the vicinity of the bottom surface of the gate trench.

Brief Description of the Drawings

[0008]

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[0009] Embodiments for carrying out the invention will be described below.

[0010] [Description of Embodiments of the Present Disclosure] First, embodiments of the present disclosure will be listed and described. In the following description, the same or corresponding elements are denoted by the same reference numerals, and the same description thereof will not be repeated. In the crystallographic description in this specification, individual orientations are indicated by [], collective orientations by <>, individual planes by (), and collective planes by {}. Also, a negative crystallographic index is usually expressed by attaching "-" (bar) above the number, but in this specification, a negative sign is attached before the number.

[0011] 〔1〕 A silicon carbide semiconductor device according to an aspect of the present disclosure includes a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface. The silicon carbide substrate has a first semiconductor region having a first conductivity type, a body region provided on the first semiconductor region and having a second conductivity type different from the first conductivity type, and a source region provided on the body region so as to be separated from the first semiconductor region and having the first conductivity type. On the first main surface, a gate trench defined by a side surface that penetrates the source region and the body region and reaches the first semiconductor region and a bottom surface continuous with the side surface is provided. The silicon carbide substrate further has an electric field relaxation region provided between the bottom surface and the second main surface and having the second conductivity type. The electric field relaxation region has a second width at a second position in contact with the bottom surface that is wider than a first width at a first position 1.5 μm away from the bottom surface toward the second main surface side, and the first width is wider than the width of the bottom surface.

[0012] An electric field relaxation region is provided between the bottom surface of the gate trench and the second main surface. When viewed in plan from a direction perpendicular to the first main surface, the gate trench can be hidden by the electric field relaxation region. Thereby, the electric field concentration in the vicinity of the bottom surface of the gate trench can be alleviated, and the dielectric breakdown of the gate insulating film can be suppressed. Also, the short-circuit withstand capacity is improved.

[0013] 〔2〕In 〔1〕, the electric field relaxation region has a first electric field relaxation region that is in contact with the bottom surface and has the first width, and a second electric field relaxation region that extends from the first electric field relaxation region in the width direction of the gate trench. The effective concentration of the impurity of the second conductivity type in the first electric field relaxation region may be lower than the effective concentration of the impurity of the second conductivity type in the second electric field relaxation region. By providing the second electric field relaxation region that extends from the first electric field relaxation region in the width direction of the gate trench, the electric field concentration near the bottom surface of the gate trench can be further relaxed.

[0014] 〔3〕In 〔2〕, the length obtained by subtracting the length in the direction perpendicular to the first main surface in the second electric field relaxation region from the length in the direction perpendicular to the first main surface in the first electric field relaxation region may be 3 times or more and 15 times or less the length in the direction perpendicular to the first main surface in the second electric field relaxation region. In this case, the electric field relaxation region directly under the gate trench becomes deeper, and the breakdown voltage and short-circuit withstand capacity are improved.

[0015] 〔4〕In 〔2〕 or 〔3〕, the first semiconductor region has a second semiconductor region located on the first electric field relaxation region and a third semiconductor region located on the second electric field relaxation region. The effective concentration of the impurity of the first conductivity type in the second semiconductor region may be higher than the effective concentration of the impurity of the first conductivity type in the third semiconductor region. In this case, the semiconductor regions located on the first electric field relaxation region and the second electric field relaxation region are narrowed, and the short-circuit withstand capacity can be improved while reducing the feedback capacitance. Since the feedback capacitance is reduced, the switching speed is improved.

[0016] 〔5〕In [4], the body region has a first body region located on the second semiconductor region and a second body region located on the third semiconductor region, and the effective concentration of the impurity of the second conductivity type in the first body region may be lower than the effective concentration of the impurity of the second conductivity type in the second body region. In this case, the effective concentration of the impurity of the second conductivity type in the second body region directly above the second electric field relaxation region can be selectively increased. Thereby, while suppressing short channeling, it becomes possible to lower the effective concentration of the impurity of the second conductivity type in the first body region, and the on-resistance can be reduced.

[0017] 〔6〕In [1] to [5], the first semiconductor region has a drift region and a current diffusion region located between the drift region and the body region, and the effective concentration of the impurity of the first conductivity type in the current diffusion region is higher than the effective concentration of the impurity of the first conductivity type in the drift region, and the side surface of the gate trench may reach the current diffusion region. By providing a current diffusion region between the drift region and the body region, the on-resistance of the narrow region can be reduced.

[0018] 〔7〕A method for manufacturing a silicon carbide semiconductor device according to another aspect of the present disclosure includes a step of preparing a silicon carbide substrate having a first main surface, a second main surface opposite to the first main surface, and a first semiconductor region having a first conductivity type, a step of forming a first mask on the first main surface, a step of forming a second mask on the first mask, and a step of forming an electric field relaxation region having a second conductivity type different from the first conductivity type by performing ion implantation on the silicon carbide substrate using the first mask and the second mask. The first mask has a first opening, and the second mask is positioned so as to overlap the first opening when viewed from a direction perpendicular to the first main surface and has a second opening having a wider opening width than the first opening.

[0019] By performing ion implantation on a silicon carbide substrate using a first mask and a second mask, an electric field relaxation region can be formed between the bottom surface of the gate trench and the second main surface. Further, when viewed in plan from a direction perpendicular to the first main surface, the gate trench can be hidden by the electric field relaxation region. Thereby, the electric field concentration in the vicinity of the bottom surface of the gate trench can be alleviated, and the dielectric breakdown of the gate insulating film can be suppressed.

[0020] Also, ions are implanted into the silicon carbide epitaxial layer without colliding with the crystal atoms of the material constituting the first mask directly below the first opening. As a result, ions are implanted to a deep position in the silicon carbide epitaxial layer directly below the first opening. As a result, a first electric field relaxation region can be formed in the silicon carbide epitaxial layer located directly below the first opening. Further, laterally of the first opening, ions are scattered by the crystal atoms of the material constituting the first mask and implanted into the silicon carbide epitaxial layer. As a result, ions are not implanted to a deep position in the silicon carbide epitaxial layer laterally of the first opening, and ions are implanted to a shallow position. As a result, a second electric field relaxation region can be formed in the silicon carbide epitaxial layer located laterally of the first opening. By providing the second electric field relaxation region that protrudes in the width direction of the gate trench from the first electric field relaxation region, the electric field concentration in the vicinity of the bottom surface of the gate trench can be further alleviated.

[0021] 〔8〕 In 〔7〕, the first opening and the second opening may extend along the [11-20] direction of the silicon carbide substrate. In this case, ions can be implanted to a deep position in the silicon carbide epitaxial layer located directly below the first opening.

[0022] 〔9〕 In 〔7〕 or 〔8〕, the first mask may be formed of polysilicon or silicon oxide, and the second mask may be formed of a resist. By forming the first mask and the second mask of different materials, it is possible to suppress the first opening of the first mask from being etched when forming the second opening in the second mask. Therefore, two openings with different opening widths can be easily formed.

[0023] 〔10〕 In [7] to [9], the opening width of the first opening may be narrower than the opening width of the second opening, and the difference between the opening width of the first opening and the opening width of the second opening may be 0.2 μm or more and 1.0 μm or less. In this case, it is easy to obtain a desired ion implantation profile.

[0024] 〔11〕 In [7] to

[10] , the amount of displacement between the center in the width direction of the first opening and the center in the width direction of the second opening may be within 0.2 μm. In this case, a second electric field relaxation region that protrudes substantially evenly in the width direction of the gate trench from the first electric field relaxation region can be formed.

[0025] 〔12〕 A method for manufacturing a silicon carbide semiconductor device according to another aspect of the present disclosure includes a step of preparing a silicon carbide substrate having a first main surface, a second main surface opposite to the first main surface, and a first semiconductor region having a first conductivity type, a step of forming a third mask formed of a resist on the first main surface, and a step of forming an electric field relaxation region having a second conductivity type different from the first conductivity type by performing ion implantation on the silicon carbide substrate using the third mask. The third mask has a third opening whose opening width changes in the thickness direction.

[0026] By performing ion implantation on the silicon carbide substrate using the third mask, an electric field relaxation region can be formed between the bottom surface of the gate trench and the second main surface. Also, when viewed in plan from a direction perpendicular to the first main surface, the gate trench can be hidden by the electric field relaxation region. Thereby, the electric field concentration in the vicinity of the bottom surface of the gate trench can be relaxed, and the dielectric breakdown of the gate insulating film can be suppressed.

[0027] In addition, since the third mask has a third opening whose opening width changes in the thickness direction, a first electric field relaxation region and a second electric field relaxation region can be formed in the silicon carbide epitaxial layer in the same manner as in the case of having the first mask and the second mask. As a result, the electric field concentration near the bottom surface of the gate trench can be further relaxed.

[0028] 〔13〕 In 〔12〕, the third opening may have a barrel shape in the cross-sectional shape in the width direction. In this case, it is easy to obtain a desired ion implantation profile.

[0029] [Details of Embodiments of the Present Disclosure] Hereinafter, embodiments of the present disclosure will be described in detail, but the present disclosure is not limited thereto.

[0030] (Silicon Carbide Semiconductor Device) Referring to FIG. 1, a silicon carbide semiconductor device according to an embodiment will be described. As shown in FIG. 1, a silicon carbide semiconductor device 100 according to an embodiment mainly includes a silicon carbide substrate 10, a gate insulating film 81, a gate electrode 82, an interlayer insulating film 83, a source electrode 60, and a drain electrode 70.

[0031] The silicon carbide substrate 10 includes a silicon carbide single crystal substrate 50 and a silicon carbide epitaxial layer 40 on the silicon carbide single crystal substrate 50. The silicon carbide substrate 10 has a first main surface 1 and a second main surface 2 opposite to the first main surface 1. The silicon carbide epitaxial layer 40 constitutes the first main surface 1. The silicon carbide single crystal substrate 50 constitutes the second main surface 2. The silicon carbide single crystal substrate 50 and the silicon carbide epitaxial layer 40 are made of, for example, polytype 4H hexagonal silicon carbide. The silicon carbide single crystal substrate 50 contains, for example, an n-type impurity such as nitrogen (N) and has an n-type. A semiconductor element is formed on the silicon carbide substrate 10.

[0032] The first main surface 1 is a surface where the {0001} plane or the {0001} plane is inclined by an off-angle of 8° or less in the off direction. Preferably, the first main surface 1 is a surface where the (000-1) plane or the (000-1) plane is inclined by an off-angle of 8° or less in the off direction. The off direction may be, for example, the <11-20> direction or the <1-100> direction. The off-angle may be, for example, 1° or more, or 2° or more. The off-angle may be 6° or less, or 4° or less.

[0033] In the embodiment, a field effect transistor is formed on the silicon carbide substrate 10 as an example of a semiconductor element. The silicon carbide epitaxial layer 40 mainly has a drift region 11, a current diffusion region 14, a body region 12, a source region 13, an electric field relaxation region 16, and a contact region 18.

[0034] The drift region 11 contains, for example, an n-type impurity such as nitrogen or phosphorus (P) and has an n-type. The addition of the n-type impurity to the drift region 11 is preferably performed by adding an impurity during the epitaxial growth of the drift region 11 rather than by ion implantation. The drift region 11 is a part of the first semiconductor region.

[0035] The current diffusion region 14 is provided on the drift region 11. The current diffusion region 14 contains, for example, an n-type impurity such as phosphorus and has an n-type. By providing the current diffusion region 14 on the drift region 11, the on-resistance of the narrowing region can be reduced. The current diffusion region 14 mainly has, for example, a first current diffusion region 14a and a second current diffusion region 14b. The first current diffusion region 14a is provided on the first electric field relaxation region 16a described later. The second current diffusion region 14b is provided on the second electric field relaxation region 16b described later. The effective concentration of the n-type impurity in the first current diffusion region 14a may be higher than the effective concentration of the n-type impurity in the second current diffusion region 14b. In this case, the current diffusion region 14 narrows, and the short-circuit withstand capacity can be improved while reducing the feedback capacitance. Since the feedback capacitance is reduced, the switching speed is improved. The effective concentration of the n-type impurity in the first current diffusion region 14a is, for example, 1.5×1017 cm -3 Above 3.0×10 18 cm -3 The following. The effective concentration of the n-type impurity in the second current diffusion region 14b is, for example, 5.0×10 16 cm -3 Above 1.0×10 17 cm -3 The following. The effective concentration of the n-type impurity is the concentration obtained by subtracting the concentration of the p-type impurity from the concentration of the n-type impurity. The current diffusion region 14 is a part of the first semiconductor region. The first current diffusion region 14a is an example of the second semiconductor region. The second current diffusion region 14b is an example of the third semiconductor region.

[0036] The body region 12 is provided on the current diffusion region 14. The body region 12 contains a p-type impurity such as aluminum (Al) and has a p-type. The body region 12 mainly has, for example, a first body region 12a and a second body region 12b. The first body region 12a is provided on the first current diffusion region 14a. The second body region 12b is provided on the second current diffusion region 14b. The effective concentration of the p-type impurity in the first body region 12a may be lower than the effective concentration of the p-type impurity in the second body region 12b. In this case, the effective concentration of the p-type impurity in the second body region 12b directly above the second electric field relaxation region 16b can be selectively increased. Thereby, while suppressing short channeling, it becomes possible to lower the effective concentration of the p-type impurity in the first body region 12a and reduce the on-resistance. The effective concentration of the p-type impurity in the first body region 12a is, for example, 2.0×10 17 cm -3 Above 3.0×10 18 cm -3 The following. The effective concentration of the p-type impurity in the second body region 12b is, for example, 3.0×10 17 cm -3 Above 5.0×10 18 cm -3 The following. The effective concentration of the p-type impurity is the concentration obtained by subtracting the concentration of the n-type impurity from the concentration of the p-type impurity.

[0037] The source region 13 is provided on the body region 12 so as to be separated from the drift region 11 by the body region 12. The source region 13 contains an n-type impurity such as nitrogen or phosphorus, for example, and has an n-type conductivity. The source region 13 constitutes the first main surface 1. The effective concentration of the n-type impurity in the source region 13 is, for example, 1.0×10 18 cm -3 or more and 7.0×10 19 cm -3 or less.

[0038] The contact region 18 contains a p-type impurity such as aluminum, for example, and has a p-type conductivity. The contact region 18 constitutes the first main surface 1. The contact region 18 penetrates the source region 13 and is in contact with the body region 12.

[0039] On the first main surface 1, a gate trench 5 defined by a side surface 3 and a bottom surface 4 is provided. The side surface 3 penetrates the source region 13, the body region 12, and the current diffusion region 14 and reaches the electric field relaxation region 16. The bottom surface 4 is continuous with the side surface 3. The bottom surface 4 is, for example, a plane parallel to the second main surface 2. The angle of the side surface 3 with respect to the plane including the bottom surface 4 is, for example, 50° or more and 65° or less. This angle may be, for example, 55° or more. This angle may be, for example, 60° or less. The side surface 3 preferably has a {0-33-8} plane. The {0-33-8} plane is a crystal plane on which excellent mobility can be obtained. The angle of the side surface 3 with respect to the plane including the bottom surface 4 may be 90°. The gate trench 5 extends in a stripe shape, for example, along a direction parallel to the first main surface 1. The gate trench 5 may extend in a honeycomb shape or may be dotted in an island shape.

[0040] The electric field relaxation region 16 contains p-type impurities such as aluminum, etc., and has a p-type. The electric field relaxation region 16 is provided between the bottom surface 4 of the gate trench 5 and the second main surface 2. The upper end surface of the electric field relaxation region 16 is in contact with the bottom surface 4 of the gate trench 5. The central axis of the electric field relaxation region 16 may coincide with the central axis of the gate trench 5. The electric field relaxation region 16 has a first width W1 that is wider than the width of the bottom surface 4 of the gate trench 5 at a position 1.5 μm away from the bottom surface 4 of the gate trench 5 toward the second main surface 2. The electric field relaxation region 16 has a second width W2 that is wider than the first width W1 at a position in contact with the bottom surface 4 of the gate trench 5.

[0041] The electric field relaxation region 16 mainly has, for example, a first electric field relaxation region 16a and a second electric field relaxation region 16b. The first electric field relaxation region 16a has a first width W1. The upper end surface of the first electric field relaxation region 16a is in contact with the bottom surface 4 of the gate trench 5 and the lower end surface of the first current diffusion region 14a. The second electric field relaxation region 16b is a region that protrudes in the width direction of the gate trench 5 from the first electric field relaxation region 16a. The upper end surface of the second electric field relaxation region 16b is in contact with the lower end surface of the second current diffusion region 14b. The depth difference D1 between the first electric field relaxation region 16a and the second electric field relaxation region 16b may be 3 times or more and 15 times or more the depth D2 of the second electric field relaxation region 16b. In this case, the electric field relaxation region 16 directly below the gate trench becomes deeper, and the breakdown voltage and short-circuit withstand capacity are improved. The effective concentration of p-type impurities in the first electric field relaxation region 16a may be lower than the effective concentration of p-type impurities in the second electric field relaxation region 16b. The effective concentration of p-type impurities in the first electric field relaxation region 16a is, for example, 5.0×10 16 cm -3 or more and 3.0×10 17 cm -3 or less. The effective concentration of p-type impurities in the second electric field relaxation region 16b is, for example, 1.0×10 17 cm -3 or more and 2.0×10 18 cm -3 or less.

[0042] The gate insulating film 81 is, for example, an oxide film. The gate insulating film 81 is composed of a material containing, for example, silicon dioxide. The gate insulating film 81 is in contact with the side surface 3 and the bottom surface 4. The gate insulating film 81 is in contact with the electric field relaxation region 16 at the bottom surface 4. The gate insulating film 81 is in contact with each of the source region 13, the body region 12, and the current diffusion region 14 at the side surface 3. The gate insulating film 81 may be in contact with the source region 13 on the first main surface 1.

[0043] The gate electrode 82 is provided on the gate insulating film 81. The gate electrode 82 is composed of, for example, polysilicon (poly-Si) containing a conductive impurity. The gate electrode 82 is disposed inside the gate trench 5. A part of the gate electrode 82 may be disposed on the first main surface 1.

[0044] The interlayer insulating film 83 is provided in contact with the gate electrode 82 and the gate insulating film 81. The interlayer insulating film 83 is composed of a material containing, for example, silicon dioxide. The interlayer insulating film 83 electrically insulates the gate electrode 82 and the source electrode 60. A part of the interlayer insulating film 83 may be provided inside the gate trench 5.

[0045] The source electrode 60 is in contact with the first main surface 1. The source electrode 60 has a contact electrode 61 and a source wiring 62.

[0046] The contact electrode 61 is in contact with the source region 13 and the contact region 18 on the first main surface 1. The contact electrode 61 is composed of a material containing, for example, nickel silicide (NiSi). The contact electrode 61 may be composed of a material containing titanium (Ti), aluminum, and silicon. The contact electrode 61 forms an ohmic contact with the source region 13 and the contact region 18.

[0047] The source wiring 62 covers the upper surface and the side surface of the interlayer insulating film 83 and the upper surface of the contact electrode 61. The source wiring 62 is in contact with each of the interlayer insulating film 83 and the contact electrode 61. The source wiring 62 is made of a material containing, for example, aluminum or copper (Cu). The source wiring 62 may be made of a material containing aluminum and copper. The source electrode 60 is electrically insulated from the gate electrode 82 by the interlayer insulating film 83. The source electrode 60 may include a barrier metal film such as a titanium nitride (TiN) film between the source wiring 62 and the interlayer insulating film 83.

[0048] The drain electrode 70 is in contact with the second main surface 2. The drain electrode 70 is in contact with the silicon carbide single crystal substrate 50 on the second main surface 2. The drain electrode 70 is electrically connected to the drift region 11. The drain electrode 70 is made of a material containing, for example, nickel silicide. The drain electrode 70 may be made of a material containing titanium, aluminum, and silicon. The drain electrode 70 makes an ohmic contact with the silicon carbide single crystal substrate 50.

[0049] Note that the concentration of the p-type impurity and the concentration of the n-type impurity in each of the above impurity regions can be measured by, for example, measurement using a scanning capacitance microscope (SCM) or secondary ion mass spectrometry (SIMS).

[0050] According to the silicon carbide semiconductor device 100 according to the embodiment described above, an electric field relaxation region 16 is provided between the bottom surface 4 of the gate trench 5 and the second main surface 2, and when viewed in a plan view from a direction perpendicular to the first main surface 1, the gate trench 5 can be hidden by the electric field relaxation region 16. Thereby, the electric field concentration in the vicinity of the bottom surface 4 of the gate trench 5 can be relaxed, and the dielectric breakdown of the gate insulating film 81 can be suppressed. Also, the short-circuit withstand capacity is improved. Further, since the second electric field relaxation region 16b protruding in the width direction of the gate trench 5 from the first electric field relaxation region 16a is provided, the electric field concentration in the vicinity of the bottom surface 4 of the gate trench 5 can be further relaxed.

[0051] (Method for manufacturing silicon carbide semiconductor device) With reference to FIGS. 2 to 15, a method for manufacturing a silicon carbide semiconductor device 100 according to an embodiment will be described.

[0052] First, as shown in FIG. 2, a silicon carbide single crystal substrate 50 is prepared. Next, a silicon carbide epitaxial layer 40 is formed on the silicon carbide single crystal substrate 50. For example, the silicon carbide single crystal substrate 50 contains an n-type impurity such as nitrogen and has an n-type. For example, the silicon carbide epitaxial layer 40 can be formed by epitaxial growth with an n-type impurity such as nitrogen added. In this way, a silicon carbide substrate 10 having a first main surface 1 and a second main surface 2 is obtained.

[0053] Next, as shown in FIG. 3, a first mask 91 is formed on the silicon carbide epitaxial layer 40. The first mask 91 has an opening 91a. The opening 91a is located above a region where a first electric field relaxation region 16a is to be formed. The opening 91a preferably extends, for example, along the [11-20] direction of the silicon carbide substrate 10. In this case, ions can be implanted deep into the silicon carbide epitaxial layer 40 located directly below the opening 91a. The first mask 91 may be a hard mask made of a material containing, for example, polysilicon or silicon oxide.

[0054] Next, as shown in FIG. 4, a second mask 92 is formed on the first mask 91. The second mask 92 is formed, for example, thicker than the first mask 91. The second mask 92 has an opening 92a. The opening 92a is located over a region where the first electric field relaxation region 16a and the second electric field relaxation region 16b are formed. The opening width Wb of the opening 92a is wider than the opening width Wa of the opening 91a. The difference between the opening width Wa and the opening width Wb is preferably 0.2 μm or more and 1.0 μm or less. In this case, it is easy to obtain a desired ion implantation profile. The opening 92a overlaps the opening 91a when viewed from a direction perpendicular to the first main surface 1. The central axis Cb of the opening 92a may coincide with the central axis Ca of the opening 91a. The central axis Cb of the opening 92a may be offset from the central axis Ca of the opening 91a. In this case, the amount of displacement between the central axis Cb of the opening 92a and the central axis Ca of the opening 91a is preferably within 0.2 μm. In this case, the second electric field relaxation region 16b that protrudes substantially evenly in the width direction of the gate trench 5 from the first electric field relaxation region 16a can be formed. The opening 92a preferably extends along the [11-20] direction of the silicon carbide substrate 10, similar to the opening 91a. The second mask 92 is composed of, for example, a material different from that of the first mask 91. In this case, etching of the opening 91a of the first mask 91 can be suppressed when forming the opening 92a in the second mask 92. Therefore, two openings 91a and 92a with different opening widths can be easily formed. The second mask 92 may be, for example, a resist mask.

[0055] Next, as shown in FIG. 5, channeling implantation into the silicon carbide epitaxial layer 40 is performed using the first mask 91 and the second mask 92. By the channeling implantation, the first electric field relaxation region 16a and an implantation region for the second electric field relaxation region 16b are formed. A part of the remainder of the silicon carbide epitaxial layer 40 functions as the drift region 11. In the channeling implantation, a p-type impurity such as aluminum is implanted, for example. In the channeling implantation, the acceleration voltage is, for example, 750 keV or more and 950 keV or less, and the dose amount is, for example, 1.0×10 13 / cm 2 or more and 2.0×10 14 / cm 2 or less.

[0056] In channeling implantation, ions are implanted into the silicon carbide epitaxial layer 40 without colliding with the crystal atoms of the material constituting the first mask 91 directly below the opening 91a. As a result, ions are implanted to a deep position in the silicon carbide epitaxial layer 40 directly below the opening 91a. As a result, a first electric field relaxation region 16a, which is a first implantation region having a long length in a direction perpendicular to the first main surface 1, is formed in the silicon carbide epitaxial layer 40 located directly below the opening 91a. On the other hand, on the side directly below the opening 91a, ions are scattered by the crystal atoms of the material constituting the first mask 91 and implanted into the silicon carbide epitaxial layer 40. As a result, ions are not implanted to a deep position in the silicon carbide epitaxial layer 40 on the side directly below the opening 91a, and ions are implanted to a shallow position. As a result, a second implantation region having a short length in a direction perpendicular to the first main surface 1 is formed in the silicon carbide epitaxial layer 40 located on the side directly below the opening 91a. A part of the second implantation region constitutes a second electric field relaxation region 16b. The amount of ions per unit depth implanted into the first implantation region is substantially the same as the amount of ions per unit depth implanted into the second implantation region. Therefore, the effective concentration of p-type impurities in the first electric field relaxation region 16a is lower than the effective concentration of p-type impurities in the second electric field relaxation region 16b.

[0057] Next, as shown in FIG. 6, the first mask 91 and the second mask 92 are removed.

[0058] Next, as shown in FIG. 7, ion implantation is performed to form a current diffusion region 14 in the silicon carbide epitaxial layer 40. In the ion implantation, for example, an n-type impurity such as phosphorus is implanted. In the ion implantation, the acceleration voltage is, for example, 400 keV or more and 900 keV or less, and the dose amount is, for example, 2.0×10 13 / cm 2 or more and 1.0×10 14 / cm 2The following is the case. In ion implantation, a first current diffusion region 14a is formed on a first electric field relaxation region 16a, and a second current diffusion region 14b is formed on the side of the first current diffusion region 14a. The first current diffusion region 14a is formed by implanting n-type impurities into a part of an n-type silicon carbide epitaxial layer 40. The second current diffusion region 14b is formed by implanting n-type impurities into a part of a second implantation region having a p-type. Therefore, the effective concentration of the n-type impurities in the first current diffusion region 14a becomes higher than the effective concentration of the n-type impurities in the second current diffusion region 14b.

[0059] Next, as shown in FIG. 8, ion implantation is performed to form a first body region 12a and a second body region 12b in the silicon carbide epitaxial layer 40. In the ion implantation, p-type impurities such as aluminum are implanted. In the ion implantation, the acceleration voltage is, for example, 150 keV or more and 600 keV or less, and the dose amount is, for example, 1.0×10 13 / cm 2 or more and 1.0×10 14 / cm 2 or less. In the ion implantation, the first body region 12a is formed on the first current diffusion region 14a, and the second body region 12b is formed on the second current diffusion region 14b. The first body region 12a is formed by implanting p-type impurities into a part of an n-type silicon carbide epitaxial layer 40. The second body region 12b is formed by implanting p-type impurities into a part of a second implantation region having a p-type. Therefore, the effective concentration of the p-type impurities in the first body region 12a becomes lower than the effective concentration of the p-type impurities in the second body region 12b.

[0060] Next, as shown in FIG. 9, ion implantation is performed to form a source region 13 and a contact region 18 in the silicon carbide epitaxial layer 40. In the ion implantation for forming the source region 13, n-type impurities such as phosphorus are implanted. In the ion implantation for forming the source region 13, the acceleration voltage is, for example, 50 keV or more and 250 keV or less, and the dose amount is, for example, 1.0×10 14 / cm 2 or more and 1.5×1015 / cm 2 The following is the case. In the ion implantation for forming the contact region 18, for example, p-type impurities such as aluminum are implanted. In the ion implantation for forming the contact region 18, the acceleration voltage is, for example, 50 keV or more and 300 keV or less, and the dose amount is, for example, 1.0×10 15 / cm 2 or more and 6.5×10 15 / cm 2 or less.

[0061] Next, as shown in FIG. 10, a gate trench 5 is formed in the source region 13, the first body region 12a, and the first current diffusion region 14a. The gate trench 5 can be formed as follows.

[0062] First, a mask (not shown) having an opening is formed on the region where the gate trench 5 is to be formed. Next, using the mask, a part of the source region 13, a part of the first body region 12a, and a part of the first current diffusion region 14a are removed by etching. By etching, a recess having a side portion substantially perpendicular to the first main surface 1 and a bottom portion continuously provided with the side portion and substantially parallel to the first main surface 1 is formed in the region where the gate trench 5 is to be formed.

[0063] Next, thermal etching is performed in the recess. The thermal etching can be performed by heating in an atmosphere containing a reactive gas having, for example, at least one or more halogen atoms with a mask formed on the first main surface 1. The at least one or more halogen atoms include at least either a chlorine (Cl) atom or a fluorine (F) atom. The atmosphere contains, for example, chlorine (Cl2), boron trichloride (BCl3), sulfur hexafluoride (SF6), or carbon tetrafluoride (CF4). For example, a mixed gas of chlorine gas and oxygen (O2) gas is used as the reactive gas, and the heat treatment temperature is 800°C or more and 900°C or less, and the thermal etching is performed. Note that the reactive gas may contain a carrier gas in addition to the above-described chlorine gas and oxygen gas. As the carrier gas, for example, nitrogen (N2) gas, argon (Ar) gas, or helium (He) gas can be used.

[0064] By the above-mentioned thermal etching, a gate trench 5 is formed on the first main surface 1. The gate trench 5 has a bottom surface 4 formed by the upper end surface of the first electric field relaxation region 16a, and a side surface 3 that penetrates the source region 13, the first body region 12a, and the first current diffusion region 14a and is continuous with the bottom surface 4. After the thermal etching, the mask is removed from the first main surface 1.

[0065] Next, as shown in FIG. 11, a gate insulating film 81 is formed. For example, by thermally oxidizing the silicon carbide substrate 10, a gate insulating film 81 in contact with the source region 13, the first body region 12a, the first current diffusion region 14a, the first electric field relaxation region 16a, and the contact region 18 is formed. Specifically, the silicon carbide substrate 10 is heated in an atmosphere containing oxygen at a temperature of, for example, 1300°C or higher and 1400°C or lower. Thereby, a gate insulating film 81 in contact with the first main surface 1, the side surface 3, and the bottom surface 4 is formed. When the gate insulating film 81 is formed by thermal oxidation, strictly speaking, a part of the silicon carbide substrate 10 is incorporated into the gate insulating film 81. Therefore, in subsequent processes, it is assumed that the first main surface 1, the side surface 3, and the bottom surface 4 have slightly moved at the interface between the thermally oxidized gate insulating film 81 and the silicon carbide substrate 10.

[0066] Next, a heat treatment (NO annealing) may be performed on the silicon carbide substrate 10 in a nitrogen monoxide (NO) gas atmosphere. In the NO annealing, the silicon carbide substrate 10 is held for about 1 hour under conditions of, for example, 1100°C or higher and 1400°C or lower. As a result, nitrogen atoms are introduced into the interface region between the gate insulating film 81 and the second body region 12b. As a result, the formation of interface levels in the interface region is suppressed, and the channel mobility can be improved.

[0067] Next, as shown in FIG. 12, a gate electrode 82 is formed. The gate electrode 82 is formed on the gate insulating film 81. The gate electrode 82 is formed, for example, by a low pressure - chemical vapor deposition (LP-CVD) method. The gate electrode 82 is formed so as to face each of the source region 13, the first body region 12a, the first current diffusion region 14a, and the first electric field relaxation region 16a.

[0068] Next, as shown in FIG. 13, an interlayer insulating film 83 is formed. Specifically, the interlayer insulating film 83 is formed so as to cover the gate electrode 82 and be in contact with the gate insulating film 81. The interlayer insulating film 83 is formed, for example, by a CVD method. The interlayer insulating film 83 is composed of a material containing, for example, silicon dioxide. A part of the interlayer insulating film 83 may be formed inside the gate trench 5.

[0069] Next, as shown in FIG. 14, by etching the interlayer insulating film 83 and the gate insulating film 81, contact holes 90 are formed in the interlayer insulating film 83 and the gate insulating film 81. As a result, the source region 13 and the contact region 18 are exposed from the interlayer insulating film 83 and the gate insulating film 81. Next, a metal film (not shown) for the contact electrode 61 that contacts the source region 13 and the contact region 18 on the first main surface 1 is formed. The metal film for the contact electrode 61 is formed, for example, by a sputtering method. The metal film for the contact electrode 61 is composed of a material containing, for example, nickel. Next, a metal film (not shown) for the drain electrode 70 that contacts the silicon carbide single crystal substrate 50 on the second main surface 2 is formed. The metal film for the drain electrode 70 is formed, for example, by a sputtering method. The metal film for the drain electrode 70 is composed of a material containing, for example, nickel. Next, alloying annealing is performed. The metal film for the contact electrode 61 and the metal film for the drain electrode 70 are held at a temperature of, for example, 900 ° C or higher and 1100 ° C or lower for about 5 minutes. As a result, at least a part of the metal film for the contact electrode 61 and at least a part of the metal film for the drain electrode 70 react with the silicon contained in the silicon carbide substrate 10 to form silicide. Thereby, a contact electrode 61 that forms an ohmic contact with the source region 13 and the contact region 18 and a drain electrode 70 that forms an ohmic contact with the silicon carbide single crystal substrate 50 are formed. The contact electrode 61 may be composed of a material containing titanium, aluminum, and silicon. The drain electrode 70 may be composed of a material containing titanium, aluminum, and silicon.

[0070] Next, as shown in FIG. 15, a source wiring 62 is formed. Specifically, a source wiring 62 that covers the contact electrode 61 and the interlayer insulating film 83 is formed. The source wiring 62 is formed, for example, by a sputtering method. The source wiring 62 is composed of a material containing, for example, aluminum or copper. The source wiring 62 may be composed of a material containing aluminum and copper. In this way, a source electrode 60 having the contact electrode 61 and the source wiring 62 is formed.

[0071] In this way, the silicon carbide semiconductor device 100 including the field effect transistor can be manufactured.

[0072] According to the manufacturing method of the silicon carbide semiconductor device 100 according to the embodiment described above, the electric field relaxation region 16 can be formed between the bottom surface 4 of the gate trench 5 and the second main surface 2. Further, when viewed in plan from a direction perpendicular to the first main surface 1, the gate trench 5 can be hidden by the electric field relaxation region 16. Thereby, the electric field concentration in the vicinity of the bottom surface 4 of the gate trench 5 can be alleviated, and the dielectric breakdown of the gate insulating film 81 can be suppressed.

[0073] Also, ions are implanted into the silicon carbide epitaxial layer 40 without colliding with the crystal atoms of the material constituting the first mask 91 directly below the opening 91a. As a result, ions are implanted to a deep position of the silicon carbide epitaxial layer 40 directly below the opening 91a. As a result, the first electric field relaxation region 16a can be formed in the silicon carbide epitaxial layer 40 located directly below the opening 91a. Also, ions are scattered by the crystal atoms of the material constituting the first mask 91 and implanted into the silicon carbide epitaxial layer 40 on the side directly below the opening 91a. As a result, ions are not implanted to a deep position of the silicon carbide epitaxial layer 40 on the side directly below the opening 91a, and ions are implanted to a shallow position. As a result, the second electric field relaxation region 16b can be formed in the silicon carbide epitaxial layer 40 located on the side directly below the opening 91a. Since the second electric field relaxation region 16b protruding in the width direction of the gate trench 5 from the first electric field relaxation region 16a is provided, the electric field concentration in the vicinity of the bottom surface 4 of the gate trench 5 can be further alleviated.

[0074] Note that instead of the stacked mask of the first mask 91 and the second mask 92, as shown in FIG. 16, a single third mask 93 may be formed on the silicon carbide epitaxial layer 40. The third mask 93 has an opening 93a. The opening 93a has a varying opening width in the thickness direction. The opening 93a preferably has a constricted barrel-shaped cross-sectional shape such that the width Wc at the central portion in the thickness direction is wider than the widths Wd at the upper and lower portions in the thickness direction. In this case, it is easy to obtain a desired ion implantation profile. The amount of constriction D (=Wc - Wd) of the opening 93a can be controlled by adjusting at least one of the exposure conditions and the development conditions.

[0075] By performing ion implantation on the silicon carbide epitaxial layer 40 using the third mask 93, an electric field relaxation region 16 can be formed between the bottom surface 4 of the gate trench 5 and the second main surface 2. Further, when viewed in plan from a direction perpendicular to the first main surface 1, the gate trench 5 can be hidden by the electric field relaxation region 16. Thereby, the electric field concentration in the vicinity of the bottom surface of the gate trench 5 can be alleviated, and the dielectric breakdown of the gate insulating film 81 can be suppressed.

[0076] Further, since the third mask 93 has the opening 93a with a varying opening width in the thickness direction, similar to the case of having the first mask 91 and the second mask 92, the first electric field relaxation region 16a and the second electric field relaxation region 16b can be formed in the silicon carbide epitaxial layer 40. Thereby, the electric field concentration in the vicinity of the bottom surface 4 of the gate trench 5 can be further alleviated.

[0077] [Modification Example] Next, a modification example of the embodiment will be described. The modification example mainly differs from the embodiment in terms of the shape of the gate trench. FIG. 17 is a cross-sectional view showing a silicon carbide semiconductor device according to a modification example of the embodiment.

[0078] As shown in FIG. 17, in the silicon carbide semiconductor device 200 according to the modified example, the bottom surface 4 of the gate trench 5 is located below the upper end surface of the first electric field relaxation region 16a. The side surface 3 of the gate trench 5 is in contact with the source region 13, the first body region 12a, the first current diffusion region 14a, and the first electric field relaxation region 16a, and is continuous with the bottom surface 4. Other configurations are the same as those in the embodiment.

[0079] Even with such a modified example, the same effects as those in the embodiment can be obtained.

[0080] In the above embodiment, the n-type is described as the first conductivity type and the p-type is described as the second conductivity type. However, the p-type may be the first conductivity type and the n-type may be the second conductivity type.

[0081] Although the embodiments have been described in detail above, the present invention is not limited to the specific embodiments, and various modifications and changes are possible within the scope described in the claims.

Description of Reference Numerals

[0082] 1 First main surface 2 Second main surface 3 Side surface 4 Bottom surface 5 Gate trench 10 Silicon carbide substrate 11 Drift region (a part of the first semiconductor region) 12 Body region 12a First body region 12b Second body region 13 Source region 14 Current diffusion region (a part of the first semiconductor region) 14a First current diffusion region (the second semiconductor region) 14b Second current diffusion region (the third semiconductor region) 16 Electric field relaxation region 16a First electric field relaxation region 16b Second electric field relaxation region 18 Contact region 40 Silicon carbide epitaxial layer 50 Silicon carbide single crystal substrate 60 Source electrode 61 Contact electrode 62 Source wiring 70 Drain electrode 81 Gate insulating film 82 Gate electrode 83 Interlayer insulating film 90 Contact hole 91 First mask 91a Opening 92 Second mask 92a Opening 93 Third mask 93a Opening 100 Silicon carbide semiconductor device 200 Silicon carbide semiconductor device

Claims

1. A silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface, wherein the silicon carbide substrate has a first semiconductor region having a first conductivity type, a body region provided on the first semiconductor region and having a second conductivity type different from the first conductivity type, and a source region provided on the body region so as to be separated from the first semiconductor region and having the first conductivity type, and a gate trench defined by a side surface penetrating the source region and the body region and a bottom surface continuous with the side surface is provided on the first main surface, the silicon carbide substrate further has an electric field relaxation region provided in contact with the bottom surface between the bottom surface and the second main surface and having the second conductivity type, the electric field relaxation region has a second width at a second position in contact with the bottom surface wider than a first width at a first position 1.5 μm away from the bottom surface toward the second main surface side, and the first width is wider than the width of the bottom surface, the electric field relaxation region has a first electric field relaxation region in contact with the bottom surface and having the first width, and a second electric field relaxation region protruding from the first electric field relaxation region in the width direction of the gate trench, and an effective concentration of impurities of the second conductivity type in the first electric field relaxation region is lower than an effective concentration of impurities of the second conductivity type in the second electric field relaxation region, the first semiconductor region has a second semiconductor region located on the first electric field relaxation region, and a third semiconductor region located on the second electric field relaxation region, and an effective concentration of impurities of the first conductivity type in the second semiconductor region is higher than an effective concentration of impurities of the first conductivity type in the third semiconductor region, a silicon carbide semiconductor device.

2. A difference between a length in a direction perpendicular to the first main surface in the first electric field relaxation region and a length in a direction perpendicular to the first main surface in the second electric field relaxation region is 3 times or more and 15 times or less the length in a direction perpendicular to the first main surface in the second electric field relaxation region, The silicon carbide semiconductor device according to Claim 1.

3. The body region has a first body region located on the second semiconductor region, and a second body region located on the third semiconductor region, and an effective concentration of impurities of the second conductivity type in the first body region is lower than an effective concentration of impurities of the second conductivity type in the second body region, The silicon carbide semiconductor device according to Claim 1 or Claim 2.

4. The first semiconductor region a drift region, a current diffusion region located between the drift region and the body region, and having the effective concentration of the impurity of the first conductivity type in the current diffusion region is higher than the effective concentration of the impurity of the first conductivity type in the drift region, the side surface of the gate trench reaches the current diffusion region, The silicon carbide semiconductor device according to any one of claims 1 to 3.

5. a step of preparing a silicon carbide substrate having a first main surface, a second main surface opposite to the first main surface, and a first semiconductor region having a first conductivity type; a step of forming a first mask on the first main surface; a step of forming a second mask on the first mask; a step of forming an electric field relaxation region having a second conductivity type different from the first conductivity type by performing ion implantation on the silicon carbide substrate using the first mask and the second mask; and having the first mask has a first opening, the second mask is positioned so as to overlap the first opening when viewed from a direction perpendicular to the first main surface, and has a second opening having a wider opening width than the first opening, the first opening and the second opening extend along the [11-20] direction of the silicon carbide substrate, A method for manufacturing a silicon carbide semiconductor device.

6. the first mask is formed of polysilicon or silicon oxide, the second mask is formed of a resist, The method for manufacturing a silicon carbide semiconductor device according to claim 5.

7. the opening width of the first opening is narrower than the opening width of the second opening, the difference between the opening width of the first opening and the opening width of the second opening is 0.2 μm or more and 1.0 μm or less, The method for manufacturing a silicon carbide semiconductor device according to claim 5 or claim 6.

8. the amount of displacement between the center in the width direction of the first opening and the center in the width direction of the second opening is within 0.2 μm, The method for manufacturing a silicon carbide semiconductor device according to any one of claims 5 to 7.

9. a step of preparing a silicon carbide substrate having a first main surface, a second main surface opposite to the first main surface, and a first semiconductor region having a first conductivity type; a step of forming a third mask formed of a resist on the first main surface; a step of forming an electric field relaxation region having a second conductivity type different from the first conductivity type by performing ion implantation on the silicon carbide substrate using the third mask; and having The third mask has a third opening whose opening width changes in the thickness direction. A method for manufacturing a silicon carbide semiconductor device. Claim 10 The third opening has a barrel-shaped cross-sectional shape in the width direction. The method for manufacturing a silicon carbide semiconductor device according to claim 9.

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