Semiconductor device, method of manufacturing the semiconductor device, and electronic device

Abstract

To prevent a semiconductor device from deteriorating in performance due to a short circuit between a semiconductor layer and an electrode.SOLUTION: A semiconductor device 1 includes a protective film 70 provided in a manner to cover the opposite side of a semiconductor layer 20 provided on the side of a surface 10a of a substrate 10, from the substrate 10. An insulation film which contains Si is used as the protective film 70. The protective film 70 has an opening part 71. A gate electrode 30 is provided on the opening part 71 of the protective film 70 and the side of a side face 20a which faces in a direction D1 of the semiconductor layer 20. An insulation film 80 which contains a metal element is provided between a side face 20a of the semiconductor layer 20 and the gate electrode 30 provided on the side of the side face 20a. The side face 20a of the semiconductor layer 20 is prevented by the insulation film 80 from being exposed to gas when the opening part 71 of the protective film 70 is formed by dry etching, and also prevented from coming into contact and short-circuit with the gate electrode 30. Consequently, performance deterioration of the semiconductor device 1 due to a leak current is suppressed.SELECTED DRAWING: Figure 5

Description

Technical Field

[0001] The present invention relates to a semiconductor device, a method for manufacturing a semiconductor device, and an electronic device.

Background Art

[0002] There is known a heterojunction field effect transistor in which elements having a heteroepitaxial structure in which a wide bandgap semiconductor layer, a narrow bandgap semiconductor layer, and a wide bandgap semiconductor layer are sequentially stacked on a substrate are removed by etching and electrically separated. Regarding such a heterojunction field effect transistor, there is known a technique in which the narrow bandgap semiconductor layer exposed on the etching end face is selectively etched and retracted to spatially separate it from the gate electrode provided at the element isolation etching step portion. Further, after retracting the narrow bandgap semiconductor layer exposed on the etching end face, an insulating film such as SiO2 (silicon oxide) is deposited, and the gate electrode and the narrow bandgap semiconductor layer are separated by a space separated by the insulating film.

[0003] Further, there is known a field effect semiconductor device in which a semiconductor layer including a channel layer on a substrate is etched to form an element isolation region, the channel layer exposed on the side surface thereof is etched to form an air gap, and a gate electrode is formed from above the semiconductor layer across the air gap.

[0004] Further, there is known a mesa-type semiconductor device in which an electrode that contacts the uppermost semiconductor layer of a mesa having an inverted taper shape at its end and is provided so as not to float from the uppermost semiconductor layer faces an active semiconductor layer that is directly involved in element operation at the side portion of the mesa with a gap. Regarding such a mesa-type semiconductor device, there are known techniques in which the gap between the electrode and the active semiconductor layer is an air gap and a technique in which the gap is filled with SiO2 which is a dielectric.

[0005] In addition, a compound field effect semiconductor device is known in which an insulating oxide film is formed on the sidewalls of a laminated and mesa-shaped compound semiconductor layer. Regarding such a compound field effect semiconductor device, techniques for forming an insulating oxide film on the sidewalls of the compound semiconductor layer by a liquid phase oxidation method or by using a combination of the liquid phase oxidation method and a steam oxidation method, and techniques for suppressing contact between a metal gate and the compound semiconductor layer by the insulating oxide film are known.

Prior Art Documents

Patent Documents

[0006]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Summary of the Invention

Problems to be Solved by the Invention

[0007] By the way, in a semiconductor device in which a semiconductor element such as a transistor is realized using a semiconductor layer provided on a substrate, the semiconductor layer may be covered with a protective film. As the protective film, Si-based insulating films containing Si (silicon), such as SiO2 and SiN (silicon nitride), are widely used.

[0008] In a semiconductor device provided with such a protective film, the protective film covering the semiconductor layer may be etched to form an opening for providing an electrode connected to a gate or the like of a semiconductor element. At this time, if the protective film is not formed on the side surface of the semiconductor layer (the side surface facing in a direction parallel to the surface of the substrate on which the semiconductor layer is provided), or if it is formed on the side surface of the semiconductor layer but is removed from the side surface of the semiconductor layer by subsequent etching, the side surface of the semiconductor layer will be exposed. If the electrode provided in the opening of the protective film is provided so as to contact the exposed side surface of the semiconductor layer, a short circuit may occur between the semiconductor layer and the electrode, and the performance of the semiconductor device may deteriorate.

[0009] On one aspect, an object of the present invention is to realize a semiconductor device capable of suppressing a performance degradation caused by a short circuit between a semiconductor layer and an electrode.

Means for Solving the Problems

[0010] In one aspect, a semiconductor device is provided, which includes a substrate, a semiconductor layer provided on a first surface side of the substrate, a first insulating film provided so as to cover the side of the semiconductor layer opposite to the substrate, having an opening and containing Si, an opening of the first insulating film, an electrode provided on a second surface side of the semiconductor layer facing in a first direction parallel to the first surface of the substrate, and a second insulating film provided between the second surface of the semiconductor layer and the electrode provided on the second surface side and containing a metal element.

[0011] Also, in another aspect, a method for manufacturing a semiconductor device as described above and an electronic device including the semiconductor device as described above are provided.

Effects of the Invention

[0012] On one aspect, it becomes possible to realize a semiconductor device capable of suppressing a performance degradation caused by a short circuit between a semiconductor layer and an electrode.

Brief Description of the Drawings

[0013]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

Figure 15

Figure 16

Figure 17

Figure 18

Figure 19

Figure 20

Figure 21

Figure 22

Figure 23

Embodiments for Carrying Out the Invention

[0014] As one type of field-effect semiconductor device using a compound semiconductor material, a High Electron Mobility Transistor (HEMT) is known. Such a field-effect semiconductor device has excellent low-noise characteristics and is used in amplifiers used in frequency bands such as microwaves and millimeter waves, signal processing circuits in optical communications, and the like. Among field-effect semiconductor devices using a compound semiconductor material, for example, an InP-based HEMT using an InP (indium phosphide) - based material is excellent in high-speed operability and has low noise, and thus is suitable for the above-described amplifiers, signal processing circuits, and the like.

[0015] In the case of InP-based HEMTs, when performing element isolation, it is difficult to form an insulating region by ion implantation. Therefore, in InP-based HEMTs, after forming a semiconductor layer including a channel layer, a carrier supply layer, etc. on a substrate, element isolation is performed by mesa-forming the semiconductor layer. When element isolation is performed by mesa-forming the semiconductor layer, the side surfaces of the semiconductor layer formed on the substrate are exposed on the side surfaces of the obtained mesa. In InP-based HEMTs, a structure is adopted in which a gate electrode is provided so as to extend from above the mesa-formed semiconductor layer to its side surface. However, in this case, if the gate electrode contacts the side surface of the channel layer included in the semiconductor layer, a short circuit may be caused. Therefore, for example, the channel layer included in the semiconductor layer is selectively side-etched with respect to other layers, the side surface of the channel layer is retracted from the side surface of other layers, and a space called an air gap is provided between the gate electrode provided on the side surface of the mesa and the channel layer, and in some cases, their contact is suppressed.

[0016] By the way, before forming the gate electrode of such an InP-based HEMT, a Si-based insulating film such as SiN may be formed as a protective film (also referred to as a passivation film) so as to cover the semiconductor layer on which element isolation and side-etching have been performed.

[0017] Here, an example of a semiconductor device that employs element isolation by mesa-forming, side-etching of a channel layer, and formation of a protective film of a Si-based insulating film, such as the above InP-based HEMT, will be described with reference to FIGS. 1 to 4.

[0018] FIG. 1 is a diagram for explaining an example of a semiconductor device. FIG. 1 schematically shows a plan view of a main part of an example of a semiconductor device. The semiconductor device 100 shown in FIG. 1 has a substrate 110, a semiconductor layer 120, a gate electrode 130, a source electrode 140, a drain electrode 150, and a protective film 170. The semiconductor layer 120 is formed on the substrate 110. The semiconductor layer 120 includes, as will be described later, a channel layer, a carrier supply layer, and the like. The semiconductor layer 120 is defined by an element isolation region 160 formed by mesa etching, and element isolation is performed. The semiconductor layer 120 has its side surface of the channel layer recessed from the side surfaces of other layers by side etching, as will be described later. Separate source electrode 140 and drain electrode 150 are provided on the semiconductor layer 120 subjected to element isolation and side etching. A protective film 170 of an Si-based insulating film is provided so as to cover the semiconductor layer 120 and the source electrode 140 and drain electrode 150 provided thereon. A gate electrode 130 is provided between the source electrode 140 and the drain electrode 150 on the semiconductor layer 120, separated from them. The gate electrode 130 is provided so as to penetrate the protective film 170 and, for example, is in contact with the semiconductor layer 120. The gate electrode 130 is provided so as to extend from above the semiconductor layer 120 to its side surface 120a (or the element isolation region 160).

[0019] FIGS. 2 to 4 are diagrams for explaining an example of a manufacturing process of a semiconductor device. FIG. 2 schematically shows a cross-sectional view of a main part of an example of a protective film forming process. FIG. 3 schematically shows a cross-sectional view of a main part of an example of an opening forming process. FIG. 4 schematically shows a cross-sectional view of a main part of an example of a gate electrode forming process. In FIGS. 2 to 4, FIGS. 2(A), 3(A), and 4(A) schematically show cross-sectional views corresponding to the positions along the line L1-L1 in FIG. 1. In FIGS. 2 to 4, FIGS. 2(B), 3(B), 4(B), and 4(C) schematically show cross-sectional views corresponding to the positions along the line L2-L2 in FIG. 1. FIG. 2(B) schematically shows a cross-sectional view taken along the line II-II in FIG. 2(A). FIG. 3(B) schematically shows a cross-sectional view taken along the line III-III in FIG. 3(A). FIGS. 4(B) and 4(C) schematically show cross-sectional views taken along the line IV-IV in FIG. 4(A).

[0020] In the manufacture of the semiconductor device 100 (Fig. 1), first, as shown in Figs. 2(A) and 2(B), a semiconductor layer 120 is formed on a substrate 110. For example, a semiconductor layer 120 in which a channel layer 121, a carrier supply layer 122, an etching stop layer 123, and a cap layer 124 are sequentially laminated is formed on the substrate 110. A two-dimensional carrier gas 128 is generated near the interface of the channel layer 121 with the carrier supply layer 122. The semiconductor layer 120 formed on the substrate 110 is mesa-shaped by etching, and element isolation is performed. Thereby, a semiconductor layer 120 defined by an element isolation region 160 as shown in Fig. 2(B) is formed.

[0021] The formation of the element isolation region 160 is performed, for example, as follows. A resist mask (not shown) with an opening in the region where the element isolation region 160 is to be formed is formed on the cap layer 124. For example, a mixed solution of phosphoric acid and hydrogen peroxide water is used, and the cap layer 124 is etched. This etching stops at the surface of the etching stop layer 123. Next, for example, hydrochloric acid is used, and the etching stop layer 123 is etched. This etching stops at the surface of the carrier supply layer 122. Thereafter, for example, a mixed solution of phosphoric acid and hydrogen peroxide water is used, and the carrier supply layer 122 and the channel layer 121 are etched. In this way, the element isolation region 160 is formed. After the formation of the element isolation region 160, the resist mask is removed. By forming the element isolation region 160 by such etching, as shown in Fig. 2(B), the etching stop layer 123 and the carrier supply layer 122 protrude outward from the channel layer 121. On the side surface 120a of the semiconductor layer 120, a protecting portion 190 of the etching stop layer 123 and the carrier supply layer 122 that protrudes outward from the channel layer 121 is formed.

[0022] After the formation of the element isolation region 160, a source electrode 140 and a drain electrode 150 are formed on the cap layer 124 of the semiconductor layer 120. Thereafter, etching is performed on the cap layer 124 between the source electrode 140 and the drain electrode 150, and a recess 124a leading to the etching stop layer 123 is formed in the cap layer 124. After the formation of the recess 124a, a protective film 170 such as SiN is formed so as to cover the semiconductor layer 120 and the source electrode 140 and the drain electrode 150 formed thereon.

[0023] Through such a process, a structure as shown in FIGS. 2(A) and 2(B) is obtained. Next, as shown in FIGS. 3(A) and 3(B), an opening 171 leading to the semiconductor layer 120 (etching stop layer 123 in the recess 124a) is formed in the region of the protective film 170 where the gate electrode 130 is to be formed. For the formation of the opening 171, for example, a lithography technique and a dry etching technique using a fluorine-based gas are used.

[0024] When the opening 171 is formed, if the protective film 170 formed on the side surface 120a of the semiconductor layer 120 is not covered or is not sufficiently covered with a resist mask (not shown), as shown in FIG. 3(B), the protective film 170 on the side surface 120a may be removed. When the protective film 170 on the side surface 120a is removed, the side surface 120a is exposed, and the etching stop layer 123 and the carrier supply layer 122 (their eaves 190) shaped to protrude outside the channel layer 121 are exposed.

[0025] Here, the etching stop layer 123 is formed thinner than the channel layer 121 in order to keep the distance between the channel layer 121 via the etching stop layer 123 and the carrier supply layer 122 and the gate electrode 130 to be described later at a predetermined distance. Therefore, when the relatively thin etching stop layer 123 exposed by the removal of the protective film 170 is further exposed to the fluorine-based gas for dry etching even after the removal of the protective film 170, the etching stop layer 123 may disappear. Then, when the carrier supply layer 122 exposed due to the disappearance of the etching stop layer 123 is further exposed to the fluorine-based gas and disappears, as indicated by the arrow and the dotted line in FIG. 3(B), the overhanging eaves portion 190 may disappear. Note that the influence due to the disappearance of such an eaves portion 190 will be described later.

[0026] After the formation of the opening 171 by dry etching, for example, as shown in FIGS. 4(A) and 4(B), the gate electrode 130 is formed. The gate electrode 130 is formed on the semiconductor layer 120 (etching stop layer 123 in the recess 124a) in the opening 171 and extends from the upper surface of the semiconductor layer 120 to its side surface 120a and is formed up to the element isolation region 160. When such a gate electrode 130 is formed, for example, a semiconductor device 100 as shown in FIGS. 4(A) and 4(B) is manufactured.

[0027] Here, consider a case where in the formation of the opening 171 (FIG. 3) performed prior to the formation of the gate electrode 130, the protective film 170 on the side surface 120a of the semiconductor layer 120 is removed and the eaves portion 190 of the etching stop layer 123 and the carrier supply layer 122 remains on the exposed side surface 120a. After the formation of the opening 171, if such an eaves portion 190 remains as shown in FIG. 4(B), a space 180 is formed between the channel layer 121 and the gate electrode 130. By forming the space 180, the contact between the channel layer 121 and the gate electrode 130 is suppressed, and a short circuit therebetween, that is, a short circuit between the two-dimensional carrier gas 128 generated in the channel layer 121 and the gate electrode 130 is suppressed.

[0028] On the other hand, in the formation of the opening 171 (FIG. 3) performed prior to the formation of the gate electrode 130, consider a case where the protective film 170 on the side surface 120a of the semiconductor layer 120 is removed and the shielding portions 190 of the etching stop layer 123 and the carrier supply layer 122 on the exposed side surface 120a disappear (arrows and dotted lines in FIG. 3(B)). After the formation of the opening 171, if the shielding portion 190 has disappeared in this way, for example, a state as shown in FIG. 4(C) may occur. That is, the above-described space 180 may not be formed between the channel layer 121 and the gate electrode 130, and the channel layer 121 and the gate electrode 130 may come into contact with each other, and they may short-circuit. Further, even when the shielding portion 190 remains on the side surface 120a of the semiconductor layer 120 exposed from the protective film 170, depending on the degree of overhang of the remaining shielding portion 190, a sufficient space 180 may not be formed between the shielding portion 190 and the gate electrode 130. As a result, similarly, contact between the channel layer 121 and the gate electrode 130 and short-circuiting due to this may occur.

[0029] For example, as shown in FIG. 4(C), when contact between the channel layer 121 and the gate electrode 130 exposed on the side surface 120a of the semiconductor layer 120 and short-circuiting due to this occur, the performance of the semiconductor device 100 may deteriorate. For example, when the channel layer 121 and the gate electrode 130 exposed on the side surface 120a of the semiconductor layer 120 short-circuit, a leakage current may occur, and there is a risk of a pinch-off defect in which the transistor does not turn off sufficiently.

[0030] Furthermore, in order to suppress the disappearance of the eaves portion 190 during the formation of the opening 171 as described above, it is conceivable to thicken the etching stop layer 123 out of the etching stop layer 123 and the carrier supply layer 122, thereby thickening the eaves portion 190. If the etching stop layer 123 is thickened, the disappearance of the etching stop layer 123 of the eaves portion 190 during the formation of the opening 171 and the resulting disappearance of the carrier supply layer 122 can be suppressed. However, when the etching stop layer 123 is thickened in this way, the distance between the channel layer 121 and the gate electrode 130 through the etching stop layer 123 and the carrier supply layer 122 increases, and the strength of the electric field applied from the gate electrode 130 to the channel layer 121 weakens. Therefore, there is a risk that the high-frequency characteristics of the semiconductor device 100 will deteriorate.

[0031] Here, an example is shown in which the protective film 170 formed on the side surface 120a of the semiconductor layer 120 is removed from the side surface 120a during the formation of the opening 171 by dry etching, and the eaves portion 190 disappears, resulting in contact and short circuit between the channel layer 121 and the gate electrode 130. In addition, even when the protective film 170 is used, the same thing can happen when a process of not originally forming the protective film 170 on the side surface 120a of the semiconductor layer 120 is adopted. That is, when the eaves portion 190 disappears due to being exposed to the dry etching during the formation of the opening 171, contact between the channel layer 121 and the gate electrode 130 and the resulting short circuit can occur.

[0032] Furthermore, for the dry etching of the protective film 170, an etching gas other than a fluorine-based gas can be used. Even when an etching gas other than a fluorine-based gas is used, the side surface 120a of the exposed semiconductor layer 120 is exposed to the etching gas, and the same thing can happen as when the fluorine-based gas is used.

[0033] In view of the above points, here, a semiconductor device capable of suppressing performance degradation caused by a short circuit between a semiconductor layer and an electrode is realized by using a method as shown below as an embodiment. [First Embodiment] FIG. 5 is a diagram for explaining an example of a semiconductor device according to the first embodiment. FIGS. 5(A) to 5(C) schematically show cross-sectional views of main parts of an example of the semiconductor device. FIG. 5(B) schematically shows a first example of the V-V cross-sectional view of FIG. 5(A). FIG. 5(C) schematically shows a second example of the V-V cross-sectional view of FIG. 5(A).

[0034] For example, as shown in FIG. 5(A), the semiconductor device 1 includes a substrate 10, a semiconductor layer 20, a gate electrode 30, a source electrode 40, a drain electrode 50, a protective film 70, and an insulating film 80. The semiconductor device 1 is an example of a HEMT.

[0035] A compound semiconductor substrate is used for the substrate 10. For example, an InP substrate is used for the substrate 10. The substrate 10 may be one in which a compound semiconductor layer such as a buffer layer is provided on a compound semiconductor substrate serving as a base substrate. For example, the substrate 10 may be one in which InAlAs (indium aluminum arsenide) is provided as a buffer layer on an InP substrate.

[0036] As shown in FIG. 5(A), the semiconductor layer 20 is provided on one surface 10a (also referred to as the first surface) of the substrate 10. The semiconductor layer 20 has a structure in which a channel layer 21 and a carrier supply layer 22 (layers including these are also referred to as the first layer), an etching stop layer 23 (this layer is also referred to as the second layer), and a cap layer 24 are sequentially stacked from the surface 10a side of the substrate 10. A compound semiconductor material is used for the channel layer 21, the carrier supply layer 22, the etching stop layer 23, and the cap layer 24. For example, InGaAs (indium gallium arsenide) is used for the channel layer 21. For example, InAlAs is used for the carrier supply layer 22. For example, InP or InGaP (indium gallium phosphide) is used for the etching stop layer 23. For example, InGaAs is used for the cap layer 24. A recess 24a communicating with the etching stop layer 23 is provided in the cap layer 24. A two-dimensional carrier gas 28 is generated near the interface of the channel layer 21 with the carrier supply layer 22.

[0037] As shown in FIG. 5(A), the source electrode 40 and the drain electrode 50 are provided on the cap layer 24 (on the side of the semiconductor layer 20 opposite to the substrate 10). The source electrode 40 and the drain electrode 50 are provided separately from each other at positions facing each other with the recess 24a of the cap layer 24 interposed therebetween. For the source electrode 40 and the drain electrode 50, a metal material such as Ti (titanium), Pt (platinum), or Au (gold) is used. The source electrode 40 and the drain electrode 50 are provided so as to function as ohmic electrodes.

[0038] As shown in FIG. 5(A), the protective film 70 (also referred to as the first insulating film) is provided so as to cover the side of the semiconductor layer 20 opposite to the substrate 10. The protective film 70 is provided so as to cover the cap layer 24, the etching stop layer 23 in the recess 24a thereof, and the source electrode 40 and the drain electrode 50 on the cap layer 24. For the protective film 70, an insulating film containing Si, that is, a Si-based insulating film, is used. For example, SiN is used for the protective film 70. The protective film 70 is provided with an opening 71 formed so as to be positioned within the recess 24a of the cap layer 24.

[0039] As shown in FIG. 5(A), the gate electrode 30 (also referred to as an electrode) is provided so as to be positioned in the opening 71 of the protective film 70 formed within the recess 24a of the cap layer 24 between the source electrode 40 and the drain electrode 50. The gate electrode 30 is provided separately from the source electrode 40 and the drain electrode 50. For the gate electrode 30, a metal material such as Ti, Pt, or Au is used. The gate electrode 30 is provided, for example, so as to have a T-shaped cross section on the side of the semiconductor layer 20 opposite to the substrate 10.

[0040] As shown in FIG. 5(A), the insulating film 80 (also referred to as the second insulating film) is provided to cover the cap layer 24, the etching stop layer 23 in its recess 24a, the source electrode 40 and the drain electrode 50 on the cap layer 24. The insulating film 80 is provided between the semiconductor layer 20 and the protective film 70 on the side of the semiconductor layer 20 opposite to the substrate 10. The opening 71 of the protective film 70 is formed to communicate with the insulating film 80. The gate electrode 30 provided in the opening 71 of the protective film 70 has its lower end in contact with the insulating film 80. The gate electrode 30 is provided on the semiconductor layer 20 via the insulating film 80.

[0041] For the insulating film 80, an insulating film containing a metal element is used. For example, for the insulating film 80, an oxide film containing Al (aluminum) as a metal element, that is, Al2O3 (aluminum oxide) is used. In the insulating film 80, in addition to Al, as metal elements, Hf (hafnium), Zr (zirconium), Ti, Ta (tantalum), Mg (magnesium), Sc (scandium), Y (yttrium), La (lanthanum), Sr (strontium), etc. may be contained. For example, in the insulating film 80, as a metal element, a metal element with an electronegativity of 1.8 or less is contained. For example, for the insulating film 80, an oxide film, a nitride film, or an oxynitride film containing one or more of Al, Hf, Zr, Ti, Ta, Mg, Sc, Y, La, and Sr is used. For the insulating film 80, a laminated film of two or more of such oxide films, nitride films, and oxynitride films may be used.

[0042] In the semiconductor device 1 having the configuration shown in FIG. 5(A), element isolation is performed on the semiconductor layer 20 by mesa formation. A structural example near the element isolation region 60 formed at the end of the semiconductor layer 20 in the depth direction of the paper surface by mesa formation of the semiconductor layer 20 of the semiconductor device 1 shown in FIG. 5(A) is shown in FIG. 5(B).

[0043] For example, as shown in FIG. 5(B), in a cross-section along the position where the gate electrode 30 is provided, on the side surface 20a of the semiconductor layer 20 in the element isolation region 60, that is, the side surface 20a (also referred to as the second surface) facing in the direction D1 (also referred to as the first direction) parallel to the surface 10a of the substrate 10, side surfaces of the channel layer 21, the carrier supply layer 22, and the etching stop layer 23 are located. For example, the etching stop layer 23 has a shape that protrudes outward beyond the side surface of the carrier supply layer 22 below it, and the carrier supply layer 22 has a shape that protrudes outward beyond the side surface of the channel layer 21 below it. On the upper layer of the channel layer 21, a covering portion 90 of the etching stop layer 23 and the carrier supply layer 22 that protrudes outward beyond its side surface is provided. Note that such a stepped shape of the side surface 20a of the semiconductor layer 20 is realized by etching when forming the element isolation region 60.

[0044] As shown in FIG. 5(A), the insulating film 80 is provided so as to cover the cap layer 24, the etching stop layer 23 in its recess 24a, the source electrode 40, and the drain electrode 50 on the cap layer 24 on the side of the semiconductor layer 20 opposite to the substrate 10. As shown in FIG. 5(B), this insulating film 80 further extends from above the semiconductor layer 20 to its side surface 20a, and on the side surface 20a, it is provided so as to cover the covering portion 90 of the etching stop layer 23 and the carrier supply layer 22 and the channel layer 21. The insulating film 80 provided on the side surface 20a of the semiconductor layer 20 has a greater thickness in the direction D1 at a position lower than the etching stop layer 23 than in the direction D1 at a position above the etching stop layer 23.

[0045] On such an insulating film 80, a protective film 70 having an opening 71 communicating with the insulating film 80 is provided (FIG. 5(A)), and the gate electrode 30 is provided in the opening 71 of the protective film 70. As shown in FIG. 5(B), the gate electrode 30 is provided so as to extend from above the semiconductor layer 20 (in the opening 71 of the protective film 70) to the element isolation region 60 on the side surface 20a side. As shown in FIG. 5(B), the insulating film 80 is provided between the side surface 20a of the semiconductor layer 20 and the gate electrode 30 provided to extend on the side surface 20a side.

[0046] In the manufacture of the semiconductor device 1, for example, an opening 71 is formed in a protective film 70 formed to cover an insulating film 80 provided as shown in FIGS. 5(A) and 5(B) by dry etching using a fluorine-based gas, and then a gate electrode 30 is formed in the opening 71.

[0047] Here, the etching stop layer 23, the eaves portion 90 of the carrier supply layer 22, and the underlying channel layer 21 thereunder are covered with the insulating film 80 and are not exposed. Therefore, the eaves portion 90 and the underlying channel layer 21 thereunder are suppressed from being exposed to the fluorine-based gas when forming the opening 71 in the protective film 70 by dry etching. When the protective film 70 is formed to cover the insulating film 80, the protective film 70 is formed on the side surface 80a facing the direction D1 of the insulating film 80, and even if the protective film 70 on the side surface 80a is removed when forming the opening 71 by dry etching, the same applies. That is, even in such a case, the eaves portion 90 and the underlying channel layer 21 thereunder are covered with the insulating film 80 and are not exposed, so they are suppressed from being exposed to the fluorine-based gas.

[0048] Therefore, disappearance of a part of the side surface 20a of the semiconductor layer 20, for example, the etching stop layer 23 of the eaves portion 90 or both it and the carrier supply layer 22, is suppressed. Further, since the side surface 20a of the semiconductor layer 20 is covered with the insulating film 80, when the gate electrode 30 is formed after forming the opening 71 by dry etching of the protective film 70, contact of the gate electrode 30 with the channel layer 21 on the side surface 20a of the semiconductor layer 20 is suppressed. In the semiconductor device 1, since contact between the gate electrode 30 and the channel layer 21 on the side surface 20a of the semiconductor layer 20 is thus suppressed, a short circuit between them, that is, a short circuit between the two-dimensional carrier gas 28 generated in the channel layer 21 and the gate electrode 30, is suppressed. Thereby, deterioration of the performance of the semiconductor device 1 due to a short circuit between the gate electrode 30 and the channel layer 21 is suppressed.

[0049] When the protective film 70 is formed so as to cover the insulating film 80, when the protective film 70 is formed on the side surface 80a of the insulating film 80, the protective film 70 on the side surface 80a may remain even after the formation of the opening 71 by dry etching. FIG. 5(C) shows an example of a structure of the semiconductor device 1 when the protective film 70 remains on the side surface 80a of the insulating film 80 even after the formation of the opening 71 by dry etching and the gate electrode 30 is formed from that state. The channel layer 21 is separated from the gate electrode 30 by the insulating film 80 covering it and the protective film 70 remaining on its side surface 80a, and contact with the gate electrode 30 and short circuit due to it are suppressed. Even with a structure as shown in FIG. 5(C), that is, a structure in which the protective film 70 remains on the side surface 80a of the insulating film 80, deterioration of the performance of the semiconductor device 1 due to a short circuit between the gate electrode 30 and the channel layer 21 can be suppressed.

[0050] As described above, in the semiconductor device 1, the etching stop layer 23, the shielding portion 90 of the carrier supply layer 22, and the channel layer 21 are covered with the insulating film 80, and are suppressed from being exposed to the fluorine-based gas used for dry etching. Therefore, it is suppressed that the shielding portion 90 disappears due to being exposed to the fluorine-based gas. Since the disappearance of the shielding portion 90 is suppressed, it is not necessary to necessarily make the thickness of the shielding portion 90, that is, the thickness in the direction D2 (also referred to as the second direction) perpendicular to the surface 10a of the substrate 10, thick enough to withstand disappearance by dry etching. For example, the thickness of the etching stop layer 23 can be set to a thickness at which etching can be stopped when forming the recess 24a of the cap layer 24, for example, a thickness of 5 nm or less. When the thickness of the etching stop layer 23 is reduced, it becomes possible to suppress an increase in the distance between the gate electrode 30 and the channel layer 21 via the etching stop layer 23 and the carrier supply layer 22, and it becomes possible to suppress deterioration of the high-frequency characteristics of the semiconductor device 1. In order to suppress an increase in the distance between the gate electrode 30 and the channel layer 21 via the etching stop layer 23 and the carrier supply layer 22, the thickness of the etching stop layer 23 is preferably set to be half or less of the thickness of the channel layer 21 in the direction D2.

[0051] The insulating film 80 of the semiconductor device 1 will be further described. It is desirable that the insulating film 80 has sufficient etching resistance against fluorine-based gases used for dry etching of the protective film 70 before the formation of the gate electrode 30. If the insulating film 80 has sufficient etching resistance, even when the insulating film 80 is exposed to fluorine-based gases in a state where it is not covered by the protective film 70 or in a state where it becomes uncovered as dry etching progresses, disappearance of the insulating film 80 can be suppressed, and the semiconductor layer 20 can be protected from fluorine-based gases.

[0052] From such a viewpoint, in the semiconductor device 1, as the insulating film 80, one containing a metal element with an electronegativity of 1.8 or less is used. For example, as the insulating film 80, one containing one or more of the above-described metal elements such as Al, Hf, Zr, Ti, Ta, Mg, Sc, Y, La, Sr is used. This is because, regarding fluorides generated during dry etching using fluorine-based gases, a metal element with a larger difference from the electronegativity of fluorine, which is 3.98, has a stronger ionic bond, so the boiling point rises and the etching resistance increases.

[0053] As an example, the boiling points of SiF4, AlF3, HfF4, and ZrF4, which are fluorides generated when an insulating film containing each of the elements Si, Al, Hf, and Zr is placed in a dry etching environment using fluorine-based gases, are as follows. The boiling point of SiF4 is -86°C. The boiling point of AlF3 is 1276°C. The boiling point (sublimation temperature) of HfF4 is 970°C. The boiling point (sublimation temperature) of ZrF4 is 912°C. It can be seen that fluorides of Al, Hf, and Zr with an electronegativity of 1.8 or less are metal elements that are difficult to etch with respect to fluorine-based gases because they have a higher boiling point compared to the fluoride of Si with an electronegativity of 1.9. From such findings, it is desirable that the insulating film 80 of the semiconductor device 1 contains a metal element with an electronegativity of 1.8 or less.

[0054] For the dry etching of the protective film 70, an etching gas other than a fluorine-based gas may be used. When an etching gas other than a fluorine-based gas is used, the electronegativity of the metal element contained in the insulating film 80 is considered according to the material of the etching gas.

[0055] By using the insulating film 80 having sufficient etching resistance, the disappearance of the insulating film 80 when dry-etching the protective film 70, the exposure of the cover portion 90 and the channel layer 21 due to this, and the disappearance of the cover portion 90 can be effectively suppressed. Thereby, the contact between the gate electrode 30 formed after the dry etching of the protective film 70 and the channel layer 21 and the resulting short circuit are suppressed, the generation of leakage current due to the short circuit and the generation of pinch-off failure are suppressed, and the performance degradation of the semiconductor device 1 is suppressed.

[0056] FIG. 6 is a diagram showing an example of the characteristic evaluation result of the semiconductor device. FIG. 6(A) shows the current-voltage characteristics of the semiconductor device 100 (FIG. 4) in which the insulating film 80 is not provided. FIG. 6(B) shows the current-voltage characteristics of the semiconductor device 1 (FIG. 5) in which the insulating film 80 is provided. In FIGS. 6(A) and 6(B), the horizontal axis represents the drain-source voltage Vds [V], and the vertical axis represents the drain current density Id [mA / mm].

[0057] As shown in FIG. 6(A), in the case of the semiconductor device 100 (FIG. 4) in which the insulating film 80 is not provided on the side surface 120a of the semiconductor layer 120, a pinch-off failure may occur in which the transistor does not turn off sufficiently (portion Q1 in FIG. 6(A)). Such a pinch-off failure occurs when the cover portion 190 of the semiconductor layer 120 disappears during the dry etching of the protective film 170, and the channel layer 121 and the gate electrode 130 come into contact with each other and short-circuit, as shown in FIG. 4(C) above.

[0058] On the other hand, as shown in FIG. 6(B), in the case of the semiconductor device 1 (FIG. 5) in which the insulating film 80 is provided on the side surface 20a of the semiconductor layer 20, the pinch-off defect as seen in the semiconductor device 100 is improved (portion Q2 in FIG. 6(B)). In the semiconductor device 1, the disappearance of the insulating film 80 when the protective film 70 is dry-etched, the resulting exposure of the protective portion 90 and the channel layer 21, and the disappearance of the protective portion 90 are effectively suppressed. Therefore, the contact between the channel layer 21 and the gate electrode 30 and the resulting short circuit are suppressed, and the occurrence of pinch-off defects is suppressed.

[0059] In addition, in this first embodiment, the semiconductor device 1 using an InP-based material for the substrate 10 and the semiconductor layer 20 is taken as an example. In addition, similarly for a semiconductor device using other semiconductor materials, such as a GaN (gallium nitride)-based material, etc., for the substrate 10 and the semiconductor layer 20, by covering the side surface 20a of the semiconductor layer 20 formed by providing the element isolation region 60 with the insulating film 80, the same effects as described above can be obtained.

[0060] Also, in this first embodiment, an example is shown in which an insulating film 80 containing a metal element is provided between the side surface 20a of the semiconductor layer 20 and the gate electrode 30 provided on the side surface 20a side to suppress the short circuit between the channel layer 21 and the gate electrode 30 on the side surface 20a. In addition, similarly, when other conductive materials, such as the source electrode 40 and the drain electrode 50, etc., are provided on the side surface 20a side of the semiconductor layer 20, the short circuit between the other conductive material and the side surface 20a of the semiconductor layer 20 can be suppressed by the insulating film 80 provided therebetween.

[0061] [Second Embodiment] FIG. 7 is a diagram for explaining an example of a semiconductor device according to the second embodiment. FIGS. 7(A) and 7(B) schematically show cross-sectional views of main parts of an example of the semiconductor device, respectively. FIG. 7(B) schematically shows an example of the VII-VII cross-sectional view of FIG. 7(A).

[0062] As shown in Fig. 7(A), the semiconductor device 1A has a substrate 10A, a semiconductor layer 20A, a gate electrode 30, a source electrode 40, a drain electrode 50, a protective film 70, and an insulating film 80. The semiconductor device 1A is an example of a HEMT.

[0063] The substrate 10A includes a base substrate 11 and a buffer layer 12. The buffer layer 12 is provided on the base substrate 11. For example, an InP substrate is used for the base substrate 11. For example, InAlAs is used for the buffer layer 12. The thickness of the buffer layer 12 is set in the range of about 200 nm to about 300 nm, for example.

[0064] The semiconductor layer 20A is provided on the surface 10a on the buffer layer 12 side of the substrate 10A. The semiconductor layer 20A has a structure in which a carrier supply layer 25, a channel layer 21, and a carrier supply layer 22 (the layers including these are also referred to as the first layer), an etching stop layer 23 (this layer is also referred to as the second layer), and a cap layer 24 are sequentially stacked from the surface 10a side of the substrate 10A. A compound semiconductor material is used for the carrier supply layer 25, the channel layer 21, the carrier supply layer 22, the etching stop layer 23, and the cap layer 24. For example, InAlAs is used for the carrier supply layer 25. For example, InGaAs is used for the channel layer 21. For example, InAlAs is used for the carrier supply layer 22. For example, InP or InGaP is used for the etching stop layer 23. For example, InGaAs is used for the cap layer 24. A recess 24a leading to the etching stop layer 23 is provided in the cap layer 24. Two-dimensional carrier gases 28 are generated near the interfaces of the channel layer 21 with the carrier supply layer 25 and the carrier supply layer 22, respectively.

[0065] Still, the thickness of the carrier supply layer 25 is set, for example, in the range of about 2 nm to about 25 nm. The thickness of the channel layer 21 is set, for example, in the range of about 9 nm to about 25 nm. The thickness of the carrier supply layer 22 is set, for example, in the range of about 9 nm to about 25 nm. The thickness of the etching stop layer 23 is set, for example, in the range of about 4 nm to about 6 nm. The thickness of the cap layer 24 is set, for example, in the range of about 30 nm to about 50 nm. For example, impurities such as Si are doped into the carrier supply layer 25, the carrier supply layer 22, and the cap layer 24 at a predetermined concentration in a predetermined region.

[0066] As shown in FIG. 7(A), the source electrode 40 and the drain electrode 50 are provided on the cap layer 24. The source electrode 40 and the drain electrode 50 are provided separately from each other at positions facing each other with the recess 24a of the cap layer 24 interposed therebetween. For the source electrode 40 and the drain electrode 50, for example, those in which Ti, Pt, and Au are sequentially laminated are used. The source electrode 40 and the drain electrode 50 are provided so as to function as ohmic electrodes.

[0067] As shown in FIG. 7(A), the protective film 70 is provided so as to cover the side of the semiconductor layer 20A opposite to the substrate 10A. The protective film 70 is provided so as to cover the cap layer 24, the etching stop layer 23 in the recess 24a thereof, and the source electrode 40 and the drain electrode 50 on the cap layer 24. For example, SiN is used for the protective film 70. The protective film 70 is provided with an opening 71 formed so as to be located within the recess 24a of the cap layer 24.

[0068] As shown in FIG. 7(A), the gate electrode 30 is provided so as to be located in the opening 71 of the protective film 70 formed in the recess 24a of the cap layer 24 between the source electrode 40 and the drain electrode 50. The gate electrode 30 is provided separately from the source electrode 40 and the drain electrode 50. For the gate electrode 30, for example, a stack of Ti, Pt, and Au in that order is used. The gate electrode 30 is provided, for example, on the side of the semiconductor layer 20A opposite to the substrate 10A so as to have a T-shaped cross section.

[0069] As shown in FIG. 7(A), the insulating film 80 is provided so as to cover the cap layer 24, the etching stop layer 23 in its recess 24a, the source electrode 40 and the drain electrode 50 on the cap layer 24. The insulating film 80 is provided between the semiconductor layer 20A and the protective film 70 on the side of the semiconductor layer 20A opposite to the substrate 10A. The opening 71 of the protective film 70 is formed so as to communicate with the insulating film 80. The gate electrode 30 provided in the opening 71 of the protective film 70 has its lower end in contact with the insulating film 80. The gate electrode 30 is provided on the semiconductor layer 20A via the insulating film 80. The insulating film 80 interposed between the gate electrode 30 and the semiconductor layer 20A (its etching stop layer 23) functions as a gate insulating film. The semiconductor device 1 is an example of a HEMT having a MIS (Metal Insulator Semiconductor) type gate structure. For the insulating film 80, for example, Al2O3 is used.

[0070] In addition, for the insulating film 80, as the metal element, one containing a metal element with an electronegativity of 1.8 or less can be used. For the insulating film 80, as the metal element, one containing one or more of Al, Hf, Zr, Ti, Ta, Mg, Sc, Y, La, and Sr can be used. For the insulating film 80, one including a laminated film of one or more of an oxide film, a nitride film, and an oxynitride film containing such a metal element can be used.

[0071] In the semiconductor device 1A having a configuration as shown in FIG. 7(A), the semiconductor layer 20A is element-separated by mesa formation. FIG. 7(B) shows a structural example near the element isolation region 60 formed at the end of the semiconductor layer 20A in the depth direction of the paper surface due to the mesa formation of the semiconductor layer 20A of the semiconductor device 1A shown in FIG. 7(A).

[0072] For example, as shown in FIG. 7(B), in a cross section along the position where the gate electrode 30 is provided, on the side surface 20a of the semiconductor layer 20A of the element isolation region 60, side surfaces of the carrier supply layer 25, the channel layer 21, the carrier supply layer 22, and the etching stop layer 23 are located. For example, the etching stop layer 23 has a shape that protrudes outward from the side surface of the carrier supply layer 22 below it, and the carrier supply layer 22 has a shape that protrudes outward from the side surface of the channel layer 21 below it. The carrier supply layer 25 has a shape that protrudes outward from the side surface of the channel layer 21 above it. On the upper layer of the channel layer 21, a protective part 90 of the etching stop layer 23 and the carrier supply layer 22 that protrudes outward from its side surface is provided. Note that such a stepped shape of the side surface 20a of the semiconductor layer 20A is realized by etching when forming the element isolation region 60.

[0073] As shown in FIG. 7(A), the insulating film 80 is provided so as to cover the cap layer 24, the etching stop layer 23 in its recess 24a, the source electrode 40, and the drain electrode 50 on the cap layer 24 on the side of the semiconductor layer 20A opposite to the substrate 10A. As shown in FIG. 7(B), this insulating film 80 further extends from above the semiconductor layer 20A to its side surface 20a (element isolation region 60), and on the side surface 20a, it is provided so as to cover the protective part 90 of the etching stop layer 23 and the carrier supply layer 22, the channel layer 21, and the carrier supply layer 25.

[0074] As shown in FIG. 7(B), the insulating film 80 has a structure in which two layers of a first insulating portion 81 and a second insulating portion 82 are partially laminated. The first insulating portion 81 covers the side surfaces of the carrier supply layer 22, the channel layer 21, and the carrier supply layer 25, which are lower than the etching stop layer 23, on the side surface 20a of the semiconductor layer 20A. The second insulating portion 82 covers the cap layer 24, the etching stop layer 23 in its recess 24a, the source electrode 40 and the drain electrode 50 on the cap layer 24, and also covers the first insulating portion 81 on the side surface 20a, on the side of the semiconductor layer 20A opposite to the substrate 10A. The first insulating portion 81 and the second insulating portion 82 are formed below the etching stop layer 23 on the side surface 20a of the semiconductor layer 20A, and the second insulating portion 82 is formed above the etching stop layer 23. Therefore, the insulating film 80 provided on the side surface 20a of the semiconductor layer 20A has a greater thickness in the direction D1 below the etching stop layer 23 than in the direction D1 above the etching stop layer 23. Note that the same material or different materials may be used for the first insulating portion 81 and the second insulating portion 82.

[0075] On the insulating film 80 having such first and second insulating portions 81 and 82, a protective film 70 having an opening 71 communicating with the insulating film 80 (its second insulating portion 82) is provided (FIG. 7(A)), and a gate electrode 30 is provided in the opening 71 of the protective film 70. As shown in FIG. 7(B), the gate electrode 30 is provided so as to extend from above the semiconductor layer 20A (in the opening 71 of the protective film 70) to the element isolation region 60 on the side surface 20a side thereof. A part of the insulating film 80, that is, the portion where the first insulating portion 81 and the second insulating portion 82 are laminated, is provided between the side surface 20a of the semiconductor layer 20A and the gate electrode 30 provided to extend to the side surface 20a side, as shown in FIG. 7(B).

[0076] Here, a method for manufacturing the semiconductor device 1A having the above-described configuration will be described. FIGS. 8 to 14 are diagrams for explaining an example of a method for manufacturing a semiconductor device according to the second embodiment. Hereinafter, each step of manufacturing the semiconductor device will be sequentially described with reference to FIGS. 8 to 14 and FIG. 7 above.

[0077] FIG. 8(A) and FIG. 8(B) schematically show cross-sectional views of the main part of an example of the semiconductor layer formation process. FIG. 8(B) schematically shows an example of the VIII-VIII cross-sectional view of FIG. 8(A).

[0078] First, the substrate 10A and the semiconductor layer 20A as shown in FIGS. 8(A) and 8(B) are formed. First, a base substrate 11 such as an InP substrate is prepared. On the prepared base substrate 11, a buffer layer 12 such as InAlAs is formed using, for example, the Metal Organic Chemical Vapor Deposition (MOCVD) method. Thereby, the substrate 10A is formed.

[0079] Next, on the buffer layer 12 of the substrate 10A, a carrier supply layer 25, a channel layer 21, a carrier supply layer 22, an etching stop layer 23, and a cap layer 24 are sequentially formed using, for example, the MOCVD method. At this time, the carrier supply layer 25 on the buffer layer 12 can be formed by introducing impurities such as delta doping (atomic layer doping). As the impurity, for example, Si is doped to about 12 cm -2 The impurity is doped in a sheet shape at the interface between the buffer layer 12 and the carrier supply layer 25. The doping interface is set to a depth of about 3 nm to about 5 nm from the surface of the carrier supply layer 25. In this case, the portion on the surface side of the doping interface of the carrier supply layer 25 can also be regarded as a spacer layer. After the formation of the carrier supply layer 25, the channel layer 21, the carrier supply layer 22, the etching stop layer 23, and the cap layer 24 are sequentially formed thereon. Thereby, the semiconductor layer 20A is formed.

[0080] After the formation of the semiconductor layer 20A, the element isolation region 60 is formed. FIG. 9(A) and FIG. 9(B) schematically show cross-sectional views of the main part of an example of the element isolation region formation (semiconductor layer mesa formation) process. FIG. 9(B) schematically shows an example of the IX-IX cross-sectional view of FIG. 9(A).

[0081] The formation of the element isolation region 60 is performed, for example, as follows. A resist mask (not shown) with an opening in the region for forming the element isolation region 60 is formed on the cap layer 24. For example, a mixed solution of phosphoric acid and hydrogen peroxide water is used, and the cap layer 24 is etched. This etching stops at the surface of the etching stop layer 23. Next, for example, hydrochloric acid is used, and the etching stop layer 23 is etched. This etching stops at the surface of the carrier supply layer 22. Then, for example, a mixed solution of phosphoric acid and hydrogen peroxide water is used, and the carrier supply layer 22, the channel layer 21, and the carrier supply layer 25 are etched. In this way, the element isolation region 60 is formed. After the formation of the element isolation region 60, the resist mask is removed. By forming the element isolation region 60 by such etching, as shown in FIG. 9(B), the etching stop layer 23, the carrier supply layer 22, and the carrier supply layer 25 protrude outward beyond the channel layer 21. The etching stop layer 23 protrudes outward beyond the carrier supply layer 22 and the carrier supply layer 25. On the upper layer of the channel layer 21, a protective portion 90 of the etching stop layer 23 and the carrier supply layer 22 that protrudes outward beyond its side surface is formed. By forming the element isolation region 60, the semiconductor layer 20A is mesa-shaped, and separation between elements is performed. By forming the element isolation region 60, a stepped side surface 20a facing in the direction D1 parallel to the surface 10a of the substrate 10A is formed in the semiconductor layer 20A.

[0082] After the formation of the element isolation region 60, the formation of the first insulating portion 81 in the insulating film 80 is performed. FIGS. 10(A) and 10(B) schematically show cross-sectional views of the main part of an example of the first insulating portion formation process. FIG. 10(B) schematically shows an example of the X-X cross-sectional view of FIG. 10(A).

[0083] First, an insulating material of the first insulating portion 81, for example, Al2O3, is formed so as to cover the mesa-shaped semiconductor layer 20A formed by the formation of the element isolation region 60. The Al2O3 of this insulating material is formed, for example, by an Atomic Layer Deposition (ALD) method. The thickness of Al2O3 is preferably set in the range of 2 nm to 50 nm, and as an example, it is set to 10 nm. In the ALD method, Al2O3 can be formed with good coverage even on the side surface 20a of the semiconductor layer 20A having a step. After the formation of Al2O3 covering the semiconductor layer 20A, a resist mask (not shown) having an opening from the etching stop layer 23 of the semiconductor layer 20A upward is formed, and the upper Al2O3 from the etching stop layer 23 is selectively removed by wet etching using an alkaline chemical solution. Thereby, a structure is obtained in which the side surfaces of the carrier supply layer 22, the channel layer 21, and the carrier supply layer 25, that is, the lower part than the etching stop layer 23 of the semiconductor layer 20A, are covered with Al2O3, and the first insulating portion 81 is formed by the Al2O3.

[0084] After the formation of the first insulating portion 81, the source electrode 40 and the drain electrode 50 are formed, and the recess 24a of the cap layer 24 is formed. FIGS. 11(A) and 11(B) schematically show cross-sectional views of main parts of an example of a source electrode, a drain electrode, and a recess formation process, respectively. FIG. 11(B) schematically shows an example of the XI-XI cross-sectional view of FIG. 11(A).

[0085] First, the source electrode 40 and the drain electrode 50 are formed on the semiconductor layer 20A defined by the element isolation region 60. At that time, a resist mask (not shown) having an opening in the region where the source electrode 40 or the drain electrode 50 is to be formed is formed on the cap layer 24, and Ti, Pt, and Au are formed using a sequential evaporation method. Then, the resist mask is removed together with the Ti, Pt, and Au formed thereon. For example, the source electrode 40 and the drain electrode 50 are formed on the cap layer 24 using such a lift-off method.

[0086] Next, a recess 24a is formed in the region of the cap layer 24 between the source electrode 40 and the drain electrode 50. At this time, a resist mask (not shown) with an opening in the region where the recess 24a is to be formed is formed on the cap layer 24. For example, a mixed solution of phosphoric acid and hydrogen peroxide water is used, and the cap layer 24 is etched. This etching stops at the surface of the etching stop layer 23. By using such a method, the recess 24a is formed in the cap layer 24.

[0087] After the formation of the source electrode 40 and the drain electrode 50, and the formation of the recess 24a in the cap layer 24, the second insulating portion 82 in the insulating film 80 is formed. FIG. 12(A) and FIG. 12(B) schematically show cross-sectional views of the main parts of an example of the second insulating portion forming step. FIG. 12(B) schematically shows an example of the XII-XII cross-sectional view of FIG. 12(A).

[0088] An insulating material of the second insulating portion 82, for example, Al2O3, is formed so as to cover the cap layer 24, the etching stop layer 23 in the recess 24a thereof, the source electrode 40 and the drain electrode 50 on the cap layer 24, and the first insulating portion 81 formed on the side surface 20a of the semiconductor layer 20A. This insulating material Al2O3 is formed, for example, by using the ALD method. The thickness of Al2O3 is preferably set in the range of 1 nm to 10 nm, and as an example, it is set to 2 nm. By this Al2O3, the second insulating portion 82 is formed. The portion of the second insulating portion 82 formed on the etching stop layer 23 functions as a gate insulating film.

[0089] The side surface 20a of the semiconductor layer 20A, below the etching stop layer 23, that is, the carrier supply layer 22, the channel layer 21, and the carrier supply layer 25 are covered with a laminated film of the second insulating portion 82 formed here and the first insulating portion 81 formed previously. In this way, by forming the first insulating portion 81 and then the second insulating portion 82, the insulating film 80 including the first insulating portion 81 and the second insulating portion 82 is formed.

[0090] Below the etching stop layer 23 on the side surface 20a of the semiconductor layer 20A, a first insulating portion 81 and a second insulating portion 82 (also referred to as a first site) of the insulating film 80 are formed, and above the etching stop layer 23, a second insulating portion 82 (also referred to as a second site) of the insulating film 80 is formed. Therefore, the insulating film 80 provided on the side surface 20a of the semiconductor layer 20A has a thickness T1a or T1b (also referred to as a first thickness) in the direction D1 below the etching stop layer 23 that is thicker than the thickness T2 (also referred to as a second thickness) in the direction D1 above the etching stop layer 23.

[0091] After the formation of the second insulating portion 82 (the insulating film 80 including the same), a protective film 70 is formed. FIG. 13(A) and FIG. 13(B) schematically show a cross-sectional view of a main part of an example of the protective film forming step. FIG. 13(B) schematically shows an example of the XIII-XIII cross-sectional view of FIG. 13(A).

[0092] A protective film 70 such as SiN is formed so as to cover the semiconductor layer 20A covered with the insulating film 80. The protective film 70 is formed, for example, using the plasma CVD method. A protective film 70 such as SiN having a thickness in the range of 2 nm to 500 nm is formed. In addition to the plasma CVD method, an ALD method, a sputtering method, or the like may be used for the formation of the protective film 70. The protective film 70 is formed so as to further cover the cap layer 24, the etching stop layer 23 in the recess 24a thereof, the source electrode 40 and the drain electrode 50 on the cap layer 24, and the insulating film 80 provided so as to cover the semiconductor layer 20A.

[0093] After the formation of the protective film 70, an opening 71 is formed in the protective film 70. FIG. 14(A) and FIG. 14(B) schematically show a cross-sectional view of a main part of an example of the opening forming step. FIG. 14(B) schematically shows an example of the XIV-XIV cross-sectional view of FIG. 14(A).

[0094] An opening 71 located within the recess 24a of the cap layer 24 is formed in the protective film 70 by dry etching using, for example, a fluorine-based gas. At that time, first, a resist mask (not shown) with an opening in the region where the opening 71 in the recess 24a is to be formed is formed, and dry etching using a fluorine-based gas is performed. By this dry etching, the opening 71 is formed in the protective film 70 within the recess 24a.

[0095] In addition, the protective film 70 formed on the side surface 80a of the insulating film 80 may be removed as shown in FIG. 14(B) during this dry etching. In this case, after the formation of the opening 71 by dry etching, the side surface 80a of the insulating film 80 is exposed.

[0096] After the formation of the opening 71 in the protective film 70, the gate electrode 30 is formed. By forming the gate electrode 30 so as to be located in the opening 71 formed in the protective film 70 and extend from above the semiconductor layer 20A (in the opening 71 of the protective film 70) to the element isolation region 60 on the side surface 20a side, the semiconductor device 1A as shown in FIGS. 7(A) and 7(B) is manufactured.

[0097] As described above, in the manufacture of the semiconductor device 1A, the opening 71 is formed by dry etching using a fluorine-based gas on the protective film 70 (FIG. 13) formed so as to cover the insulating film 80 (FIG. 14). Then, the gate electrode 30 is formed in the opening 71 (FIG. 7).

[0098] Here, since the side surface 20a of the semiconductor layer 20A is covered with the insulating film 80 and is not exposed, it is suppressed from being exposed to the fluorine-based gas when forming the opening 71 in the protective film 70 by dry etching. When the protective film 70 is formed so as to cover the insulating film 80, the protective film 70 is formed on the side surface 80a of the insulating film 80. Even if the protective film 70 on the side surface 80a is removed by dry etching, the side surface 20a of the semiconductor layer 20A is covered with the insulating film 80. Therefore, it is suppressed that the side surface 20a of the semiconductor layer 20A is exposed to the fluorine-based gas. By using a material with high etching resistance to the fluorine-based gas, such as Al2O3 as described above, for the insulating film 80, the disappearance of the insulating film 80 exposed to the fluorine-based gas is suppressed, and the side surface 20a of the semiconductor layer 20A is suppressed from being exposed to the fluorine-based gas.

[0099] Therefore, it is suppressed that a part of the side surface 20a of the semiconductor layer 20A, for example, the etching stop layer 23 of the eaves portion 90 or it and the carrier supply layer 22 disappear. Further, since the side surface 20a of the semiconductor layer 20A is covered with the insulating film 80, when the gate electrode 30 is formed after forming the opening 71 by dry etching of the protective film 70, it is suppressed that the gate electrode 30 is formed in contact with the channel layer 21 on the side surface 20a of the semiconductor layer 20A. In the semiconductor device 1A, since the contact between the gate electrode 30 and the channel layer 21 on the side surface 20a of the semiconductor layer 20A is suppressed in this way, their short circuit, that is, the short circuit between the two-dimensional carrier gas 28 generated in the channel layer 21 and the gate electrode 30 is suppressed. Thereby, the performance degradation of the semiconductor device 1A due to the short circuit between the gate electrode 30 and the channel layer 21 is suppressed.

[0100] In the semiconductor device 1A, the side surface 20a of the semiconductor layer 20A is covered with the insulating film 80, and exposure to the fluorine-based gas is suppressed. Therefore, the eaves portion 90 provided on the side surface 20a of the semiconductor layer 20A is suppressed from disappearing due to exposure to the fluorine-based gas. Since the disappearance of the eaves portion 90 is suppressed, it is not necessary to make the thickness of the eaves portion 90 necessarily thick enough to withstand disappearance by dry etching. For example, the thickness of the etching stop layer 23 forming the eaves portion 90 can be set to a thickness at which etching can be stopped when forming the recess 24a of the cap layer 24, for example, a thickness of 5 nm or less. When the thickness of the etching stop layer 23 is reduced, an increase in the distance between the gate electrode 30 and the channel layer 21 through the etching stop layer 23 and the carrier supply layer 22 is suppressed, and a decrease in the intensity of the electric field applied from the gate electrode 30 to the channel layer 21 is suppressed. Therefore, deterioration of the high-frequency characteristics of the semiconductor device 1A is suppressed. In order to suppress an increase in the distance between the gate electrode 30 and the channel layer 21 through the etching stop layer 23 and the carrier supply layer 22, the thickness of the etching stop layer 23 is preferably set to be half or less of the thickness of the channel layer 21 in the direction D2.

[0101] [Third Embodiment] FIG. 15 is a diagram for explaining an example of a semiconductor device according to the third embodiment. FIGS. 15(A) and 15(B) schematically show cross-sectional views of main parts of an example of the semiconductor device. FIG. 15(B) schematically shows an example of a cross-sectional view taken along line XV-XV of FIG. 15(A).

[0102] The semiconductor device 1B shown in FIGS. 15(A) and 15(B) has a structure in which the protective film 70 remains on the side surface 80a of the insulating film 80. The semiconductor device 1B is different from the semiconductor device 1A described in the second embodiment in that it has such a structure.

[0103] In the semiconductor device 1B, the protective film 70 provided on the side of the semiconductor layer 20A opposite to the substrate 10A extends to the side surface 20a side of the semiconductor layer 20A and remains on the side surface 80a of the insulating film 80 that covers the side surface 20a of the semiconductor layer 20A. The protective film 70 remaining on the side surface 80a of the insulating film 80 is provided between the insulating film 80 that covers the side surface 20a of the semiconductor layer 20A and the gate electrode 30 provided on the side surface 20a side of the semiconductor layer 20A.

[0104] In the semiconductor device 1B, as shown in FIG. 15(B), the channel layer 21 is separated from the gate electrode 30 by the insulating film 80 covering it and the protective film 70 remaining on the side surface 80a thereof, and contact with the gate electrode 30 and short - circuiting due to it are suppressed. Since the protective film 70 remains on the side surface 80a of the insulating film 80, the distance between the side surface of the channel layer 21 and the gate electrode 30 facing it becomes larger compared to the case where the protective film 70 does not remain, and the influence of the electric field from the gate electrode 30 on the channel layer 21 (the two - dimensional carrier gas 28 generated therein) is suppressed. Also, with the semiconductor device 1B having a structure as shown in FIG. 15(B), that is, a structure in which the protective film 70 remains on the side surface 80a of the insulating film 80, it is possible to suppress a performance degradation caused by a short - circuit between the gate electrode 30 and the channel layer 21.

[0105] FIG. 16 is a diagram for explaining an example of a manufacturing method of a semiconductor device according to the third embodiment. FIGS. 16(A) and 16(B) schematically show cross - sectional views of main parts of an example of the opening formation process. FIG. 16(B) schematically shows an example of the XVI - XVI cross - sectional view of FIG. 16(A).

[0106] In the manufacture of the semiconductor device 1B, the steps from FIG. 8 to FIG. 13 described in the second embodiment above can be the same. That is, first, the formation of the substrate 10A and the semiconductor layer 20A (FIG. 8), the formation of the element isolation region 60 (FIG. 9), the formation of the first insulating portion 81 (FIG. 10), the formation of the source electrode 40, the drain electrode 50, and the recess 24a (FIG. 11), the formation of the second insulating portion 82 (FIG. 12), and the formation of the protective film 70 (FIG. 13) are performed. Then, an opening 71 as shown in FIGS. 16(A) and 16(B) is formed in the protective film 70.

[0107] For example, when forming the opening 71 by dry etching, a resist mask (not shown) is formed so as to cover the protective film 70 formed on the side surface 80a of the insulating film 80. Thereby, the protective film 70 formed on the side surface 80a of the insulating film 80 is protected from the fluorine-based gas used when forming the opening 71 by dry etching. Therefore, as shown in FIG. 16(B), the protective film 70 remains on the side surface 80a of the insulating film 80. Incidentally, even when the protective film 70 formed on the side surface 80a of the insulating film 80 is not covered with the resist mask in this way, it is also possible to adjust the thickness of the protective film 70 formed on the side surface 80a and the dry etching conditions so that the protective film 70 remains on the side surface 80a.

[0108] [Fourth Embodiment] FIG. 17 is a diagram for explaining an example of a semiconductor device according to the fourth embodiment. FIGS. 17(A) and 17(B) schematically show cross-sectional views of main parts of an example of the semiconductor device. FIG. 17(B) schematically shows an example of the XVII-XVII cross-sectional view of FIG. 17(A).

[0109] The semiconductor device 1C shown in FIGS. 17(A) and 17(B) has a structure in which the insulating film 80 is provided only below the etching stop layer 23 among the lower part of the semiconductor layer 20A than the etching stop layer 23 and the upper part from the etching stop layer 23. That is, the semiconductor device 1C has a structure in which the insulating film 80 is provided only on the side surfaces of the carrier supply layer 25, the channel layer 21, and the carrier supply layer 22 among the carrier supply layer 25, the channel layer 21, the carrier supply layer 22, the etching stop layer 23, and the cap layer 24 of the semiconductor layer 20A. The semiconductor device 1C has a structure in which only the first insulating portion 81 among the first insulating portion 81 and the second insulating portion 82 described in the second embodiment is provided as the insulating film 80. The semiconductor device 1C is different from the semiconductor device 1A described in the second embodiment in that it has such a structure.

[0110] In the semiconductor device 1C, the side surfaces of the carrier supply layer 22, the channel layer 21, and the carrier supply layer 25 on the side surface 20a of the semiconductor layer 20A are covered by a first insulating portion 81 provided as an insulating film 80. Thereby, contact between the gate electrode 30 and the channel layer 21 on the side surface 20a of the semiconductor layer 20A and the resulting short circuit are suppressed, and degradation in the performance of the semiconductor device 1C is suppressed.

[0111] In the semiconductor device 1C, among the first insulating portion 81 and the second insulating portion 82 described in the second embodiment above, only the first insulating portion 81 is provided as the insulating film 80, and the semiconductor device 1C has a structure in which the second insulating portion 82 is not provided. In the manufacture of the semiconductor device 1C, formation of the substrate 10A and the semiconductor layer 20A (FIG. 8), formation of the element isolation region 60 (FIG. 9), formation of the first insulating portion 81 (FIG. 10), and formation of the source electrode 40, the drain electrode 50, and the recess 24a (FIG. 11) described in the second embodiment above are performed. Thereafter, formation of the second insulating portion 82 (FIG. 12) is omitted, and formation of the protective film 70 (FIG. 13) and formation of the opening 71 (FIG. 14) are performed according to the examples of FIGS. 13 and 14 above, and formation of the gate electrode 30 (FIG. 17) is performed. In the manufacture of the semiconductor device 1C, since the formation process of the second insulating portion 82 is omitted, the manufacturing efficiency is improved by reducing the man-hours.

[0112] Also, since formation of the second insulating portion 82 is omitted, an opening 71 communicating with the etching stop layer 23 is formed in the protective film 70, and the gate electrode 30 is formed on the etching stop layer 23 of the opening 71. The gate electrode 30 provided in the opening 71 has its lower end in contact with the etching stop layer 23. In the semiconductor device 1C, a Schottky gate structure is realized in which the gate electrode 30 is Schottky-connected to the semiconductor layer 20A without passing through a gate insulating film.

[0113] Note that in the semiconductor device 1C, a protective film 70 may remain on the side surface 80a of the first insulating portion 81 provided as the insulating film 80 according to the example described in the third embodiment above. [Fifth Embodiment] FIG. 18 is a diagram for explaining an example of a semiconductor device according to the fifth embodiment. FIGS. 18(A) and 18(B) schematically show cross-sectional views of main parts of an example of the semiconductor device. FIG. 18(B) schematically shows an example of the XVIII-XVIII cross-sectional view of FIG. 18(A).

[0114] In the semiconductor device 1D shown in FIGS. 18(A) and 18(B), on the side surface 20a of the semiconductor layer 20A, the carrier supply layer 25, the channel layer 21, the carrier supply layer 22, and the etching stop layer 23 have a structure in which the positions of the side surfaces are the same or equivalent. Here, although illustration is omitted, in the semiconductor device 1D, also for the cap layer 24 of the semiconductor layer 20A, the position of its side surface is the same or equivalent to the positions of the side surfaces of the carrier supply layer 25, the channel layer 21, the carrier supply layer 22, and the etching stop layer 23. In the semiconductor device 1D, the step shape of the side surface 20a as described in the second embodiment above, that is, the step shape in which the carrier supply layer 25 and the carrier supply layer 22 protrude outward more than the channel layer 21 and the etching stop layer 23 protrudes outward more than them, is not adopted. The semiconductor device 1D is different from the semiconductor device 1A described in the second embodiment above in that it has such a structure.

[0115] The semiconductor layer 20A having a relatively flat side surface 20a shape like the semiconductor device 1D is realized by adjusting the etching conditions during the formation of the element isolation region 60 (FIG. 9), which is performed after the formation of the substrate 10A and the semiconductor layer 20A (FIG. 8) described in the second embodiment above. After the etching of the cap layer 24 and the etching of the etching stop layer 23, the etching of the carrier supply layer 22, the etching of the channel layer 21, and the etching of the carrier supply layer 25 are performed so that the positions of the etching stop layer 23 and the side surface are the same or equivalent. By appropriately adjusting conditions such as the solution, time, temperature, and stirring speed when etching each layer, a semiconductor layer 20A having a relatively flat side surface 20a shape like the semiconductor device 1D is realized.

[0116] After forming the semiconductor layer 20A having such a relatively flat side surface 20a, each process is performed according to the example described in the second embodiment. That is, formation of the first insulating portion 81 (FIG. 10), formation of the source electrode 40, drain electrode 50, and recess 24a (FIG. 11), formation of the second insulating portion 82 (FIG. 12), formation of the protective film 70 (FIG. 13), formation of the opening 71 (FIG. 14) are performed, and formation of the gate electrode 30 (FIG. 18) is performed. Note that the first insulating portion 81 is provided so as to cover at least the carrier supply layer 25, channel layer 21, and carrier supply layer 22 among the carrier supply layer 25, channel layer 21, carrier supply layer 22, etching stop layer 23, and cap layer 24 on the side surface 20a of the semiconductor layer 20A.

[0117] In the semiconductor device 1D, the side surface 20a of the semiconductor layer 20A is covered with the first insulating portion 81 and the second insulating portion 82 of the insulating film 80. Thereby, contact between the gate electrode 30 and the channel layer 21 on the side surface 20a of the semiconductor layer 20A and a short circuit due thereto are suppressed, and deterioration of the performance of the semiconductor device 1D is suppressed.

[0118] In the semiconductor device 1D, when forming the opening 71 in the protective film 70 by dry etching using a fluorine-based gas, exposure of the side surface 20a of the semiconductor layer 20A to the fluorine-based gas is suppressed by the insulating film 80. Therefore, even if the eaves portion 90 as described above is not provided in the carrier supply layer 22 and the etching stop layer 23 above the channel layer 21, contact between the gate electrode 30 and the channel layer 21 on the side surface 20a of the semiconductor layer 20A and a short circuit due thereto can be suppressed.

[0119] Note that in the semiconductor device 1D, the protective film 70 may remain on the side surface 80a of the insulating film 80 according to the example described in the third embodiment. [Sixth Embodiment] FIG. 19 is a diagram for explaining an example of a semiconductor device according to the sixth embodiment. FIGS. 19(A) and 19(B) schematically show cross-sectional views of main parts of an example of the semiconductor device. FIG. 19(B) schematically shows an example of the XIX-XIX cross-sectional view of FIG. 19(A).

[0120] The semiconductor device 1E shown in FIGS. 19(A) and 19(B) has a structure in which only the first insulating portion 81 of the first insulating portion 81 and the second insulating portion 82 described in the fifth embodiment is provided as the insulating film 80. The semiconductor device 1E is different from the semiconductor device 1D described in the fifth embodiment in that it has such a structure. Incidentally, the first insulating portion 81 is provided so as to cover at least the carrier supply layer 25, the channel layer 21, and the carrier supply layer 22 among the carrier supply layer 25, the channel layer 21, the carrier supply layer 22, the etching stop layer 23, and the cap layer 24 on the side surface 20a of the semiconductor layer 20A.

[0121] In the semiconductor device 1E, the side surface 20a of the semiconductor layer 20A is covered by the first insulating portion 81 provided as the insulating film 80. Thereby, the contact between the gate electrode 30 and the channel layer 21 on the side surface 20a of the semiconductor layer 20A and the resulting short circuit are suppressed, and the performance degradation of the semiconductor device 1E is suppressed.

[0122] In the manufacture of the semiconductor device 1E, since the formation process of the second insulating portion 82 is omitted, the manufacturing efficiency is improved by reducing the man-hours. Further, since the formation of the second insulating portion 82 is omitted, an opening 71 leading to the etching stop layer 23 is formed in the protective film 70, and the gate electrode 30 is formed on the etching stop layer 23 of the opening 71. The gate electrode 30 provided in the opening 71 has its lower end in contact with the etching stop layer 23. In the semiconductor device 1E, a Schottky gate structure in which the gate electrode 30 is Schottky-connected to the semiconductor layer 20A without passing through a gate insulating film is realized.

[0123] Incidentally, in the semiconductor device 1E, a protective film 70 may remain on the side surface 80a of the insulating film 80 according to the example described in the third embodiment. The first to sixth embodiments have been described above.

[0124] In the above description, an example in which a fluorine-based gas is used for the dry etching to form the opening 71 of the protective film 70 has been mainly shown. However, an etching gas other than the fluorine-based gas can also be used for the dry etching.

[0125] Semiconductor devices 1, 1A, 1B, 1C, 1D, 1E, etc. having the configurations described in the first to sixth embodiments can be applied to various electronic devices. As an example, the case where a semiconductor device having the above configuration is applied to a semiconductor package, a power factor improvement circuit, a power supply device, and an amplifier will be described below.

[0126] [Seventh Embodiment] Here, an application example of a semiconductor device having the above configuration to a semiconductor package will be described as the seventh embodiment.

[0127] FIG. 20 is a diagram for explaining an example of a semiconductor package according to the seventh embodiment. FIG. 20 schematically shows a plan view of a main part of an example of the semiconductor package. The semiconductor package 200 shown in FIG. 20 is an example of a discrete package. The semiconductor package 200 includes, for example, a semiconductor device 1 (FIG. 5) as described in the first embodiment above, a lead frame 210 on which the semiconductor device 1 is mounted, and a resin 220 that seals them.

[0128] The semiconductor device 1 is mounted, for example, on the die pad 210a of the lead frame 210 using a die attach material or the like (not shown). The semiconductor device 1 is provided with a pad 30a connected to the gate electrode 30, a pad 40a connected to the source electrode 40, and a pad 50a connected to the drain electrode 50. The pad 30a, the pad 40a, and the pad 50a are respectively connected to the gate lead 211, the source lead 212, and the drain lead 213 of the lead frame 210 using wires 230 such as Au and Al. The lead frame 210, the semiconductor device 1 mounted thereon, and the wires 230 connecting them are encapsulated with a resin 220 so that a part of each of the gate lead 211, the source lead 212, and the drain lead 213 is exposed.

[0129] An external connection electrode connected to the source electrode 40 may be provided on the surface of the semiconductor device 1 opposite to the surface on which the pad 30a connected to the gate electrode 30 and the pad 50a connected to the drain electrode 50 are provided. The external connection electrode may be connected to the die pad 210a connected to the source lead 212 using a conductive bonding material such as solder.

[0130] For example, the semiconductor device 1 as described in the first embodiment above is used, and a semiconductor package 200 having such a configuration is obtained. As described above, in the semiconductor device 1, the side surface 20a of the semiconductor layer 20 formed by the element isolation region 60 is covered with an insulating film 80 containing a metal. By covering the side surface 20a of the semiconductor layer 20 with the insulating film 80, exposure to a fluorine-based gas used for dry etching when forming the opening 71 in the protective film 70 covering the semiconductor layer 20 can be suppressed. Thereby, disappearance of a part of the side surface 20a of the semiconductor layer 20 can be suppressed, and contact between the gate electrode 30 and the channel layer 21 on the side surface 20a of the semiconductor layer 20 can be suppressed. A high-performance semiconductor device 1 in which performance degradation due to a short circuit caused by contact between the gate electrode 30 and the channel layer 21 is suppressed is realized. Such a semiconductor device 1 is used, and a high-performance semiconductor package 200 is realized.

[0131] Here, the semiconductor device 1 is taken as an example, but it is also possible to obtain a semiconductor package in the same manner using other semiconductor devices 1A, 1B, 1C, 1D, 1E, etc. [Eighth Embodiment] Here, an application example of the semiconductor device having the above-described configuration to a power factor improvement circuit will be described as the eighth embodiment.

[0132] FIG. 21 is a diagram for explaining an example of a power factor improvement circuit according to the eighth embodiment. FIG. 21 shows an equivalent circuit diagram of an example of the power factor improvement circuit. The power factor correction (PFC) circuit 300 shown in FIG. 21 includes a switch element 310, a diode 320, a choke coil 330, a capacitor 340, a capacitor 350, a diode bridge 360, and an AC power supply 370 (AC).

[0133] In the PFC circuit 300, the drain electrode of the switch element 310 is connected to the anode terminal of the diode 320 and one terminal of the choke coil 330. The source electrode of the switch element 310 is connected to one terminal of the capacitor 340 and one terminal of the capacitor 350. The other terminal of the capacitor 340 is connected to the other terminal of the choke coil 330. The other terminal of the capacitor 350 is connected to the cathode terminal of the diode 320. Also, a gate driver is connected to the gate electrode of the switch element 310. The AC power supply 370 is connected between both terminals of the capacitor 340 via the diode bridge 360, and a DC power supply (DC) is taken out between both terminals of the capacitor 350.

[0134] For example, the semiconductor devices 1, 1A, 1B, 1C, 1D, 1E, etc. are used for the switch element 310 of the PFC circuit 300 having such a configuration. As described above, in semiconductor devices 1, 1A, 1B, 1C, 1D, 1E, etc., the side surface 20a of the semiconductor layer 20 or the semiconductor layer 20A formed by the element isolation region 60 is covered with an insulating film 80 containing metal. By covering the side surface 20a of the semiconductor layer 20 or the semiconductor layer 20A with the insulating film 80, exposure to a fluorine-based gas used in dry etching when forming the opening 71 in the protective film 70 covering the semiconductor layer 20 or the semiconductor layer 20A can be suppressed. Thereby, disappearance of a part of the side surface 20a of the semiconductor layer 20 or the semiconductor layer 20A can be suppressed, and contact between the gate electrode 30 and the channel layer 21 on the side surface 20a of the semiconductor layer 20 or the semiconductor layer 20A can be suppressed. High-performance semiconductor devices 1, 1A, 1B, 1C, 1D, 1E, etc. in which performance degradation due to a short circuit caused by contact between the gate electrode 30 and the channel layer 21 is suppressed are realized. Such semiconductor devices 1, 1A, 1B, 1C, 1D, 1E, etc. are used, and a high-performance PFC circuit 300 is realized.

[0135] [Ninth Embodiment] Here, an application example of a semiconductor device having the above-described configuration to a power supply device will be described as a ninth embodiment.

[0136] FIG. 22 is a diagram for explaining an example of a power supply device according to the ninth embodiment. FIG. 22 shows an equivalent circuit diagram of an example of the power supply device. The power supply device 400 shown in FIG. 22 includes a primary side circuit 410, a secondary side circuit 420, and a transformer 430 provided between the primary side circuit 410 and the secondary side circuit 420.

[0137] The primary side circuit 410 includes the PFC circuit 300 as described in the eighth embodiment above, and an inverter circuit, for example, a full-bridge inverter circuit 440 connected between both terminals of the capacitor 350 of the PFC circuit 300. The full-bridge inverter circuit 440 includes a plurality of, here, four switch elements 441, switch element 442, switch element 443, and switch element 444 as an example.

[0138] The secondary circuit 420 includes a plurality of, here as an example, three switching elements 421, a switching element 422, and a switching element 423. For example, the semiconductor devices 1, 1A, 1B, 1C, 1D, 1E, etc. are used for the switching element 310 of the PFC circuit 300 included in the primary circuit 410 and the switching elements 441, 442, 443, 444 of the full-bridge inverter circuit 440 of the power supply device 400 having such a configuration. For example, for the switching elements 421, 422, 423 of the secondary circuit 420 of the power supply device 400, ordinary MIS-type field effect transistors using Si are used.

[0139] As described above, in the semiconductor devices 1, 1A, 1B, 1C, 1D, 1E, etc., the side surface 20a of the semiconductor layer 20 or the semiconductor layer 20A formed by the element isolation region 60 is covered with the insulating film 80 containing metal. By covering the side surface 20a of the semiconductor layer 20 or the semiconductor layer 20A with the insulating film 80, it is suppressed that the side surface 20a is exposed to the fluorine-based gas used for dry etching when forming the opening 71 in the protective film 70 covering the semiconductor layer 20 or the semiconductor layer 20A. Thereby, it is suppressed that a part of the side surface 20a of the semiconductor layer 20 or the semiconductor layer 20A disappears, and the contact between the gate electrode 30 and the channel layer 21 on the side surface 20a of the semiconductor layer 20 or the semiconductor layer 20A is suppressed. High-performance semiconductor devices 1, 1A, 1B, 1C, 1D, 1E, etc. are realized in which the performance degradation due to the short circuit caused by the contact between the gate electrode 30 and the channel layer 21 is suppressed. Such semiconductor devices 1, 1A, 1B, 1C, 1D, 1E, etc. are used, and a high-performance power supply device 400 is realized.

[0140] [Tenth Embodiment] Here, an application example of the semiconductor device having the above configuration to an amplifier will be described as the tenth embodiment.

[0141] FIG. 23 is a diagram for explaining an example of an amplifier according to the tenth embodiment. FIG. 23 shows an equivalent circuit diagram of an example of the amplifier. The amplifier 500 shown in FIG. 23 includes a digital predistortion circuit 510, a mixer 520, a mixer 530, and a power amplifier 540.

[0142] The digital predistortion circuit 510 compensates for the non-linear distortion of the input signal. The mixer 520 mixes the input signal SI with the non-linear distortion compensated and an AC signal. The power amplifier 540 amplifies the signal obtained by mixing the input signal SI with the AC signal. In the amplifier 500, for example, by switching the switch, the output signal SO can be mixed with the AC signal by the mixer 530 and sent to the digital predistortion circuit 510. The amplifier 500 can be used as a high-frequency amplifier or a high-output amplifier.

[0143] The semiconductor devices 1, 1A, 1B, 1C, 1D, 1E, etc. are used for the power amplifier 540 of the amplifier 500 having such a configuration. As described above, in the semiconductor devices 1, 1A, 1B, 1C, 1D, 1E, etc., the side surface 20a of the semiconductor layer 20 or the semiconductor layer 20A formed by the element isolation region 60 is covered with an insulating film 80 containing metal. By covering the side surface 20a of the semiconductor layer 20 or the semiconductor layer 20A with the insulating film 80, it is possible to suppress exposure to a fluorine-based gas used for dry etching when forming the opening 71 in the protective film 70 covering the semiconductor layer 20 or the semiconductor layer 20A. As a result, it is possible to suppress a part of the side surface 20a of the semiconductor layer 20 or the semiconductor layer 20A from disappearing, and also to suppress the contact between the gate electrode 30 and the channel layer 21 on the side surface 20a of the semiconductor layer 20 or the semiconductor layer 20A. High-performance semiconductor devices 1, 1A, 1B, 1C, 1D, 1E, etc. with reduced performance degradation due to short circuits caused by the contact between the gate electrode 30 and the channel layer 21 are realized. Such semiconductor devices 1, 1A, 1B, 1C, 1D, 1E, etc. are used, and a high-performance amplifier 500 is realized.

[0144] The various electronic devices (such as the semiconductor packages 200, PFC circuits 300, power supply devices 400, and amplifiers 500 described in the seventh to tenth embodiments) to which the semiconductor devices 1, 1A, 1B, 1C, 1D, 1E, etc. are applied can be mounted on various electronic equipment or electronic devices. For example, they can be mounted on various electronic equipment or electronic devices such as computers (personal computers, supercomputers, servers, etc.), smartphones, mobile phones, tablet terminals, sensors, cameras, audio equipment, measuring devices, inspection devices, manufacturing devices, transmitters, receivers, and radar devices.

[0145] Regarding the embodiments described above, the following additional remarks are disclosed. (Supplementary Note 1) A substrate, a semiconductor layer provided on the first surface side of the substrate, a first insulating film provided so as to cover the side of the semiconductor layer opposite to the substrate, having an opening, and containing Si, an electrode provided in the opening of the first insulating film and on the second surface side of the semiconductor layer facing the first surface of the substrate in a first direction parallel to the first surface of the substrate, a second insulating film provided between the second surface of the semiconductor layer and the electrode provided on the second surface side and containing a metal element, A semiconductor device including the above.

[0146] (Supplementary Note 2) The semiconductor device according to Supplementary Note 1, wherein the first insulating film extends to the second surface side of the semiconductor layer and is provided between the second insulating film and the electrode provided on the second surface side.

[0147] (Supplementary Note 3) The semiconductor layer includes a first layer including a channel layer and a carrier supply layer laminated on the channel layer, a second layer laminated on the side of the first layer opposite to the substrate, and the semiconductor device according to Supplementary Note 1 or 2, wherein the second insulating film covers the first layer of the first layer and the second layer on the second surface of the semiconductor layer.

[0148] ​(Supplementary Note 4) The opening in the first insulating film communicates with the semiconductor layer on the side of the semiconductor layer opposite to the substrate. The electrode provided in the opening is in contact with the semiconductor layer, and the semiconductor device according to Supplementary Note 3.

[0149] (Supplementary Note 5) The semiconductor layer includes a first layer including a channel layer and a carrier supply layer laminated on the channel layer, and a second layer laminated on the side of the first layer opposite to the substrate, and includes: The second insulating film covers the first layer and the second layer on the second surface of the semiconductor layer, and extends on the side of the semiconductor layer opposite to the substrate. The semiconductor device according to Supplementary Note 1 or 2.

[0150] (Supplementary Note 6) The opening in the first insulating film communicates with the second insulating film on the side of the semiconductor layer opposite to the substrate. The electrode provided in the opening is in contact with the second insulating film, and the semiconductor device according to Supplementary Note 5.

[0151] (Supplementary Note 7) The second insulating film covers the first layer on the second surface of the semiconductor layer, and has a first portion having a first thickness in the first direction parallel to the first surface of the substrate from the first layer; covers the second layer on the second surface of the semiconductor layer, extends on the side of the semiconductor layer opposite to the substrate, and has a second portion having a second thickness thinner than the first thickness in the first direction parallel to the first surface of the substrate from the second layer, and includes: The semiconductor device according to Supplementary Note 5 or 6.

[0152] (Supplementary Note 8) The second layer has a shape protruding in the first direction parallel to the first surface of the substrate more than the first layer. The semiconductor device according to any one of Supplementary Notes 3 to 7. (Supplementary Note 9) The second layer has a shape protruding in the first direction parallel to the first surface of the substrate more than the carrier supply layer of the first layer, The carrier supply layer of the first layer has a shape that protrudes in the first direction parallel to the first surface of the substrate more than the channel layer of the first layer. The semiconductor device according to any one of Appendices 3 to 8.

[0153] (Appendix 10) The thickness of the second layer in the second direction perpendicular to the first surface of the substrate is half or less of the thickness of the channel layer of the first layer. The semiconductor device according to any one of Appendices 3 to 9.

[0154] (Appendix 11) InGaAs is used for the channel layer of the first layer, InAlAs is used for the carrier supply layer of the first layer, InP or InGaP is used for the second layer. The semiconductor device according to any one of Appendices 3 to 10.

[0155] (Appendix 12) The metal element contained in the second insulating film has an electronegativity of 1.8 or less. The semiconductor device according to any one of Appendices 1 to 11. (Appendix 13) The second insulating film contains, as the metal element, one or more of Al, Hf, Zr, Ti, Ta, Mg, Sc, Y, La, and Sr. The semiconductor device according to any one of Appendices 1 to 12.

[0156] (Appendix 14) The second insulating film includes one or more of an oxide film, a nitride film, and an oxynitride film. The semiconductor device according to any one of Appendices 1 to 13. (Appendix 15) A step of forming a semiconductor layer provided on the first surface side of the substrate, A step of forming a first insulating film that is provided so as to cover the side of the semiconductor layer opposite to the substrate, has an opening, and contains Si, A step of forming an electrode provided on the opening of the first insulating film and on the second surface side of the semiconductor layer facing in the first direction parallel to the first surface of the substrate, including, A method of manufacturing a semiconductor device, including a step of forming a second insulating film containing a metal element, which is provided between the second surface of the semiconductor layer and the electrode provided on the second surface side, before the step of forming the first insulating film.

[0157] (Appendix 16) The step of forming the first insulating film includes a step of forming the first insulating film extending to the second surface side of the semiconductor layer, The first insulating film extending to the second surface side of the semiconductor layer is formed between the second insulating film and the electrode provided on the second surface side, and is the method of manufacturing a semiconductor device according to Appendix 15.

[0158] (Appendix 17) The step of forming the first insulating film includes a step of forming the opening by etching using a gas, and is the method of manufacturing a semiconductor device according to Appendix 15 or 16. (Appendix 18) A substrate, A semiconductor layer provided on the first surface side of the substrate, A first insulating film provided so as to cover the side of the semiconductor layer opposite to the substrate, having an opening, and containing Si, An electrode provided between the opening of the first insulating film and the second surface side of the semiconductor layer facing the first surface of the substrate in a first direction parallel to the first surface of the substrate, A second insulating film provided between the second surface of the semiconductor layer and the electrode provided on the second surface side, and containing a metal element, An electronic device including a semiconductor device including the above.

Explanation of Reference Numerals

[0159] 1, 1A, 1B, 1C, 1D, 1E, 100 Semiconductor device 10, 10A, 110 Substrate 10a Surface 11 Underlying substrate 12 Buffer layer 20, 20A, 120 Semiconductor layer 20a, 80a, 120a Side surface 21, 121 Channel layer 22, 25, 122 Carrier supply layer 23. 123 Etching Stop Layer 24. 124 Cap Layer 24a. 124a Recess 28. 128 Two-Dimensional Carrier Gas 30. 130 Gate Electrode 40. 140 Source Electrode 50. 150 Drain Electrode 60. 160 Element Isolation Region 70. 170 Protective Film 71. 171 Opening 80 Insulating Film 81 First Insulating Portion 82 Second Insulating Portion 90. 190 Flap Portion 180 Space 200 Semiconductor Package 210 Lead Frame 210a Die Pad 211 Gate Lead 212 Source Lead 213 Drain Lead 220 Resin 230 Wire 30a, 40a, 50a Pad 300 PFC Circuit 310, 421, 422, 423, 441, 442, 443, 444 Switch Element 320 Diode 330 Choke Coil 340, 350 Capacitor 360 Diode Bridge 370 AC Power Supply 400 Power Supply Device 410 Primary Side Circuit 420 Secondary Side Circuit 430 Transformer 440 Full Bridge Inverter Circuit 500 Amplifier 510 Digital Predistortion Circuit 520, 530 Mixer 540 Power Amplifier D1, D2 Direction Parts Q1 and Q2 Thicknesses of T1a, T1b, and T2

Claims

1. A substrate, A semiconductor layer provided on the first surface side of the substrate, A first insulating film provided so as to cover the side of the semiconductor layer opposite to the substrate, having an opening, and containing Si, An electrode provided in the opening of the first insulating film and on the second surface side of the semiconductor layer facing the first direction parallel to the first surface of the substrate, A second insulating film provided between the second surface of the semiconductor layer and the electrode provided on the second surface side and containing a metal element, A semiconductor device including the above.

2. The semiconductor device according to claim 1, wherein the first insulating film extends to the second surface side of the semiconductor layer and is provided between the second insulating film and the electrode provided on the second surface side.

3. The semiconductor layer includes: A first layer including a channel layer and a carrier supply layer laminated on the channel layer, A second layer laminated on the side of the first layer opposite to the substrate, The semiconductor device according to claim 1 or 2, wherein the second insulating film covers the first layer of the first layer and the second layer on the second surface of the semiconductor layer.

4. The semiconductor layer includes: A first layer including a channel layer and a carrier supply layer laminated on the channel layer, A second layer laminated on the side of the first layer opposite to the substrate, The semiconductor device according to claim 1 or 2, wherein the second insulating film covers the first layer and the second layer on the second surface of the semiconductor layer and extends to the side of the semiconductor layer opposite to the substrate.

5. The second insulating film includes: A first portion covering the first layer on the second surface of the semiconductor layer and having a first thickness in the first direction parallel to the first surface of the substrate from the first layer, A second portion covering the second layer on the second surface of the semiconductor layer, extending to the side of the semiconductor layer opposite to the substrate, and having a second thickness thinner than the first thickness in the first direction parallel to the first surface of the substrate from the second layer, The semiconductor device according to claim 4, including the above.

6. The semiconductor device according to any one of claims 3 to 5, wherein the second layer has a shape protruding in the first direction parallel to the first surface of the substrate more than the first layer.

7. The semiconductor device according to any one of claims 1 to 6, wherein the metal element contained in the second insulating film has an electronegativity of 1.8 or less.

8. A step of forming a semiconductor layer provided on the first surface side of the substrate, ​ ​ A step of forming a first insulating film which is provided so as to cover the side of the semiconductor layer opposite to the substrate, has an opening, and contains Si; A step of forming an electrode provided at the opening of the first insulating film and on the second surface side of the semiconductor layer facing in a first direction parallel to the first surface of the substrate; Including; A method of manufacturing a semiconductor device, including a step of forming a second insulating film containing a metal element, provided between the second surface of the semiconductor layer and the electrode provided on the second surface side, before the step of forming the first insulating film.

9. The method of manufacturing a semiconductor device according to claim 8, wherein the step of forming the first insulating film includes a step of forming the opening by etching using a gas.

10. A substrate; A semiconductor layer provided on the first surface side of the substrate; A first insulating film which is provided so as to cover the side of the semiconductor layer opposite to the substrate, has an opening, and contains Si; An electrode provided at the opening of the first insulating film and on the second surface side of the semiconductor layer facing in a first direction parallel to the first surface of the substrate; A second insulating film containing a metal element, provided between the second surface of the semiconductor layer and the electrode provided on the second surface side; An electronic device including a semiconductor device including the above.

Images