Periodic Development of Metal Oxide-Based Photoresist for Etch Stop Prevention

Abstract

A process is provided for the development of photopatterned metal or metal oxide based thin film photoresist after EUV exposure to remove non-volatile species and prevent etch stop. Repeated cycles of alternating treatments with an etchant and an oxidant, or treatment with an etchant followed by a cleaning agent, are effective techniques for removing the unwanted unexposed portions of the photoresist.

Description

Technical Field

[0001] Incorporation by Reference As part of this application, a PCT application form is filed simultaneously with this specification. Each application specified in the simultaneously filed PCT application form, for which this application claims benefit or priority, is hereby incorporated by reference in its entirety for all purposes into this specification.

Background Art

[0002] The fabrication of semiconductor devices such as integrated circuits is a multi-step process involving photolithography. Generally, this process includes depositing materials onto a wafer and patterning the materials using lithographic techniques to form the structural features (e.g., transistors and circuits) of the semiconductor device. Steps of a typical photolithography process known in the art include preparing a substrate, applying a photoresist by spin coating or the like, exposing the photoresist to light in a desired pattern to render the exposed areas of the photoresist somewhat soluble in a developer, developing by applying the developer to remove either the exposed or unexposed areas of the photoresist, and performing subsequent processing to form features on the areas of the substrate where the photoresist has been removed, such as by etching or material deposition.

[0003] One challenge in manufacturing devices with such small features is the ability to reliably and reproducibly form a photolithography mask with sufficient resolution. Current photolithography processes typically use 193 nm ultraviolet (UV) light to expose photoresist. The fact that the light has a wavelength significantly longer than the desired size of the features fabricated on the semiconductor substrate causes inherent problems. To achieve feature sizes smaller than the wavelength of the light, the use of complex resolution enhancement techniques such as multipatterning is necessary. Therefore, there has been great interest and research effort in the development of photolithography techniques that use short-wavelength light such as extreme ultraviolet (EUV) light having a wavelength of 10 nm to 15 nm, for example, 13.5 nm.

[0004] However, EUV photolithography processes can present challenges such as reduced output and light loss during patterning. Conventional chemically amplified resists (CARs) similar to those used in 193 nm UV lithography have potential drawbacks when used in EUV lithography because they have a low absorption coefficient, particularly in the EUV region, and can cause blurring or line edge roughness due to the diffusion of photoactivated species. Furthermore, small features patterned with conventional CAR materials can result in high aspect ratios that pose a risk of pattern collapse in order to provide the etching resistance necessary to pattern the underlying device layer. Therefore, there remains a need for improved EUV photoresist materials having properties such as reduced thickness, greater absorbance, and greater etching resistance.

[0005] The background description provided here is for the purpose of generally presenting the content of the present technology. Within the scope described in this background art section, research by the inventors named at the present time, as well as aspects of the description that cannot be separately regarded as prior art at the time of filing, are not admitted as prior art against the present technology, whether expressly or impliedly.

SUMMARY OF THE INVENTION

[0006] A process is provided for developing a metal or metal oxide-based thin film photoresist after EUV exposure to remove non-volatile species and prevent etch stop. Repeated cycles of alternating treatment with an etchant and an oxidizing agent, or treatment with an etchant followed by treatment with a cleaning agent, are effective techniques for removing unwanted unexposed portions of the photoresist.

[0007] Accordingly, in a first aspect, the present invention encompasses a method for processing a semiconductor substrate. In some embodiments, the method includes providing a photopatterned metal-containing resist on a semiconductor substrate on a pedestal within a process chamber, and developing the photopatterned metal-containing resist to form a resist mask by selectively removing a portion of the photopatterned metal-containing resist by exposing the photopatterned metal-containing resist to at least one cycle including alternating pulses of an etchant and pulses of an oxidizing agent.

[0008] In some embodiments, the pulses of the etchant and the pulses of the oxidizing agent are temporally separate.

[0009] In some embodiments, the pedestal is at a first temperature during the pulses of the etchant, and the oxidizing agent is fed into the process chamber at a second temperature.

[0010] In some embodiments, the pedestal is at a first temperature during the pulses of the etchant, and the pedestal is at a second temperature during the pulses of the oxidizing agent.

[0011] In some embodiments, the duration of the pulses of the etchant is from about 1 to about 120 seconds, and the duration of the pulses of the oxidizing agent is from about 1 to about 120 seconds.

[0012] In some embodiments, the first temperature is from about -60°C to about 120°C.

[0013] In some embodiments, the second temperature is from about 20°C to about 150°C.

[0014] In some embodiments, the second temperature is from about 50°C to about 250°C.

[0015] In some embodiments, the non-volatile by-products of the etchant pulse are removed from the photopatterned metal-containing resist.

[0016] In some embodiments, the photopatterned metal-containing resist is an organometallic oxide, a metal oxide, a metal, or an organometallic.

[0017] In some embodiments, the metal oxide is tin oxide.

[0018] In some embodiments, the etchant is a halide etchant.

[0019] In some embodiments, the halide etchant is hydrogen halide, hydrogen gas and halogen gas, organic halide, acyl halide, carbonyl halide, thionyl halide, or a combination thereof.

[0020] In some embodiments, the halide etchant is hydrogen fluoride, hydrogen chloride, boron trichloride, hydrogen bromide, hydrogen iodide, or a combination thereof.

[0021] In some embodiments, the etchant is an etchant plasma.

[0022] In some embodiments, the etchant plasma is generated remotely.

[0023] In some embodiments, the oxidizing agent is oxygen, ozone, hydrogen peroxide, water, nitrous oxide, nitric oxide, nitrogen dioxide, nitric acid, sulfur dioxide, chlorine, fluorine, bromine, iodine, or a combination thereof.

[0024] In some embodiments, the oxidizing agent is a gaseous oxidizing agent of water and oxygen or chlorine.

[0025] In some embodiments, the oxidizing agent is an oxidizing agent plasma.

[0026] In some embodiments, the oxidizing agent plasma is generated remotely.

[0027] In some embodiments, the method also includes exposing a photopatterned metal-containing resist to an inert plasma gas.

[0028] In some embodiments, the method also includes purging the process chamber with an inert gas between pulses of the etchant and the oxidizing agent, or after a cycle of pulses of the etchant and the oxidizing agent.

[0029] In some embodiments, developing a photopatterned metal-containing resist by exposing it to alternating pulses of an etchant and an oxidizing agent is dry developing the photopatterned metal-containing resist.

[0030] In some embodiments, developing a photopatterned metal-containing resist by exposing it to alternating pulses of an etchant and an oxidizing agent is wet developing the photopatterned metal-containing resist.

[0031] In some embodiments, each cycle has the same etchant pulse duration.

[0032] In a second aspect, the present invention encompasses a method of processing a semiconductor substrate. In some embodiments, the method includes providing a photopatterned metal-containing resist on a semiconductor substrate on a pedestal within a process chamber, and developing the photopatterned metal-containing resist to form a resist mask by exposing the photopatterned metal-containing resist to an etchant and subsequently exposing it to a cleaning agent to selectively remove a portion of the photopatterned metal-containing resist.

[0033] In some embodiments, the cleaning agent is water, methanol, ethanol, isopropanol, acetone, acetonitrile, tetrahydrofuran, dimethyl sulfide, or a combination thereof.

[0034] In some embodiments, the pedestal temperature is from about 10 °C to about 50 °C during exposure to the cleaning agent.

[0035] In some embodiments, the cleaning agent is a supercritical fluid.

[0036] In some embodiments, the supercritical fluid is a supercritical liquid with low surface tension.

[0037] In some embodiments, the supercritical liquid with low surface tension is carbon dioxide, sulfur dioxide, dimethyl ether, or a combination thereof.

[0038] In some embodiments, the process chamber pressure is from about 5 psi to about 3,000 psi during exposure to the cleaning agent.

[0039] In some embodiments, non-volatile by-products from exposure to the etchant are removed from the photopatterned metal-containing resist.

[0040] In some embodiments, the photopatterned metal-containing resist is an organometallic oxide, a metal, a metal oxide, or an organometallic.

[0041] In some embodiments, the metal oxide is tin oxide.

[0042] In some embodiments, the etchant is a halide etchant.

[0043] In some embodiments, the halide etchant is hydrogen halide, hydrogen gas and halogen gas, organic halide, acyl halide, carbonyl halide, thionyl halide, or a combination thereof.

[0044] In some embodiments, the halide etchant is hydrogen fluoride, hydrogen chloride, boron trichloride, hydrogen bromide, hydrogen iodide, or a combination thereof.

[0045] In some embodiments, the etchant is an etchant plasma.

[0046] In some embodiments, the etchant plasma is generated remotely.

[0047] In a third aspect, the present invention includes a method for promoting atomic layer etching on a substrate. In some embodiments, the method comprises providing a photopatterned metal-containing resist on a semiconductor substrate on a pedestal within a process chamber, and developing the photopatterned metal-containing resist by selectively removing a portion of the resist by exposing the photopatterned metal-containing resist to at least one cycle comprising alternating pulses of an etchant and pulses of an oxidant, thereby forming a resist mask, whereby etch stop due to non-volatile by-products of the etchant pulses is eliminated.

[0048] In a fourth aspect, the present invention encompasses a method for processing a semiconductor substrate. In some embodiments, the method comprises providing a photopatterned metal oxide EUV resist dry deposited on a semiconductor substrate on a pedestal within a process chamber, and selectively removing the EUV unexposed portions of the EUV resist by exposing to at least one cycle of alternately fed pulses of an etchant and pulses of an oxidant, thereby dry developing the photopatterned metal oxide EUV resist to form a resist hard mask.

[0049] In a fifth aspect, the present invention encompasses an apparatus for developing a resist. In some embodiments, the apparatus comprises a process chamber having a substrate support, a vacuum line coupled to the process chamber, an etchant and oxidant line coupled to the process chamber, and a controller configured with instructions for processing a semiconductor substrate, the instructions comprising providing a photopatterned metal-containing resist on the semiconductor substrate within the process chamber and selectively removing a portion of the resist by exposing to at least one cycle of alternately fed etchant pulses and oxidant pulses, thereby developing the photopatterned metal-containing resist to form a resist mask.

[0050] In some embodiments, the photopatterned metal-containing resist is a photopatterned metal-containing EUV resist, and the controller configured with instructions for developing the photopatterned metal-containing EUV resist has code for selectively removing the EUV unexposed portions of the EUV resist compared to the EUV exposed portions by at least one cycle of alternately fed etchant pulses and oxidant pulses to form a resist mask.

[0051] In some embodiments, the apparatus also comprises one or more heaters coupled to the substrate support, the one or more heaters comprising one or more heaters having a plurality of independently controllable temperature control zones.

[0052] In some embodiments, the apparatus also includes a heated oxidant feed line.

[0053]

[0054] These and other features of the disclosed embodiments are described in detail below with reference to the associated drawings.

Brief Description of the Drawings

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DETAILED DESCRIPTION OF THE INVENTION

[0067] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the presented embodiments. The disclosed embodiments can be practiced without some or all of these specific details. In other instances, well-known process operations have not been described in detail so as not to unnecessarily obscure the disclosed embodiments. The disclosed embodiments are described in conjunction with specific embodiments, but it will be understood that the disclosed embodiments are not intended to be limiting.

[0068] The embodiments disclosed below describe the deposition of materials onto substrates such as wafers, substrates, or other workpieces. Workpieces can be of various shapes, sizes, and materials. In this application, the terms "semiconductor wafer", "wafer", "substrate", "wafer substrate", and "partially fabricated integrated circuit" are used interchangeably. Those skilled in the art will understand that the term "partially fabricated integrated circuit" can refer to a silicon wafer at any of many stages of integrated circuit fabrication. Wafers or substrates used in the semiconductor device industry typically have a diameter of 200 mm, or 300 mm, or 450 mm. Unless otherwise specified, the process details described herein (e.g., flow rates, output levels, etc.) relate to a process chamber configured to process a 300 mm diameter substrate, or a process chamber that can be scaled according to other substrate sizes or chambers. In addition to semiconductor wafers, other workpieces that can be used in the embodiments disclosed herein include various articles such as printed circuit boards. The processes and apparatus can be used in the fabrication of semiconductor devices, displays, LEDs, solar power panels, etc.

[0069] A halide means an anion of F, Cl, Br, or I.

[0070] As used herein, the term "about" means + / - 10% of any recited value, unless otherwise specified. As used herein, this term modifies any recited value, range of values, or endpoints of one or more ranges.

[0071] As used herein, the terms "top", "bottom", "upper", "lower", "above", and "below" are used to provide a relative relationship between structures. The use of these terms does not imply or require that a particular structure must be located in a particular location within the device.

[0072] As used herein, the expression "at least one of A, B, and C" should be interpreted in the sense of a logical (A or B or C) using non-exclusive logical OR, and should not be interpreted in the sense of "at least one of A, at least one of B, and at least one of C".

[0073] "Atomic layer deposition" (ALD) means a vapor deposition process in which deposition cycles, preferably a plurality of consecutive deposition cycles, are performed in a process chamber (i.e., a deposition chamber). Typically, during each cycle, the precursor chemisorbs onto the deposition surface (i.e., the substrate assembly surface or a previously deposited underlying surface such as the material from a previous ALD cycle) to form a monolayer or sub-monolayer that does not readily react with additional precursors (i.e., a self-limiting reaction). Thereafter, if desired, a reactant (i.e., another precursor or reaction gas) can be introduced into the process chamber for use in converting the chemisorbed precursor to the desired material on the deposition surface. Typically, this reactant is capable of reacting with the chemisorbed precursor. Additionally, a purge step can be utilized during each cycle to remove excess precursor from the process chamber after conversion of the chemisorbed precursor and / or to remove excess reactant and / or reaction by-products from the process chamber.

[0074] "Deposition" or "vapor deposition" means a process in which a metal layer is formed on one or more surfaces of a substrate from a vaporized precursor composition containing one or more metal-containing compounds. The metal-containing compounds are vaporized and directed towards and / or contacted with one or more surfaces of a substrate (i.e., a semiconductor substrate or semiconductor assembly) placed in a deposition chamber. Typically, the substrate is heated. These metal-containing compounds form a thin, uniform, non-volatile metal-containing layer on the surface of the substrate. One operation of the method is one cycle, and it is possible to repeat the process for the number of cycles required to obtain the desired metal thickness.

[0075] "Etchant" means any compound used to remove materials such as layers, by-products, or contaminants from a surface.

[0076] " Wafer " means a material that may include the substrate and substrate layers to be etched. In some embodiments, the substrate layer includes a spin-on carbon (SoC) or other material, such as an ashing-capable hard mask of silicon, silicon oxide, silicon nitride, silicon carbide, etc. In some embodiments, the substrate layer may be a layer stack disposed on the substrate.

[0077] The "photo-patterned metal-containing resist film" means a thin film that may have an organometallic-containing layer disposed on a substrate layer to be etched. The photo-patterned metal-containing EUV resist film may have a thickness of about 5 nm to about 50 nm, or about 10 nm to about 30 nm. The photo-patterned metal-containing EUV resist film may be provided in a process chamber after photo-patterning and / or after PEB treatment in an EUV scanner, as described above. The photo-patterned metal-containing EUV resist film includes a non-EUV exposure region and an EUV exposure region. The non-EUV exposure region of the photo-patterned metal-containing EUV resist film can be removed in a dry development process by exposing it to a flow of dry development chemicals without applying plasma. The dry development chemicals may include hydrogen halide or halide-containing chemicals such as hydrogen and halogen gases. By removing the non-EUV exposure region after development, a resist mask is formed. Thereafter, it is possible to etch the substrate layer to be etched using the resist mask to provide a desired structure.

[0078] "By-product" means any compound that can be an impurity, decomposition product, or contaminant of the gas fed into the deposition chamber.

[0079] "Feed line" means any process equipment such as pipes, tubes, or conduits that can be used to convey or carry a gas (e.g., a reactant and / or a precursor). In a semiconductor manufacturing process, a precursor feed line can be used to convey a precursor to a deposition chamber and can be formed of stainless steel or nickel alloy.

[0080] The present disclosure generally relates to the field of semiconductor processing. In some aspects, the present disclosure is directed to processes and apparatuses for developing a photoresist (e.g., an EUV-sensitive metal and / or metal oxide-containing photoresist) in a periodic dry development process in combination with an oxidizing agent or in combination with a cleaning agent using an etchant to form a patterning mask in the context of EUV patterning. Such processes can advantageously widen the process window of dry development and / or extend the applicability of dry development to different metal or metal oxide-based photoresist systems.

[0081] Reference will now be made in detail to specific embodiments of the present disclosure. Examples of specific embodiments are shown in the accompanying drawings. While the present disclosure will be described in conjunction with these specific embodiments, it is to be understood that the present disclosure is not intended to be limited to such specific embodiments. On the contrary, the present disclosure is intended to cover alternatives, modifications, and equivalents that may be included within the spirit and scope of the present disclosure. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. The present disclosure may be practiced without some or all of these specific details. In other instances, well-known process operations have not been described in detail so as not to unnecessarily obscure the present disclosure.

[0082] Patterning of thin films in semiconductor processing is often an important step in semiconductor fabrication. Patterning involves lithography. In conventional photolithography, such as 193 nm photolithography, a pattern is printed by emitting photons from a photon source onto a mask and printing that pattern onto a photosensitive photoresist, thereby causing a chemical reaction within the photoresist and, after development, removing specific portions of the photoresist to form a pattern.

[0083] Advanced technology nodes (as defined by the International Technology Roadmap for Semiconductors) include 22 nm, 16 nm, and subsequent nodes. For example, at the 16 nm node, the width of a typical via or line in a damascene structure is typically about 30 nm or less. Scaling of features on advanced semiconductor integrated circuits (ICs) and other devices drives lithography to improve resolution.

[0084] Extreme ultraviolet (EUV) lithography can extend lithography technology by shifting to an imaging source wavelength shorter than what can be achieved with conventional photolithography methods. An EUV light source with a wavelength of about 10 - 20 nm, or 11 - 14 nm, such as a wavelength of 13.5 nm, can be used in state-of-the-art lithography tools, also called scanners. EUV radiation operates in a vacuum because it is strongly absorbed by a wide range of solid and fluid materials, including quartz and water vapor.

[0085] EUV lithography utilizes EUV resist patterned to form a mask for use in etching the underlying layer. The EUV resist may be a polymer-based chemically amplified resist (CAR) obtained by a liquid-based spin-on technique. Alternatives to CAR are available from Inpria of Corvallis, Oregon, and are, for example, metal oxide-containing films that are directly photopatternable, such as those described in U.S. Patent Application Publication No. 2017 / 0102612, U.S. Patent Application Publication No. 2016 / 021660, and U.S. Patent Application Publication No. 2016 / 0116839, the disclosures of which are incorporated herein by reference at least with respect to the disclosure of the photopatternable metal oxide-containing films. Such films may be provided by spin-on techniques or dry vapor deposition. The metal oxide-containing films can be patterned directly (i.e., without using a separate photoresist) by EUV exposure in a vacuum atmosphere that provides a patterning resolution of less than 30 nm, as described in, for example, U.S. Patent No. 9,996,004, issued June 12, 2018, entitled EUV PHOTOPATTERNING OF VAPOR-DEPOSITED METAL OXIDE-CONTAINING HARDMASKS, and / or Application PCT / US19 / 31618, filed May 9, 2019, entitled METHODS FOR MAKING EUV PATTERNABLE HARD MASKS, the disclosures of which are incorporated herein by reference at least with respect to the composition, deposition, and patterning of the directly photopatternable metal oxide film for forming an EUV resist mask. Generally, patterning involves exposing the EUV resist with EUV radiation to form a photopattern in the resist, followed by development to remove a portion of the resist according to the photopattern to form the mask.

[0086] This disclosure relates to lithographic patterning techniques and materials exemplified by EUV lithography, but it should also be understood that it is applicable to other next-generation lithography techniques. In addition to EUV including the standard 13.5 nm EUV wavelength currently in use and being developed, the radiation sources most relevant to such lithography generally refer to DUV (deep UV), which refers to the use of an excimer laser source of 248 nm or 193 nm, X-rays including EUV in the lower energy range of the X-ray range, and e-beams that can cover a wide energy range. The particular method may depend on the particular materials and applications used in the semiconductor substrate and the final semiconductor device. Thus, the methods described in this application are merely illustrative of methods and materials that may be used in this technology.

[0087] EUV resists that are directly photo-patternable can be composed of, or contain, metals and / or metal oxides mixed within an organic component. The metals / metal oxides are very promising in that they can enhance the absorption of EUV photons, generate secondary electrons, and / or exhibit high etching selectivity with respect to the underlying film stack and device layers. To date, these resists have been developed using wet (solvent) techniques, which require the wafers to be transferred to a track where the wafers are exposed to the developing solvent, dried, and baked. Wet development not only limits productivity but can also cause line collapse due to surface tension effects and / or delamination between layers.

[0088] To overcome these problems by eliminating delamination and interfacial fracture of the substrate, dry development techniques have been proposed. Dry development can improve performance (e.g., prevent line collapse and delamination due to surface tension in wet development) and can improve throughput (e.g., by avoiding wet development tracks). Other advantages can include elimination of the use of organic solvent developers, reduced sensitivity to adhesion problems, increased EUV absorption due to improved dose efficiency, and elimination of solubility-based limitations. Dry development provides further adjustability and can also perform further critical dimension (CD) control and scum removal.

[0089] Dry development has unique issues, including etching selectivity between unexposed resist material and EUV-exposed resist material, and the dose for effective resist exposure can be higher when compared to wet development. Suboptimal selectivity can also round the PR corners due to long exposure under the etching gas, which may increase the variation of line CD in the next transfer etching step.

[0090] Development of EUV resist According to various aspects of the present disclosure, a photopatterned metal-containing photoresist is developed by exposure to a halide-containing chemical. An EUV-sensitive metal or metal oxide-containing film, such as an organotin oxide, is disposed on a semiconductor substrate. The EUV-sensitive metal or metal oxide-containing film is directly patterned by EUV exposure in a vacuum atmosphere. Next, a pattern is developed using a developing chemical to form a resist mask. In some embodiments, the developing chemical is a dry developing chemical. In some embodiments, the dry developing chemical includes hydrogen and a halide. Such dry development techniques can be performed while flowing a hydrogen and halide dry developing chemical and using either a mild plasma (high pressure, low power) or a thermal process. The present disclosure provides a process and apparatus configured to develop a metal-containing resist as part of a resist mask formation process.

[0091] Metals and / or metal oxide photoresists are attractive material candidates for advanced photolithography. Their ability to function at higher resolution, higher etching selectivity, and lower doses enables enhanced light absorption and secondary electron generation. After EUV exposure, wet development is conventionally applied to remove unwanted materials. However, this process can lead to an increase in defects due to interface breakdown and / or line collapse caused by surface tension.

[0092] Dry development helps overcome these problems by eliminating interlayer delamination and interface breakdown of the substrate. However, complete removal of unwanted unexposed portions of the photoresist depends on the production of volatile and stable by-products of dry development. The volatility and stability of by-products from dry development can be affected by the organic ligands utilized in metal and / or metal oxide photoresist systems. In some cases, the by-products are non-volatile or, although volatile, are unstable. When the by-products are volatile but unstable, the by-products may further decompose into non-volatile species. Non-volatile by-products result in etch stop and incomplete development, increasing the risk of high surface roughness and defect formation.

[0093] An optional post-application bake (PAB) is performed after deposition of the EUV-patternable film and before EUV exposure. The PAB process can involve a combination of heat treatment, exposure to chemicals, and moisture to increase the EUV sensitivity of the EUV-patternable film, thereby reducing the EUV dose to develop a pattern in the EUV-patternable film. The PAB treatment temperature can be adjusted and optimized to increase the sensitivity of the EUV-patternable film. For example, the treatment temperature can be about 90 °C to about 200 °C, or about 150 °C to about 190 °C. In some embodiments, the PAB process can be performed at a pressure between atmospheric pressure and vacuum for a treatment duration of about 1 to 15 minutes, such as about 2 minutes. In some embodiments, the PAB process is performed at a temperature of about 100 °C to 200 °C for about 1 to 2 minutes.

[0094] The metal-containing EUV resist film is exposed to EUV radiation to develop a pattern. Generally speaking, EUV exposure causes changes in the chemical composition and cross-linking in the metal-containing EUV resist film, resulting in a contrast in etching selectivity that can be utilized in subsequent development.

[0095] Next, the metal-containing EUV resist film can typically be patterned by exposing regions of the film to EUV light, typically under relatively high vacuum. EUV devices and imaging methods useful herein include those known in the art. In particular, as described above, the exposed area of the film is formed by EUV patterning with physical or chemical properties changed compared to the unexposed area. For example, in the exposed area, cleavage of the metal-carbon bond may occur by elimination of beta hydride, leaving reactive and accessible metal hydride functional groups that can be converted to hydroxide and cross-linked metal oxide moieties via metal-oxygen bridges during subsequent post-exposure bake (PEB) steps. This process can be used to form a chemical contrast for development as a negative resist. Generally, the higher the number of beta Hs in the alkyl group, the higher the sensitivity of the film. This can also be explained as a weak Sn-C bond with more branching. Following exposure, baking the metal-containing EUV resist film can cause further cross-linking of the metal oxide film. The difference in properties between the exposed and unexposed areas can be utilized in subsequent processing, such as dissolving the unexposed area or depositing material on the exposed area. For example, a dry method can be used to develop the pattern and form a metal oxide-containing mask.

[0096] In particular, in various embodiments, the hydrocarbyl-terminated tin oxide present on the surface is converted to hydrogen-terminated tin oxide in the exposed region of the imaging layer, particularly when the exposure is carried out in vacuum using EUV. However, by removing the exposed imaging layer from vacuum to air, or by controlling the introduction of oxygen, ozone, H2O2, or water, the surface Sn-H may oxidize to Sn-OH. The difference in properties between the exposed and unexposed areas can be utilized in subsequent processing, for example, by reacting one or both of the irradiated area, non-irradiated area, or both with one or more reagents to selectively add material to or remove material from the imaging layer.

[0097] Without limiting the mechanism, function, or utility of the present technology, for example, EUV exposure at a dose of 10 mJ / cm 2 ~100 mJ / cm 2 results in cleavage of the Sn-C bond, thereby losing the alkyl substituent and reducing steric hindrance, thus enabling the collapse of the low-density film. In addition, the reactive metal-H bond generated by the beta-hydrogen elimination reaction can react with adjacent active groups such as hydroxyl in the film, which results in further cross-linking and densification and can form a chemical contrast between the exposed area and the unexposed area.

[0098] After exposing the metal-containing EUV resist film to EUV light, a photopatterned metal-containing EUV resist is provided. The photopatterned metal-containing EUV resist includes an EUV exposure region and an EUV unexposed region.

[0099] An optional post-exposure bake (PEB) is performed to further enhance the contrast of the etching selectivity of the photopatterned metal-containing EUV resist. The photopatterned metal-containing EUV resist can be heat-treated in the presence of various chemical species to promote cross-linking in the EUV exposure region, or can simply be baked on a hot plate in ambient air at, for example, 150 °C to 250 °C for 1 to 5 minutes (for example, 2 minutes at 190 °C).

[0100] In various embodiments, the bake strategy involves careful control of the bake atmosphere, introduction of reactive gases, and / or careful control of the ramp rate of the bake temperature. Examples of useful reactive gases include, for example, air, H2O, H2O2 vapor, CO2, CO, O2, O3, CH4, CH3OH, N2, H2, NH3, N2O, NO, alcohol, acetylacetone, formic acid, Ar, He, or mixtures thereof. The PEB process is designed to (1) drive complete evaporation of the organic fragments generated during EUV exposure, (2) oxidize any Sn-H, Sn-Sn, or Sn radical species generated by EUV exposure to metal hydroxides, and (3) promote cross-linking between adjacent Sn-OH groups to form a more highly cross-linked SnO2-like network. The bake temperature is carefully selected to achieve optimal EUV lithography performance. If the PEB temperature is too low, cross-linking will be insufficient, and as a result, the chemical contrast for development at a given dose may decrease. If the PEB temperature is too high, adverse effects such as intense oxidation and film shrinkage in the unexposed regions (the regions removed by development of the patterned film to form the mask in this example), as well as unwanted interdiffusion at the interface between the photopatterned metal-containing EUV resist and the underlying layer, may occur, both of which may contribute to loss of chemical contrast due to insoluble scum and an increase in defect density. The PEB process temperature can be from about 100°C to about 300°C, from about 170°C to about 290°C, or from about 200°C to about 240°C. In some embodiments, the PEB process can be carried out at a pressure between atmospheric pressure and vacuum for a treatment duration of about 1 to 15 minutes, such as about 2 minutes. In some embodiments, the PEB heat treatment can be repeated to further enhance the etch selectivity.

[0101] The photo-patterned metal-containing EUV resist is developed to form a resist mask. In various embodiments, the exposed area is removed (positive type) or the unexposed area is removed (negative type). In some embodiments, development can include selective deposition onto either the exposed or unexposed area of the photo-patterned metal-containing EUV resist, followed by an etching operation. In various embodiments, these processes can be either dry processes or wet processes. Development can, in some embodiments, be performed without applying plasma. Or, development can be performed by a flow of hydrogen and halides (e.g., H2, Cl2, and / or Br2) that are activated within a remote plasma source or by exposure to remote UV radiation. The photoresist for development can include an element selected from the group consisting of tin, hafnium, tellurium, bismuth, indium, antimony, iodine, and germanium. The element can have a high cross-section for absorbing patterning radiation. In some embodiments, the element can have a high EUV absorption cross-section. In some embodiments, the metal-containing EUV resist can have an overall absorption rate of greater than 30%. In a fully dry lithography process, this enables more efficient utilization of EUV photons and allows for the development of thicker and more EUV-opaque resists.

[0102] An example of the development process involves subjecting an organic tin oxide-containing EUV-sensitive photoresist thin film (e.g., having a thickness of 10 - 30 nm, e.g., 20 nm) to EUV exposure dose and post-exposure bake, and then developing it. The photoresist film can be deposited, for example, based on a gas-phase reaction of an organic tin precursor such as isopropyl(tris)(dimethylamino)tin with water vapor, or can be a spin-on film containing tin clusters in an organic matrix.

[0103] The photo-patterned metal-containing EUV resist is developed by exposure to a developing chemical, which is a halide-containing chemical. In some embodiments, the developing chemical comprises hydrogen and a halide, such as a hydrogen halide (e.g., HBr or HCl) or hydrogen and a halogen gas (e.g., H2 and Cl2). In some embodiments, the developing chemical comprises a hydrogen halide, hydrogen and a halogen gas, boron trichloride, or a combination thereof. Development of the EUV resist can be performed by wet development using a halide-containing chemical or dry development using a hydrogen halide-containing chemical. In embodiments where the EUV resist is developed using wet development, the wet development can be combined with other wet processing operations, such as wet deposition (e.g., spin-on deposition) of the metal-containing EUV resist film. Alternatively, the wet development may be combined with other dry processing operations, such as vapor deposition (e.g., CVD) of the metal-containing EUV resist film. In embodiments where the EUV resist is developed using dry development, the dry development can be combined with other dry processing operations, such as dry deposition (e.g., CVD) of the metal-containing EUV resist film. In an alternative embodiment where the EUV resist is developed using dry development, the dry development may be combined with other wet processing operations, such as wet deposition (e.g., spin-on deposition) of the metal-containing EUV resist film.

[0104] In some embodiments, the processing of the semiconductor substrate may combine all dry steps including film formation by vapor deposition, EUV lithography patterning, and dry development. In fact, each of operations 102-112 of process 100 may be a dry processing operation. Such processing operations can avoid the material costs and production costs associated with wet processing operations such as wet development. Dry processing can provide additional adjustability and enable additional critical dimension (CD) control and scum removal. Wet processing generally involves moisture and / or oxygen and is more likely to cause scum formation. Wet development is limited by solubility and cluster size, while dry development is not limited by solubility and cluster size. Wet development is more likely to cause problems of pattern collapse and delamination that dry development avoids. In addition, by using all-dry processing operations, integration within an interconnected vacuum processing chamber can be facilitated without exposure to ambient air or trace contaminants contained therein and contamination therefrom. For example, it will be understood that the PEB heat treatment in which the exposed area undergoes further crosslinking may be performed in the same chamber as the development, but the PEB heat treatment may also be performed in a separate chamber.

[0105] The development process can be performed by feeding the development chemical in a liquid phase or a gas phase. In some embodiments, the dry development process can be performed by using either a mild plasma (high pressure, low power) or a thermal process while flowing a hydrogen halide-containing dry development chemical such as HF, HCl, HBr, or HI. For example, dry development can be performed in a thermal process using a dry development chemical such as HCl or HBr. In some embodiments, the hydrogen halide-containing chemical can rapidly remove non-exposed materials and leave a pattern of the exposed film that can be transferred to the underlying layer by a plasma-based etching process, such as a conventional etching process.

[0106] In a thermal imaging process, a substrate is exposed to a developing chemical (e.g., a Lewis acid) within a process chamber (e.g., an oven). In some embodiments, a vacuum line may be coupled to the process chamber for pressure control, and a developing chemical line may be coupled to the process chamber for feeding the developing chemical into the process chamber. The process chamber may include one or more heaters for temperature control, such as a heater coupled to a substrate support within the process chamber for substrate temperature control. In some embodiments, the interior of the chamber can be coated with a corrosion-resistant film, such as an organic polymer or an inorganic coating. One such coating is polytetrafluoroethylene (PTFE), e.g., Teflon 1M. Such materials can be used in the thermal processes of the present disclosure without the risk of removal by plasma exposure.

[0107] In a thermal development process, a photopatterned metal-containing EUV resist is exposed to a developing chemical at a temperature optimized for the etching selectivity between the exposed and unexposed regions. At low temperatures, the contrast in etching selectivity may increase, and at high temperatures, the contrast in etching selectivity may decrease. In some embodiments, the temperature may be from about -60°C to about 120°C, from about -20°C to about 60°C, or from about -20°C to about 20°C, such as about -10°C. The chamber pressure can be adjusted, and the chamber pressure may affect the etching selectivity between the exposed and unexposed regions during development. In some embodiments, the chamber pressure is relatively low and may be without dilution, and the chamber pressure may be from about 0.1 mTorr to about 300 mTorr, from about 0.2 mTorr to about 100 mTorr, or from about 0.5 mTorr to about 50 mTorr. In some embodiments, the chamber pressure may be from about 20 mTorr to about 800 mTorr, or from about 20 mTorr to about 500 mTorr, such as about 300 mTorr. In some embodiments, the chamber pressure is relatively high with high flow rate and may be with dilution, and the chamber pressure may be from about 100 Torr to about 760 Torr, or from about 200 Torr to about 760 Torr. The flow rate of the reactant can be adjusted, and the flow of the reactant may affect the etching selectivity between the exposed and unexposed regions during development. In some embodiments, the flow of the reactant may be from about 50 sccm to about 2000 sccm, from about 100 sccm to about 2000 sccm, or from about 100 sccm to about 1000 sccm, such as about 500 sccm. In the case of high flow rate, the flow of the reactant may be from about 1 L to about 10 L. The duration of exposure can be adjusted in the thermal development process. The duration of exposure may depend, among other factors, on the amount of resist desired to be removed, the developing chemical, the amount of cross-linking in the resist, and the composition and properties of the resist. In some embodiments, the duration of exposure may be from about 5 seconds to about 5 minutes, from about 10 seconds to about 3 minutes, or from about 10 seconds to about 1 minute.

[0108] The thermal imaging process can expose a photo-patterned metal-containing EUV resist to specific halide-containing chemicals in the gas phase or liquid phase. In some embodiments, the developing chemical can include hydrogen halides, hydrogen and halogen gases, boron trichloride, organic halides, acyl halides, carbonyl halides, thionyl halides, or mixtures thereof. The hydrogen halides can include, but are not limited to, HF, HCl, HBr, and HI. For example, the hydrogen halide can be HCl or HBr. The hydrogen and halogen gases can include, but are not limited to, hydrogen gas (H2) mixed with F2, Cl2, Br2, or I2. Boron trichloride (BCl3) can be used in combination with any of the aforementioned hydrogen halides or hydrogen and halogen gases. The organic halides can include, but are not limited to, C x H y F z 、C x H y Cl z 、C x H y Br z 、およびC x H y I z where x, y, and z are values of 0 or greater. The acyl halides can include, but are not limited to, CH3COF, CH3COCl, CH3COBr, and CH3COI. The carbonyl halides can include, but are not limited to, COF2, COCl2, COBr2, and COI2. The thionyl halides can include, but are not limited to, SOF2, SOCl2, SoBr2, and SOI2. In some embodiments, the halide-containing chemical can be flowed with or without an inert gas / carrier gas such as He, Ne, Ar, Xe, and N2.

[0109] In the formation of semiconductor devices, various layers can be selectively etched. It is possible to provide highly selective etching using atomic layer etching. In atomic layer etching (ALE), a cyclic process is provided. The cyclic process can have a first step of modifying a portion of the etching layer and a second step of removing the modified portion of the etching layer. Such ALE can modify a portion of the etching layer using a self-limiting process. The self-limiting process can modify several monolayers of the etching layer that form a self-limiting layer. In such a case, the removal of the modified portion of the etching layer can remove only a small number of atomic layers of the etching layer. As a result, many cycles are required to substantially etch a portion of the etching layer. Each cycle can be longer than 12 seconds. As a result, the ALE process can take a long time to substantially etch a portion of the etching layer.

[0110] The ALE process used to etch a carbon-containing etching layer such as amorphous carbon uses a low bias voltage. In such a process, the low bias voltage can be applied for several seconds to perform ALE while preventing or reducing sputtering caused by a higher bias. Some of the drawbacks for such a process using a low bias are that such an ALE process is slow and the ion directivity under low bias for the ALE process is not high. Since the ion directivity is not high, the resulting feature does not have a high aspect ratio of height to width.

[0111] The atomic layer etching process is described in U.S. Patent No. 10,566,212, titled "Designer Atomic Layer Etching" by Kanarik, issued on February 18, 2020; U.S. Patent No. 10,763,083, titled "High Energy Atomic Layer Etching" by Yang et al., issued on September 1, 2020; U.S. Patent Application Publication No. 2021 / 0005425, titled "Atomic Layer Etching and Smoothing of Refractory Metals and Other High Surface Binding Energy Materials" by Yang et al., published on January 2, 2021; International Publication No. 2020 / 223152, titled "Atomic Layer Etching for Subtractive Metal Etch" by Yang et al., published on November 5, 2020; and U.S. Provisional Patent Application No. 63 / 322,535, titled "Fast Atomic Layer Etch", filed on March 22, 2022, all of which are incorporated by reference for all purposes.

[0112] The thermal development process can be performed without plasma. By applying a non-plasma thermal approach, multiple wafers can be batch-developed simultaneously in a low-cost thermal vacuum chamber / oven, significantly improving productivity. However, in some embodiments, exposure to plasma may follow the thermal development process. The subsequent exposure to plasma may be performed for desorption, descumming, smoothing, or other processing operations.

[0113] In a plasma development process, a photo-patterned metal-containing EUV resist is exposed to a development chemical containing radicals / ions of one or more gases. The process chamber for processing the semiconductor substrate may be a plasma generation chamber or may be coupled to a plasma generation chamber remote from the process chamber. In some embodiments, dry development may be performed by remote plasma. The plasma generation chamber may be an inductively coupled plasma (ICP) reactor, a capacitively coupled plasma (CCP) reactor, or a capacitively coupled plasma (CCP) reactor that uses equipment and techniques known in the art. An electromagnetic field acts on one or more gases to generate a plasma in the plasma generation chamber. Ions and / or radicals from the remote plasma can interact with the photo-patterned metal-containing EUV resist. In some embodiments, a vacuum line may be coupled to the process chamber for pressure control, and a development chemical line may be coupled to the plasma generation chamber for feeding one or more gases to the plasma generation chamber. The process chamber may include one or more heaters for temperature control, such as a heater coupled to a substrate support within the process chamber for substrate temperature control. In some embodiments, the interior of the process chamber can be coated with a corrosion-resistant film such as an organic polymer or an inorganic coating. One such coating is polytetrafluoroethylene (PTFE), for example, Teflon 1M. Such materials can be used in the thermal processes of the present disclosure without the risk of removal by plasma exposure.

[0114] In the plasma development process, the photopatterned metal-containing EUV resist is exposed to a remote plasma under conditions where the etching selectivity between the exposed and unexposed regions is optimized. The conditions can be optimized to generate a mild plasma, which can be characterized by high pressure and low power. The chamber pressure can be adjusted, and the chamber pressure may affect the etching selectivity between the exposed and unexposed regions during development. In some embodiments, the chamber pressure may be about 5 mTorr or more, or about 15 mTorr or more. In some embodiments, the chamber pressure is relatively high at a high flow rate and may involve dilution, and the chamber pressure may be about 100 Torr to about 760 Torr, or about 200 Torr to about 760 Torr. The RF power level can be adjusted, and the RF power may affect etching selectivity, roughness, descum, and other characteristics of the development. In some embodiments, the RF power may be about 1000 W or less, about 800 W or less, or about 500 W or less. The temperature can be adjusted, and the temperature may affect various aspects of the development such as etching selectivity. In some embodiments, the temperature may be about -60 °C to about 300 °C, about 0 °C to about 300 °C, or about 30 °C to about 120 °C. The gas flow rate can be adjusted, and the gas flow may affect the etching selectivity between the exposed and unexposed regions during development. In some embodiments, the gas flow rate may be about 50 sccm to about 2000 sccm, about 100 sccm to about 2000 sccm, or about 200 sccm to about 1000 sccm, for example about 500 sccm. The exposure duration can be adjusted in the plasma development process. The exposure duration may depend, among other factors, on the amount of resist to be removed, the development chemistry, the amount of crosslinking in the resist, and the composition and properties of the resist. In some embodiments, the exposure duration may be about 1 second to about 50 minutes, about 3 seconds to about 20 minutes, or about 10 seconds to about 6 minutes.

[0115] The plasma development process can expose a photopatterned metal-containing EUV resist to radicals of a specific halide-containing gas. In some embodiments, the radicals are generated from a remote plasma source. For example, plasma development can expose a photopatterned metal-containing EUV resist to radicals of hydrogen and halide gas generated from a remote plasma source. In some embodiments, the halide-containing gas can include hydrogen halide, hydrogen and halogen gas, boron trichloride, organic halide, acyl halide, carbonyl halide, thionyl halide, or mixtures thereof. Hydrogen halide can include, but is not limited to, hydrogen fluoride (HF), hydrogen chloride (HCl), hydrogen bromide (HBr), and hydrogen iodide (HI). For example, the hydrogen halide can be HCl or HBr. Hydrogen and halogen gas can include, but is not limited to, hydrogen gas (H2) mixed with fluorine gas (F2), chlorine gas (Cl2), bromine gas (Br2), or iodine gas (I2). Organic halides can include, but are not limited to, C x H y F z 、C x H y Cl z 、C x H y Br z 、and C x H y I z where x, y, and z are values of 0 or more. Acyl halides can include, but are not limited to, CH3COF, CH3COCl, CH3COBr, and CH3COI. Carbonyl halides can include, but are not limited to, COF2, COCl2, COBr2, and COI2. Thionyl halides can include, but are not limited to, SOF2, SOCl2, SoBr2, and SOI2. In some embodiments, the halide-containing gas can be flowed with or without an inert gas / carrier gas such as He, Ne, Ar, Xe, and N2.

[0116] In addition to, or in place of, plasma activation, activation of one or more gases in a dry development process can occur by photoactivation. In some embodiments, photoactivation can be achieved by exposure to ultraviolet (UV) radiation. For example, the process chamber may include a lamp, such as a UV lamp, configured to generate UV radiation. By exposing one or more gases to UV radiation, radicals of one or more gases that can be used for dry development of a photopatterned metal-containing EUV resist can be generated. Exposure of one or more gases to UV radiation can be performed without exposing the photopatterned resist to UV radiation. In other words, the photopatterned resist is not visible from the UV lamp. Thus, the UV lamp may be remote from the process chamber or positioned to avoid exposing the photopatterned resist to UV radiation.

[0117] It will be understood that the foregoing methods of thermal development, plasma development, and photoactivation development may be combined with each other. Such development methods can be applied simultaneously or sequentially. The development method can be applied while flowing a dry development chemical in a liquid phase or a gas phase, in which case the dry development chemical can include a compound of the formula R x Z y where R = B, Al, Si, C, S, SO, x > 0, Z = Cl, H, Br, F, CH4, and y > 0. Development can result in a positive or negative type, and the R x Z y species selectively removes either the unexposed material or the exposed material, leaving the corresponding exposed or unexposed counterpart as a mask.

[0118] As described above, the etching selectivity during dry development is adjustable by controlling process conditions such as, among other adjustable process conditions, temperature, pressure, gas flow, gas composition, and plasma power. By adjusting the etching selectivity in a single step or multiple steps, desired patterned characteristics can be achieved. In some embodiments, the etching selectivity during dry development is adjusted over one or more steps, thereby affecting the EUV resist profile. More specifically, the amount of taper or reentrant angle in the EUV resist profile can be controlled by applying development chemistries with different etching selectivities over one or more steps. The descum, photoresist rework, curing, smoothing, and cleaning operations can also be adjusted according to an adjustable etching selectivity.

[0119] FIG. 1 shows a flowchart of an exemplary method for depositing and developing a photoresist according to some embodiments. The operations of process 100 may be performed in a different order and / or with a different, fewer, or additional number of operations. One or more operations of process 100 can be performed using the apparatus described in any one of FIGS. 7-10. In some embodiments, the operations of process 100 may be implemented, at least in part, in accordance with software stored on one or more non-transitory computer-readable media.

[0120] In operation 102 of process 100, a photo-patterned metal-containing resist is provided. The resist can be deposited by a dry deposition process such as a vapor deposition process or by a wet process such as a spin-on deposition process.

[0121] The photoresist may be a metal-containing EUV resist. The EUV-sensitive metal or metal oxide-containing film can be deposited on the semiconductor substrate by any suitable technique including wet (e.g., spin-on) or dry (e.g., CVD) deposition techniques. For example, the described process has been demonstrated for EUV photoresist compositions based on organotin oxides and is applicable to both commercially available spin-coatable formulations and formulations applied using the dry vacuum deposition techniques further described below.

[0122] The semiconductor substrate can include any material structure suitable for photolithography processing, particularly for the production of integrated circuits and other semiconductor devices. In some embodiments, the semiconductor substrate is a silicon wafer. The semiconductor substrate may be a silicon wafer having features ( "underlying features") with irregular surface topography formed thereon. As referred to herein, "surface" is the surface on which the film of the present disclosure is deposited or the surface that is exposed to EUV during processing. The underlying features can include regions where material has been removed (e.g., by etching) or regions where material has been added (e.g., by deposition) during processing prior to performing the method of the present disclosure. Such pretreatment can include the method of the present disclosure or other processing methods in an iterative process in which layers of two or more features are formed on the substrate.

[0123] An EUV-sensitive thin film can be deposited on a semiconductor substrate, and such a film can operate as a resist for subsequent EUV lithography and processing. When such an EUV-sensitive thin film is exposed to EUV, it undergoes changes such as the loss of bulky pendant substituents bonded to metal atoms in a low-density M-OH-enriched material, enabling cross-linking to a higher-density M-O-M-bonded metal oxide material. Through EUV patterning, areas of the film with changed physical or chemical properties compared to the unexposed areas are formed. These properties can be utilized in subsequent processing, such as to dissolve either the unexposed areas or the exposed areas, or to selectively deposit material on either the exposed areas or the unexposed areas. In some embodiments, the unexposed film has a more hydrophobic surface than the exposed film under the conditions under which such subsequent processing is carried out. For example, the removal of material may be carried out by taking advantage of differences in the chemical composition, density, and cross-linking of the film. The removal can be performed by wet processing or dry processing as further described below.

[0124] The thin film, in various embodiments, comprises an organometallic material, such as an organotin material containing tin oxide, or other metal oxide materials / portions. The organometallic compound can be made by a gas-phase reaction of an organometallic precursor and a counter-reagent. In various embodiments, the organometallic compound is formed by mixing a specific combination of organometallic precursors having bulky alkyl or fluoroalkyl groups with a counter-reagent and polymerizing the mixture in the gas phase, generating a low-density EUV-sensitive material that deposits on the semiconductor substrate.

[0125] In various embodiments, the organometallic precursor contains at least one alkyl group on each metal atom capable of withstanding a gas-phase reaction, but other ligands or ions coordinated to the metal atoms can be substituted by the counter-reagent. The organometallic precursor includes organometallic precursors of the following formula: M a R b L c (Formula 1) In the formula, M is an element having a high patterning radiation absorption cross-section, and R is C n H 2n+1 and the like, preferably n ≧ 2, L is a ligand, ion, or other moiety that reacts with the reverse reactant, and a ≧ 1, b ≧ 1, and c ≧ 1.

[0126] In various embodiments, M has an atomic absorption cross-section of 1×10 7 cm 2 / mol or more. M can be selected from the group consisting of, for example, tin, hafnium, tellurium, bismuth, indium, antimony, germanium, and combinations thereof. In some embodiments, M is tin. R may be fluorinated, for example, to have the formula C n F x H (2n+1) . In various embodiments, R has at least one beta hydrogen or beta fluorine. For example, R can be selected from the group consisting of ethyl, i-propyl, n-propyl, t-butyl, i-butyl, n-butyl, sec-butyl, n-pentyl, i-pentyl, t-pentyl, sec-pentyl, and mixtures thereof. L may be any moiety that is easily substituted by the reverse reactant to form an M-OH moiety, such as a moiety selected from the group consisting of amines (dialkylamino, monoalkylamino, etc.), alkoxy, carboxylate, halogen, and mixtures thereof.

[0127] The organometallic precursor may be any of a wide variety of candidate metal-organic precursors. For example, when M is tin, such precursors include t-butyltris(dimethylamino)tin, i-butyltris(dimethylamino)tin, n-butyltris(dimethylamino)tin, sec-butyltris(dimethylamino)tin, i-propyl(tris)dimethylaminotin, n-propyltris(dimethylamino)tin, ethyltris(dimethylamino)tin, and similar alkyl(tris)(t-butoxy)tin compounds, such as t-butyltris(t-butoxy)tin. In some embodiments, the organometallic precursor is partially fluorinated.

[0128] The reverse reactant has the ability to replace a reactive moiety, ligand, or ion (e.g., L in Formula 1 above) in order to link at least two metal atoms via a chemical bond. Reverse reactants can include water, peroxides (e.g., hydrogen peroxide), dihydroxy or polyhydroxy alcohols, fluorinated dihydroxy or polyhydroxy alcohols, fluorinated glycols, and other sources of hydroxyl moieties. In various embodiments, the reverse reactant reacts with the organometallic precursor by forming an oxygen bridge between adjacent metal atoms. Other potential reverse reactants include hydrogen sulfide and hydrogen disulfide, which can bridge metal atoms via sulfur bridges.

[0129] The thin film can include optional materials in addition to the organometallic precursor and the reverse reactant, and can modify the chemical or physical properties of the film, such as modifying the sensitivity of the film to EUV or enhancing the etch resistance. Such optional materials may be introduced, for example, by doping during vapor phase formation before deposition onto the semiconductor substrate, after deposition of the thin film, or both. In some embodiments, some Sn-L bonds can be replaced with Sn-H by introducing a mild remote H2 plasma, which can enhance the reactivity of the resist under EUV.

[0130] In various embodiments, the EUV-patternable film is fabricated using vapor deposition equipment and processes known in the art and deposited onto a semiconductor substrate. In such processes, a polymeric organometallic material is formed in the vapor phase or in situ on the surface of the semiconductor substrate. Suitable processes include, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), and ALD using CVD components, such as a discontinuous ALD-like process in which the metal precursor and the reverse reactant are separated either in time or in space.

[0131] Generally, the method includes mixing a vapor stream of an organometallic precursor with a vapor stream of a counter-reactant to form a polymeric organometallic material and depositing the organometallic material on the surface of a semiconductor substrate. In some embodiments, a plurality of organometallic precursors are included in the vapor stream. In some embodiments, a plurality of counter-reactants are included in the vapor stream. As will be appreciated by those skilled in the art, the mixing and deposition aspects of the process can be performed simultaneously in a substantially continuous process.

[0132] In an exemplary continuous CVD process, in separate inlet paths, two or more gas streams from sources of organometallic precursors and counter-reactants are introduced into the deposition chamber of a CVD apparatus where they mix and react in the gas phase to form an agglomerated polymeric material (e.g., via metal-oxygen-metal bond formation). The gas streams can be introduced, for example, using separate injection inlets or a dual-plenum showerhead. The apparatus is configured such that the streams of organometallic precursors and counter-reactants are mixed within the chamber, whereby the organometallic precursors and counter-reactants can react to form a polymeric organometallic material. Without limiting the mechanism, function, or utility of the present technology, the product from such a gas-phase reaction is thought to increase in molecular weight as metal atoms are cross-linked by the counter-reactant and then either condense or, in some cases, deposit on the semiconductor substrate. In various embodiments, the steric hindrance of bulky alkyl groups prevents the formation of a densely packed network and generates a smooth, amorphous, low-density film.

[0133] The CVD process is generally performed at a reduced pressure, such as from 10 milliTorr to 10 Torr. In some embodiments, the process is performed at 0.5 to 2 Torr. In some embodiments, the temperature of the semiconductor substrate is below the temperature of the stream of reactants. For example, the substrate temperature can be from 0 °C to 250 °C, or from ambient temperature (e.g., 23 °C) to 150 °C. In various processes, the deposition of the polymeric organometallic material onto the substrate occurs at a rate that is inversely proportional to the surface temperature.

[0134] In some embodiments, the EUV-patternable film is fabricated using wet deposition equipment and processes known in the art and deposited on a semiconductor substrate. For example, an organometallic material is formed by spin coating on the surface of the semiconductor substrate.

[0135] The thickness of the EUV-patternable film formed on the surface of the semiconductor substrate can vary according to surface properties, the materials used, and processing conditions. In various embodiments, the film thickness can be in the range of 0.5 nm to 100 nm and can be thick enough to absorb most of the EUV light under EUV patterning conditions. The EUV-patternable film can be capable of corresponding to an absorption of 30% or more, whereby the available EUV photons are significantly reduced towards the bottom of the EUV-patternable film. When the EUV absorption is high, crosslinking and densification are more likely to occur near the upper part of the EUV exposure film compared to the bottom of the EUV exposure film. If the crosslinking is insufficient, the resist may be prone to lift-off or collapse in wet development, but such risks do not exist in dry development. The all-dry lithography approach can facilitate more efficient utilization of EUV photons by a more opaque resist film. The efficient utilization of EUV photons can be achieved with an EUV-patternable film having a higher overall absorption rate, but it will be understood that in some cases, the EUV-patternable film can be less than about 30%. For comparison, since the maximum overall absorption rate of most other resist films is less than 30% (e.g., 10% or less, or 5% or less), the resist material at the bottom of the resist film is sufficiently exposed. In some embodiments, the film thickness is 10 nm to 40 nm, or 10 nm to 20 nm. Without limiting the mechanism, function, or utility of the present disclosure, unlike the wet spin coating process in the art, the process of the present disclosure has few limitations on the surface adhesion properties of the substrate and is therefore considered applicable to a wide variety of substrates. Further, as described above, the deposited film closely conforms to the surface features and can provide advantages when forming a mask on a substrate such as a substrate having underlying features without "filling" or planarizing such features.

[0136] Returning to FIG. 1, in operation 104, the photopatterned metal-containing resist is exposed to pulses of the etchant. As used herein, a pulse refers to a specific amount of gas flow over a specified period. In some embodiments, the etchant pulse duration is from about 1 to about 120 seconds. In some embodiments, the etchant pulse duration is from about 5 to about 30 seconds. In some embodiments, the etchant pulse duration is from about 1 to about 20 seconds. In some embodiments, the etchant flow rate is from about 50 to about 3,000 sccm.

[0137] In some embodiments, operation 104 is a thermal process and the etchant is fed into the process chamber in gaseous form. In other embodiments, the etchant may be fed into the process chamber in the form of a plasma. The etchant plasma can include reactive species such as electrons, positive ions, neutrals, radicals, and other plasma species. In some embodiments, the etchant is a halide etchant such as hydrogen bromide or hydrogen chloride, or a mixture of hydrogen and a halogen such as hydrogen and chlorine (Cl2) or hydrogen and bromine (Br2).

[0138] Operation 104 can be performed by flowing a dry development etchant such as BCl3 (boron trichloride) or other Lewis acid while using either a mild plasma (high pressure, low power) or a thermal process. In some embodiments, BCl3 can rapidly remove the unexposed material, leaving a pattern of the exposed film that can be transferred to the underlying layer by a plasma-based etching process, such as a conventional etching process.

[0139] The plasma process includes transformer-coupled plasma (TCP), inductively coupled plasma (ICP), or capacitively coupled plasma (CCP) using equipment and techniques known in the art. For example, the process can be carried out at a pressure >5 mT (e.g., >15 mT) and a power level <1000 W (e.g., <500 W). The temperature can be 0 to 300 °C (e.g., 30 to 120 °C), the flow rate 100 to 1000 standard cubic centimeters per minute (sccm), e.g., about 500 sccm, and 1 to 3000 seconds (e.g., 10 to 600 seconds).

[0140] In the thermal development process, the substrate is exposed to a dry development chemical (e.g., a Lewis acid) in a vacuum chamber (e.g., an oven). A suitable chamber can include a vacuum line, a dry development chemical gas (e.g., BCl3) line, and a heater for temperature control. In some embodiments, the interior of the chamber can be coated with a corrosion-resistant film such as an organic polymer or an inorganic coating. One such coating is polytetrafluoroethylene ((PTFE), e.g., Teflon 1M). Such materials can be used in the thermal processes of the present technology without the risk of removal by plasma exposure.

[0141] During the etchant pulse, the pressure in the process chamber can be about 5 mTorr to about 1 Torr in some embodiments. In some embodiments, the pedestal temperature in the process chamber can be about -60 °C to about 120 °C during the etchant pulse. Further, by adjusting the gas flow, hydrogen-to-halogen ratio, pressure, temperature, or RF power, the etching selectivity between the non-exposed photoresist and the EUV-exposed photoresist can be adjusted from 5:1 to over 50:1.

[0142] In operation 106, in some embodiments, an optional purge is performed by flowing an inert carrier gas through the process chamber after exposure to the etchant. The purge gas or carrier gas is selected to not react with the etchant. It is possible to utilize gases such as helium, argon, nitrogen, or combinations thereof.

[0143] In operation 108, the resist etched in operation 104 is cleaned with pulses of an oxidizing agent. The oxidizing agent is used to remove non-volatile by-products that may form during the etchant pulse and that form an undesirable etch stop on the resist. The non-volatile by-products are etch-resistant residues and can prevent further processing. In some embodiments, the non-volatile by-products are at the bottom of the unexposed photoresist. Treatment with the oxidizing agent makes the non-volatile by-products volatile and can enable further etching.

[0144] The oxidizing agent may be oxygen, ozone, hydrogen peroxide, water, nitrous oxide, nitric oxide, nitrogen dioxide, nitric acid, sulfur dioxide, chlorine, fluorine, bromine, iodine, or combinations thereof. In some embodiments, the oxidizing agent is air, water and oxygen, or chlorine (Cl2).

[0145] In some embodiments, operation 108 is a thermal process and the oxidizing agent is fed into the process chamber in gaseous form. In other embodiments, the oxidizing agent may be fed into the process chamber in plasma form. The etchant plasma can include reactive species such as electrons, cations, neutrals, radicals, and other plasma species.

[0146] In some embodiments, operation 108 is performed at a temperature higher than operation 104. The high temperature can be achieved by feeding the oxidant as a high-temperature gas or by heating the pedestal in the process chamber to a second temperature higher than the first temperature utilized in operation 104. When fed as a high-temperature gas, the temperature of the gas may be from about 50°C to about 250°C. When the pedestal of the process chamber is heated for the oxidant pulse, the pedestal may be heated to a temperature of about 20°C to about 150°C.

[0147] In operation 108, the oxidant is fed as a pulse at a specific flow rate for a specific duration. The duration of the pulse may be from about 1 to about 60 seconds. The ratio of the oxidant to the etchant may be 1:1. In some embodiments, the oxidant flow rate is from about 50 to about 3,000 sccm.

[0148] Operations 108 and 104 are separate pulses in time, meaning temporally separated pulses. The pulse of the etchant and the pulse of the oxidant fed to the process chamber in operation 104 are one cycle. Cycle 114 can be repeated the desired number of times to completely remove the by-products. In addition, the feeding of the etchant and the oxidant for each cycle may have the same pulse duration or the pulse duration may be changed after a specified number of cycles. The relationship between the timing and the temperature of an exemplary pulse sequence of etchant HBr and exemplary oxidant Cl2 with an optional argon purge is graphically shown in FIG. 2.

[0149] Returning to FIG. 1, in operation 110, in some embodiments, an optional purge can be performed after one cycle of operations 104 and 108 by flowing an inert carrier gas through the process chamber. The purge gas or carrier gas is selected to not react with the etchant. It is possible to utilize gases such as helium, argon, nitrogen, or combinations thereof. If an optional purge is utilized after a cycle, the next cycle begins with exposure to the etchant as shown at 116.

[0150] In operation 112, a resist mask is formed. Plasma can be utilized to assist in the solidification of the exposed photoresist.

[0151] In some cases, residues or scum may remain after development. Residues can result from slow etching components in a non-uniform EUV resist formulation, including those applied by spin coating techniques. Such scum may contain high concentrations of metal, which can be a problem during subsequent pattern transfer.

[0152] Additionally or alternatively, roughness may be formed on the sidewalls of the features etched with the developed pattern after development. Some of this may be due to a probabilistic or non-optimal Gaussian distribution of light where material is partially or fully exposed in areas where the resist should have remained unexposed, or vice versa.

[0153] In some embodiments, dry development may be accompanied by a descum / smoothing operation. In some embodiments, the descum and smoothing operations can be an inert gas plasma desorption operation. For example, the inert gas plasma desorption operation may be a helium plasma desorption operation. The inert gas plasma desorption operation can be performed after dry development or repeatedly in conjunction with dry development.

[0154] Various embodiments include combining all dry operations by vapor deposition, EUV lithography patterning, and dry development. Various other embodiments include combinations of wet processing operations and dry processing operations. For example, spin-on EUV photoresist (a wet process) can be combined with dry development or other wet or dry processes as described herein. Various post-deposition (or post-application) processes such as bevel cleaning and backside cleaning, chamber cleaning, descumming, smoothing, and curing to modify and enhance film characteristics, as well as photoresist rework processes, are also described.

[0155] Figures 3A - 3C are graphs of some parameters of a particular embodiment of the method described herein. Figure 3A demonstrates that an etch stop occurs in the absence of an oxidizing agent, with the residual thickness of the initially 25 nm thick EUV non-exposed layer being 10 nm. The higher the purge temperature of the Cl2 oxidizing agent, the more effective it is in removing by-products.

[0156] Figure 3B shows that in combination with Cl2 oxidant pulses in a periodic dry development process, shorter pulses of HBr etchant at a process temperature of 20 °C result in more removal of by-products with a larger number of cycles.

[0157] Figure 3C shows that in combination with HBr etchant pulses in a periodic dry development process, increasing the purge time of the Cl2 oxidizing agent at a process temperature of 40 °C is more effective in reducing the residual thickness.

[0158] Figure 4 shows a scanning electron microscope image of the patterned photoresist surface, comparing conventional dry development using only an etchant with a periodic dry development process using successive alternating pulses of an etchant and an oxidizing agent. The HBr etchant was utilized under process conditions of a flow rate of 500 sccm, a pressure of 300 mTorr, and a temperature of 20 °C. After applying a 5-cycle periodic dry development process, cleaner non-exposed areas and better edge roughness are achieved in both the open and dense areas.

[0159] Figure 5 shows the limits of a single dry development process (HBr etchant only) and a periodic process. For a 25-nm non-exposed photoresist film, when using only the etchant, an etch stop occurs at a residual thickness of less than 15 nm. In contrast, when using a periodic process (total time 240 seconds), much more of the non-exposed photoresist film is removed by using either Cl2 or an air oxidizing agent.

[0160] Figure 6 shows a flow diagram of an exemplary alternative method for depositing and developing a photoresist according to some embodiments. The operations of process 200 may be performed in a different order and / or with a different, fewer, or additional number of operations. One or more operations of process 200 may be performed using the apparatus described in any one of FIGS. 7-10. In some embodiments, the operations of process 200 may be implemented, at least in part, in accordance with software stored on one or more non-transitory computer-readable media.

[0161] In operation 202 of process 200, a photo-patterned metal-containing resist is provided.

[0162] In operation 204, the photo-patterned metal-containing resist is exposed to an etchant.

[0163] In operation 206, after treatment with an etchant, a cleaning agent is used to dissolve non-volatile by-products. In some embodiments, the cleaning agent may be a suitable polar solvent such as water, methanol, ethanol, isopropanol, acetone, acetonitrile, tetrahydrofuran, dimethyl sulfide, or combinations thereof. In some embodiments, the cleaning agent may be a supercritical fluid such as a supercritical liquid with low surface tension. Suitable liquids include, but are not limited to, carbon dioxide, sulfur dioxide, dimethyl ether, or combinations thereof.

[0164] During the cleaning process using the cleaning agent, the temperature of the pedestal in the process chamber is about 10°C to about 50°C in some embodiments. In some embodiments, the process chamber pressure is about 5 psi to about 3,000 psi during exposure to the cleaning agent.

[0165] In operation 208, a resist mask is formed. It is possible to utilize plasma to cure the exposed photoresist, improve surface roughness, and help remove scum.

[0166] The process conditions for descumming and smoothing operations can be controlled during or after development. In some embodiments, the flow rate of the reactant may be from about 50 sccm to about 1000 sccm, or from about 100 sccm to about 500 sccm, such as about 500 sccm of He. In some embodiments, the temperature may be from about -60°C to about 120°C, from about -20°C to about 60°C, or from about 20°C to about 40°C, such as about 20°C. In some embodiments, the chamber pressure may be from about 1 mTorr to about 300 mTorr, from about 5 mTorr to about 100 mTorr, from about 5 mTorr to about 20 mTorr, such as about 10 mTorr. The plasma power may be relatively low when the ion energy is high. In some embodiments, the plasma power may be from about 50 W to about 1000 W, from about 100 W to about 500 W, or from about 100 W to about 300 W, such as about 300 W. In some embodiments, the wafer bias is from about 10 V to about 500 V, from about 50 V to about 300 V, such as about 200 V. The plasma can be generated using a high RF frequency. In some embodiments, the RF frequency is 13.56 MHz. The duration of exposure to the inert gas plasma may be relatively short to avoid excessive exposure to UV radiation during plasma exposure. In some embodiments, the duration of exposure is from about 0.5 second to about 5 seconds, from about 1 second to about 3 seconds, such as about 2 seconds.

[0167] The inert gas plasma treatment for descumming and cleaning of non-exposed resist residues has the additional advantage of hardening and solidifying the exposed resist, thereby enhancing its hard mask function in subsequent operations for etching the underlying substrate. This resist solidification is achieved by exposing the EUV exposed resist to the UV radiation generated by the inert gas plasma, which can continue even after descumming / smoothing is completed with the bias turned off. If descumming / smoothing is not required or not performed, inert gas plasma hardening may be performed instead.

[0168] In some embodiments, inert gas plasma descum and planarization can be used in conjunction with a wet development process. Wet development has been shown to have very high selectivity and exhibit distinct on / off behavior, such that in a wet development process, areas exposed by "stray" EUV photons cannot be removed. Residuals remain after the wet development process, thereby causing scum and resulting in rough line edges and widths. Interestingly, due to the controllability of a dry development process in which the etching rate and selectivity can be adjusted based on multiple knobs (e.g., time, temperature, pressure, gas / flow rate), inert gas plasma and / or dry development can be further applied to descum and planarize metal-containing resist lines by removing these partially exposed residues.

[0169] The descum and planarization operations may be performed after wet or dry development.

[0170] Device The apparatus of the present disclosure is configured for the development of EUV resist. The apparatus can be configured to perform other processing operations such as deposition, bevel and backside cleaning, post-application bake, EUV scanning, post-exposure bake, photoresist rework, descum, planarization, curing, and other operations. In some embodiments, the apparatus is configured to perform all drying operations. In some embodiments, the apparatus is configured to perform all wet operations. In some embodiments, the apparatus is configured to perform a combination of wet and dry operations. The apparatus can include a single wafer chamber or multiple stations within the same process chamber. If there are multiple stations within the same process chamber, the various processing operations as described in the present disclosure may be performed at different stations within the same process chamber. For example, PEB heat treatment can be performed at one station and development can be performed at another station.

[0171] An apparatus configured for developing EUV resist includes a process chamber having a substrate support. The apparatus can include a vacuum line coupled to the process chamber for pressure control and a developer chemical line coupled to the process chamber for feeding a developer chemical. In some embodiments, the developer chemical includes a halide-containing gas or radicals of a halide-containing gas. In some embodiments, the process chamber is a plasma generation chamber or is coupled to a plasma generation chamber that functions as a remote plasma source. The plasma generation chamber may be an ICP, TCP, or CCP reactor. The apparatus may include one or more heaters for temperature control. Such heaters can be provided within the process chamber and / or within the substrate support.

[0172] In some embodiments, the interior of the process chamber is coated with a corrosion-resistant film such as a polymer or an inorganic coating. In one example, the interior of the process chamber is coated with anodized alumina. In another example, the interior of the process chamber is coated with yttrium oxide (Y2O3).

[0173] In some embodiments, the process chamber is made of an inexpensive material such as plastic. The process chamber does not necessarily have to be made of metal or ceramic. The plastic material may be sufficient to withstand the halide-containing chemical during development. The vacuum line and / or the developer chemical line can be coupled to the plastic chamber.

[0174] In some embodiments, the substrate support can be used to process the substrate using a temperature distribution having a radial component and an azimuthal component. The substrate support may include a plurality of independently controllable temperature control zones disposed proximate to the substrate location over the temperature control zones. This enables one or more heaters in the substrate support to control the temperature more accurately and locally. The temperature control zones can be arranged in a predefined pattern, such as a rectangular grid, a hexagonal grid, or other suitable pattern, to generate a desired temperature profile. In some embodiments, the temperature control zones can be spatially arranged within the electrostatic chuck to correct azimuthal non-uniformity or local CD non-uniformity.

[0175] In some embodiments, the apparatus can further include a showerhead for feeding one or more gases into the process chamber. In some embodiments, the showerhead can supply a plurality of separate gases to the reaction area while keeping the gases mainly isolated within the showerhead. The showerhead can include a plurality of plenum volumes. This enables the isolation of, among other chemicals, precursor gases, carrier gases, development gases, and cleaning gases.

[0176] Removing water or moisture from the process chamber can facilitate the reaction between the photopatterned metal-containing EUV resist and the development chemical. In some embodiments, a cold trap may be coupled to the process chamber to remove the byproduct water vapor. The cold trap can condense the byproduct water vapor into a liquid or solid form.

[0177] In some embodiments, the apparatus may further include a UV source, such as a UV lamp, and / or an IR source, such as an IR lamp, for resist curing and dehalogenation. The UV source and / or IR source can provide exposure to radiation to cure the EUV resist. Additionally or alternatively, the UV source may assist in photoactivating the developing chemicals. Additionally or alternatively, the UV source may assist in removing halogens. Halogen residues may be formed on the semiconductor substrate or chamber surface, which can be removed by UV exposure.

[0178] FIG. 7 illustrates a schematic view of one embodiment of a process station 700 having a process chamber body 702 for maintaining a low pressure environment suitable for implementing the described dry development, cleaning, reprocessing, descumming, and planarization embodiments. A plurality of process stations 700 may be included in a common low pressure process tool environment. In some embodiments, one or more hardware parameters (including those described in detail below) of the process station 700 can be programmatically adjusted by one or more computer controllers 750.

[0179] The process station can be configured as a module within a cluster tool. FIG. 10 illustrates a semiconductor process cluster tool architecture having vacuum integrated deposition and patterning modules suitable for implementing the embodiments described herein. Such a cluster process tool architecture can include resist deposition, resist exposure (EUV scanner), resist development, and etching modules, as described above and further described below with reference to FIGS. 9 and 10.

[0180] In some embodiments, certain processing functions, such as dry development and etching, can be performed sequentially within the same module. Further, embodiments of the present disclosure are directed to methods and apparatus for receiving a wafer including a photopatterned EUV resist thin film layer disposed on an etched layer or layer stack, as described herein, into a dry development / etch chamber following photopatterning in an EUV scanner, dry developing the photopatterned EUV resist thin film layer, and then etching a lower layer using the EUV resist patterned as a mask.

[0181] Returning to FIG. 7, process station 700 is in fluid communication with a reactant delivery system 701 for delivering a process gas to a distribution showerhead 706. Reactant delivery system 701 includes a mixing vessel 704 for blending and / or conditioning the process gas delivered to showerhead 706. One or more mixing vessel inlet valves 720 can control the introduction of the process gas into mixing vessel 704. When plasma exposure is used, the plasma can also be delivered to showerhead 706 or generated at process station 700. As noted above, in at least some embodiments, non-plasma thermal exposure is preferred.

[0182] FIG. 7 includes an optional vaporization point 703 for vaporizing a liquid reactant supplied to mixing vessel 704. In some embodiments, a liquid flow controller (LFC) can be provided upstream of vaporization point 703 to control the mass flow rate of the liquid that is vaporized and delivered to process station 700. For example, the LFC can include a thermal mass flow meter (MFM) located downstream of the LFC. The plunger valve of the LFC can then be adjusted in response to a feedback control signal provided by a proportional integral derivative (PID) controller that is in electrical communication with the MFM.

[0183] The showerhead 706 distributes process gas toward the substrate 712. In the embodiment shown in FIG. 7, the substrate 712 is positioned beneath the showerhead 706 and is shown stationary on the pedestal 708. The showerhead 706 may have any suitable shape and may have any suitable number and arrangement of ports for distributing process gas to the substrate 712.

[0184] In some embodiments, the pedestal 708 can be raised or lowered to expose the substrate 712 to the volume between the substrate 712 and the showerhead 706. It will be appreciated that in some embodiments, the height of the pedestal can be programmatically adjusted by a suitable computer controller 750. In some embodiments, the showerhead 706 can have a plurality of plenum volumes with a plurality of temperature controls.

[0185] In some embodiments, the pedestal 708 can be temperature controlled via the heater 710. In some embodiments, the pedestal 708 can be heated to a temperature above 0°C to above 300°C, such as 50 - 120°C, such as about 65 - 80°C, during non-plasma thermal exposure of the photopatterned resist to a hydrogen halide dry development chemical such as HBr or HCl, as described in the disclosed embodiments. In some embodiments, the heater 710 of the pedestal 708 can include a plurality of independently controllable temperature control zones.

[0186] Further, in some embodiments, pressure control for the process station 700 can be provided by the butterfly valve 718. As shown in the embodiment of FIG. 7, the butterfly valve 718 throttles the vacuum provided by a downstream vacuum pump (not shown). However, in some embodiments, pressure control of the process station 700 can also be adjusted by varying the flow rate of one or more gases introduced into the process station 700 .

[0187] In some embodiments, the position of the showerhead 706 can be adjusted relative to the pedestal 708 to vary the volume between the substrate 712 and the showerhead 706. Further, it will be appreciated that the vertical position of the pedestal 708 and / or the showerhead 706 may be varied by any suitable mechanism within the scope of the present disclosure. In some embodiments, the pedestal 708 may include a rotational axis for rotating the orientation of the substrate 712. In some embodiments, it will be appreciated that one or more of these exemplary adjustments can be programmatically implemented by one or more suitable computer controllers 750.

[0188] For example, in embodiments of gentle plasma-based dry development and / or where plasma can be used in an etching operation performed within the same chamber, the showerhead 706 and the pedestal 708 are electrically communicative with a radio frequency (RF) power source 714 and a matching network 716 to supply power to the plasma. In some embodiments, the plasma energy can be controlled by controlling one or more of the process station pressure, gas concentration, RF source power, RF source frequency, and plasma power pulse timing. For example, the RF power source 714 and the matching network 716 can operate at any suitable power to form a plasma having a desired composition of radical species. An example of suitable power is up to about 500 W.

[0189] In some embodiments, the instructions to the controller 750 may be provided via input / output control (IOC) sequence instructions. In one example, the instructions for setting conditions for a process step may be included in the corresponding recipe step of the process recipe. In some cases, the process recipe steps may be arranged in sequence such that all instructions for a process step are executed simultaneously with that process step. In some embodiments, the recipe step may include instructions for setting one or more reactor parameters. For example, the recipe step may include instructions for setting the flow rate of a dry development chemical reactant gas such as HBr or HCl, and a time delay instruction for the recipe step. In some embodiments, the controller 750 may include any of the features described below with respect to the system controller 850 of FIG. 8.

[0190] As described above, one or more process stations can be included in the multi-station processing tool. FIG. 8 shows a schematic diagram of one embodiment of a multi-station processing tool 800 having an inbound load lock 802 and an outbound load lock 804, either or both of which may include a remote plasma source. Robot 806 is configured to move wafers from a cassette loaded via pod 808 at atmospheric pressure to inbound load lock 802 via atmospheric port 810 at atmospheric pressure. The wafer is placed on pedestal 812 of inbound load lock 802 by robot 806, atmospheric port 810 is closed, and the load lock is pumped down. If inbound load lock 802 includes a remote plasma source, the wafer may be subjected to remote plasma processing to treat the silicon nitride surface within the load lock before being introduced into process chamber 814. Further, the wafer may also be heated in inbound load lock 802, for example, to remove moisture and absorbed gases. Next, chamber transfer port 816 to process chamber 814 is opened, and another robot (not shown) places the wafer on the pedestal of the first station shown within the reactor for processing. Although the embodiment illustrated in FIG. 8 includes load locks, it will be understood that in some embodiments, wafers may be directly accessed to the process station.

[0191] The illustrated processing chamber 814 includes four process stations numbered from 1 to 4 in the embodiment shown in FIG. 8. Each station has a heating pedestal (shown as 818 for station 1) and a gas line inlet. It will be understood that in some embodiments, each process station may have different purposes or multiple purposes. For example, in some embodiments, the process station may be switchable between a dry development mode and an etching process mode. Additionally or alternatively, in some embodiments, the processing chamber 814 may include one or more corresponding pairs of dry development and etching process stations. Although the illustrated processing chamber 814 includes four stations, it will be understood that a processing chamber according to the present disclosure may have any suitable number of stations. For example, in some embodiments, the processing chamber may have five or more stations, and in other embodiments, the processing chamber may have three or fewer stations.

[0192] FIG. 8 illustrates one embodiment of a wafer handling system 890 for transferring wafers within the processing chamber 814. In some embodiments, the wafer handling system 890 can transfer wafers between various process stations and / or between a process station and a load lock. It will be understood that any suitable wafer handling system may be used. Non-limiting examples include a wafer carousel and a wafer handling robot. FIG. 8 also illustrates one embodiment of a system controller 850 used to control the process conditions and hardware state of the process tool 800. The system controller 850 can include one or more memory devices 856, one or more mass storage devices 854, and one or more processors 852. The processor 852 can include a CPU or computer, analog and / or digital input / output connections, a stepper motor controller board, and the like.

[0193] In some embodiments, system controller 850 controls all of the activities of process tool 800. System controller 850 executes system control software 858 that is stored on mass storage device 854, loaded into memory device 856, and executed by processor 852. Alternatively, the control logic may be hard-coded into controller 850. Application specific integrated circuits, programmable logic devices (e.g., field programmable gate arrays, or FPGAs), etc. may be used for these purposes. In the following description, whenever "software" or "code" is used, functionally equivalent hard-coded logic may be used instead. System control software 858 may include instructions for controlling timing, gas mixing, gas flow rate, chamber pressure and / or station pressure, chamber temperature and / or station temperature, wafer temperature, target power level, RF power level, substrate pedestal, chuck position and / or susceptor position, and other parameters of a particular process implemented by process tool 800. System control software 858 may be configured in any suitable manner. For example, various process tool component subroutines or control objects may be written to control the operation of the process tool components used to execute various process tool processes. System control software 858 may be coded in any suitable computer-readable programming language.

[0194] In some embodiments, system control software 858 may include input / output control (IOC) sequence instructions for controlling the various parameters described above. In some embodiments, other computer software and / or programs stored on mass storage device 854 and / or memory device 856 associated with system controller 850 may be used. Examples of programs or program sections for this purpose include a substrate positioning program, a process gas control program, a pressure control program, a heater control program, and a plasma control program.

[0195] The substrate positioning program can include program code for process tool components used to load a substrate onto pedestal 818 and control the spacing between the substrate and other parts of process tool 800.

[0196] The process gas control program can include code for controlling the composition (e.g., HBr or HCl gas as described herein) and flow rate of a halide-containing gas, and optionally code for flowing the gas through one or more process stations to stabilize the pressure of the process station. The pressure control program can include, for example, code for controlling the pressure of the process station by adjusting a throttle valve in the exhaust system of the process station, the gas flow to the process station, etc.

[0197] The heater control program can include code for controlling the current to a heating unit used to heat the substrate. Alternatively, the heater control program can control the delivery of a heat transfer gas (such as helium) to the substrate.

[0198] The plasma control program can include code for setting the RF power level applied to a process electrode within one or more process stations according to the embodiments herein.

[0199] The pressure control program can include code for maintaining the pressure within the reaction chamber according to the embodiments herein.

[0200] In some embodiments, a user interface associated with system controller 850 may be present. The user interface can include a display screen, a graphical software display of device and / or process conditions, and user input devices such as a pointing device, keyboard, touch screen, microphone, etc.

[0201] In some embodiments, the parameters adjusted by the system controller 850 may relate to process conditions. Non-limiting examples include process gas composition and flow rate, temperature, pressure, plasma conditions (such as RF bias power level), and the like. These parameters may be provided to the user in the form of a recipe and can be input using a user interface.

[0202] Signals for monitoring the process may be provided from various process tool sensors to the analog and / or digital input connections of the system controller 850. Signals for controlling the process can be output at the analog and digital output connections of the process tool 800. Non-limiting examples of process tool sensors that can be monitored include mass flow controllers, pressure sensors (such as pressure gauges), thermocouples, and the like. Appropriately programmed feedback and control algorithms can be used with the data from these sensors to maintain process conditions.

[0203] The system controller 850 can provide program instructions for performing the deposition process described above. The program instructions can control various process parameters such as DC power level, RF bias power level, pressure, temperature, and the like. The instructions can control parameters for operating development and / or etching processes according to the various embodiments described herein.

[0204] The system controller 850 typically includes one or more memory devices and one or more processors configured to execute instructions so that the apparatus performs methods according to the disclosed embodiments. A machine-readable medium containing instructions for controlling process operations according to the disclosed embodiments can be coupled to the system controller 850.

[0205] In some embodiments, system controller 850 is part of a system, and such a system may be part of the example described above. Such a system can include semiconductor processing equipment that includes one or more processing tools, one or more chambers, one or more processing platforms, and / or specific processing components (such as wafer pedestals, gas flow systems, etc.). These systems may be integrated with electronics for controlling system operation before, during, and after processing of a semiconductor wafer or substrate. Such electronics may sometimes be referred to as a "controller" and may control various components or subcomponents of one or more systems. System controller 850 may be programmed to control any of the processes disclosed herein, depending on the processing conditions and / or the type of system. Such processes include delivery of process gases, temperature setting (e.g., heating and / or cooling), pressure setting, vacuum setting, power setting, radio frequency (RF) generator setting, RF matching circuit setting, frequency setting, flow rate setting, fluid delivery setting, position and motion setting, loading and unloading of wafers to and from tools connected or interfaced to a particular system and other transfer tools, and / or loading and unloading of wafers to and from a load lock.

[0206] In a broad sense, the system controller 850 may be defined as an electronic device having various integrated circuits, logics, memories, and / or software that receive commands, issue commands, control operations, enable cleaning operations, enable endpoint measurements, etc. The integrated circuits may include a chip in the form of firmware that stores program instructions, a digital signal processor (DSP), a chip defined as an application-specific integrated circuit (ASIC), and / or one or more microprocessors, i.e., a microcontroller that executes program instructions (e.g., software). The program instructions are commands communicated to the system controller 850 in the form of various individual settings (or program files) that may define the operating parameters for performing a specific process on or for a semiconductor wafer or for the system. The operating parameters may, in some embodiments, be part of a recipe defined by a process engineer to implement one or more processing steps in the fabrication of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or wafer dies.

[0207] In some embodiments, the system controller 850 may be part of a computer integrated with or coupled to the system, network-connected to the system in some other way, or coupled to such a computer, or a combination thereof. For example, the system controller 850 may be within the "cloud" or may be all or part of the fab host computer system. This enables remote access to wafer processing. The computer can enable remote access to the system, monitor the current progress of the fabrication operation, consider the history of past fabrication operations, consider trends or performance criteria from multiple fabrication operations, change the parameters of the current process, set the process steps following the current process, or initiate a new process. In some examples, a remote computer (e.g., a server) can provide a process recipe to the system over a network. Such a network may include a local network or the Internet. The remote computer may include a user interface that enables entry or programming of parameters and / or settings, and such parameters and / or settings are then communicated from the remote computer to the system. In some examples, the system controller 850 receives instructions in the form of data. Such data specifies the parameters for each process step to be performed during one or more operations. It should be understood that the parameters may be specific to the type of process being performed and the type of tools that the system controller 850 is configured to interact with or control. Thus, as described above, the system controller 850 may be distributed, for example, by including one or more individual controllers that are network-connected to each other and cooperate towards a common purpose (such as the processes and controls described herein).As an example of a distributed controller for such purposes, one or more integrated circuits on a chamber, which are remotely located (e.g., at the platform level or as part of a remote computer) and are combined to control the process in the chamber, could communicate with one or more integrated circuits.

[0208] Exemplary systems can include, but are not limited to, plasma etching chambers or modules, deposition chambers or modules, spin rinse chambers or modules, metal plating chambers or modules, cleaning chambers or modules, bevel edge etching chambers or modules, physical vapor deposition (PVD) chambers or modules, chemical vapor deposition (CVD) chambers or modules, ALD chambers or modules, atomic layer etching (ALE) chambers or modules, ion implantation chambers or modules, tracking chambers or modules, EUV lithography chambers (scanners) or modules, development chambers or modules, and any other semiconductor processing systems that may be related to or used in the fabrication and / or manufacturing of semiconductor wafers.

[0209] As described above, depending on one or more process steps performed by a tool, system controller 850 may communicate with one or more other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, nearby tools, tools located throughout the factory, the main computer, another controller, or a tool used for wafer container loading and unloading in the tool locations and / or load ports within a semiconductor manufacturing factory.

[0210] In certain embodiments, an inductively coupled plasma (ICP) reactor, which may be suitable for etching operations suitable for the implementation of some embodiments, is described herein. Although the ICP reactor is described herein, it should be understood that in some embodiments, capacitively coupled plasma reactors can also be used.

[0211] FIG. 9 schematically shows a cross-sectional view of an inductively coupled plasma apparatus 900 suitable for implementing certain embodiments or aspects of embodiments, such as dry development and / or etching. In other embodiments, it can be implemented using other tools or tool types having the function of performing the dry development and / or etching processes described herein.

[0212] The inductively coupled plasma apparatus 900 includes an integrated process chamber 924 structurally defined by a chamber wall 901 and a window 911. The chamber wall 901 can be fabricated from stainless steel, aluminum, or plastic. The window 911 can be fabricated from quartz or other dielectric materials. An optional internal plasma grid 950 divides the integrated process chamber into an upper sub-chamber 902 and a lower sub-chamber 903. In many embodiments, the plasma grid 950 can be removed, thereby utilizing the chamber space consisting of sub-chambers 902 and 903. A chuck 917 is positioned within the lower sub-chamber 903 near the bottom inner surface. The chuck 917 is configured to receive and hold a semiconductor wafer 919 on which etching and deposition processes are performed. The chuck 917, if present, can be an electrostatic chuck for supporting the wafer 919. In some embodiments, an edge ring (not shown) surrounds the chuck 917 and has an upper surface that is substantially planar with the upper surface of the wafer 919 when present above the chuck 917. The chuck 917 also includes electrostatic electrodes for chucking and de-chucking the wafer 919. For this purpose, a filter and a DC clamp power supply (not shown) may be provided. Other control systems for lifting the wafer 919 from the chuck 917 may also be provided. The chuck 917 can be charged using an RF power supply 923. The RF power supply 923 is connected to a matching circuit 921 through a connection 927. The matching circuit 921 is connected to the chuck 917 through a connection 925. In this way, the RF power supply 923 is connected to the chuck 917. In various embodiments, the bias power of the electrostatic chuck may be set to about 50V, or may be set to different bias powers depending on the process implemented according to the disclosed embodiments. For example, the bias power may be about 20 V~ about 100V, or may be about 30V to about 150V.

[0213] The element for plasma generation includes coil 933 and is positioned above window 911. In some embodiments, the coil is not used in the disclosed embodiments. Coil 933 is fabricated from a conductive material and includes at least one complete turn. The example of coil 933 shown in FIG. 9 includes three turns. The cross-section of coil 933 is indicated by symbols, where the coil with an "X" extends by rotating within the page, while the coil with a "●" extends by rotating outside the page. The element for plasma generation also includes RF power source 941 configured to supply RF power to coil 933. Generally, RF power source 941 is connected to matching circuit 939 through connection 945. Matching circuit 939 is connected to coil 933 through connection 943. In this way, RF power source 941 is connected to coil 933. Optional Faraday shield 949 is positioned between coil 933 and window 911. Faraday shield 949 can be maintained at a spaced-apart relationship with respect to coil 933. In some embodiments, Faraday shield 949 is disposed immediately above window 911. In some embodiments, Faraday shield 949 is between window 911 and chuck 917. In some embodiments, Faraday shield 949 is not maintained at a spaced-apart relationship with respect to coil 933. For example, Faraday shield 949 may be directly under window 911 without a gap. Coil 933, Faraday shield 949, and window 911 are each configured to be substantially parallel to each other. Faraday shield 949 can prevent metal or other species from depositing on window 911 of process chamber 924.

[0214] Process gas can flow into the process chamber through one or more main gas inlets 960 and / or one or more side gas inlets 970 positioned in the upper sub-chamber 902. Similarly, although not explicitly shown, similar gas inlets can be used to supply process gas to the capacitively coupled plasma processing chamber. A vacuum pump, e.g., a single- or two-stage mechanical dry pump and / or a turbomolecular pump 940, can be used to draw process gas out of the process chamber 924 and maintain the pressure within the process chamber 924. For example, a vacuum pump can be used to evacuate the lower sub-chamber 903 during the purge operation of ALD. To selectively control the application of the vacuum environment provided by the vacuum pump, a valve control conduit can be used to fluidly connect the vacuum pump to the process chamber 924. This can be done using a closed-loop control flow restriction device such as a throttle valve (not shown) or a pendulum valve (not shown) during the plasma processing operation. Similarly, a vacuum pump and valve control fluid connection to the capacitively coupled plasma processing chamber can also be used.

[0215] During operation of apparatus 900, one or more process gases can be supplied through gas inlets 960 and / or 970. In certain embodiments, the process gas can be supplied through only the main gas inlet 960 or only the side gas inlet 970. In some cases, the gas inlets shown in the figure may be replaced with more complex gas inlets, e.g., one or more showerheads. The Faraday shield 949 and / or optional grid 950 can include internal channels and holes that allow for the feeding of process gas to the process chamber 924. Either or both of the Faraday shield 949 and optional grid 950 may function as a showerhead for feeding process gas. In some embodiments, a liquid vaporization and feeding system can be disposed upstream of the process chamber 924 such that when a liquid reactant or precursor is vaporized, the vaporized reactant or precursor is introduced into the process chamber 924 through the gas inlets 960 and / or 970.

[0216] High-frequency power is supplied from the RF power supply 941 to the coil 933 so that an RF current flows through the coil 933. The RF current flowing through the coil 933 generates an electromagnetic field around the coil 933. The electromagnetic field generates an induced current within the upper sub-chamber 902. Through the physical and chemical interactions of the various generated ions and radicals with the wafer 919, the features of the wafer 919 are etched and a layer is selectively deposited on the wafer 919.

[0217] When the plasma grid 950 is used such that both the upper sub-chamber 902 and the lower sub-chamber 903 are present, the induced current acts on the gas present in the upper sub-chamber 902 to generate an electron-ion plasma in the upper sub-chamber 902. Optional internal plasma grid 950 limits the number of hot electrons in the lower sub-chamber 903. In some embodiments, the apparatus 900 is designed and operated such that the plasma present in the lower sub-chamber 903 is an ion-ion plasma.

[0218] Both the upper electron-ion plasma and the lower ion-ion plasma can contain positive and negative ions, but the ion-ion plasma has a higher ratio of negative ions to positive ions. Volatile etching and / or deposition by-products can be removed from the lower sub-chamber 903 through the port 922. The chuck 917 disclosed herein can operate at a high temperature in the range of about 10 °C to about 250 °C. The temperature depends on the process operation and the specific recipe.

[0219] When the apparatus 900 is installed in a clean room or a fabrication facility, it may be coupled to a facility (not shown). The facility includes piping that provides process gas, vacuum, temperature control, and environmental particle control. These facilities are coupled to the apparatus 900 when installed in the intended fabrication facility. In addition, the apparatus 900 can be coupled to a transfer chamber that allows a robot to move semiconductor wafers in and out of the apparatus 900 using typical automated operations.

[0220] In some embodiments, a system controller 930 (which can include one or more physical or logical controllers) controls some or all of the operations of the process chamber 924. The system controller 930 can include one or more memory devices and one or more processors. In some embodiments, the apparatus 900 includes a switching system for controlling flow rate and duration when the disclosed embodiments are implemented. In some embodiments, the apparatus 900 can have a switching time of up to about 500 ms, or up to about 750 ms. The switching time can depend on the flowing chemical, the selected recipe, the reactor architecture, and other factors.

[0221] In some embodiments, the system controller 930 is part of a system, and such a system can be part of the examples described above. Such a system can include semiconductor processing equipment including one or more processing tools, one or more chambers, one or more processing platforms, and / or specific processing components (such as wafer pedestals, gas flow systems, etc.). These systems can be integrated with electronics for controlling system operations before, during, and after processing of a semiconductor wafer or substrate. Such electronics can be integrated into the system controller 930 and can control various components or sub-components of one or more systems. The system controller may be programmed to control any of the processes disclosed herein, depending on the processing parameters and / or the type of system. Such processes include delivery of process gases, temperature setting (e.g., heating and / or cooling), pressure setting, vacuum setting, power setting, radio frequency (RF) generator setting, RF matching circuit setting, frequency setting, flow rate setting, fluid delivery setting, position and motion setting, loading and unloading of wafers to and from tools and other transfer tools connected or coupled to a particular system, and / or loading and unloading of wafers to and from a load lock.

[0222] In a broad sense, system controller 930 may be defined as an electronic device having various integrated circuits, logic, memory, and / or software that receive commands, issue commands, control operations, enable cleaning operations, enable endpoint measurements, etc. The integrated circuits may include a chip in the form of firmware that stores program instructions, a digital signal processor (DSP), a chip defined as an application specific integrated circuit (ASIC), and / or one or more microprocessors, i.e., a microcontroller that executes program instructions (e.g., software). The program instructions are commands communicated to the controller in the form of various individual settings (or program files) that may define operating parameters for performing a particular process on or for a semiconductor wafer or for the system. In some embodiments, the operating parameters may be part of a recipe defined by a process engineer to implement one or more processing steps in the fabrication or removal of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or wafer dies.

[0223] In some embodiments, the system controller 930 may be part of a computer that is integrated or coupled with the system or otherwise network-connected to the system, or may be coupled to such a computer, or may be a combination thereof. For example, the controller may be within the "cloud" or may be all or part of a fab host computer system. This enables remote access to wafer processing. The computer enables remote access to the system, monitors the current progress of the fabrication operation, reviews the history of past fabrication operations, reviews trends or performance criteria from multiple fabrication operations, changes the parameters of the current process, sets the process steps following the current process, or may initiate a new process. In some examples, a remote computer (e.g., a server) can provide a process recipe to the system over a network. Such a network may include a local network or the Internet. The remote computer may include a user interface that enables entry or programming of parameters and / or settings, and such parameters and / or settings are then communicated from the remote computer to the system. In some examples, the system controller 930 receives instructions in the form of data. Such data identifies parameters for each process step to be performed during one or more operations. It should be understood that the parameters may be specific to the type of process being performed and the type of tools that the controller is configured to interact with or control. Thus, as described above, the system controller 930 may be distributed, for example, by including one or more individual controllers that are network-connected to each other and cooperate towards a common purpose (such as the processes and controls described herein).As an example of a distributed controller for such purposes, one or more integrated circuits on a chamber, remotely located (e.g., at the platform level or as part of a remote computer) and communicable with one or more integrated circuits combined to control a process in the chamber, may be mentioned.

[0224] Exemplary systems can include, but are not limited to, plasma etching chambers or modules, deposition chambers or modules, spin rinse chambers or modules, metal plating chambers or modules, cleaning chambers or modules, bevel edge etching chambers or modules, physical vapor deposition (PVD) chambers or modules, chemical vapor deposition (CVD) chambers or modules, ALD chambers or modules, ALE chambers or modules, ion implantation chambers or modules, tracking chambers or modules, EUV lithography chambers (scanners) or modules, dry development chambers or modules, and any other semiconductor processing systems that may be related to or used in the fabrication and / or manufacture of semiconductor wafers.

[0225] As described above, depending on one or more process steps performed by a tool, the controller may communicate with one or more other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, proximate tools, tools located throughout the factory, the main computer, another controller, or a tool used for material transport to load and unload wafer containers to and from tool locations and / or load ports within a semiconductor manufacturing facility.

[0226] EUVL patterning can often be performed using any suitable tool, often referred to as a scanner. The EUVL patterning tool may be a stand-alone device that shuttles substrates in and out of it for deposition and etching as described herein. Alternatively, as described below, the EUVL patterning tool may be a module on a larger multi-component tool. FIG. 10 illustrates a semiconductor process cluster tool architecture having a vacuum integrated deposition, EUV patterning, and dry development / etching module that interfaces with a vacuum transfer module suitable for implementation of the processes described herein. The process can be performed without such a vacuum integrated device, but such a device may be advantageous in some embodiments.

[0227] FIG. 10 illustrates a semiconductor process cluster tool architecture 1000 having a vacuum integrated deposition and patterning module that interfaces with a vacuum transfer module suitable for implementation of the processes described herein. The arrangement of transfer modules for "transferring" wafers between multiple storage facilities and processing modules is sometimes referred to as a "cluster tool architecture" system. The deposition and patterning modules are vacuum integrated according to the requirements of a particular process. Other modules, such as for etching, can also be included in the cluster.

[0228] Vacuum Transfer Module (VTM) 1038 interfaces with four processing modules 1020a - 1020d and can be individually optimized to perform various fabrication processes. As an example, the processing modules 1020a - 1020d can be implemented to perform deposition, evaporation, ELD, dry development, etching, strip, and / or other semiconductor processes. For example, module 1020a may be an ALD reactor operable to perform non-plasma thermal atomic layer deposition as described herein. It should be understood that the figure is not necessarily drawn to scale.

[0229] Airlocks 1042 and 1046, also known as load locks or transfer modules, interface with the VTM 1038 and the patterning module 1040. This tool architecture enables the transfer of workpieces, such as semiconductor substrates or wafers, under vacuum so as not to react prior to exposure. The integration of the deposition module and the lithography tool is facilitated by the fact that EUVL also requires a significantly reduced pressure, taking into account the strong light absorption of incident photons by ambient gases such as H2O, O2.

[0230] As described above, this integrated architecture is only one possible embodiment of a tool for implementing the described process. The process can also be implemented using more conventional stand-alone EUVL scanners and, as modules, stand-alone or integrated into a cluster architecture with other tools such as etching, stripping, etc., deposition reactors without an integrated patterning module, as described with reference to FIG. 10.

[0231] Airlock 1042 can be an "unloading" load lock that refers to the transfer of the substrate from the VTM 1038 that operates the deposition module 1020a to the patterning module 1040, and airlock 1046 can be a "loading" load lock that refers to the transfer of the substrate back from the patterning module 1040 to the VTM 1038. The loading load lock 1046 can also provide an interface to the outside of the tool for access and exit of the substrate. Each process module has a facet that interfaces the module to the VTM 1038. For example, the deposition process module 1020a has a facet 1036. Within each facet, sensors, such as the illustrated sensors 1 to 18, are used to detect the passage of the wafer 1026 when moving between the respective stations. The patterning module 1040 and the airlocks 1042 and 1046 can similarly be provided with additional facets and sensors (not shown).

[0232] The main VTM robot 1022 transfers the wafer 1026 between modules including the airlocks 1042 and 1046. In one embodiment, the robot 1022 has one arm, and in another embodiment, the robot 1022 has two arms, and each arm has an end effector 1024 for lifting wafers such as the wafer 1026 for conveyance. The front-end robot 1044 is 、w used to transfer the wafer 1026 from the outfeed airlock 1042 to the patterning module 1040 and from the patterning module 1040 to the infeed airlock 1046. The front-end robot 1044 can also transfer the wafer 1026 between the infeed load lock and the outside of the tool for access and exit of the substrate. Since the infeed airlock module 1046 has the ability to adapt the environment between atmospheric pressure and vacuum, the wafer 1026 can move between the two pressure environments without being damaged.

[0233] Note that EUVL tools typically operate at a higher vacuum than deposition tools. In this case, it is desirable to increase the vacuum environment of the substrate during transfer between the deposition tool and the EUVL tool to enable outgassing of the substrate before entering the patterning tool. The outfeed airlock 1042 can provide this function by holding wafers transferred at a low pressure not higher than the pressure within the patterning module 1040 for a certain period of time and discharging off-gas, thereby preventing the optical system of the patterning tool 1040 from being contaminated by off-gas from the substrate. The appropriate pressure for the off-gas discharge airlock is 1E-8 Torr or less.

[0234] In some embodiments, system controller 1050 (which can include one or more physical or logical controllers) controls some or all of the operation of the cluster tool and / or its individual modules. Note that the controller can be local to the cluster architecture, or can be located external to the cluster architecture on the manufacturing floor, or can be located remotely and connected to the cluster architecture via a network. System controller 1050 can include one or more memory devices and one or more processors. The processor can include a central processing unit (CPU) or computer, analog and / or digital input / output connections, a stepper motor controller board, and other similar components. Instructions for performing appropriate control operations are executed on the processor. These instructions can be stored in a memory device associated with the controller or can be provided via a network. In certain embodiments, the system controller executes system control software.

[0235] The system control software can include instructions for controlling the timing of application and / or the magnitude of any aspect of the tool or module operation. The system control software can be configured in any suitable manner. For example, various process tool component subroutines or control objects may be written to control the operation of the process tool components required to execute various process tool processes. The system control software can be coded in any suitable computer-readable programming language. In some embodiments, the system control software includes input / output control (IOC) sequence instructions for controlling the various parameters described above. For example, each stage of a semiconductor manufacturing process can include one or more instructions executed by the system controller. For example, instructions for setting process conditions for condensation, deposition, evaporation, patterning, and / or etching stages may be included in the corresponding recipe stage.

[0236] In various embodiments, an apparatus for forming a negative pattern mask is provided. The apparatus can include a processing chamber for patterning, deposition, and etching, and a controller including instructions for forming a negative pattern mask. The instructions can include code for patterning features in a chemically amplified resist (CAR) on a semiconductor substrate by EUV exposure to expose the surface of the substrate, developing the photopatterned resist, and etching an underlying layer or layer stack using the patterned resist as a mask. The development may be performed using a halide-containing chemical.

[0237] Note that a computer controlling wafer movement can be local to the cluster architecture, or can be located external to the cluster architecture of the manufacturing floor, or can be located remotely and connected to the cluster architecture via a network. The controller described above with respect to any of FIGS. 7, 8, or 9 can be implemented using the tool of FIG. 10.

[0238] Conclusion It is understood that the examples and embodiments described herein are for illustrative purposes only, and various modifications or changes will be suggested to those skilled in the art in light of them. Various details have been omitted for clarity, but alternative designs can be implemented. Thus, this example is considered to be illustrative rather than limiting, and the present disclosure is not limited to the details given herein and can be modified within the scope of the present disclosure. The present disclosure may be implemented in the following forms. [Form 1] A method for processing a semiconductor substrate, comprising: providing a photopatterned metal-containing resist on a semiconductor substrate on a pedestal in a process chamber; developing the photopatterned metal-containing resist to form a resist mask by selectively removing a portion of the photopatterned metal-containing resist by exposing the photopatterned metal-containing resist to at least one cycle including alternately fed pulses of an etchant and pulses of an oxidizing agent; A method comprising. [Form 2] The method according to Form 1, wherein the pulses of the etchant and the pulses of the oxidizing agent are temporally separate. [Form 3] The method according to Form 1, wherein the pedestal is at a first temperature during the pulses of the etchant and the oxidizing agent is fed into the process chamber at a second temperature. [Form 4] The method according to Form 1, wherein the pedestal is at a first temperature during the pulses of the etchant and the pedestal is at a second temperature during the pulses of the oxidizing agent. [Form 5] The method according to Form 1, wherein the duration of the pulses of the etchant is about 1 to about 120 seconds and the duration of the pulses of the oxidizing agent is about 1 to about 120 seconds. [Form 6] The method according to Form 3, wherein the first temperature is about -60°C to about 120°C. [Form 7] The method according to Form 4, wherein the second temperature is about 20°C to about 150°C. [Form 8] The method according to Form 3, wherein the second temperature is about 50°C to about 250°C. [Form 9] The method according to Form 1, wherein non-volatile by-products of the pulses of the etchant are removed from the photopatterned metal-containing resist. [Form 10] The method according to Form 1, wherein the photopatterned metal-containing resist contains an organometallic oxide, a metal, a metal oxide, or an organometallic. [Form 11] The method according to Form 10, wherein the metal oxide contains tin oxide. [Form 12] The method according to Form 1, The method wherein the etchant is a halide etchant. [Form 13] The method according to Form 12, wherein the halide etchant includes hydrogen halide, hydrogen gas and halogen gas, organic halide, acyl halide, carbonyl halide, thionyl halide, or a combination thereof. [Form 14] The method according to Form 12, wherein the halide etchant includes hydrogen fluoride, hydrogen chloride, boron trichloride, hydrogen bromide, hydrogen iodide, or a combination thereof. [Form 15] The method according to Form 1, wherein the etchant includes etchant plasma. [Form 16] The method according to Form 15, wherein the etchant plasma is generated remotely. [Form 17] The method according to Form 1, wherein the oxidizing agent includes oxygen, ozone, hydrogen peroxide, water, nitrous oxide, nitric oxide, nitrogen dioxide, nitric acid, sulfur dioxide, chlorine, fluorine, bromine, iodine, or a combination thereof. [Form 18] The method according to Form 17, wherein the oxidizing agent is a gaseous oxidizing agent including water and oxygen or chlorine. [Form 19] The method according to Form 1, wherein the oxidizing agent includes oxidizing agent plasma. [Form 20] The method according to Form 19, wherein the oxidizing agent plasma is generated remotely. [Form 21] The method according to Form 1, further including exposing the photopatterned metal-containing resist to an inert plasma gas. [Form 22] The method according to Form 1, further including purging the process chamber with an inert gas between the pulse of the etchant and the pulse of the oxidizing agent, or after the cycles of the pulses of the etchant and the pulses of the oxidizing agent. [Form 23] The method according to Form 1, wherein developing the photopatterned metal-containing resist by exposing it to alternating pulses of an etchant and an oxidizing agent includes dry-developing the photopatterned metal-containing resist. [Form 24] The method according to Form 1, wherein developing the photopatterned metal-containing resist by exposing it to alternating pulses of an etchant and an oxidizing agent includes wet-developing the photopatterned metal-containing resist. [Form 25] The method according to Form 1, wherein each cycle has the same etchant pulse duration, the method. [Form 26] A method for processing a semiconductor substrate, comprising providing a photopatterned metal-containing resist on a semiconductor substrate on a pedestal in a process chamber; and developing the photopatterned metal-containing resist to form a resist mask by selectively removing a portion of the photopatterned metal-containing resist by exposing the photopatterned metal-containing resist to an etchant and subsequently exposing it to a cleaning agent. The method comprising. [Form 27] The method according to Form 26, wherein the cleaning agent includes water, methanol, ethanol, isopropanol, acetone, acetonitrile, tetrahydrofuran, dimethyl sulfide, or a combination thereof, the method. [Form 28] The method according to Form 26, wherein the pedestal temperature is from about 10 °C to about 50 °C during exposure to the cleaning agent, the method. [Form 29] The method according to Form 26, wherein the cleaning agent includes a supercritical fluid, the method. [Form 30] The method according to Form 29, wherein the supercritical fluid is a supercritical liquid with low surface tension, the method. [Form 31] The method according to Form 30, wherein the supercritical liquid with low surface tension includes carbon dioxide, sulfur dioxide, dimethyl ether, or a combination thereof, the method. [Form 32] The method according to Form 29, wherein the process chamber pressure is from about 5 psi to about 3,000 psi during exposure to the cleaning agent, the method. [Form 33] The method according to Form 26, wherein non-volatile by-products from exposure to the etchant are removed from the photopatterned metal-containing resist, the method. [Form 34] The method according to Form 26, wherein the photopatterned metal-containing resist includes an organometallic oxide, a metal, a metal oxide, or an organometallic, the method. [Form 35] The method according to Form 34, wherein the metal oxide includes tin oxide, the method. [Form 36] The method according to Form 26, wherein the etchant is a halide etchant, the method. [Form 37] The method according to Form 36, wherein the halide etchant includes hydrogen halide, hydrogen gas and halogen gas, organic halide, acyl halide, carbonyl halide, thionyl halide, or a combination thereof, the method. [Form 38] The method according to Form 36, wherein the halide etchant comprises hydrogen fluoride, hydrogen chloride, boron trichloride, hydrogen bromide, hydrogen iodide, or a combination thereof. [Form 39] The method according to Form 26, wherein the etchant comprises an etchant plasma. [Form 40] The method according to Form 39, wherein the etchant plasma is remotely generated. [Form 41] A method for promoting atomic layer etching on a substrate, comprising: providing a photopatterned metal-containing resist on a semiconductor substrate on a pedestal in a process chamber; developing the photopatterned metal-containing resist to form a resist mask by selectively removing a part of the resist by exposing the photopatterned metal-containing resist to at least one cycle including alternately fed pulses of an etchant and pulses of an oxidant; thereby excluding etch stop by non-volatile by-products of the etchant pulses. A method. [Form 42] A method for processing a semiconductor substrate, comprising: providing a dry-deposited photopatterned metal oxide EUV resist on a semiconductor substrate on a pedestal in a process chamber; dry-developing the photopatterned metal oxide EUV resist to form a resist hard mask by selectively removing a EUV non-exposed portion of the EUV resist by exposing it to at least one cycle including alternately fed pulses of an etchant and pulses of an oxidant. A method. [Form 43] An apparatus for developing a resist, comprising: a process chamber having a substrate support; a vacuum line coupled to the process chamber; an etchant and oxidant line coupled to the process chamber; a controller configured with instructions for processing a semiconductor substrate, the instructions including providing a photopatterned metal-containing resist on a semiconductor substrate in the process chamber; developing the photopatterned metal-containing resist to form a resist mask by selectively removing a part of the resist by exposing it to at least one cycle of alternately fed etchant pulses and oxidant pulses; a controller including code for this purpose; An apparatus. [Form 44] ​ The apparatus according to Form 43, wherein the photo-patterned metal-containing resist is a photo-patterned metal-containing EUV resist, and the controller configured by instructions including code for developing the photo-patterned metal-containing EUV resist selectively removes the non-EUV-exposed portion of the EUV resist compared to the EUV-exposed portion by at least one cycle of alternately fed etchant pulses and oxidant pulses, and includes code for forming a resist mask, the apparatus. [Form 45] The apparatus according to Form 43, wherein one or more heaters coupled to the substrate support, and the one or more heaters include one or more heaters including a plurality of independently controllable temperature control zones and further includes the apparatus. [Form 46] The apparatus according to Form 45, wherein the apparatus further includes a heated oxidant supply line.

Claims

1. A method for processing a semiconductor substrate, comprising: providing a photopatterned metal-containing resist on a semiconductor substrate on a pedestal within a process chamber; developing the photopatterned metal-containing resist to form a resist mask by selectively removing a portion of the photopatterned metal-containing resist by exposing the photopatterned metal-containing resist to at least one cycle including alternately fed pulses of an etchant and pulses of an oxidant; purging the process chamber with an inert gas between the pulses of the etchant and the pulses of the oxidant. A method comprising the above steps.

2. The method according to claim 1, wherein the pulses of the etchant and the pulses of the oxidant are temporally separate.

3. The method according to claim 1, wherein the pedestal is at a first temperature during the pulses of the etchant, and the oxidant is fed into the process chamber at a second temperature.

4. The method according to claim 1, wherein the pedestal is at a first temperature during the pulses of the etchant and at a second temperature during the pulses of the oxidant.

5. The method according to claim 1, wherein the duration of the pulses of the etchant is from 1 to 120 seconds, and the duration of the pulses of the oxidant is from 1 to 120 seconds.

6. The method according to claim 3, wherein the first temperature is from -60°C to 120°C.

7. The method according to claim 4, wherein the second temperature is from 20°C to 150°C.

8. The method according to claim 3, wherein the second temperature is from 50°C to 250°C.

9. The method according to claim 1, wherein non-volatile by-products of the pulses of the etchant are removed from the photopatterned metal-containing resist.

10. The method according to claim 1, wherein the photopatterned metal-containing resist comprises an organometallic oxide, a metal, a metal oxide, or an organometallic.

11. The method according to claim 10, wherein the metal oxide comprises tin oxide.

12. The method according to claim 1, wherein the etchant is a halide etchant.

13. The method according to claim 12, wherein the halide etchant comprises hydrogen halide, hydrogen gas and halogen gas, organic halide, acyl halide, carbonyl halide, thionyl halide, or a combination thereof.

14. The method according to claim 12, wherein the halide etchant comprises hydrogen fluoride, hydrogen chloride, boron trichloride, hydrogen bromide, hydrogen iodide, or a combination thereof.

15. The method according to claim 1, wherein the etchant comprises etchant plasma.

16. The method according to claim 15, wherein the etchant plasma is generated remotely.

17. The method according to claim 1, wherein the oxidizing agent comprises oxygen, ozone, hydrogen peroxide, water, nitrous oxide, nitric oxide, nitrogen dioxide, nitric acid, sulfur dioxide, chlorine, fluorine, bromine, iodine, or a combination thereof.

18. The method according to claim 17, wherein the oxidizing agent is a gaseous oxidizing agent comprising water and oxygen or chlorine.

19. The method according to claim 1, wherein the oxidizing agent comprises oxidizing agent plasma.

20. The method according to claim 19, wherein the oxidizing agent plasma is generated remotely.

21. The method according to claim 1, further comprising exposing the photopatterned metal-containing resist to an inert plasma gas.

22. The method according to claim 1, further comprising purging the process chamber with the inert gas after a cycle of pulses of the etchant and pulses of the oxidizing agent.

23. The method according to claim 1, wherein developing the photopatterned metal-containing resist by exposing it to alternating pulses of etchant and oxidizing agent comprises dry-developing the photopatterned metal-containing resist.

24. The method according to claim 1, wherein each cycle has the same etchant pulse duration.

25. A method for promoting atomic layer etching on a substrate, comprising providing a photopatterned metal-containing resist on a semiconductor substrate on a pedestal within a process chamber, Developing the photopatterned metal-containing resist to form a resist mask by selectively removing a portion of the resist by exposing the photopatterned metal-containing resist to at least one cycle of alternately delivered pulses of an etchant and pulses of an oxidizing agent. Purging the process chamber with an inert gas between the pulses of the etchant and the pulses of the oxidizing agent. comprising thereby eliminating etch stop due to non-volatile by-products of the pulses of the etchant. Method. **Claim 26** A method of processing a semiconductor substrate, comprising: Providing a photopatterned metal oxide EUV resist dry-deposited on a semiconductor substrate on a pedestal within a process chamber. Developing the photopatterned metal oxide EUV resist to form a resist hard mask by selectively removing the EUV non-exposed portion of the EUV resist by exposing it to at least one cycle of alternately delivered pulses of an etchant and pulses of an oxidizing agent. Purging the process chamber with an inert gas between the pulses of the etchant and the pulses of the oxidizing agent. Method. **Claim 27** An apparatus for developing a resist, comprising: A process chamber having a substrate support. A vacuum line coupled to the process chamber. An etchant and oxidizing agent line coupled to the process chamber. A controller configured with instructions for processing a semiconductor substrate, the instructions including: Providing a photopatterned metal-containing resist on a semiconductor substrate within the process chamber. Developing the photopatterned metal-containing resist to form a resist mask by selectively removing a portion of the resist by exposing it to at least one cycle of alternately delivered etchant pulses and oxidizing agent pulses. Purging the process chamber with an inert gas between the etchant pulses and the oxidizing agent pulses. controller including code for Apparatus. **Claim 28** The apparatus according to claim 27, The photo-patterned metal-containing resist is a photo-patterned metal-containing EUV resist, and the controller composed of instructions including code for developing the photo-patterned metal-containing EUV resist selectively removes the non-EUV-exposed portion of the EUV resist compared to the EUV-exposed portion by at least one cycle of alternately supplied etchant pulses and oxidant pulses, and includes code for forming a resist mask, a device.

29. The device according to claim 27, One or more heaters coupled to the substrate support, wherein the one or more heaters include one or more heaters including a plurality of independently controllable temperature control zones further comprising a device.

30. The device according to claim 29, further comprising a heated oxidant supply line, a device.

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