Wafer and method for manufacturing the same

Abstract

To provide a wafer and a wafer manufacturing method capable of suppressing the remaining of a resist layer used for forming a conductive bump.SOLUTION: A wafer includes a substrate having a first surface provided with a first region in which a plurality of effective chip regions are arranged and a second region provided around the first region, a plurality of first conductive bumps provided on the first surface of the substrate within the first region, and a plurality of second conductive bumps provided on the first surface of the substrate within the second region, and in plan view from a direction perpendicular to the first surface, the areal density of the second conductive bumps in the second region is lower than the areal density of the first conductive bumps in the first region.SELECTED DRAWING: Figure 11

Description

Technical Field

[0001] The present disclosure relates to a wafer and a method for manufacturing a wafer.

Background Art

[0002] As a method for manufacturing a wafer used in the manufacture of semiconductor devices, a method of forming on a substrate having an active region and an inactive region Electrode pad and then forming a plurality of conductive bumps by an electrolytic plating method is known. The active region is a region where a plurality of active chips are arranged, and the inactive region is provided around the active region. The conductive bumps are formed in both the active region and the inactive region with substantially the same size and substantially the same pitch.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] When forming conductive bumps by a subtractive method, the resist layer is removed after the plating process. However, in a conventional wafer, the resist layer may remain in the inactive region even after the process for removing the resist layer is performed.

[0005] An object of the present disclosure is to provide a wafer and a method for manufacturing a wafer that can suppress the remaining of a resist layer used for forming conductive bumps.

Means for Solving the Problems

[0006] According to one embodiment of the present disclosure, a substrate having a first surface includes a first region in which a plurality of effective chip regions are arranged, and a second region provided around the first region. The substrate has a plurality of first conductive bumps provided on the first surface of the substrate within the first region, and a plurality of second conductive bumps provided on the first surface of the substrate within the second region. In a plan view from a direction perpendicular to the first surface, the area density of the second conductive bumps in the second region is lower than the area density of the first conductive bumps in the first region. wherein an area density of the second conductive bump in the second region continuously or stepwise decreases as it moves away from the first region A wafer is provided.

Advantages of the Invention

[0007] According to the disclosed technology, the residue of the resist layer used for forming the conductive bumps can be suppressed.

Brief Description of the Drawings

[0008]

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MODE FOR CARRYING OUT THE INVENTION

[0009] The inventors of the present application have conducted intensive studies to investigate the cause of the remaining resist layer in the invalid region in the conventional wafer. As a result, in the conventional wafer, since no conductive bumps are formed outside the invalid region, when the conductive bumps are formed by the electroplating method, the current density in the invalid region becomes higher than the current density in the valid region, and it has been found that the conductive bumps formed in the invalid region are more likely to be higher than the conductive bumps formed in the valid region. The higher the conductive bumps become, the more difficult it is to inhibit the swelling of the resist layer during the removal of the resist layer, and the more difficult it is to remove the resist layer.

[0010] In this way, by forming the conductive bumps high in the invalid region, the resist layer is likely to remain.

[0011] Based on such findings, the inventors of the present application have conceived the following embodiments.

[0012] Hereinafter, the embodiments will be specifically described with reference to the accompanying drawings. In the present specification and drawings, for components having substantially the same functional configuration, the same reference numerals may be given to omit redundant explanations.

[0013] (First Embodiment) First, the first embodiment will be described. The first embodiment relates to a wafer.

[0014] [Configuration of Wafer] Figs. 1 and 2 are top views showing a wafer according to the first embodiment. Fig. 2 shows an enlarged view of region 40 in Fig. 1. Fig. 3 is a cross-sectional view showing the wafer according to the first embodiment. Fig. 3 corresponds to a cross-sectional view taken along line III-III in Fig. 1. Fig. 4 is a diagram showing the distribution of the area density of the conductive bumps in the wafer according to the first embodiment.

[0015] As shown in Figs. 1 and 2, the wafer 1 according to the first embodiment has a substrate 10, a plurality of first conductive bumps 135, and a plurality of second conductive bumps 235. In the present disclosure, for convenience, the side of the first conductive bumps 135 and the second conductive bumps 235 of the wafer 1 is defined as the upper side or one side, and the opposite side is defined as the lower side or the other side. Also, the surface on the side of the first conductive bumps 135 and the second conductive bumps 235 of the wafer 1 is defined as one surface or the upper surface, and the surface on the opposite side is defined as the other surface or the lower surface.

[0016] The substrate 10 has a circuit formation surface 11. The diameter of the substrate 10 is, for example, 300 mm (12 inches) or 200 mm (8 inches). The first conductive bumps 135 and the second conductive bumps 235 are provided on the circuit formation surface 11. In the present disclosure, a plan view refers to viewing an object from the normal direction of the circuit formation surface 11 of the wafer 1, and a planar shape refers to the shape of an object viewed from the normal direction of the circuit formation surface 11 of the wafer 1. The circuit formation surface 11 is an example of the first surface.

[0017] The substrate 10 includes a bump formation region 21 and a bump non-formation region 22 provided around the bump formation region 21. Although conductive bumps described later are formed in the bump formation region 21, no conductive bumps are formed in the bump non-formation region 22. The radial dimension (width) of the bump non-formation region 22 is, for example, about 1.5 mm. The bump formation region 21 includes an effective region 100 in which a plurality of effective chip regions 110 are arranged, and an invalid region 200 provided around the effective region 100. The effective chip regions 110 are arranged in an array in a plan view. The effective chip regions 110 are inside the boundary 30 between the effective region 100 and the invalid region 200. The chip regions on the boundary 30 are defined as invalid chip regions 210. The semiconductor chips cut out from the effective chip regions 110 by dicing are used as products, while the semiconductor chips cut out from the invalid chip regions 210 are not used as products. The radial dimension (width) of the invalid region 200 is, for example, about 3 mm to 10 mm. The effective region 100 is an example of a first region, and the invalid region 200 is an example of a second region.

[0018] The substrate 10 is configured, for example, by forming a semiconductor integrated circuit or the like on a semiconductor substrate made of silicon or the like. As shown in FIG. 3, a plurality of first electrode pads 130 and a plurality of second electrode pads 230 are provided on the substrate 10. The first electrode pads 130 are provided within the effective region 100, and the second electrode pads 230 are provided within the invalid region 200. The first electrode pads 130 are connected to the semiconductor integrated circuit, while the second electrode pads 230 are not connected to the semiconductor integrated circuit. The first electrode pads 130 and the second electrode pads 230 are formed of, for example, aluminum (Al).

[0019] In plan view, the area density of the second electrode pads 230 within the invalid region 200 is lower than the area density of the first electrode pads 130 within the effective region 100, for example, about 25%. In plan view, the pitch of the second electrode pads 230 within the invalid region 200 is larger than the pitch of the first electrode pads 130 within the effective region 100, for example, about 200%. In plan view, the area density and pitch of the second electrode pads 230 within the invalid region 200 are substantially uniform. For example, the pitch of the first electrode pads 130 is 10 μm to 100 μm, and the pitch of the second electrode pads 230 is 20 μm to 200 μm. Note that in plan view, the equivalent circle diameters may be equal between each of the plurality of first electrode pads 130 and each of the plurality of second electrode pads 230. In plan view, the number density of the second electrode pads 230 within the invalid region 200 is lower than the number density of the first electrode pads 130 within the effective region 100. Here, the area density of the pads refers to the ratio of the area occupied by the pads per unit area. The number density of the pads refers to the number of pads contained per unit area. The pitch of the pads refers to the center-to-center distance in plan view between adjacent pads.

[0020] The first conductive bumps 135 are provided on the first electrode pads 130 within the effective region 100. The first conductive bumps 135 include a first seed layer 131, a first copper (Cu) layer 132, and a first solder layer 133.

[0021] The first seed layer 131 is in direct contact with the first electrode pads 130. The material of the first seed layer 131 is, for example, copper, titanium (Ti), chromium (Cr), tungsten (W), or an alloy of any combination thereof. The first seed layer 131 may include a laminated film, and each material of the laminated film may be, for example, copper, titanium, chromium, tungsten, or an alloy of any combination thereof. The thickness of the first seed layer 131 is, for example, about 0.01 μm to 0.3 μm. The planar shape of the first seed layer 131 is, for example, substantially circular. In this case, the diameter of the first seed layer 131 is, for example, about 5 μm to 100 μm, preferably about 10 μm to 20 μm.

[0022] The first copper layer 132 has a columnar shape such as a cylindrical shape. The first copper layer 132 is an electrolytic plating layer and is in direct contact with the first seed layer 131. The thickness of the first copper layer 132 is, for example, about 10 μm to 200 μm, preferably about 20 μm to 150 μm. The planar shape of the first copper layer 132 is substantially the same as the planar shape of the first seed layer 131, and the first copper layer 132 is formed so as to overlap the first seed layer 131 in plan view. The first copper layer 132 is an example of the first copper pillar.

[0023] The first solder layer 133 is in direct contact with the first copper layer 132. The shape of the first solder layer 133 is, for example, dome-shaped. Here, the dome shape means a shape in which the height in the vicinity of the central portion is high and decreases toward the peripheral portion. The thickness (the maximum thickness in the vicinity of the central portion) of the first solder layer 133 is, for example, about 10 μm. The planar shape of the first solder layer 133 is substantially the same as the planar shape of the first copper layer 132, and the first solder layer 133 is formed so as to overlap the first copper layer 132 in plan view. The material of the first solder layer 133 is, for example, an alloy containing lead (Pb), an alloy of tin (Sn) and Cu, an alloy of Sn and silver (Ag), an alloy of Sn, Ag and Cu, etc.

[0024] The height of the first conductive bump 135 is, for example, about 10 μm to 200 μm. The first solder layer 133 may not be provided. Another metal layer such as a nickel (Ni) layer may be provided between the first copper layer 132 and the first solder layer 133.

[0025] The second seed layer 231 is in direct contact with the second electrode pad 230. The material of the second seed layer 231 may be the same as the material of the first seed layer 131. The thickness of the second seed layer 231 is, for example, about 0.01 μm to 0.3 μm. The planar shape of the second seed layer 231 is, for example, substantially circular. In this case, the diameter of the second seed layer 231 is, for example, about 5 μm to 100 μm, preferably about 10 μm to 20 μm.

[0026] The second copper layer 232 has a columnar shape such as a cylindrical shape. The second copper layer 232 is an electrolytic plating layer and is in direct contact with the second seed layer 231. The thickness of the second copper layer 232 is, for example, about 10 μm to 200 μm, preferably about 20 μm to 150 μm. The planar shape of the second copper layer 232 is substantially the same as the planar shape of the second seed layer 231, and the second copper layer 232 is formed so as to overlap the second seed layer 231 in plan view. The second copper layer 232 is an example of the second copper pillar.

[0027] The second solder layer 233 is in direct contact with the second copper layer 232. The shape of the second solder layer 233 is, for example, dome-shaped. The thickness (maximum thickness near the central portion) of the second solder layer 233 is, for example, about 10 μm. The planar shape of the second solder layer 233 is substantially the same as the planar shape of the second copper layer 232, and the second solder layer 233 is formed so as to overlap the second copper layer 232 in plan view. The material of the second solder layer 233 may be the same as the material of the first solder layer 133.

[0028] The height of the second conductive bump 235 is, for example, about 10 μm to 200 μm. The second solder layer 233 may not be provided. Another metal layer such as a nickel layer may be provided between the second copper layer 232 and the second solder layer 233.

[0029] As described above, in plan view, the area density of the second electrode pads 230 within the invalid region 200 is lower than the area density of the first electrode pads 130 within the effective region 100, for example, about 25%. Therefore, as shown in FIGS. 2 to 4, in plan view, the area density of the second conductive bumps 235 within the invalid region 200 is lower than the area density of the first conductive bumps 135 within the effective region 100, for example, about 25%. Also, in plan view, the pitch of the second conductive bumps 235 within the invalid region 200 is larger than the pitch of the first conductive bumps 135 within the effective region 100, for example, about 200%. In plan view, the area density and pitch of the second conductive bumps 235 within the invalid region 200 are substantially uniform. For example, the pitch of the first conductive bumps 135 is 10 μm to 100 μm, and the pitch of the second conductive bumps 235 is 20 μm to 200 μm. Note that, in plan view, the equivalent circle diameter may be equal between each of the plurality of first conductive bumps 135 and each of the plurality of second conductive bumps 235. In plan view, the number density of the second conductive bumps 235 within the invalid region 200 is lower than the number density of the first conductive bumps 135 within the effective region 100.

[0030] [Method of manufacturing a wafer] Next, a method of manufacturing the wafer 1 according to the first embodiment will be described. FIGS. 5 to 10 are cross-sectional views showing the method of manufacturing the wafer according to the first embodiment. FIGS. 5 to 10 correspond to cross-sectional views taken along line III-III in FIG. 1.

[0031] First, as shown in FIG. 5, a substrate 10 having a plurality of first electrode pads 130 and a plurality of second electrode pads 230 formed on the circuit formation surface 11 is prepared.

[0032] Next, as shown in FIG. 6, a seed layer 331 is formed on the substrate 10 so as to cover the first electrode pad 130 and the plurality of second electrode pads 230. The seed layer 331 is a layer that will later become the first seed layer 131 and the second seed layer 231. The material of the seed layer 331 is the same as that of the first seed layer 131 and the second seed layer 231, and the thickness of the seed layer 331 is equal to the thicknesses of the first seed layer 131 and the second seed layer 231. The seed layer 331 can be formed, for example, by sputtering or electroless plating.

[0033] Next, as shown in FIG. 7, a resist layer 300 is formed on the seed layer 331. Specifically, for example, a dry film resist made of a photosensitive resin or the like as the resist layer 300 is laminated on the seed layer 331. Then, the resist layer 300 is patterned by exposure and development to form a plurality of first openings 311 and a plurality of second openings 312 in the resist layer 300. The first openings 311 and the second openings 312 are formed so that the seed layer 331 is exposed. The first openings 311 are formed at positions where the first conductive bumps 135 are to be formed within the effective region 100, and the second openings 312 are formed at positions where the second conductive bumps 235 are to be formed within the invalid region 200. The thickness of the resist layer 300 is larger than the heights of the first conductive bumps 135 and the second conductive bumps 235 to be formed, and is, for example, about 20 μm to 210 μm.

[0034] Next, as shown in FIG. 8, a first copper layer 132 is formed on the upper surface of the seed layer 331 exposed from the first opening 311, and a second copper layer 232 is formed on the upper surface of the seed layer 331 exposed from the second opening 312 by an electrolytic plating method using the seed layer 331 as a plating power supply path. Next, a first solder layer 133 is formed on the first copper layer 132, and a second solder layer 233 is formed on the second copper layer 232 by an electrolytic plating method using the seed layer 331 as a plating power supply path.

[0035] Next, as shown in FIG. 9, the resist layer 300 is removed. The resist layer 300 can be peeled off, for example, using a peeling solution containing sodium hydroxide or the like.

[0036] Next, as shown in FIG. 10, using an etching solution, the portions of the seed layer 331 exposed from the first solder layer 133 or the second solder layer 233 are removed. As the etching solution, for example, an aqueous solution mainly composed of hydrogen peroxide and sulfuric acid, an aqueous solution of sodium persulfate, an aqueous solution of ammonium persulfate, an etching solution such as nitric acid can be used.

[0037] Next, by reflow or the like, the first solder layer 133 and the second solder layer 233 are melted and then solidified to be formed into a dome shape or the like. In this way, the first conductive bump 135 is formed on the first electrode pad 130, and the second conductive bump 235 is formed on the second electrode pad 230.

[0038] In this way, the wafer 1 according to the first embodiment can be manufactured.

[0039] In the wafer 1 according to the first embodiment, in a plan view, the area density of the second electrode pads 230 in the non-effective region 200 is lower than the area density of the first electrode pads 130 in the effective region 100. Therefore, in a plan view, the area density of the second conductive bumps 235 in the non-effective region 200 is lower than the area density of the first conductive bumps 135 in the effective region 100. Accordingly, even when forming the first copper layer 132 and the second copper layer 232, and when forming the first solder layer 133 and the second solder layer 233, an excessive increase in the current density in the non-effective region 200 can be suppressed. For this reason, it is easy to adjust the height of the second conductive bump 235 to be approximately the same as the height of the first conductive bump 135. As a result, also in the non-effective region 200, when removing the resist layer 300, the resist layer 300 is likely to swell due to the stripping solution, and the remaining of the resist layer 300 used for forming the first conductive bump 135 and the second conductive bump 235 can be suppressed.

[0040] Furthermore, since the arrangement of the second conductive bumps 235 is sparser than the arrangement of the first conductive bumps 135, the stripping solution easily penetrates into the resist layer 300, and in this respect also, the remaining of the resist layer 300 can be suppressed.

[0041] (Second Embodiment) Next, the second embodiment will be described. The second embodiment is mainly different from the first embodiment in terms of the arrangement of the second conductive bumps 235. FIG. 11 is a top view showing a wafer according to the second embodiment. FIG. 12 is a diagram showing the distribution of the area density of the conductive bumps in the wafer according to the second embodiment.

[0042] As shown in FIGS. 11 and 12, in a plan view, the area density and the number density of the second electrode pads 230 and the second conductive bumps 235 within the non-effective region 200 continuously decrease as they move away from the effective region 100. That is, in a plan view, the area density and the number density of the second electrode pads 230 and the second conductive bumps 235 within the non-effective region 200 continuously decrease in the radial direction of the substrate 10. For example, the area density and the number density of the second electrode pads 230 and the second conductive bumps 235 in the vicinity of the boundary 30 between the effective region 100 and the non-effective region 200 may be of the same degree as the area density and the number density of the first electrode pads 130 and the first conductive bumps 135. Also, for example, the area density and the number density of the second electrode pads 230 and the second conductive bumps 235 at the outer edge of the non-effective region 200 may be substantially zero.

[0043] Other configurations are the same as those in the first embodiment.

[0044] The second embodiment can also achieve the same effects as the first embodiment. Also, since the area density and the number density of the second conductive bumps 235 continuously decrease as they move away from the effective region 100, during the formation of the first copper layer 132 and the second copper layer 232, and also during the formation of the first solder layer 133 and the second solder layer 233, the current density in the non-effective region 200 changes gently. Therefore, it is easier to further adjust the height of the second conductive bumps 235 to be approximately the same as the height of the first conductive bumps 135. As a result, it is easier to further suppress the residue of the resist layer 300 used for the formation of the first conductive bumps 135 and the second conductive bumps 235.

[0045] (Third Embodiment) Next, the third embodiment will be described. The third embodiment is mainly different from the first and second embodiments in terms of the arrangement of the second conductive bumps 235. FIG. 13 is a top view showing a wafer according to the third embodiment. FIG. 14 is a diagram showing the distribution of the area density of the conductive bumps in the wafer according to the third embodiment.

[0046] As shown in FIGS. 13 and 14, the invalid region 200 has a first annular region 201, a second annular region 202, a third annular region 203, and a fourth annular region 204. In a plan view, the entire inner edge of the first annular region 201 is in contact with the entire outer edge of the effective region 100. In a plan view, the entire inner edge of the second annular region 202 is in contact with the entire outer edge of the first annular region 201. In a plan view, the entire inner edge of the third annular region 203 is in contact with the entire outer edge of the second annular region 202. In a plan view, the entire inner edge of the fourth annular region 204 is in contact with the entire outer edge of the third annular region 203. In a plan view, the entire outer edge of the fourth annular region 204 is in contact with the entire inner edge of the bump non-formation region 22.

[0047] The area density, number density, and pitch of the second electrode pads 230 and the second conductive bumps 235 within the first annular region 201 are substantially uniform. The area density and pitch of the second electrode pads 230 and the second conductive bumps 235 within the first annular region 201 are of the same degree as the area density and pitch of the first electrode pads 130 and the first conductive bumps 135 within the effective region 100.

[0048] The area density, number density, and pitch of the second electrode pads 230 and the second conductive bumps 235 within the second annular region 202 are substantially uniform. The pitch of the second electrode pads 230 and the second conductive bumps 235 within the second annular region 202 is about 150% of the pitch of the first electrode pads 130 and the first conductive bumps 135 within the effective region 100. The area density and number density of the second electrode pads 230 and the second conductive bumps 235 within the second annular region 202 are and number density about 44% of the area density

[0049] The area density, number density, and pitch of the second electrode pads 230 and the second conductive bumps 235 in the third annular region 203 are substantially uniform. The pitch of the second electrode pads 230 and the second conductive bumps 235 in the third annular region 203 is about 200% of the pitch of the first electrode pads 130 and the first conductive bumps 135 in the active region 100. The area density and number density of the second electrode pads 230 and the second conductive bumps 235 in the third annular region 203 are the area density of the first electrode pads 130 and the first conductive bumps 135 in the active region 100 and number density at about 25%.

[0050] The area density, number density, and pitch of the second electrode pads 230 and the second conductive bumps 235 in the fourth annular region 204 are substantially uniform. The pitch of the second electrode pads 230 and the second conductive bumps 235 in the fourth annular region 204 is about 250% of the pitch of the first electrode pads 130 and the first conductive bumps 135 in the active region 100. The area density and number density of the second electrode pads 230 and the second conductive bumps 235 in the fourth annular region 204 are the area density of the first electrode pads 130 and the first conductive bumps 135 in the active region 100 and number density at about 16%.

[0051] Thus, in the third embodiment, in a plan view, the area density and number density of the second electrode pads 230 and the second conductive bumps 235 in the inactive region 200 gradually decrease as they move away from the active region 100. That is, in a plan view, the area density and number density of the second electrode pads 230 and the second conductive bumps 235 in the inactive region 200 gradually decrease in the radial direction of the substrate 10.

[0052] Other configurations are the same as those in the first embodiment.

[0053] The third embodiment can also achieve the same effects as the first embodiment. In addition, since the area density and the number density of the second conductive bumps 235 gradually decrease as the distance from the effective region 100 increases, the current density in the ineffective region 200 changes gently during the formation of the first copper layer 132 and the second copper layer 232, and also during the formation of the first solder layer 133 and the second solder layer 233. Therefore, it is easier to further adjust the height of the second conductive bumps 235 to be approximately the same as the height of the first conductive bumps 135. As a result, it is easier to further suppress the residue of the resist layer 300 used for forming the first conductive bumps 135 and the second conductive bumps 235.

[0054] Note that the area density of the second conductive bumps 235 within the ineffective region 200 is, for example, 5% to 80% of the area density of the first conductive bumps 135 within the effective region 100, preferably 10% to 70%, and more preferably 20% to 60%. When the area density of the second conductive bumps 235 within the ineffective region 200 is excessively low, if the ineffective region 200 is not ensured to be wide enough, the current density may become high during electrolytic plating near the outer edge of the effective region 100. Ensuring a wide ineffective region 200 will result in a decrease in yield. When the area density of the second conductive bumps 235 within the ineffective region 200 is excessively high, the effect of suppressing the residue of the resist layer 300 in the ineffective region 200 may decrease.

[0055] Although the preferred embodiments etc. have been described in detail above, the present invention is not limited to the above-described embodiments etc., and various modifications and substitutions can be made to the above-described embodiments etc. without departing from the scope described in the claims.

Explanation of Reference Numerals

[0056] 1, 2, 3 wafers 10 substrate 11 circuit formation surface 21 bump formation region 22 bump non-formation region 100 effective region 110 effective chip region 130 first electrode pad 131 first seed layer 132 First copper layer 133 First solder layer 135 First conductive bump 200 Invalid area 210 Invalid chip area 230 Second electrode pad 231 Second seed layer 232 Second copper layer 233 Second solder layer 235 Second conductive bump 300 Resist layer 311 First opening 312 Second opening

Claims

1. A substrate having a first surface, comprising: a first region in which a plurality of active chip regions are arranged; and a second region provided around the first region; A plurality of first conductive bumps provided on the first surface of the substrate within the first region; A plurality of second conductive bumps provided on the first surface of the substrate within the second region; having In a plan view from a direction perpendicular to the first surface, the area density of the second conductive bumps in the second region is lower than the area density of the first conductive bumps in the first region, A wafer, wherein the area density of the second conductive bumps in the second region continuously decreases as the distance from the first region increases.

2. A substrate having a first surface, comprising: a first region in which a plurality of active chip regions are arranged; and a second region provided around the first region; A plurality of first conductive bumps provided on the first surface of the substrate within the first region; A plurality of second conductive bumps provided on the first surface of the substrate within the second region; having In a plan view from a direction perpendicular to the first surface, the area density of the second conductive bumps in the second region is lower than the area density of the first conductive bumps in the first region, A wafer, wherein the area density of the second conductive bumps in the second region decreases stepwise as the distance from the first region increases.

3. The wafer according to claim 1 or 2, wherein the area density of the second conductive bumps in the second region is 5% to 80% of the area density of the first conductive bumps in the first region.

4. The wafer according to any one of claims 1 to 3, wherein in a plan view from a direction perpendicular to the first surface, the equivalent circle diameter is equal between each of the plurality of first conductive bumps and each of the plurality of second conductive bumps.

5. The wafer according to any one of claims 1 to 4, wherein in a plan view from a direction perpendicular to the first surface, the number density of the second conductive bumps in the second region is lower than the number density of the first conductive bumps in the first region.

6. The first conductive bump includes a first copper pillar, The wafer according to any one of claims 1 to 5, wherein the second conductive bump includes a second copper pillar.

7. A step of preparing a substrate having a first surface, comprising: a first region in which a plurality of active chips are arranged; and a second region provided around the first region; forming a plurality of first conductive bumps on the first surface of the substrate within the first region, and forming a plurality of second conductive bumps on the first surface of the substrate within the second region; having; in a plan view from a direction perpendicular to the first surface, making the area density of the second conductive bumps in the second region lower than the area density of the first conductive bumps in the first region; a method for manufacturing a wafer, characterized in that the area density of the second conductive bumps in the second region is continuously decreased as the distance from the first region increases.

8. A step of preparing a substrate having a first surface including a first region in which a plurality of effective chips are arranged and a second region provided around the first region; forming a plurality of first conductive bumps on the first surface of the substrate within the first region, and forming a plurality of second conductive bumps on the first surface of the substrate within the second region; having; in a plan view from a direction perpendicular to the first surface, making the area density of the second conductive bumps in the second region lower than the area density of the first conductive bumps in the first region; a method for manufacturing a wafer, characterized in that the area density of the second conductive bumps in the second region is stepwise decreased as the distance from the first region increases.

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