Silicon carbide semiconductor device

Abstract

To suppress expansion of basal plane dislocation contained in a silicon carbide single crystal substrate to a stacking fault.SOLUTION: A silicon carbide semiconductor device includes a silicon carbide single crystal substrate 10 having one surface 10a and the other surface 10b opposite to the one surface 10a, and an epitaxial layer 12 composed of silicon carbide placed on the one surface 10a. With the silicon carbide single crystal substrate 10, an impurity element 11a is placed on one surface side, and the impurity element is placed more around basal plane dislocation 10c existing on the one surface side than in a portion different from the surroundings.SELECTED DRAWING: Figure 4

Description

Technical Field

[0001] The present invention relates to a SiC semiconductor device in which an epitaxial layer is formed on a silicon carbide (hereinafter simply referred to as SiC) single crystal substrate.

Background Art

[0002] Conventionally, SiC single crystal substrates have attracted attention as materials for constructing various semiconductor devices including vehicle power devices because of their excellent semiconductor characteristics. However, the current SiC single crystal substrates contain wavy dislocations having dislocation lines on the (0001) plane called basal plane dislocations.

[0003] When a switching element such as a MOSFET (abbreviation for Metal Oxide Semiconductor Field Effect Transistor) is formed by growing an epitaxial layer on such a SiC single crystal substrate to form a SiC semiconductor device, a parasitic diode is formed. In this case, it is known that when the parasitic diode operates in a bipolar manner, holes passing near the basal plane dislocation may cause the basal plane dislocation to expand into stacking defects. And stacking defects are defects that are more likely to degrade the electrical characteristics of the SiC semiconductor device than basal plane dislocations. For this reason, a SiC semiconductor device capable of suppressing the expansion of basal plane dislocations into stacking defects is desired.

[0004] For example, Patent Document 1 proposes a SiC semiconductor device in which, after forming an epitaxial layer on a SiC single crystal, a lifetime killer is formed in the epitaxial layer to reduce holes passing near the basal plane dislocation.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0006] However, since the basal plane dislocation is contained in the SiC single crystal substrate, in the configuration of the SiC semiconductor device, there is a possibility that the basal plane dislocation cannot be sufficiently suppressed from expanding into stacking defects.

[0007] In view of the above points, an object of the present invention is to provide an SiC semiconductor device capable of suppressing the expansion of basal plane dislocations contained in an SiC single crystal substrate into stacking defects.

Means for Solving the Problems

[0008] In claim 1 for achieving the above object, an SiC semiconductor device having an SiC single crystal substrate (10), the SiC single crystal substrate having one surface (10a) and the other surface (10b) opposite to the one surface, and an epitaxial layer (12) made of SiC disposed on the one surface, wherein an impurity element (11a) is disposed on one surface side of the SiC single crystal substrate, and the impurity element is disposed more on the periphery of the basal plane dislocation (10c) existing on one surface side than on a portion different from the periphery.

[0009] According to this, when the impurity element terminates the carbon vacancy defect constituting the basal plane dislocation, the crystallinity of the SiC single crystal substrate is improved. Therefore, the energy required for the basal plane dislocation to expand into stacking defects can be increased, and the expansion of the basal plane dislocation into stacking defects can be suppressed. Further, when the impurity element functions as a lifetime killer, holes passing near the basal plane dislocation can be reduced. Therefore, the supply of the energy required for the basal plane dislocation to expand into stacking defects can be suppressed, and the expansion of the basal plane dislocation into stacking defects can be suppressed.

[0010] The reference numerals in parentheses attached to each component etc. indicate an example of the correspondence relationship between the component etc. and the specific components etc. described in the embodiments described later.

Brief Description of the Drawings

[0011]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Embodiments for Carrying Out the Invention

[0012] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, parts that are the same or equivalent to each other are denoted by the same reference numerals for explanation.

[0013] (First Embodiment) The SiC semiconductor device of the first embodiment will be described with reference to the drawings. In this embodiment, a semiconductor device in which a MOSFET is formed using the SiC single crystal substrate 10 will be described. That is, a semiconductor device in which a switching element in which a parasitic diode is configured using the SiC single crystal substrate 10 is formed will be described. Note that in FIG. 1, only one cell constituting the MOSFET is shown, but actually, the MOSFETs shown in FIG. 1 are arranged adjacent to each other in a plurality of cells to form a SiC semiconductor device.

[0014] As shown in FIG. 1, the semiconductor device has a SiC single crystal substrate 10 having one surface 10a and the other surface 10b opposite to the one surface 10a. In this embodiment, the SiC single crystal substrate 10 has a high concentration of n-type impurities (for example, phosphorus or nitrogen, etc.), for example, 1×10 19 ~1×10 20 cm -3It is composed of a 4H-type SiC single crystal with a thickness of about 300 μm doped with an impurity concentration. In the SiC single crystal substrate 10, as shown in FIG. 2, basal plane dislocations 10c are introduced.

[0015] On one surface 10a of the SiC single crystal substrate 10, an n-type impurity, for example, 1×10 15 ~1×10 16 cm -3 An n-type drift layer 12 made of SiC with an impurity concentration and a thickness of about 5 to 15 μm is formed. That is, on one surface 10a of the SiC single crystal substrate 10, a drift layer 12 with a lower impurity concentration than that of the SiC single crystal substrate 10 is arranged. The drift layer 12 is formed by growing an epitaxial layer on the SiC single crystal substrate 10. In this embodiment, the drift layer 12 corresponds to the epitaxial layer.

[0016] A p-type base layer 13 is formed on the drift layer 12. This base layer 13 is a layer that constitutes the channel of the MOSFET and is formed so as to be in contact with the side surfaces of the trenches 15 that constitute the trench gate structure described later on both sides of the trenches 15.

[0017] On the surface layer portion of the base layer 13, an n + -type source region 14 doped with a high concentration of n-type impurities is formed so as to be in contact with the trench gate structure. In this embodiment, the source region 14 has, for example, an impurity concentration of 1×10 21 cm -3 and a thickness of about 0.3 μm.

[0018] Then, a trench 15 is formed so as to penetrate the base layer 13 and the source region 14 and reach the drift layer 12. As a result, the base layer 13 and the source region 14 are arranged so as to be in contact with the side surfaces of the trench 15.

[0019] The inner wall surface of the trench 15 is covered with a gate insulating film 16 formed of an oxide film or the like, and a gate electrode 17 formed of doped Poly-Si is formed on the surface of the gate insulating film 16 so as to fill the inside of the trench 15. In this way, by forming the gate insulating film 16 and the gate electrode 17 in the trench 15, a trench gate structure is configured.

[0020] Note that the trench gate structure is formed, for example, in a strip shape with the longitudinal direction perpendicular to the paper surface, and a structure including a plurality of cells is formed by arranging a plurality of trench gate structures in a stripe pattern at equal intervals in the left-right direction of the paper surface.

[0021] A source electrode 18 is formed on the surfaces of the source region 14 and the base layer 13. The source electrode 18 is composed of a plurality of metals (for example, Ni / Al, etc.). Specifically, the portion connected to the source region 14 is composed of a metal capable of forming an ohmic contact with n-type SiC, and the portion connected to the base layer 13 is composed of a metal capable of forming an ohmic contact with p-type SiC. Note that the source electrode 18 is electrically separated from a gate wiring (not shown) that is electrically connected to the gate electrode 17 by an interlayer insulating film 19. Then, the source electrode 18 is electrically contacted with the source region 14 and the base layer 13 through a contact hole 19a formed in the interlayer insulating film 19.

[0022] A drain electrode 20 electrically connected to the SiC single crystal substrate 10 is formed on the other surface 10b side of the SiC single crystal substrate 10. That is, in this embodiment, the drain layer is configured by the SiC single crystal substrate 10. Such a structure configures a MOSFET.

[0023] In this embodiment, an impurity element 11a different from the elements constituting SiC is disposed on one surface 10a side of the SiC single crystal substrate 10. Specifically, at least one type of impurity element 11a among boron, hydrogen, helium, titanium, vanadium, and aluminum is disposed on the SiC single crystal substrate 10 by ion implantation. In other words, an ion implantation portion 11b into which the impurity element 11a is implanted is formed on one surface 10a side of the SiC single crystal substrate 10. And the SiC single crystal substrate 10 is in a state where more impurity element 11a is disposed on one surface 10a side than on the other surface 10b side. For example, in this embodiment, about 1×10 16 to 1×10 18 cm -3 of boron is ion implanted as the impurity element 11a.

[0024] The above is the configuration of the SiC semiconductor device in this embodiment. In such a SiC semiconductor device, a parasitic diode is formed by connecting a drift layer 12 which is an n-type semiconductor layer and a base layer 13 which is a p-type semiconductor layer between the source electrode 18 and the drain electrode 20. And in the SiC semiconductor device, when the parasitic diode operates, since this parasitic diode is a bipolar operation, not only electrons but also holes are generated, and the hole current density increases. And when the holes recombine with the electrons, the basal plane dislocation 10c may expand into stacking defects.

[0025] However, in this embodiment, more impurity element 11a is disposed on one surface 10a side of the SiC single crystal substrate 10 than on the other surface 10b side.

[0026] Therefore, on one surface 10a side of the SiC single crystal substrate 10, when the impurity element 11a terminates the carbon vacancy defect constituting the basal plane dislocation 10c existing on one surface 10a side, the crystallinity of the SiC single crystal substrate 10 is improved. Accordingly, the energy required for the basal plane dislocation 10c to expand into stacking defects can be increased, and the expansion of the basal plane dislocation 10c into stacking defects can be suppressed.

[0027] Also, on one surface 10a side of the SiC single crystal substrate 10, when the impurity element 11a functions as a lifetime killer, holes passing near the basal plane dislocation 10c on the one surface 10a side can be reduced in order to capture holes during bipolar operation. Therefore, it is possible to suppress the supply of energy necessary for the basal plane dislocation 10c to expand into a stacking defect, and it is possible to suppress the basal plane dislocation 10c from expanding into a stacking defect.

[0028] Next, a method for manufacturing the SiC semiconductor device will be described. First, a SiC single crystal substrate 10 having one surface 10a and the other surface 10b is prepared. Such a SiC single crystal substrate 10 is prepared by slicing a SiC ingot and then polishing it as necessary.

[0029] Then, before growing an epitaxial layer on one surface 10a of the SiC single crystal substrate 10, the impurity element 11a is ion-implanted from one surface 10a side of the SiC single crystal substrate 10. Thereby, a SiC single crystal substrate 10 in which more impurity element 11a is arranged on the one surface 10a side than on the other surface 10b side is configured.

[0030] Next, an epitaxial layer constituting the drift layer 12 is grown on one surface 10a of the SiC single crystal substrate 10. Thereafter, a predetermined semiconductor manufacturing process is performed to form a trench gate structure, a source region, etc., whereby the semiconductor device shown in FIG. 1 is manufactured.

[0031] As described above, in the SiC semiconductor device of the present embodiment, in the SiC single crystal substrate 10, more impurity element 11a is arranged on the one surface 10a side than on the other surface 10b side.

[0032] Therefore, on one surface 10a side of the SiC single crystal substrate 10, when the impurity element 11a terminates the carbon vacancy defect that constitutes the basal plane dislocation 10c existing on the one surface 10a side, the crystallinity of the SiC single crystal substrate 10 is improved. Accordingly, the energy required for the basal plane dislocation 10c to expand into a stacking defect can be increased, and the expansion of the basal plane dislocation 10c into a stacking defect can be suppressed.

[0033] Also, on one surface 10a side of the SiC single crystal substrate 10, when the impurity element 11a functions as a lifetime killer, holes passing near the basal plane dislocation 10c on the one surface 10a side can be reduced in order to capture holes during bipolar operation. Accordingly, the supply of the energy required for the basal plane dislocation 10c to expand into a stacking defect can be suppressed, and the expansion of the basal plane dislocation 10c into a stacking defect can be suppressed. Therefore, when a switching element such as a MOSFET is formed, a decrease in electrical characteristics can be suppressed.

[0034] And in the present embodiment, after preparing the SiC single crystal substrate 10, the impurity element 11a is arranged on the one surface 10a side by ion-implanting the impurity element 11a from the one surface 10a side. For this reason, for example, compared with the case where the impurity element 11a is ion-implanted from the epitaxial layer side so as to reach the SiC single crystal substrate 10 after growing an epitaxial layer on the SiC single crystal substrate 10, a large-scale apparatus is not required, and an increase in the manufacturing process can be suppressed.

[0035] Furthermore, since the impurity element 11a is arranged in the SiC single crystal substrate 10 by ion implantation, the setting of the concentration of the impurity element 11a and the like can be easily changed.

[0036] (Second Embodiment) The second embodiment will be described. In this embodiment, the impurity element 11a is also arranged in the drift layer 12 as compared with the first embodiment. Since other aspects are the same as those of the first embodiment, the description is omitted here.

[0037] In the SiC semiconductor device of this embodiment, as shown in FIG. 3, impurity elements 11a are also arranged in the portion of the drift layer 12 on the SiC single crystal substrate 10 side. Therefore, it is expected that the impurity elements 11a are arranged so as to surround the basal plane dislocations 10c existing on the one surface 10a side of the SiC single crystal substrate 10.

[0038] For such a SiC semiconductor device, as the impurity element 11a to be arranged on the SiC single crystal substrate 10, it is sufficient to contain a large amount of Ti, V, etc. having a large diffusion coefficient in SiC. Thereby, during a high temperature state such as growing the drift layer 12 on the SiC single crystal substrate 10, the impurity element 11a diffuses also to the drift layer 12 side and is manufactured.

[0039] As described above, in this embodiment, impurity elements 11a are also arranged in the portion of the drift layer 12 on the SiC single crystal substrate 10 side, and it is expected that the impurity elements 11a are arranged so as to surround the basal plane dislocations 10c. Therefore, the expansion of the basal plane dislocations 10c into stacking defects can be further suppressed.

[0040] (Third Embodiment) The third embodiment will be described. This embodiment is different from the first embodiment in that the impurity elements 11a are arranged only around the basal plane dislocations 10c existing in the SiC single crystal substrate 10. Since the other aspects are the same as those of the first embodiment, the description is omitted here.

[0041] In the SiC semiconductor device of this embodiment, as shown in FIG. 4, in the SiC single crystal substrate 10, the impurity elements 11a are not arranged entirely on the one surface 10a side, but are arranged only around the basal plane dislocations 10c.

[0042] Such a SiC single crystal substrate 10 is prepared as follows. That is, first, the position of the basal plane dislocation 10c existing in the SiC single crystal substrate 10 is specified by a photoluminescence imaging method or the like. Then, a mask having a predetermined region including the specified basal plane dislocation 10c is disposed on one surface 10a of the SiC single crystal substrate 10. Subsequently, the impurity element 11a is ion-implanted from the one surface 10a side of the SiC single crystal substrate 10. Thereby, a SiC single crystal substrate 10 in which the impurity element 11a is disposed only around the basal plane dislocation 10c is prepared.

[0043] As described above, even if the impurity element 11a is disposed only around the basal plane dislocation 10c, the same effects as those of the first embodiment can be obtained. Further, since the impurity element 11a is disposed only around the basal plane dislocation 10c, it is possible to suppress an increase in the on-resistance when the MOSFET is operated due to the impurity element 11a.

[0044] (Fourth Embodiment) The fourth embodiment will be described. In this embodiment, impurities are disposed throughout the SiC single crystal substrate 10 as compared with the first embodiment. Since other aspects are the same as those of the first embodiment, the description thereof is omitted here.

[0045] In the SiC semiconductor device of this embodiment, as shown in FIG. 5, impurity elements 11a are disposed throughout the SiC single crystal substrate 10. That is, the impurity elements 11a are evenly disposed between the one surface 10a and the other surface 10b of the SiC single crystal substrate 10. That is, in the SiC single crystal substrate 10, the amount of the impurity elements 11a on the one surface 10a side is substantially equal to the amount of the impurity elements 11a on the other surface 10b side.

[0046] Such a SiC single crystal substrate 10 is prepared as follows. For example, when preparing a SiC ingot that constitutes the SiC single crystal substrate 10 by the sublimation recrystallization method, the atmosphere in the sublimation furnace is set to an atmosphere containing impurity elements 11a such as boron. Then, in this state, the sublimation recrystallization method is performed to grow SiC crystals, thereby manufacturing a SiC ingot that entirely contains the impurity element 11a. Thereafter, by cutting this SiC ingot, a SiC single crystal substrate 10 in which the impurity element 11a is disposed throughout is prepared.

[0047] As described above, even if the impurity element 11a is disposed throughout the SiC single crystal substrate 10, the same effects as those of the first embodiment can be obtained. Further, in this embodiment, since the impurity element 11a is mixed when preparing the SiC ingot, it is not necessary to perform a special process after preparing the SiC ingot. For this reason, a SiC single crystal substrate 10 containing the impurity element 11a can be easily prepared, and an increase in the manufacturing process can be suppressed.

[0048] (Other Embodiments) The present invention is not limited to the above-described embodiments, and can be appropriately modified within the scope described in the claims.

[0049] For example, in each of the above embodiments, the SiC single crystal substrate 10 has been described as an example of the 4H type, but it may be of the 3C type, 6H type, 15R type, or the like.

[0050] Further, in each of the above embodiments, the SiC semiconductor device may be formed as a planar gate type MOSFET, a super junction MOSFET, or the like, instead of a trench gate type MOSFET. Further, the SiC semiconductor device may be formed as a Schottky barrier diode, an IGBT (abbreviation for Insulated Gate Bipolar Transistor), or the like, instead of a MOSFET. Note that when an IGBT is formed in the SiC semiconductor device, the SiC single crystal substrate 10 is of the p type.

[0051] Furthermore, in the first to third embodiments described above, instead of ion implantation, the impurity element 11a may be disposed on the SiC single crystal substrate 10 by thermal diffusion. That is, after applying a solution containing the impurity element 11a on one surface 10a, the impurity element 11a may be disposed on the SiC single crystal substrate 10 by performing heat treatment in a heating furnace.

[0052] Also, in the fourth embodiment described above, the method for manufacturing the SiC ingot that entirely contains the impurity element 11a may be a solution growth method, a gas source growth method, or the like, instead of the sublimation recrystallization method. When manufacturing the SiC ingot that entirely contains the impurity element 11a by the solution growth method, the impurity element 11a may be mixed into the raw material solution. When manufacturing the SiC ingot that entirely contains the impurity element 11a by the gas source growth method, the impurity element 11a may be mixed into the raw material gas.

[0053] Furthermore, the above embodiments may be combined. For example, the second embodiment and the fourth embodiment may be combined so that the impurity element 11a is disposed on the entire SiC single crystal substrate 10 and on the portion of the drift layer 12 on the SiC single crystal substrate 10 side.

Explanation of Reference Numerals

[0054] 10 SiC single crystal substrate 10a One surface 10b The other surface 10c Base plane dislocation 11a Impurity element 12 Drift layer (epitaxial layer)

Claims

1. A silicon carbide semiconductor device having a silicon carbide single crystal substrate (10), the silicon carbide single crystal substrate having one surface (10a) and the other surface (10b) opposite to the one surface, and an epitaxial layer (12) made of silicon carbide disposed on the one surface, wherein the silicon carbide single crystal substrate has an impurity element (11a) disposed on the one surface side, and the impurity element is disposed in a larger amount around a basal plane dislocation (10c) existing on the one surface side than in a portion different from the periphery. A silicon carbide semiconductor device.

2. In the epitaxial layer, the impurity element is disposed on the silicon carbide single crystal substrate side, and the impurity element is disposed in a larger amount around the basal plane dislocation existing on the one surface side than in a portion different from the periphery. The silicon carbide semiconductor device according to Claim 1.

3. The silicon carbide semiconductor device according to Claim 1 or 2, wherein the concentration of the portion of the impurity element located around the basal plane dislocation on the one surface side is made higher than the concentration of the portion different from the periphery.

4. The impurity element around the base plane dislocation has a concentration of 1×10 １６ to 1×10 １８ cm －３ The silicon carbide semiconductor device according to any one of claims 1 to 3, which is so configured.

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