Time difference digital conversion circuit and control method for time difference digital conversion circuit

Abstract

To provide a time difference digital conversion circuit that can measure a width time of a pulse to be measured while suppressing fluctuation due to PVT variation.SOLUTION: One TDC 24 digitally converts the time difference between a pair of edges of a pulse PW to be measured using a delay time generated by an RDL. The TDC 24 measures a first edge time difference between a pair of edges of the pulse PW to be measured and a second edge time difference in a period of a reference clock SCLK in a time-division manner. A divider 28 calculates a result of dividing the first edge time difference by the second edge time difference, at least to the decimal point.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a time-difference digital conversion circuit and a method for controlling the time-difference digital conversion circuit.

Background Art

[0002] For example, when quickly detecting a surge analog current waveform generated when a motor control circuit drives a motor through a switching element drive circuit, the surge analog current can be converted into pulses by comparing it with a desired threshold value using a comparator. In order for control logic to sample the pulses at the time of surge detection with high resolution using a reference clock, it is necessary to operate the reference clock for sampling at high speed. However, when adopting a high breakdown voltage process, it becomes difficult to implement a reference clock that operates at high speed.

[0003] The sampling period of the pulses that can be acquired by the control logic depends on the period of the reference clock. For this reason, it has been proposed to create a reference clock that operates at high speed by multi-phasing the phase using a DLL while preparing a low-speed reference clock.

[0004] In addition, when implementing such a technique, it has been proposed to use a time-difference digital conversion circuit (see, for example, Patent Document 1). According to the technique described in Patent Document 1, data is delayed using a delay line and time-difference digital conversion is performed by sampling with a reference clock. In the technique described in this Patent Document 1, calibration is performed in a timely manner.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0006] As described in Patent Document 1, using timely calibration complicates the design. Moreover, it has been found to be vulnerable to PVT variations due to processes, power supply voltages, or temperatures.

[0007] An object of the present invention is to provide a time difference digital conversion circuit capable of measuring the width time between edges of a current waveform's surge width as accurately as possible as a measurement target pulse while suppressing variations due to PVT variations, and a control method for the time difference digital conversion circuit.

Means for Solving the Problems

[0008] According to Claim 1, one TDC (Time to Digital Converter) measures, in a time-division manner, a first edge time difference between a pair of edges of a measurement target pulse and a second edge time difference of a reference clock period, and a division unit calculates a division result obtained by dividing the first edge time difference by the second edge time difference.

[0009] The first edge time difference between a pair of edges of a measurement target pulse and the second edge time difference of a reference clock period tend to vary similarly due to PVT variations such as power supply voltage changes and temperature changes. According to the invention described in Claim 1, the TDC measures the surge width of the current waveform as the first edge time difference between a pair of edges of the measurement target pulse. The influence of the reference clock period variation can be compensated, and the width time between the edges of the pulse of the surge width of the current waveform to be measured can be measured as accurately as possible.

Brief Description of the Drawings

[0010]

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Mode for Carrying Out the Invention

[0011] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. The time difference digital conversion circuit 1 shown in FIG. 1 mainly operates by inputting a measurement target pulse PW and a reference clock SCLK, and is a circuit capable of digitally converting and measuring the width of the measurement target pulse PW that is shorter than the period of the reference clock SCLK. Hereinafter, the measurement target pulse PW will be abbreviated as pulse PW as necessary. The time difference digital conversion circuit 1 may be applied, for example, to the input portion of the control logic 3 of the motor control circuit 2 shown in FIG. 2. The motor control circuit 2 shown in FIG. 2 is configured as shown in the figure with a control logic 3, an analog drive circuit 4, a three-phase inverter 5, and an analog detection circuit 6, and performs feedback control on the motor 7.

[0012] When the motor control circuit 2 drives the motor 7 by the control logic 3, the analog drive circuit 4, and the three-phase inverter 5, a large current flows through the three-phase inverter 5 during motor drive as shown in FIG. 3. The analog detection circuit 6 analog-detects the surge current flowing through the three-phase inverter 5. The analog detection circuit 6 digitally converts the amplified current using the amplifier 8 and then compares the amplified signal with a predetermined threshold value Vt input through the DAC 9 using the comparator 10. That is, the comparator 10 can peak-slice the surge width of the surge current waveform (equivalent to the analog signal waveform) obtained by driving the motor 7 with the predetermined threshold value Vt and output it as digital data.

[0013] The control logic 3 can input the output of this comparator 10 to the D input of the DFF 11 at the input stage, for example. However, when the time width of the output digital data of the comparator 10 is shorter than or equal to the period of the reference clock SCLK, the control logic 3 cannot accurately detect the width of the high-speed pulse at the time of surge detection.

[0014] Therefore, it is desirable to configure the time-digital conversion circuit 1 described below at the input stage of the control logic 3 to detect the peak-slice width as the pulse PW. Here, the relationship between the length of the measurement target pulse PW and the period of the reference clock SCLK is not limited. However, in this embodiment, an embodiment in which the pulse PW is set to be approximately equal to the period of the reference clock SCLK will be described. When the width time of the pulse PW is set to a time sufficiently shorter than the period of the reference clock SCLK, the effect becomes more prominent.

[0015] The time-digital conversion circuit 1 shown in FIG. 1 includes a TDC control circuit 21, OR gates 22, 23, a TDC 24 (Time to Digital Converter), latches 25, 26, 27 as a holding unit, a divider 28, and a measurement frequency change circuit 29. The TDC control circuit 21 is input with the measurement target pulse PW, the reference clock SCLK used for measuring the width of the pulse PW, and a clear signal CLR for instructing to clear the state from the outside.

[0016] The frequency of the reference clock SCLK is set to a low frequency of about 10 MHz, for example. This can suppress the influence of power consumption, parasitic capacitance, etc., and improve the ease of manufacturing.

[0017] TDC24, which is an example of the time difference measurement unit, includes an RDL31 (Ring Delay Line) as a delay circuit, a counter 32, a latch and encoder 33, latches 34, 35, and a subtractor 36, as shown in FIG. 5. As shown in FIG. 6, RDL31 is configured by connecting a NAND gate 37, which is an inverting delay element for startup, and NOT gates 38, which are, for example, 30 inverting delay elements, in a ring shape. A signal PA is input to one side of the NAND gate 37. Hereinafter, the NAND gate 37 and the NOT gate 38 will be described as inverting delay elements as necessary.

[0018] Here, the common connection nodes of the inverting delay elements 37 and 38 connected in a ring shape are defined as nodes N1... N16, respectively, as shown in FIG. 6. One NAND gate 37 is connected between adjacent nodes N16 - N1, and two NOT gates 38 are connected between the other adjacent nodes N1 - N2, N2 - N3,..., N15 - N16. Since the NAND gate 37 has a slightly longer delay time than the NOT gate 38, which is another inverting delay element, only one NAND gate 37 is configured between adjacent nodes N16 - N1.

[0019] In FIG. 5, a combination of two NOT gates 38 is shown as one forward delay element DU, respectively. Also, as shown in FIG. 6, RDL31 includes a gate 39 that acquires delay signals from the nodes N1... N16 by the forward delay element DU, respectively, performs waveform shaping, and outputs them as digital levels R1... R16.

[0020] When the signal PA = "1" is continuously input to the NAND gate 37, as shown in the state change in FIG. 7, the signal "1" is transmitted in sequence through the forward delay element DU. Then, when the signal "1" circulates through the forward delay elements DU connected in a ring shape, after one round, the signal "1" also reaches the input of the NAND gate 37. Then, the NAND gate 37 outputs "0", and thereafter, the forward delay element DU transmits the signal "0" in sequence.

[0021] Furthermore, when the signal "0" circulates through the forward delay elements DU connected in a ring shape, after one round, the signal "0" also reaches the input of the NAND gate 37. Thereby, it returns to the initial state. This operation is repeated as long as the signal PA = "1", and RDL31 changes 32 states by outputting digital levels R1...R16 through the gate 39 for waveform shaping. When 32 states change, one round is completed.

[0022] The latch and encoder 33 is configured by combining 16 DFFs 40 and an encoder 41, as partially shown in FIG. 8. The DFF 40 inputs each digital level R1...R16 related to the output of the forward delay element DU to the D input, and is latched by the same latch signal PB.

[0023] The encoder 41 inputs and encodes the Q outputs of the 16 DFFs 40, and encodes 32 states represented by the digital levels R1...R16 into 5 bits. Thereby, the latch and encoder 33 can obtain phase information obtained by dividing the one-round time of RDL31 into 32 parts.

[0024] Note that the one-round time of the edge by RDL31 is set to be sufficiently shorter than the period of the reference clock SCLK. In this embodiment, 200 ps is assumed as the time resolution of the TDC24.

[0025] The counter 32 shown in Fig. 1 counts the number of revolutions in RDL31 and is composed of, for example, a 17-bit counter. Although details are as described in Japanese Patent Laid-Open No. 6-283984, the outline is as follows. The latch 34 latches the count value of the counter 32. The latch 35 latches 22-bit data DTp obtained by combining the 17-bit data of the latch 34 and the 5-bit data of the latch-and-encoder 33. The latch signals of the latch-and-encoder 33, the latches 34 and 35 are all composed of the latch signal PB. The subtractor 36 subtracts the latched data of the latch 35 from the data DTp and outputs 22-bit data DT. This subtractor 36 is provided for comparing the previous measurement value and the current measurement value in order to remove digital noise, and may be provided as necessary.

[0026] Note that as long as RDL31 does not input any edge as a signal, the NAND gate 37 and the NOT gate 38 do not change their respective outputs. Therefore, each inverter 37, 38 also holds a stable logic output state without consuming power. At this time, RDL31 can hold a low power consumption state with lower power consumption than the normal operating state, and other circuits of the TDC24, that is, the counter 32, the latch-and-encoder 33, the latches 34, 35 can also hold the low power consumption state.

[0027] When the TDC24 inputs any signal edge, for example, the pulse PAW corresponding to the measurement target pulse PW described later, or the pulse PAB corresponding to the period of the reference clock SCLK, it returns from the low power consumption state to the normal operating state and operates. Then, when the input is interrupted, the TDC24 can suppress power consumption because the output digital level of its internal circuit is stabilized, and returns from the normal operating state to the low power consumption state.

[0028] The TDC control circuit 21 includes a width time acquisition circuit 50 of the pulse PW illustrated in FIGS. 9 and 10, and a period acquisition circuit 70 of the reference clock SCLK illustrated in FIGS. 11 and 12. The width time acquisition circuit 50 of the pulse PW includes a main circuit 51 that mainly acquires the width time of the pulse PW, and a slave circuit 52 that operates dependently in response to the output of the main circuit 51.

[0029] As shown in FIG. 9, the main circuit 51 includes DFFs 53a to 53d connected in four-stage cascade, AND gates 54 and 55, a first delay circuit 56, and an OR gate 57. The D input of the first-stage DFF 53a is pulled up, and the pulse PW is positively input to the clock terminal. The pulse PW is negatively input to the clock terminal of the second-stage DFF 53b. The D input of the second-stage DFF 53b is positively input to each of the AND gates 54 and 55, and the Q output of the DFF 53b is negatively input to each of the AND gates 54 and 55. As a result, the AND gate 54 outputs a pulse PAW1 having a width from the rising input timing of the pulse PW to the falling input timing.

[0030] A first delay circuit 56 is interposed between the second-stage DFF 53b and the negative input of the AND gate 55. The AND gate 55 corresponds to a first pulse output unit that outputs a pulse PAW corresponding to a pair of edges of the measurement target pulse PW to the TDC 24 as a signal PA. The AND gate 55 outputs a pulse PAW having a width from the rising input timing of the pulse PW to the falling input timing + the first delay time Delay1 of the first delay circuit 56 to the TDC control circuit 21. The first delay circuit 56 corresponds to a first delay unit that extends the width of the pulse PAW output by the AND gate 55 by the first delay time Delay1. The first delay circuit 56 is a timing adjustment circuit provided to set the output stop timing of the pulse PAW after the output of the TDC 24 is latched by the latch signal PB1W.

[0031] The reference clock SCLK is negatively input to the clock terminal of the third-stage DFF53c, and the reference clock SCLK is positively input to the clock terminal of the fourth-stage DFF53d. The Q output of the fourth-stage DFF53d is input to the clear terminal of the first-stage DFF53a through the OR gate 57. The clear signal CLR is input to the OR gate 57, and the clear signal CLR is also input to the clear terminals of the second-stage to fourth-stage DFF53b...53d. Thereby, after the main circuit 51 detects the pulse PAW1 corresponding to the width of the pulse PW, the Q output of the first-stage DFF53a can be cleared.

[0032] As shown in FIG. 10, the slave circuit 52 includes DFFs 58a...58h connected in multiple stages in series, AND gates 59, 60, and OR gates 61 and 62. The D input of the first-stage DFF58a is pulled up, and the pulse PAW1 is negatively input to the clock terminal. The first-stage DFF58a corresponds to a first latch output unit that outputs a latch signal PB1W corresponding to the edge that occurs later among a pair of edges of the measurement target pulse PW, and the Q output of the first-stage DFF58a is output as the latch signal PB1W.

[0033] The reference clock SCLK is input to the clock terminals of the second-stage to seventh-stage DFFs 58b...58g. The second, fourth, and sixth-stage DFFs 58b, 58d, and 58f receive the rising edge of the reference clock SCLK as a trigger and output the D input to the Q output. The third, fifth, and seventh-stage DFFs 58c, 58e, and 58g receive the falling edge of the reference clock SCLK as a trigger and output the D input to the Q output. Therefore, when the reference clock SCLK is input to the clock terminals of each of the DFFs 58b...58g, every time the rising edge is input to the second, fourth, and sixth-stage DFFs 58b, 58d, and 58f, and the falling edge is input to the third, fifth, and seventh-stage DFFs 58c, 58e, and 58g, the pulse PAW1 input to the clock of the first-stage DFF58a can be sequentially shifted.

[0034] The D input of the fifth-stage DFF58e is positively input to the AND gate 59, and the Q output of the DFF58e is negatively input to the AND gate 59. As a result, the AND gate 59 can obtain the pulse PB2W by delaying the pulse PAW1 by one reference clock SCLK. Similarly, the D input of the seventh-stage DFF58g is positively input to the AND gate 60, and the Q output of the DFF58g is negatively input to the AND gate 60. As a result, the AND gate 60 can obtain the pulse PB3W by further delaying the pulse PAW1 by one reference clock SCLK.

[0035] Also, the reference clock SCLK is negatively input to the clock terminal of the eighth-stage DFF58h. The D input of the eighth-stage DFF58h is positively input to the OR gate 61, and the Q output of the seventh-stage DFF58g is positively input to the OR gate 61. Therefore, the OR gate 61 can detect that the pulse PAW1 has shifted to the eighth-stage DFF58h as the signal PBSTW.

[0036] The Q output of the third-stage DFF58c is input to the clear terminal of the first-stage DFF58a through the OR gate 62. The clear signal CLR is input to the OR gate 62, and the clear signal CLR is also input to the clear terminals of the DFF58b... 58h from the second stage to the eighth stage. As a result, the slave circuit 52 can clear the Q output of the first-stage DFF58a after detecting the pulse PAW1.

[0037] After the OR gate 61 detects the signal PBSTW, the period acquisition circuit 70 of the reference clock SCLK starts to operate. The period acquisition circuit 70 of the reference clock SCLK includes a main circuit 71 that mainly acquires the period of the reference clock SCLK, and a slave circuit 72 that operates dependently in response to the output of the main circuit 71.

[0038] As shown in FIG. 11, the main circuit 71 includes DFFs 73a to 73d connected in four stages in series, AND gates 74 and 75, a second delay circuit 76, and an OR gate 77. The D input of the first-stage DFF 73a receives the signal PBSTW output from the OR gate 61 shown in FIG. 10, and the reference clock SCLK is positively input to the clock terminal. The reference clock SCLK is positively input to the clock terminal of the second-stage DFF 73b. The D input of the second-stage DFF 73b is positively input to each of the AND gates 74 and 75, and the Q output of the DFF 73b is negatively input to each of the AND gates 74 and 75. As a result, the AND gate 74 outputs a pulse PAB1 with a width from the rising edge input timing to the falling edge input timing of the reference clock SCLK.

[0039] A second delay circuit 76 is interposed between the Q output of the second-stage DFF 73b and the negative input of the AND gate 75. The AND gate 75 corresponds to a second pulse output section that outputs a pulse PAB corresponding to the period of the reference clock SCLK to the TDC 24, and outputs a pulse PAB with a width from the rising edge input timing to the falling edge input timing + the second delay time Delay2 of the second delay circuit 76 of the reference clock SCLK.

[0040] The second delay circuit 76 corresponds to a second delay section that extends the width of the period of the reference clock SCLK output by the AND gate 75 by the second delay time Delay2. The second delay circuit 76 is a timing adjustment circuit provided to set the output stop timing of the pulse PAB after the output of the TDC 24 is latched by the latch signal PB1B.

[0041] The reference clock SCLK is negatively input to the clock terminal of the third-stage DFF73c, and the reference clock SCLK is positively input to the clock terminal of the fourth-stage DFF73d. The Q output of the fourth-stage DFF73d is input to the clear terminal of the first-stage DFF73a through the OR gate 77. As a result, after the main circuit 71 detects the pulse PAB1 corresponding to the width of the reference clock SCLK, the Q output of the first-stage DFF73a can be cleared.

[0042] As shown in FIG. 12, the slave circuit 72 includes a plurality of stages of serially connected DFFs 78a... 78g, AND gates 79, 80, and an OR gate 81. The D input of the first-stage DFF78a is pulled up, and the pulse PAB1 is negatively input to the clock terminal. The first-stage DFF78a corresponds to a second latch output section that outputs a latch signal PB1B corresponding to the edge that occurs later among the edges defining the period of the reference clock SCLK, and the Q output of the first-stage DFF78a is output as the latch signal PB1B.

[0043] The reference clock SCLK is input to the clock terminals of the second-stage to seventh-stage DFFs 78b... 78g. The second, fourth, and sixth-stage DFFs 78b, 78d, and 78f receive the rising edge of the reference clock SCLK as a trigger and output the D input to the Q output. The third, fifth, and seventh-stage DFFs 78c, 78e, and 78g receive the falling edge of the reference clock SCLK as a trigger and output the D input to the Q output. Therefore, when the reference clock SCLK is input to the clock terminals of the respective DFFs 78b... 78g, each time the rising edge is input to the second, fourth, and sixth-stage DFFs 78b, 78d, and 78f and the falling edge is input to the third, fifth, and seventh-stage DFFs 78c, 78e, and 78g, the pulse PAB1 input to the first-stage DFF78a can be shifted in order.

[0044] The D input of the DFF78e at the fifth stage is positively input to the AND gate 79, and the Q output of the DFF78e is negatively input to the AND gate 79. As a result, the AND gate 79 can obtain a pulse PB2B which delays the pulse PAB1 by one reference clock SCLK. Similarly, the D input of the DFF78g at the seventh stage is positively input to the AND gate 80, and the Q output of the DFF78g is negatively input to the AND gate 80. As a result, the AND gate 80 can output a pulse PB3W which further delays the pulse PB2B by one reference clock SCLK.

[0045] Returning to the reference drawing in FIG. 1, the overall configuration will be described. As described above, when the TDC control circuit 21 inputs the pulse PW and the reference clock SCLK, it sequentially outputs signals PAW, PAB, PB1W... PB3W, PB1B... PB3B according to the above-mentioned logic. The OR gate 22 uses the logical sum of the pulses PAW and PAB as a signal PA to be input to the TDC 24. The OR gate 23 inputs signals PB1W... PB3W, PB1B... PB3B and the clear signal CLR, and outputs them as a latch signal PB to the TDC 24.

[0046] Note that a measurement frequency change circuit 29 is configured between the output terminal of the pulse PAB and the OR gate 22, and between the output terminals of the pulses PB1B... PB3B and the OR gate 23. The measurement frequency change circuit 29 illustrated in FIG. 4 is configured by combining a TFF29a and AND gates 29b... 29e in the illustrated form, and is a circuit capable of reducing the measurement frequency indicating the ratio of the number of cycles of the reference clock SCLK to the number of measurement times of the width time of the pulse PAW to less than 1.

[0047] The TFF29a is a toggle flip-flop that repeatedly changes the output level between "0" and "1" each time the pulse PAW is input. Each of the AND gates 29b... 29e is provided as an enable / disable switching circuit that switches whether to input each of the pulses PAB, PB1B... PB3B as each of the signals PA, PB of the TDC 24 based on the output levels "0" and "1" of the TFF29a.

[0048] Each time the pulse PAW is input to the TFF29a once, the output level of the TFF29a repeatedly changes between "0" and "1". Therefore, each time the pulse PAW is generated, the AND gates 29b... 29e pass or block each of the pulses PAB, PB1B... PB3B. The pulses PAB, PB1B... PB3B are outputs of the period acquisition circuit 70 of the reference clock SCLK. For this reason, in one out of two occurrences of the generation of the pulse PAW, the AND gates 29b... 29e block the pulses PAB, PB1B... PB3B, and the period measurement of the reference clock SCLK by the TDC24 can be stopped. As a result, each time the width time of the pulse PAW is measured twice, the period of the reference clock SCLK can be measured once.

[0049] In this case, since the number of times of measuring the period of the reference clock SCLK by the TDC24 can be reduced, the operation time of the TDC24 can be shortened, and the power consumption can be reduced. Note that the measurement frequency change circuit 29 may be provided as needed. If the pulses PAB, PB1B... PB3B are directly passed through to the respective OR gates 22, 23 without providing the measurement frequency change circuit 29, each time the width time of the pulse PAW is measured by the TDC24, the period of the reference clock SCLK can be measured once.

[0050] On the other hand, the latch 25 shown in FIG. 1 latches the output of the TDC24 using the edge of the pulse PB2W as a latch signal. At this time, the latch 25 holds the measurement result by the TDC24 that has measured the width time of the pulse PAW.

[0051] The latch 26 latches the output of the TDC24 using the edge of the pulse PB2B after passing through the AND gate 29d of the measurement frequency change circuit 29 as a latch signal. The latch 26 holds the measurement result by the TDC24 that has measured the period of the reference clock SCLK. However, when the pulse PB2B does not pass through the AND gate 29d, no latch signal is input to the latch 26. In this case, the latch 26 holds the output of the TDC24 measured in advance before the previous time, that is, the data of the period of the reference clock SCLK measured in advance before the previous time.

[0052] The divider 28 as a division unit calculates the quotient Q (Q3:Q0) and the remainder R (R3:R0) obtained by dividing the dividend A (A3:A0) by the divisor B (B3:B0), and is configured by combining division circuits 82 in a matrix form as shown in FIG. 13.

[0053] As shown in FIG. 14, each division circuit 82 is configured by combining NAND gates 83…93, NOR gate 94, NOT gates 95, 96 in the illustrated form, and the truth table is as shown in FIG. 15. The configuration of the division circuit 82 is a common one, and a detailed description of the operation is omitted. The divider 28 may have any circuit form as long as it is a circuit capable of dividing the dividend A by the divisor B and calculating at least up to the decimal point.

[0054] The operation and action of the above configuration will be described with reference to the timing charts shown in FIGS. 16 and 17. A reference clock SCLK is constantly input as pulses to the TDC control circuit 21. However, when the TDC control circuit 21 is not input with the measurement target pulse PW, no clock is input to the DFF58a shown in FIG. 9. For this reason, the TDC control circuit 21 does not output each signal PAW, PAB, PB1W…PB3W, PB1B…PB3B. At this time, since signals PA and PB are not input to the TDC21, no signal is input to the RDL31 either.

[0055] Unless the TDC21 is input with a signal PA serving as a start pulse or a latch signal PB, the output states of the respective inverter delay elements 37, 38 do not change, and a low power consumption state with lower power consumption than the normal operating state can be maintained. For this reason, the time difference digital conversion circuit 1 can maintain the low power consumption state when the measurement target pulse PW is not input.

[0056] After that, when the TDC control circuit 21 receives the rising edge of the pulse PW to be measured, it returns to the normal operating state. When the pulse PW is input, the pulse width acquisition circuit 50 for the pulse PW shown in FIG. 9 outputs a pulse PAW1 having the same length as the length of the pulse PW and also outputs a pulse PAW. When the OR gate 22 passes the pulse PAW and inputs it as a signal PA serving as a start pulse to the TDC 24, the TDC 21 starts digital conversion of the time width from the generation timing of the rising edge of the pulse PAW. The TDC 21 acquires a digital value corresponding to the integer digits by means of a 17-bit counter 32 and also acquires a digital value corresponding to the 5-bit fractional digits by means of a latch and encoder 33, digitally converts these values into a total of 22 bits, and outputs them to a latch 35 and a subtracter 36.

[0057] The TDC control circuit 21 outputs the rising edge of the pulse PAW and simultaneously outputs the rising edge of the pulse PAW1 at the timing t1 in FIG. 16. After the passage of time of the pulse PAW1, when the DFF 58a of the slave circuit 52 shown in FIG. 10 receives the falling edge of the pulse PAW1 as a negative input, it outputs the rising edge of the latch signal PB1W at the timing t2.

[0058] The pulse width acquisition circuit 50 for the pulse PW shown in FIG. 9 is provided with a first delay circuit 56. The TDC control circuit 21 latches the pulse PAW extended by the first delay circuit 56 with the latch signal PB1W from the Q output of the DFF 58a and stops the output of the pulse PAW by the AND gate 55 after the elapse of the first delay time Delay1.

[0059] Therefore, the TDC 24 can surely input the latch signal PB1W as the latch signal PB at the timing t2 before the pulse PAW falls at the timing t3. The TDC 24 can surely measure the width time of the pulse PAW1 as a digital value. When the TDC 24 latches the pulse PAW with the latch signal PB1W, the data change settles after a slight passage of time.

[0060] After the slave circuit 52 outputs the latch signal PB1W, it sequentially outputs the pulses PB2W and PB3W. The pulse PB2W is input to the latch 25 shown in FIG. 1. Therefore, the latch 25 can hold, as the dividend DB, the width time of the pulse PAW1 which is the output of the TDC24 at the timing t4 when the pulse PB2W is input. At this time, the width time acquisition circuit 50 of the pulse PW can acquire the length between the edges of the measurement target pulse PW as the first edge time difference.

[0061] The slave circuit 52 outputs the pulse PB3W and also outputs the signal PBSTW. Then, the reference clock SCLK period acquisition circuit (period measurement circuit) 70 shown in FIGS. 11 and 12 starts operating. After that, when the rising edge of the reference clock SCLK is input to the TDC control circuit 21, the reference clock SCLK period acquisition circuit 70 shown in FIG. 11 outputs the edges of the pulse PAB1 having the same length as the period of the reference clock SCLK and also outputs the edge of the pulse PAB.

[0062] As described above, the measurement frequency change circuit 29 passes or blocks the pulses PAB, PB1B... PB3B every time the pulse PAW is generated by the TDC control circuit 21. When the measurement frequency change circuit 29 passes the pulses PAB, PB1B... PB3B, the OR gate 22 passes the pulse PAB and inputs it to the TDC24 as the signal PA serving as the start pulse. Then, the TDC24 starts digital conversion of the time width from the rising edge of the pulse PAB. The TDC24 performs digital conversion corresponding to the integer digits by the 17-bit counter 32 and also performs digital conversion corresponding to the 5-bit fractional digits by the latch and encoder 33, and digitally converts these values into a total of 22 bits and outputs them to the latch 35 and the subtractor 36.

[0063] The TDC control circuit 21 outputs the rising edge of the pulse PAB and simultaneously outputs the rising edge of the pulse PAB1 at the timing t5 in FIG. 16. After the passage of time of the pulse PAB1, when the DFF78a of the slave circuit 72 shown in FIG. 12 receives the falling edge of the pulse PAB1 as a negative input, the DFF78a outputs the rising edge of the signal PB1B as a latch signal at the timing t6.

[0064] A second delay circuit 76 is provided in the reference clock SCLK period acquisition circuit 70 shown in FIG. 11. The TDC control circuit 21 latches the pulse PAB extended by the second delay circuit 76 with the latch signal PB1B from the DFF78a, and stops the output of the pulse PAB by the AND gate 75 after the elapse of the second delay time Delay2.

[0065] Therefore, the TDC 24 can surely input the latch signal PB1B as the latch signal PB at the timing t6 before the pulse PAB falls at the timing t7. Thereby, the TDC 24 can surely digitally convert the width time of the pulse PAB1. When the TDC 24 latches the pulse PAB with the latch signal PB1B, the change in data subsides after a lapse of a certain time.

[0066] After the slave circuit 72 outputs the latch signal PB1B, it sequentially outputs the pulses PB2B and PB3B. The pulse PB2B is input to the latch 26 shown in FIG. 1. Therefore, the latch 26 can hold the width time of the pulse PAB1, which is the output of the TDC 24, as the divisor DA at the timing t8 when the pulse PB2B is input. At this time, the reference clock SCLK period acquisition circuit 70 can measure the period of the reference clock SCLK as the second edge time difference.

[0067] The divider 28 divides the dividend DB by the divisor DA at least to the decimal point. When the slave circuit 72 outputs the pulse PB3B, the pulse PB3B is input to the latch 27. The latch 27 holds the division result of the divider 28. Thereby, the ratio of the width time of the pulse PW to the period of the reference clock SCLK at the measurement time point can be calculated.

[0068] The width time of the pulse PW to be measured and the period of the reference clock SCLK tend to vary in the same direction due to PVT variations such as power supply voltage changes and temperature changes. Therefore, by calculating the ratio of the width time of the pulse PW to the period of the reference clock SCLK by the divider 28, the width time of the pulse PW to be measured with the influence of the period variation of the reference clock SCLK compensated can be calculated.

[0069] In particular, since RDL31 uses the gate delay method, when the TDC24 is operated for a long time, the time difference digital conversion result is likely to change due to PVT variations. According to this embodiment, immediately after the pulse PW width time acquisition circuit 50 acquires the width time of the pulse PW and the TDC24 measures it, the reference clock SCLK period acquisition circuit 70 acquires the period of the reference clock SCLK in a time-division manner and measures it by the TDC24. Therefore, even considering the influence of PVT variations, the influence is small, and the width time of the pulse PW to be measured can be calculated as accurately as possible.

[0070] Also, by calculating the ratio of the width time of the pulse PW to the period of the reference clock SCLK, the influence of the variation due to PVT variations of the reference clock SCLK can also be compensated. Also, since the width time of the pulse PW is measured prior to the reference clock SCLK, it is not necessary to continuously measure the change in the period of the reference clock SCLK at all times. The TDC control circuit 21 and the TDC24 return to the low power consumption state when the measurement of the width time of the pulse PW to be measured and the period of the reference clock SCLK is completed.

[0071] When the TDC24 inputs the edge of the pulse PW to be measured in the low power consumption state, it returns to the normal operating state and sequentially measures the first edge time difference of the pair of edges of the pulse PW to be measured and the second edge time difference of the period of the reference clock SCLK, and then returns from the normal operating state to the low power consumption state. Thereby, the width time of the pulse PW to be measured and the period of the reference clock SCLK can be measured with minimal power consumption.

[0072] Also, when the measurement frequency change circuit 29 cuts off the pulses PAB, PB1B... PB3B, even if the latch 25 holds the width time of the pulse PW as the dividend at the timing t4, since the pulses PAB, PB1B... PB2B are not input to the TDC 24 and the latch 26 at the timings t5 to t9, the latch 26 holds the time data of the period of the reference clock SCLK measured last time.

[0073] The divider 28 can divide the width time of the pulse PW by the period of the reference clock SCLK measured last time and held in the latch 26 in advance. In this case, the number of measurements of the reference clock SCLK can be reduced, and the power consumption of the TDC 24 can be reduced.

[0074] In this embodiment, since the measurement frequency change circuit 29 is configured using the TFF 29a, the measurement frequency indicating the ratio of the number of measurements of the period of the reference clock SCLK to the number of measurements of the width time of the pulse PW is set to 1 / 2, but the measurement frequency is not limited to 1 / 2.

[0075] For example, the measurement frequency may be set to 1 / 10, that is, each time the width time of the pulse PAW is measured 10 times by the TDC 24, the period of the reference clock SCLK may be measured once. Or, each time a predetermined time preset to the extent that the timing change of the period of the reference clock SCLK appears significantly elapses, the period of the reference clock SCLK may be measured by the TDC 24.

[0076] According to the present embodiment, in response to the decrease in the measurement frequency of the period of the reference clock SCLK, when the period of the reference clock SCLK is not measured in a time-division manner although the pulse PAW is measured, the divider 28 divides the data of the width time of the pulse PAW measured this time by the data of the period of the reference clock SCLK held in the latch 26 in advance. Therefore, the number of measurements of the reference clock SCLK by the TDC 24 can be reduced, and the power consumption of the TDC 24 can be reduced.

[0077] Also, regardless of the order of input of a pair of edges of the pulse PW to be measured and the reference clock SCLK, the TDC control circuit 21 causes the pulses PAW and PAB to be sequentially input to the TDC 24 in a predetermined order, so that the first edge time difference and the second edge time difference are measured by the TDC 24 in a time-division manner.

[0078] Although the reference clock SCLK is constantly input to the TDC control circuit 21, even if there is a possibility of metastability occurring due to two stable states on the digital circuit depending on the order of input of a pair of edges of the pulse PW and the edge of the reference clock SCLK, the TDC control circuit 21 sequentially inputs the pulses PAW and PAB to the TDC 24 in a predetermined order, so it does not affect the division result of the divider 28.

[0079] (Other embodiments) The present invention is not limited to the foregoing embodiments, and for example, the following modifications or expansions are possible. Although the TDC 24 using the RDL 31 as a delay circuit has been shown in a form of measuring the time difference, it is not limited thereto. Also, in the foregoing embodiments, the form of generating the delay time by the signal propagation delay of the gate, for example, the method using the NAND gate 37 and the NOT gate 38 as the inversion delay elements has been described, but it is not limited thereto, and any delay circuit may be used as long as the time difference can be measured.

[0080] Although the form of measuring the time difference between a pair of edges of the pulse PW to be measured, that is, the time difference of the pulse from the rising edge to the falling edge has been described, it is not limited thereto, and it may be applied to the form of measuring the time difference of the pulse from the falling edge to the rising edge.

[0081] Furthermore, as shown in FIG. 18, the time difference between the rising edges of the pulse signals PWX1 and PWY1 respectively transmitted through the two signal lines is defined as the "pulse to be measured PW", and the "time difference between a pair of edges of the pulse to be measured PW" shown at the timings t1 to t2 in FIG. 18 may be taken as the measurement target. Similarly, as shown in FIG. 19, the time difference between the falling edges of the pulse signals PWX2 and PWY2 is defined as the "pulse to be measured PW", and the "time difference between a pair of edges of the pulse to be measured PW" shown at the timings t1 to t2 in FIG. 19 may be taken as the measurement target.

[0082] Also, the time difference from the rising edge of the pulse signal PWX1 to the falling edge of the pulse signal PWY2 may be considered as the "pulse to be measured PW", or the time difference from the falling edge of the pulse signal PWX2 to the rising edge of the pulse signal PWY1 may be considered as the "pulse to be measured PW".

[0083] The reference numerals in parentheses described in the claims indicate the correspondence with the specific means described in the embodiments above as one aspect of the present invention, and do not limit the technical scope of the present invention. It is possible to regard a mode in which a part of the above-described embodiments is omitted as long as the problem can be solved as an embodiment. Also, all conceivable modes can be regarded as embodiments as long as they do not deviate from the essence of the invention specified by the language described in the claims.

[0084] Also, although the present invention has been described in accordance with the above-described embodiments, it is understood that the present invention is not limited to the embodiments or structures. The present invention includes various modifications and variations within the equivalent scope. In addition, various combinations and forms, and further other combinations and forms including one element, more, or less thereof, fall within the scope and spirit of the present disclosure.

Explanation of Reference Numerals

[0085] In the drawings, 24 represents the TDC, 26 represents the latch (holding section), 28 represents the divider (division section), 31 represents the RDL (delay circuit), 55 represents the AND gate (first pulse output section), 56 represents the first delay circuit (first delay section), 58a represents the DFF (first latch output section), 75 represents the AND gate (second pulse output section), 76 represents the second delay circuit (second delay section), and 78a represents the DFF (second latch output section).

Claims

A circuit for digitally converting a time difference between a pair of edges of a pulse to be measured using a delay time by a delay circuit, wherein as the time difference, a first edge time difference (PAW) between a pair of edges of the pulse to be measured and a second edge time difference (PAB) of a period of a reference clock are measured in a time-division manner by one TDC (24) (Time to Digital Converter), a division unit (28) for calculating a division result obtained by dividing the first edge time difference by the second edge time difference, wherein the TDC is a time difference digital conversion circuit that measures a surge width of a current waveform as the first edge time difference between a pair of edges of the pulse to be measured. **Claim 2** The TDC operates in a normal operating state when a pair of edges of the pulse to be measured or a period of the reference clock is input, and enters a low power consumption state with lower power consumption than the normal operating state when the input is interrupted. The time difference digital conversion circuit according to claim 1. **Claim 3** The TDC When an edge of the pulse to be measured is input in the low power consumption state, it returns to the normal operating state, sequentially measures the first edge time difference between a pair of edges of the pulse to be measured and the second edge time difference of the period of the reference clock, and then returns from the normal operating state to the low power consumption state. The time difference digital conversion circuit according to claim 2. **Claim 4** a first pulse output unit (55) that outputs a pulse corresponding to a pair of edges of the pulse to be measured to the TDC, a first latch output unit (58a) that outputs a latch signal corresponding to an edge that occurs later among a pair of edges of the pulse to be measured, a first delay unit (56) that extends the width of the pulse output by the first pulse output unit by a first delay time, and a TDC control circuit (21) is provided, wherein the TDC control circuit latches the pulse extended by the first delay unit with the latch signal of the first latch output unit, and stops the output of the pulse by the first pulse output unit after the elapse of the first delay time. The time difference digital conversion circuit according to any one of claims 1 to 3. **Claim 5** a second pulse output unit (75) that outputs a pulse corresponding to the period of the reference clock to the TDC, a second latch output unit (78a) that outputs a latch signal corresponding to an edge that occurs later among the edges defining the period of the reference clock, A TDC control circuit (21) comprising: a second delay unit (76) that extends the width of the pulse output by the second pulse output unit by a second delay time. The TDC control circuit is The time difference digital conversion circuit according to any one of claims 1 to 4, wherein the pulse extended by the second delay unit is latched by the latch signal of the second latch output unit, and the output of the pulse by the second pulse output unit is stopped after the elapse of the second delay time.

6. A TDC control circuit (21) comprising: a first pulse output unit (55) that inputs a pair of edges of the measurement target pulse and the reference clock, and outputs a pulse corresponding to the pair of edges of the measurement target pulse to the TDC; and a second pulse output unit (75) that outputs a pulse corresponding to the period of the reference clock to the TDC. The TDC control circuit causes the TDC to measure the first edge time difference and the second edge time difference in the time division by sequentially inputting the pulse from the first pulse output unit and the pulse from the second pulse output unit to the TDC in a predetermined order regardless of the input order of the pair of edges of the measurement target pulse and the reference clock. The time difference digital conversion circuit according to any one of claims 1 to 5.

7. The time difference digital conversion circuit according to any one of claims 1 to 6, wherein the TDC measures the width obtained by peak slicing an analog signal waveform as the first edge time difference between the edges of the measurement target pulse.

8. A measurement frequency change circuit (29) that reduces the measurement frequency indicating the ratio of the measurement frequency of the second edge time difference to the measurement frequency of the first edge time difference to less than 1, A holding unit (26) that holds the second edge time difference measured in advance in the time division, In response to the reduction of the measurement frequency by the measurement frequency change circuit, when the first edge time difference is measured but the second edge time difference is not measured in the time division, The time difference digital conversion circuit according to any one of claims 1 to 7, wherein the division unit divides the measured first edge time difference by the second edge time difference previously held in the holding unit.

9. The time difference digital conversion circuit according to any one of claims 1 to 8, wherein the delay time is generated by a delay circuit.

10. The time difference digital conversion circuit according to claim 9, wherein the delay circuit generates the delay time using the signal propagation delay of a gate.

11. The time difference digital conversion circuit according to any one of claims 1 to 10, wherein the current waveform is a current waveform obtained by driving a motor (7).

12. The time difference digital conversion circuit according to any one of claims 1 to 11, wherein the division unit calculates the division result at least up to the decimal part.

13. The time difference digital conversion circuit according to any one of claims 1 to 12, wherein a time difference between a pair of edges of the measurement target pulse is output based on the division result by the division unit.

14. A circuit that digitally converts a time difference between a pair of edges of a measurement target pulse using a delay time by a delay circuit, and as the time difference, a first edge time difference (PAW) between a pair of edges of the measurement target pulse and a second edge time difference (PAB) of a cycle of a reference clock are measured in a time-division manner by one TDC (24) (Time to Digital Converter), a division unit (28) that calculates a division result obtained by dividing the first edge time difference by the second edge time difference, A control method for a time difference digital conversion circuit comprising: The control method of a time difference digital conversion circuit, wherein the TDC measures a surge width of a current waveform as the first edge time difference between a pair of edges of the measurement target pulse.

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