Method for manufacturing a semiconductor device

Abstract

To suppress separation of nitrogen from a GaN-based semiconductor substrate by a protection film and suppress an adverse effect on characteristics of the semiconductor element caused by removal of the protection film.SOLUTION: A method for manufacturing a semiconductor element includes steps of: injecting a dopant into a GaN-based semiconductor substrate (12); epitaxially growing a protection film (50) on a surface of the GaN-based semiconductor substrate after injecting the dopant into the GaN-based semiconductor substrate; injecting the dopant into the protection film; and activating the dopant injected into the GaN-based semiconductor substrate by annealing the GaN-based semiconductor substrate at a temperature of 1200°C or higher after epitaxially growing the protection film. The protection film into which the dopant was injected serves as a part of a semiconductor layer of the semiconductor element.SELECTED DRAWING: Figure 5

Description

Technical Field

[0001] The technology disclosed in this specification relates to a method for manufacturing semiconductor devices.

[0002] In the method for manufacturing a semiconductor device disclosed in Patent Document 1, a protective film is formed on the surface of a GaN-based semiconductor substrate after doping. Thereafter, the GaN-based semiconductor substrate is annealed. During annealing, the dopant implanted into the GaN-based semiconductor substrate is activated. Also, during annealing, the protective film prevents nitrogen from being removed from the surface of the GaN-based semiconductor substrate. The protective film is removed after annealing.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In the technology of Patent Document 1, when removing the protective film, the GaN-based semiconductor substrate is damaged. For example, when removing the protective film by dry etching, the surface of the GaN-based semiconductor substrate under the protective film is damaged by etching. Also, when removing the protective film by CMP (chemical mechanical polishing), the surface of the GaN-based semiconductor substrate under the protective film is polished and damaged. Further, when removing the protective film by TMAH (that is, tetramethylammonium hydroxide), pits are formed on the surface of the GaN-based semiconductor substrate because the surface of the GaN-based semiconductor substrate is exposed to TMAH for a long time. Also, in the technology of Patent Document 1, the protective film cannot be completely removed, and a thin protective film may remain on the surface of the GaN-based semiconductor substrate. In this case, the remaining thin protective film becomes a resistance component. Thus, in the technology of Patent Document 1, various problems occur in the process of removing the protective film, which has an adverse effect on the characteristics of the semiconductor device. In this specification, a technology is proposed that can suppress the detachment of nitrogen from the GaN-based semiconductor substrate by the protective film and can suppress the adverse effect on the characteristics of the semiconductor device caused by the removal of the protective film.

Means for Solving the Problems

[0005] The method for manufacturing a semiconductor device disclosed in this specification includes a step of implanting a dopant into a GaN-based semiconductor substrate (12), a step of epitaxially growing a protective film (50) on the surface of the GaN-based semiconductor substrate after implanting the dopant into the GaN-based semiconductor substrate, a step of implanting the dopant into the protective film, and a step of annealing the GaN-based semiconductor substrate at a temperature of 1200 °C or higher after epitaxially growing the protective film to activate the dopant implanted into the GaN-based semiconductor substrate. The protective film implanted with the dopant becomes a part of the semiconductor layer of the semiconductor device.

[0006] Note that the dopant to be implanted into the GaN-based semiconductor substrate may be either n-type or p-type. Also, the dopant to be implanted into the protective film may be either n-type or p-type. Further, the protective film that forms part of the semiconductor layer of the semiconductor device may be the entire epitaxially grown protective film or a part thereof.

[0007] In this manufacturing method, by implanting a dopant into the protective film, the protective film is made into an n-type or p-type semiconductor. All or part of the protective film into which the dopant has been implanted remains as part of the GaN-based semiconductor substrate and becomes part of the semiconductor layer of the semiconductor device. Therefore, within the range of the remaining protective film, the protective film is not removed, so problems caused by the removal of the protective film (i.e., damage to the GaN-based semiconductor substrate or an increase in resistance due to the remaining protective film) can be prevented. Thus, according to this manufacturing method, a semiconductor device with high characteristics can be manufactured.

Brief Description of the Drawings

[0008]

Figure 1

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Embodiments for Carrying Out the Invention

[0009] In the manufacturing method of an example disclosed in this specification, after performing the step of implanting a dopant into the protective film, the step of annealing the GaN-based semiconductor substrate at a temperature of 1200°C or higher may be performed.

[0010] According to this configuration, dopants in the protective film are activated in the annealing process. That is, in the annealing process, not only dopants in the GaN-based semiconductor substrate but also dopants in the protective film are activated.

[0011] In an example of the manufacturing method disclosed in this specification, the protective film may have an AlN layer.

[0012] According to this configuration, the protective film can preferably suppress the detachment of nitrogen from the GaN-based semiconductor substrate.

[0013] When the protective film has an AlN layer, the protective film may have an AlGaN layer disposed between the AlN layer and the GaN-based semiconductor substrate.

[0014] According to this configuration, the protective film can more preferably suppress the detachment of nitrogen from the GaN-based semiconductor substrate.

[0015] In an example of the manufacturing method disclosed in this specification, the semiconductor element may be a field effect transistor. The GaN-based semiconductor substrate may have an n-type drain region (40) disposed in a range including the lower surface of the GaN-based semiconductor substrate, and an n-type drift region (36) disposed in a range including the upper surface of the GaN-based semiconductor substrate and having an n-type impurity concentration lower than that of the drain region. In the step of implanting dopants into the GaN-based semiconductor substrate, a p-type body region (34) may be formed in the drift region by implanting a p-type dopant onto the upper surface of the GaN-based semiconductor substrate. In the step of epitaxially growing the protective film, the protective film may be epitaxially grown on the lower surface of the GaN-based semiconductor substrate within the range of the drain region. The manufacturing method may further include a step of forming a drain electrode (26) on the surface of the protective film.

[0016] According to this configuration, the resistance between the drain region and the drain electrode can be reduced.

Example

[0017] The field effect transistor 10 (hereinafter referred to as FET10) of Example 1 shown in FIG. 1 has a semiconductor substrate 12. The semiconductor substrate 12 is made of gallium nitride (i.e., GaN). However, in other embodiments, the semiconductor substrate 12 may be made of AlGaN, InGaN, or the like. On the upper part of the semiconductor substrate 12, a gate insulating film 20, a gate electrode 22, and a source electrode 24 are arranged. The gate insulating film 20 covers a part of the upper surface 12a of the semiconductor substrate 12. The gate electrode 22 covers the upper surface of the gate insulating film 20. The source electrode 24 covers the upper surface 12a of the semiconductor substrate 12 in a range where the gate insulating film 20 is not provided. Below the semiconductor substrate 12, a semiconductor layer 50 and a drain electrode 26 are arranged. The semiconductor layer 50 is made of aluminum nitride (i.e., AlN). The semiconductor layer 50 covers the entire lower surface 12b of the semiconductor substrate 12. The drain electrode 26 covers the entire lower surface of the semiconductor layer 50.

[0018] The semiconductor substrate 12 has a plurality of source regions 30, a plurality of contact regions 32, a plurality of body regions 34, a drift region 36, a buffer region 38, and a drain region 40. Each source region 30 is an n-type region with a high n-type impurity concentration. Each source region 30 is disposed in a range facing the upper surface 12a of the semiconductor substrate 12. Each source region 30 is disposed in a range in contact with the source electrode 24 and the gate insulating film 20. Each source region 30 has an ohmic contact with the source electrode 24. Each contact region 32 is a p-type region with a high p-type impurity concentration. Each contact region 32 is disposed in a range facing the upper surface 12a of the semiconductor substrate 12. Each contact region 32 has an ohmic contact with the source electrode 24 in a range adjacent to the source region 30. Each body region 34 is a p-type region with a lower p-type impurity concentration than the contact region 32. Each body region 34 is disposed around the source region 30 and the contact region 32. Each body region 34 is in contact with the gate insulating film 20 in a range adjacent to the source region 30. The drift region 36 is an n-type region with a low n-type impurity concentration. The drift region 36 is separated from the source region 30 by the body region 34. The drift region 36 is in contact with the gate insulating film 20 at a window portion sandwiched between two body regions 34. The buffer region 38 is an n-type region with a higher n-type impurity concentration than the drift region 36. The buffer region 38 is in contact with the drift region 36 from below. The drain region 40 is an n-type region with a higher n-type impurity concentration than the buffer region 38. The drain region 40 is in contact with the buffer region 38 from below. The semiconductor layer 50 is an n-type region having an n-type impurity concentration as high as that of the drain region 40. The semiconductor layer 50 is in contact with the drain region 40 from below. The semiconductor layer 50 has an ohmic contact with the drain electrode 26.

[0019] The gate electrode 22 extends across the upper part of the source region 30, the body region 34, and the drift region 36 within the window portion. When a potential equal to or higher than the threshold value is applied to the gate electrode 22, a channel is formed in the body region 34 in the vicinity of the gate insulating film 20, and the source region 30 and the drift region 36 within the window portion are connected by the channel. Therefore, electrons flow from the source electrode 24 through the source region 30, the channel, the drift region 36, the buffer region 38, the drain region 40, and the semiconductor layer 50 to the drain electrode 26. That is, the FET 10 is turned on. When the potential of the gate electrode 22 is decreased below the threshold value, the channel disappears and the flow of electrons stops. That is, the FET 10 is turned off.

[0020] Next, a method for manufacturing the FET 10 will be described. The FET 10 is manufactured from the semiconductor substrate 12 shown in FIG. 2. The semiconductor substrate 12 shown in FIG. 2 has a drain region 40, a buffer region 38, and a drift region 36. The buffer region 38 is disposed on the drain region 40, and the drift region 36 is disposed on the buffer region 38. Each of the drain region 40, the buffer region 38, and the drift region 36 may be constituted by a wafer cut out from an ingot, may be an epitaxial layer, or may be a diffusion layer formed by ion implantation.

[0021] In the method for manufacturing the FET 10, first, p-type and n-type impurities (i.e., dopants) are selectively ion-implanted into the upper surface 12a of the semiconductor substrate 12 shown in FIG. 2. As a result, as shown in FIG. 3, a source region 30, a contact region 32, and a body region 34 are formed in the drift region 36. Note that at the stage of FIG. 3, the impurities inside the source region 30, the contact region 32, and the body region 34 are not activated.

[0022] Next, as shown in FIG. 4, a protective film 60 is formed on the upper surface 12a of the semiconductor substrate 12, and a protective film 50 is formed on the lower surface 12b of the semiconductor substrate 12. The protective films 50 and 60 are films composed of single crystals of aluminum nitride. Here, the protective film 60 is formed by MOCVD (metal organic chemical vapor deposition) so as to cover the entire area of the upper surface 12a. Also, here, the protective film 50 is formed by MOCVD so as to cover the entire area of the lower surface 12b. At this stage, the conductivity of the protective films 50 and 60 is low. Note that the protective films 50 and 60 may be formed by an epitaxial growth method other than MOCVD (for example, vapor phase growth or liquid phase growth).

[0023] Next, as shown in FIG. 5, n-type impurities are ion-implanted into the protective film 50. Here, the n-type impurities are implanted into the protective film 50 at a concentration similar to that of the drain region 40.

[0024] Next, the semiconductor substrate 12 is annealed at a temperature of 1200° C. or higher. This activates the dopants implanted into the source region 30, the contact region 32, and the body region 34. Also, generally, when a GaN-based semiconductor substrate is heated to a temperature of 1200° C. or higher, a phenomenon occurs in which the GaN-based semiconductor decomposes on the surface of the GaN-based semiconductor substrate and nitrogen is released. However, in Example 1, since the upper surface 12a and the lower surface 12b of the semiconductor substrate 12 are covered with the protective films 50 and 60, the release of nitrogen is suppressed on the upper surface 12a and the lower surface 12b. Also, in this step, when the protective film 50 is heated to 1200° C. or higher, the n-type impurities implanted into the protective film 50 are activated. As a result, the insulating protective film 50 becomes a semiconductor layer 50 having the characteristics of an n-type semiconductor.

[0025] Next, as shown in FIG. 6, an insulating film 62 made of silicon oxide is formed on the upper surface of the protective film 60. Next, as shown in FIG. 7, a gate electrode 22 is formed so as to cover a part of the upper surface of the insulating film 62. Next, the insulating film 62 and the protective film 60 are removed above the source region 30 and the contact region 32 to form a contact hole, and a source electrode 24 is formed in the contact hole. Below the gate electrode 22, the insulating film 62 and the protective film 60 are left remaining. The remaining insulating film 62 and protective film 60 become the gate insulating film 20.

[0026] Next, as shown in FIG. 1, a drain electrode 26 is formed so as to cover the lower surface of the semiconductor layer 50 (that is, the protective film 50). Since the n-type impurity concentration of the semiconductor layer 50 is high, the drain electrode 26 makes an ohmic contact with the semiconductor layer 50. Thereafter, the semiconductor substrate 12 is diced to manufacture the FET 10.

[0027] As described above, in this manufacturing method, protective films 50 and 60 that cover the upper surface 12a and the lower surface 12b of the semiconductor substrate 12 are formed. Therefore, in the annealing for activating the dopants in the source region 30, the contact region 32, and the body region 34 thereafter, the detachment of nitrogen is suppressed on the upper surface 12a and the lower surface 12b. Further, in this manufacturing method, since an n-type impurity is implanted into the protective film 50 before annealing, the n-type impurity in the protective film 50 is also activated in the annealing for activating the dopants in the source region 30, the contact region 32, and the body region 34. Therefore, the protective film 50 becomes the n-type semiconductor layer 50. The semiconductor layer 50 is used as a part of the semiconductor layer of the FET 10. For this reason, in this manufacturing method, the protective film 50 (that is, the semiconductor layer 50) is not removed from the semiconductor substrate 12. For this reason, problems caused by the protective film removal process (for example, damage to the semiconductor and an increase in resistance due to the remaining protective film, etc.) do not occur. Therefore, the drain electrode 26 is connected to the drain region 40 with low resistance through the semiconductor layer 50. Therefore, according to this manufacturing method, the FET 10 having high characteristics can be manufactured.

Example

[0028] In the FET 110 of Example 2 shown in FIG. 8, unlike the FET 10 of Example 1, the semiconductor layer 50 has an AlGaN layer 50a and an AlN layer 50b. The AlGaN layer 50a is in contact with the lower surface 12b of the semiconductor substrate 12, and the AlN layer 50b is in contact with the lower surface of the AlGaN layer 50a. The source electrode 24 is in ohmic contact with the lower surface of the AlN layer 50b. Both the AlGaN layer 50a and the AlN layer 50b are n-type regions having an n-type impurity concentration comparable to that of the drain region 40. Therefore, the FET 110 of Example 2 operates substantially in the same manner as the FET 10 of Example 1.

[0029] A method for manufacturing the FET 110 of Example 2 will be described. In the manufacturing method of Example 2, the semiconductor substrate 12 is processed to the state shown in FIG. 3 in the same manner as in the manufacturing method of Example 1. Next, a protective film 60 is formed on the upper surface 12a of the semiconductor substrate 12, and a protective film 50 is formed on the lower surface 12b of the semiconductor substrate 12. The protective film 60 is formed in the same manner as in Example 1. In the step of forming the protective film 50, first, an AlGaN layer 50a is formed on the lower surface 12b of the semiconductor substrate 12 by MOCVD. Next, an AlN layer 50b is formed on the lower surface of the AlGaN layer 50a by MOCVD. At this stage, the conductivity of the AlGaN layer 50a and the AlN layer 50b is low. Next, n-type impurities are ion-implanted into the protective film 50. Here, n-type impurities are implanted into the entire AlGaN layer 50a and AlN layer 50b. Next, the semiconductor substrate 12 is annealed at a temperature of 1200 °C or higher. As a result, the dopants implanted into the source region 30, the contact region 32, and the body region 34 are activated. Also, the dopants implanted into the AlGaN layer 50a and the AlN layer 50b are activated. As a result, the AlGaN layer 50a and the AlN layer 50b become semiconductor layers having the characteristics of n-type semiconductors. Further, since the upper surface 12a and the lower surface 12b of the semiconductor substrate 12 are covered with the protective films 50 and 60, the detachment of nitrogen is suppressed on the upper surface 12a and the lower surface 12b. Thereafter, the gate insulating film 20, the gate electrode 22, the source electrode 24, and the drain electrode 26 are formed in the same manner as in Example 1. Thereby, the FET 110 of Example 2 is manufactured.

[0030] When the protective film 50 has a two-layer structure of an AlGaN layer 50a and an AlN layer 50b as in Example 2, the desorption of nitrogen from the lower surface 12b can be more effectively suppressed. For example, in the FETs 10 and 110 manufactured by the manufacturing methods of Examples 1 and 2, an experiment was conducted in which the semiconductor layer 50 was removed and the lower surface 12b of the semiconductor substrate 12 was observed. As a result, in the FET 10 of Example 1, the area ratio of the decomposition region (the region where nitrogen was desorbed) on the lower surface 12b was 0.2%, while in the FET 110 of Example 2, the area ratio of the decomposition region on the lower surface 12b was 0.06%. Thus, according to the manufacturing method of Example 2, the desorption of nitrogen from the lower surface 12b can be more effectively suppressed.

[0031] In addition, in Examples 1 and 2 described above, the upper portions of the source region 30 and the contact region 32 of the protective film 60 covering the upper surface 12a of the semiconductor substrate 12 were removed. In the process of removing the protective film 60, damage may be caused to the surfaces of the source region 30 and the contact region 32, or a thin protective film 60 may remain on these surfaces. However, in the manufacturing methods of Examples 1 and 2, at least damage to the lower surface 12b of the semiconductor substrate 12 can be suppressed. In other embodiments, a dopant may be implanted into the protective film 60 above the source region 30 and the contact region 32, and this portion of the protective film 60 may be used as a semiconductor layer (for example, a part of the source region 30 and the contact region 32). By using the protective film 60 as a semiconductor layer in this way, damage to the upper surface 12a of the semiconductor substrate 12 can be suppressed.

[0032] Also, in Examples 1 and 2 described above, the protective film 60 below the gate electrode 22 is used as a part of the gate insulating film 20. Therefore, it is not necessary to remove the protective film 60 below the gate electrode 22, and damage to the upper surface 12a below the gate electrode 22 can be suppressed. In other embodiments, the protective film 60 below the gate electrode 22 may be removed. That is, the gate insulating film 20 may be composed only of the insulating film 62.

[0033] Also, in the above-described Examples 1 and 2, n-type impurities were implanted into the protective film 50 before the annealing process for activating dopants such as the body region 34. However, n-type impurities may be implanted into the protective film 50 after the annealing process. However, in this case, it is necessary to separately perform annealing for activating the n-type impurities inside the protective film 50. When n-type impurities are implanted into the protective film 50 before the annealing process for activating dopants such as the body region 34 as in the above-described Examples, the n-type impurities in the protective film 50 can also be simultaneously activated in the annealing process, and the FET 10 can be efficiently manufactured.

[0034] Also, in the above-described Examples 1 and 2, the entire semiconductor layer 50 (i.e., the protective film 50) was left intact, but a part of the semiconductor layer 50 may be removed. Even with such a configuration, damage to the lower surface 12b of the semiconductor substrate 12 can be suppressed in the range where the semiconductor layer 50 remains.

[0035] Also, materials different from those in the above-described Examples 1 and 2 may be used for the protective film 50. As the protective film 50, a material (e.g., nitride) that can suppress the detachment of nitrogen from the GaN-based semiconductor substrate and that can function as a semiconductor by implanting dopants can be used. For example, the protective film 50 may be composed only of an AlGaN layer. Also, the protective film 50 may be composed of Si3N4. Also, the protective film 50 may have a multilayer structure combining at least two of an AlN layer, an AlGaN layer, and a Si3N4 layer.

[0036] Although the embodiments have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above. The technical elements described in this specification or the drawings exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Also, the technology illustrated in this specification or the drawings achieves multiple purposes simultaneously, and achieving one of those purposes itself has technical utility.

Explanation of Reference Numerals

[0037] 10: FET, 12: Semiconductor Substrate, 30: Source Region, 32: Contact Region, 34: Body Region, 36: Drift Region, 38: Buffer Region, 40: Drain Region, 50: Semiconductor Layer

Claims

1. A method for manufacturing a semiconductor device, comprising: a step of implanting a dopant into a GaN-based semiconductor substrate (12); a step of epitaxially growing a protective film (50) on the surface of the GaN-based semiconductor substrate after implanting the dopant into the GaN-based semiconductor substrate; a step of implanting a dopant of the same conductivity type as the surface of the GaN-based semiconductor substrate into the protective film; a step of activating the dopant implanted into the GaN-based semiconductor substrate by annealing the GaN-based semiconductor substrate at a temperature of 1200°C or higher after epitaxially growing the protective film; a step of forming a drain electrode (26) on the surface of the protective film on the side opposite to the surface of the GaN-based semiconductor substrate; characterized by: a manufacturing method, wherein the protective film implanted with the dopant becomes a part of the semiconductor layer of the semiconductor device.

2. A method for manufacturing a semiconductor device, comprising: a step of implanting a dopant into a GaN-based semiconductor substrate (12); a step of epitaxially growing a protective film (50) over the entire surface of the GaN-based semiconductor substrate after implanting the dopant into the GaN-based semiconductor substrate; a step of implanting a dopant into the protective film; a step of activating the dopant implanted into the GaN-based semiconductor substrate by annealing the GaN-based semiconductor substrate at a temperature of 1200°C or higher after epitaxially growing the protective film; characterized by: retaining the entire protective film; a manufacturing method, wherein the protective film implanted with the dopant becomes a part of the semiconductor layer of the semiconductor device.

3. A method for manufacturing a semiconductor device, comprising: a step of implanting a dopant into a GaN-based semiconductor substrate (12); a step of epitaxially growing a protective film (50) on the surface of the GaN-based semiconductor substrate after implanting the dopant into the GaN-based semiconductor substrate; a step of implanting a dopant into the protective film; a step of activating the dopant implanted into the GaN-based semiconductor substrate by annealing the GaN-based semiconductor substrate at a temperature of 1200°C or higher after epitaxially growing the protective film; a step of forming a drain electrode (26) on the surface of the protective film; characterized by: the protective film implanted with the dopant becomes a part of the semiconductor layer of the semiconductor device; the semiconductor device is a field effect transistor. The GaN-based semiconductor substrate has an n-type drain region (40) disposed in a range including the lower surface of the GaN-based semiconductor substrate, and an n-type drift region (36) disposed in a range including the upper surface of the GaN-based semiconductor substrate and having an n-type impurity concentration lower than that of the drain region. In the step of implanting a dopant into the GaN-based semiconductor substrate, a p-type body region (34) is formed in the drift region by implanting a p-type dopant onto the upper surface of the GaN-based semiconductor substrate. A manufacturing method in which, in the step of epitaxially growing the protective film, the protective film is epitaxially grown on the lower surface of the GaN-based semiconductor substrate within the range of the drain region. Claim 4 The manufacturing method according to any one of claims 1 to 3, wherein, after the step of implanting a dopant into the protective film, the step of annealing the GaN-based semiconductor substrate at a temperature of 1200 °C or higher is performed. Claim 5 The manufacturing method according to any one of claims 1 to 4, wherein the protective film has an AlN layer. Claim 6 The manufacturing method according to claim 5, wherein the protective film has an AlGaN layer (50a) disposed between the AlN layer and the GaN-based semiconductor substrate.

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