Semiconductor device and method of manufacturing the same

Abstract

An embodiment of the present invention discloses a semiconductor device and a manufacturing method thereof. The semiconductor device includes an active region and a passive region, and further includes a source, a drain, and a gate located between the source and the drain, which are located on one side of a substrate. The gate includes a first end and a middle portion. The middle portion, the source, and the drain are all located in the active region. The first end is located in the passive region. The first end includes a first sub-end and a second sub-end. In a first direction, the extension width of the first sub-end is wider than that of the middle portion, and the extension width of the second sub-end is wider than that of the first sub-end. The first direction is parallel to the direction from the source to the drain. By widening the extension width of the gate end, the contact area between the gate end metal and the substrate is increased, the sealing efficiency of the device is improved, the stability of the gate structure and the stability of the performance are ensured, and the operation stability and reliability of the semiconductor device are further improved.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductor technology, and in particular, to semiconductor devices and manufacturing methods thereof.

Background Art

[0002] Gallium nitride (GaN) as a semiconductor material has characteristics such as strong spontaneous and piezoelectric polarization effects, a large bandgap, a high electron drift velocity, a high breakdown electric field strength, and excellent thermal conductivity. Therefore, it shows significant advantages in the application fields of high-frequency, high-voltage, and high-temperature-resistant high-power electronic devices.

[0003] Currently, for 5G communication, high bandwidth and operating frequency of semiconductor devices are required. The gate structure design and manufacturing process strongly depend on the frequency characteristics of semiconductor devices, and the gate structure directly affects the operating frequency of semiconductor devices. During the manufacturing process of semiconductor devices, it is very important to study the design of the gate.

[0004] Therefore, further improving the reliability of semiconductor gates, stabilizing the performance of semiconductor devices, and realizing large-scale commercial production and manufacturing are problems to be solved.

Summary of the Invention

Problems to be Solved by the Invention

[0005] Therefore, embodiments of the present invention provide a semiconductor device and a manufacturing method thereof, which further improve the reliability of semiconductor gates, stabilize the performance of semiconductor devices, and meet the requirements of large-scale commercial production and manufacturing.

Means for Solving the Problems

[0006] In the first aspect, an embodiment of the present invention provides a semiconductor device, including an active region and a passive region surrounding the active region. The semiconductor device further includes a substrate, a source located on one side of the substrate, a drain, and a gate located between the source and the drain. The gate includes a first end portion and an intermediate portion. The intermediate portion, the source, and the drain are all located in the active region. The first end portion is located in the passive region. The first end portion includes a first sub-end portion and a second sub-end portion. In a first direction, the extension width of the first sub-end portion is wider than the extension width of the intermediate portion, and the extension width of the second sub-end portion is wider than the extension width of the first sub-end portion. The first direction is parallel to the direction from the source to the drain.

[0007] Preferably, the first sub-end portion is curved toward the source side and / or the drain side, and the second sub-end portion is curved toward the source side and / or the drain side.

[0008] Preferably, the distance W1 between the bending end point of the first sub-end portion and the boundary of the active region satisfies 2 μm ≤ W1 ≤ 10 μm. The distance W2 between the bending end point of the second sub-end portion and the boundary of the active region satisfies 10 μm ≤ W2 ≤ 50 μm.

[0009] Preferably, the edge profile of at least one side of the first sub-end portion close to the source and / or the drain includes a first curve, and the center of the circle corresponding to the arc where any two points of the first curve are located is located on the same side of the first curve. The edge profile of at least one side of the second sub-end portion close to the source and / or the drain includes a second curve, and the center of the circle corresponding to the arc where any two points of the second curve are located is located on the same side of the second curve.

[0010] Preferably, the first curve includes a first point and a second point. The second point is located on the side of the first point close to the passive region, and the radius of curvature corresponding to the second point is larger than the radius of curvature corresponding to the first point. Preferably, at least one side edge profile of the first sub-end portion close to the source and / or the drain further includes a third curve that is smoothly connected to the first curve, the third curve is located on a side close to the passive region of the first curve, and the centers corresponding to the arcs where any two points of the first curve and any two points of the third curve are located are respectively located on different sides of the edge profile.

[0011] Preferably, the first curve includes a first curve start point and a first curve end point, the second curve includes a second curve start point and a second curve end point, the third curve includes a third curve start point and a third curve end point, the first curve end point overlaps with the third curve start point, when the bending directions of the first sub-end portion and the second sub-end portion are the same, the third curve end point overlaps with the second curve start point, when the bending directions of the first sub-end portion and the second sub-end portion are different, the extending direction of the connecting line between the third curve end point and the second curve start point is parallel to the first direction, the first curve start point is the connection point between the middle portion and the first sub-end portion, and the second curve start point is the connection point between the first sub-end portion and the second sub-end portion.

[0012] Preferably, the gate further includes a second end portion. In the second direction, the first end portion, the middle portion, and the second end portion are sequentially arranged, and the second end portion is located in the passive region. The second direction is perpendicular to the first direction. The second end portion includes a third sub-end portion, and in the first direction, the extending width of the third sub-end portion is wider than the extending width of the middle portion.

[0013] Preferably, the second end portion further includes a fourth sub-end portion. The fourth sub-end portion is located on a side away from the active region of the third sub-end portion and is in contact with and connected to the third sub-end portion. In the first direction, the extending width of the fourth sub-end portion is wider than the extending width of the third sub-end portion.

[0014] Preferably, in the first direction, the extension width of the first sub-end portion is L1, the extension width of the second sub-end portion is L2, the extension width of the third sub-end portion is L3, the extension width of the fourth sub-end portion is L4, and the extension width of the intermediate portion is D. 1.2×D ≤ L1 ≤ 30×D 2.4×D ≤ L2 ≤ 60×D 1.2×D ≤ L3 ≤ 30×D 2.4×D ≤ L4 ≤ 60×D.

[0015] In a second aspect, an embodiment of the present invention provides a method of manufacturing a semiconductor device, which is for manufacturing the semiconductor device according to the first aspect. The method includes providing a substrate and manufacturing a source, a drain, and a gate located between the source and the drain on one side of the substrate. The gate includes a first end portion and an intermediate portion. The intermediate portion, the source, and the drain are all located in the active region. The first end portion is located in the passive region. The first end portion includes a first sub-end portion and a second sub-end portion. In a first direction, the extension width of the first sub-end portion is wider than the extension width of the intermediate portion, and the extension width of the second sub-end portion is wider than the extension width of the first end portion. The first direction is parallel to the direction from the source to the drain.

[0016] In the semiconductor device according to an embodiment of the present invention, the gate is installed so as to sequentially include a first end portion and an intermediate portion, the intermediate portion, the source, and the drain are all installed so as to be located in the active region, the first end portion is installed so as to be located in the passive region, and further, the first end portion located in the passive region is installed so as to include a first sub-end portion and a second sub-end portion. The extension width of the first sub-end portion in the direction from the source to the drain is wider than the extension width of the intermediate portion in the direction from the source to the drain, and the extension width of the second sub-end portion in the direction from the source to the drain is wider than the extension width of the first end portion in the direction from the source to the drain. According to such a structural design, it contributes to the penetration of the developing solution from the first sub-end portion to the intermediate portion, significantly reduces the difficulty of development, corrects the shape distortion of the gate corresponding to both end corner portions of the source and drain due to light diffraction, and ensures that the shape of the gate corresponding to both end corner portions of the source and drain is the same as the shape of the intermediate portion or reduces the difference in shape between the two. In addition, it increases the contact area between the gate end metal and the substrate, improves the adhesiveness between the gate metal and the substrate, prevents the phenomenon of partial dropout of the gate metal during manufacturing and testing, and reduces the contact resistance of the gate metal. The increased gate end area facilitates the interconnection between the gate metals of the device and improves the sealing efficiency of the device. According to such a gate structural design, the structural stability and performance stability of the gate are ensured, the operation stability and reliability of the semiconductor device are further improved, and it is applicable to fields such as RF / microwaves and power electronics.

Brief Description of the Drawings

[0017]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Mode for Carrying Out the Invention

[0018] Hereinafter, the present invention will be described in detail with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are merely for interpreting the present invention and are not intended to limit the present invention. Also, for convenience of explanation, only a part related to the present invention is shown in the drawings, and not all structures are shown.

[0019] The semiconductor device according to an embodiment of the present invention is applicable to fields such as RF / microwaves and power electronics. FIG. 1 is a diagram showing the configuration of a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a diagram showing the planar configuration of a semiconductor device according to an embodiment of the present invention. As shown in FIGS. 1 and 2, the semiconductor device 20 includes an active region aa and a passive region bb surrounding the active region aa. The semiconductor device 20 further includes a substrate 21, a source 23 located on one side of the substrate 21, a drain 25, and a gate 24 located between the source 23 and the drain 25. The gate 24 includes a first end portion 24a and an intermediate portion 241. The intermediate portion 241, the source 23, and the drain 25 are all located in the active region aa. The first end portion 24a is located in the passive region bb. The first end 24a portion includes a first sub-end portion 242a and a second sub-end portion 243a. In the first direction (the X direction shown in the figure), the extension width of the first sub-end portion 242a is wider than the extension width of the intermediate portion 241, and the extension width of the second sub-end portion 243a is wider than the extension width of the first sub-end portion 242a. The first direction is parallel to the direction from the source 23 to the drain 25.

[0020] Exemplarily, as shown in FIGS. 1 and 2, the source 23, the gate 24, and the drain 25 are arranged along a first direction (the illustrated X direction) and extend along the illustrated Y direction. The gate 24 is located between the source 23 and the drain 25. Note that the X direction in the figure is parallel to the direction from the source 23 to the drain 25. The Y direction is perpendicular to the X direction. The semiconductor device 20 includes an active region aa and a passive region bb surrounding the active region aa. The gate 24 sequentially includes a first end portion 24a and an intermediate portion 241. The intermediate portion 241, the source 23, and the drain 25 are all located in the active region aa. The first end portion 24a is located in the passive region bb. Note that the first end 24a portion includes a first sub-end portion 242a and a second sub-end portion 243a, both of which are located in the passive region bb. Note that a two-dimensional electron gas, electrons, or holes exist in the active region aa, which is the active operation region of the semiconductor chip. The passive region bb is a region that participates in the operation of the device outside the active region but whose operating state is not affected by an external circuit.

[0021] As shown in FIGS. 1 and 2, the extension width of the first sub-end portion 242a installed in the passive region bb in the X direction of the figure is wider than the extension width of the intermediate portion 241 in the X direction of the figure. By doing so, the first sub-end portion 242a with a wide extension width contributes to the penetration of the developing solution from the first sub-end portion 242a to the intermediate portion 241, reduces the difficulty of photolithography development of the gate 24, can correct the shape distortion of the gate corresponding to the both-end corner portions of the source and drain due to light diffraction, significantly reduces the difficulty of development, ensures that the shape of the gate corresponding to the both-end corner portions of the source and drain is the same as the shape of the intermediate portion 241 or reduces the difference in shape between the two, ensures the stability of the structure and performance of the gate 24, and further can suppress the influence of gate deformation on the power and frequency of the semiconductor device, ensuring the stability of the performance of the semiconductor device.

[0022] Furthermore, as shown in FIGS. 1 and 2, the extension width in the X direction of the figure of the second sub-end portion 243a located within the passive region bb is set to be wider than the extension width in the X direction of the figure of the first sub-end portion 242a, and further wider than the extension width in the X direction of the figure of the intermediate portion 241. According to such a structural design, by widening the extension width of the gate end portion, the contact area between the gate end metal and the substrate is increased, the adhesion between the gate metal and the substrate is improved, a part of the gate metal from falling off during manufacturing and testing is prevented, and the contact resistance of the gate metal is reduced. Furthermore, due to the increased gate end area, the interconnection between the gate metals of the device is facilitated, the sealing efficiency of the device is improved, and the stability of the performance of the semiconductor device is further improved.

[0023] Preferably, the material of the substrate 21 may be formed of one or more materials among silicon, sapphire, silicon carbide, gallium arsenide, gallium nitride, diamond, etc., or may be other materials suitable for the growth of gallium nitride.

[0024] To summarize the above, in the semiconductor device according to the embodiment of the present invention, a gate including a first end portion and an intermediate portion is sequentially provided, and the intermediate portion, the source, and the drain are all provided so as to be located in the active region, the first end portion is located in the passive region, and further, the first end portion located in the passive region is provided to include a first sub-end portion and a second sub-end portion. The extension width of the first sub-end portion in the direction from the source to the drain is wider than the extension width of the intermediate portion in the direction from the source to the drain, and the extension width of the second sub-end portion in the direction from the source to the drain is wider than the extension width of the first end portion in the direction from the source to the drain. According to such a structural design, it contributes to the penetration of the developer from the first sub-end portion to the intermediate portion, significantly reduces the difficulty of development, corrects the shape distortion of the gate corresponding to both end corners of the source / drain due to light diffraction, and ensures that the shape of the gate corresponding to both end corners of the source / drain is the same as the shape of the intermediate portion or reduces the difference in shape between the two. In addition, it increases the contact area between the gate end metal and the substrate, improves the adhesiveness between the gate metal and the substrate, prevents the phenomenon of partial detachment of the gate metal during manufacturing and testing, and reduces the contact resistance of the gate metal. Furthermore, by providing the second sub-end portion, the area of the gate end is further increased, facilitating the interconnection between the gate metals of the device and improving the sealing efficiency of the device. According to such a gate structural design, the stability of the gate structure and the performance stability are ensured, the operation stability and reliability of the semiconductor device are further improved, and it is applicable to fields such as RF / microwaves and power electronics.

[0025] Preferably, referring continuously to FIGS. 1 and 2, the first sub-end portion 242a is curved toward the source 23 side and / or the drain 25 side, and the second sub-end portion 243a is curved toward the source 23 side and / or the drain 25 side.

[0026] Exemplarily, with continued reference to FIGS. 1 and 2, the first sub-end 242a and the second sub-end 243a extend to the passive region bb. The first sub-end 242 may extend and curve in the Y direction of the figure in the direction of the source 23, or extend and curve in the direction of the drain 25 (not shown), or may extend and curve simultaneously in the direction of the source 23 and the drain 25 (not shown). The second sub-end 243a connected to the first sub-end 242a may extend and curve in the direction of the source 23 (not shown), or extend and curve in the direction of the drain 25, or may extend and curve simultaneously in the direction of the source 23 and the drain 25 (not shown). In an embodiment of the present invention, since the first sub-end 242a and the second sub-end 243a extend to the passive region, there is no limitation on how to increase the width. At least the extension widths of the first sub-end 242a and the second sub-end 243a located in the passive region bb are both made wider than the extension width of the middle portion 241, and it is ensured that the extension width of the second sub-end 243a is wider than the extension width of the first sub-end 242a, so that the gate corresponding to both end corner portions of the source-drain can be corrected, and the contact area between the gate end metal and the substrate can be increased.

[0027] FIG. 3 is an enlarged view of the configuration of the cc region in FIG. 2. In FIG. 3, only the example that the first end 24a located in the passive region bb includes the first sub-end 242a and the second sub-end 243a will be described. As shown in FIGS. 2 and 3, preferably, the distance W1 between the bending end point C of the first sub-end 242a and the boundary of the active region aa is 2 μm ≤ W1 ≤ 10 μm, and the distance W2 between the bending end point D of the second sub-end 243a and the boundary of the active region aa is 10 μm ≤ W2 ≤ 50 μm.

[0028] Exemplarily, as shown in FIGS. 2 and 3, the distance W1 between the bending end point C of the first sub-end portion 242a and the boundary of the active region aa is set to satisfy 2 μm ≤ W1 ≤ 10 μm. If the distance W1 between the bending end point C of the first sub-end portion 242a and the boundary of the active region aa is reasonably set, the first sub-end portion 242a of the gate does not occupy an excessive substrate area, and the capacitance between the first sub-end portion 242a of the gate and the active region aa, the source 23 or the drain 25 is not increased.

[0029] Furthermore, the distance W2 between the bending end point D of the second sub-end portion 243a and the boundary of the active region aa is set to satisfy 10 μm ≤ W2 ≤ 50 μm. If the distance W2 between the bending end point D of the second sub-end portion 243a and the boundary of the active region aa is reasonably set, by controlling the distance between the second sub-end portion 243a of the gate and the active region aa, the source 23 or the drain 25, the capacitance between the second sub-end portion 243a and the active region aa, the source 23 or the drain 25 is controlled to reduce the power consumption of the device, and it is prevented that the second sub-end portion 243a of the gate occupies an excessive substrate area.

[0030] Based on the above embodiments, as shown in FIGS. 2 and 3, the edge profile of at least one side of the first sub-end portion 242a close to the source 23 and / or the drain 25 includes a first curve 242a1. The center of the circle corresponding to the arc where any two points of the first curve 242a1 are located is located on the same side of the first curve 242a1. The edge profile of at least one side of the second sub-end portion 243a close to the source 23 and / or the drain 25 includes a second curve 243a1. The center of the circle corresponding to the arc where any two points of the second curve 243a1 are located is located on the same side of the second curve 243a1.

[0031] Exemplarily, as shown in FIGS. 2 and 3, the first sub-end portion 242a curves toward the source 23 side, and the edge profile on the side of the first sub-end portion 242a close to the source 23 includes the first curve 242a1. The second sub-end portion 243a curves toward the drain 25 side, and the edge profile on the side of the second sub-end portion 243a close to the drain 25 includes the second curve 243a1. As shown in FIG. 3, the center of the circle corresponding to the arc where any two points of the first curve 242a1 are located is located on the same side of the first curve 242a1. According to such a structure, the electric field spike between the gate and the source can be reduced. The center of the circle corresponding to the arc where any two points of the second curve 243a1 are located is located on the same side of the second curve 243a1. According to such a structure, the electric field spike between the gate and the drain can be reduced, and further, the stability of the performance of the semiconductor device can be ensured.

[0032] Note that in this embodiment, only the example that the edge profile on the side of the first sub-end portion 242a close to the source 23 includes the first curve 242a1 and the edge profile on the side of the second sub-end portion 243a close to the drain 25 includes the second curve 243a1 is taken. However, the edge profile on the side of the first sub-end portion 242a close to the drain 25 may include the first curve 242a1, or both the edge profile on the side of the first sub-end portion 242a close to the source 23 and the edge profile on the side of the first sub-end portion 242a close to the drain 25 may include the first curve 242a1. Similarly, the edge profile on the side of the second sub-end portion 243a close to the source 23 may include the second curve 243a1, or both the edge profile on the side of the second sub-end portion 243a close to the source 23 and the edge profile on the side of the second sub-end portion 243a close to the drain 25 may include the second curve 243a1. However, the embodiments of the present invention are not limited thereto.

[0033] Preferably, FIG. 4 is a diagram showing a partial planar configuration of a gate according to an embodiment of the present invention. As shown in FIG. 4, the first curve 242a1 includes a first point A and a second point B. The second point B is located on one side close to the passive region bb of the first point A. The radius of curvature R2 corresponding to the second point B is larger than the radius of curvature R1 corresponding to the first point A.

[0034] Exemplarily, in FIG. 4, an example will be described in which the first point is the start point A of the first curve and the second point is the end point B of the first curve. As shown in FIG. 4, the start point A of the first curve is the demarcation point between the active region aa and the passive region bb. The radius of curvature R2 corresponding to the second point B is larger than the radius of curvature R1 corresponding to the first point A. In this way, along the direction from the active region aa to the passive region bb, the distance between the first curve 242a1 and the chamfering of the opposing source 23 gradually increases, further optimizing the electric field between the gate 24 and the source 23 and further ensuring the stability of the performance of the semiconductor device.

[0035] Preferably, FIG. 5 is a diagram showing a partial planar configuration of another gate according to an embodiment of the present invention. As shown in FIG. 5, the edge profile on at least one side close to the source 23 and / or the drain 25 of the first sub-end 242a further includes a third curve 242a2 that is smoothly connected to the first curve 242a1. The third curve 242a2 is located on one side close to the passive region bb of the first curve 242a1. The centers of the circles corresponding to the arcs where any two points of the first curve 242a1 and any two points of the third curve 242a2 are located are located on different sides of the edge profile, respectively.

[0036] By way of example, in FIG. 5, the first end portion 24a located within the passive region bb includes a first sub-end portion 242a and a second sub-end portion 243a. The first sub-end portion 242a is curved toward the source 23, and the edge profile on the side of the first sub-end portion 242a close to the source 23 includes a first curve 242a1 and a third curve 242a2. The second sub-end portion 243a is curved toward the drain 25, and the edge profile on the side of the second sub-end portion 243a close to the drain 25 includes only a second curve 243a1. This will be described as an example only. As shown in FIG. 5, the third curve 242a2 is installed on the side of the first curve 242a1 close to the passive region bb, and the first curve 242a1 is smoothly connected to the third curve 242a2. Thereby, on the side of the second sub-end portion 243a close to the source 23, it is ensured to avoid the generation of electric field spikes due to sharp corners, further improve the electrical performance stability of the semiconductor device, and avoid stress concentration, ensuring the mechanical performance stability of the semiconductor device.

[0037] Furthermore, by installing the centers of the circles corresponding to the arcs where any two points of the first curve 242a1 and any two points of the third curve 242a2 are located on different sides of the edge profile respectively, it is further ensured to gradually increase the distance between the first curve 2341 and the chamfer of the opposing source 23, optimize the electric field between the gate 24 and the source 23, and improve the performance stability of the semiconductor device.

[0038] It should be noted that in this embodiment, only the case where the edge profile on the side of the first sub-end portion 242a close to the source 23 includes the first curve 242a1 and the third curve 242a2, and the edge profile on the side of the second sub-end portion 243a close to the drain 25 includes the second curve 243a1 is described as an example. It should be noted that the edge profile on the side of the first sub-end portion 242a close to the drain 25 may be installed to include the first curve 242a1 and the third curve 242a2, or the edge profiles on both the side of the first sub-end portion 242a close to the source 23 and the side close to the drain 25 may be installed to include the first curve 242a1 and the third curve 242a2, but the embodiments of the present invention are not limited thereto.

[0039] Preferably, with continued reference to FIGS. 3 and 5, the first curve 242a1 includes a first curve start point A and a first curve end point B, the second curve 243a1 includes a second curve start point E and a second curve end point D, and the third curve 242a2 includes a third curve start point B and a third curve end point C. The first curve end point B overlaps with the third curve start point B. When the bending directions of the first sub-end portion 242a and the second sub-end portion 243a are the same, the third curve end point C overlaps with the second curve start point E (not shown). When the bending directions of the first sub-end portion 242a and the second sub-end portion 243a are different, the extending direction of the connecting line between the third curve end point C and the second curve start point E is First direction (X direction in the figure) parallel to. The first curve start point A is the connection point between the middle portion 241 and the first sub-end portion 242a, and the second curve start point E is the connection point between the first sub-end portion 242a and the second sub-end portion 243a.

[0040] Exemplarily, as shown in FIG. 3, the first curve 242a1 end point overlaps with the third curve start point, both being point B. The first curve 242a1 start point A is the connection point between the middle portion 241 and the first sub-end portion 242a. The second curve 243a1 start point E is set as the connection point between the first sub-end portion 242a and the second sub-end portion 243a. The extending direction of the connecting line between the third curve end point C and the second curve start point E is parallel to the second direction (the Y direction in the figure), and divides the first sub-end portion 242a and the second sub-end portion 243a. By doing so, the structures of the first sub-end portion 242a and the second sub-end portion 243a are set more reasonably.

[0041] In the embodiments of the present invention, only the case where the bending directions of the first sub-end portion 242a and the second sub-end portion 243a are different is taken as an example. However, when the bending directions of the first sub-end portion 242a and the second sub-end portion 243a are the same, the third curve end point C overlaps with the second curve start point E, and the edge profiles of the source 23 and / or the drain 25 are formed. Here, the detailed description thereof is omitted.

[0042] As a feasible embodiment, FIG. 6 is a diagram showing the configuration of another semiconductor device according to an embodiment of the present invention. As shown in FIG. 6, preferably, the gate 24 further includes a second end portion 24b. In the second direction (the Y direction in the figure), the first end portion 24a, the intermediate portion 241, and the second end portion 24b are sequentially installed. The second end portion 24b is located in the passive region bb, and the second direction is perpendicular to the first direction (the X direction in the figure). The second end portion 24b includes a third sub-end portion 242b. In the first direction, the extension width of the third sub-end portion 242b is wider than the extension width of the intermediate portion 241.

[0043] Exemplarily, as shown in FIG. 6, in the Y direction in the figure, the gate 24 includes the first end portion 24a, the intermediate portion 241, and the second end portion 24b that are sequentially installed. Note that both the first end portion 24a and the second end portion 24b are located in the passive region bb. The second end portion 24b includes a third sub-end portion 242b. In the X direction in the figure, the extension width of the third sub-end portion 242b is wider than the extension width of the intermediate portion 241. Note that the first end portion 24a may have the same shape as or a different shape from the second end portion 24b, but the embodiments of the present invention are not limited thereto. Further, the third sub-end portion 242b may be curved toward the source 23 side and / or the drain 25 side. Preferably, as shown in FIG. 6, the third sub-end portion 242b is curved toward the source 23 side. By extending the second end portion 24b to the gate end of the passive region bb and adjusting the width of the gate corresponding to both end corners of the source-drain, the shape distortion of the gate corresponding to both end corners of the source-drain due to light diffraction can be corrected, the stability of the gate can be improved, and the influence of the gate deformation on the power and frequency of the semiconductor device can be suppressed. Also, the first end portion 24a and the second end portion 24b are installed at both ends of the gate to increase the contact area between the gate end metal and the substrate, improve the adhesiveness between the gate metal and the substrate, prevent a part of the gate metal from falling off during manufacturing and testing, and reduce the contact resistance of the gate metal. Further, the increased gate end area facilitates the interconnection between the gate metals of the device, improves the sealing efficiency of the device, and further improves the performance stability of the semiconductor device.

[0044] Based on the above embodiments, FIG. 7 is a diagram showing the configuration of another semiconductor device according to an embodiment of the present invention. As shown in FIG. 7, preferably, the second end portion 24b further includes a fourth sub-end portion 243b, and the fourth sub-end portion 243b is located on one side away from the active region aa of the third sub-end portion and is in contact with and connected to the third sub-end portion 242b. In the first direction (the X direction in the figure), the extension width of the fourth sub-end portion 243b is wider than the extension width of the third sub-end portion 242b.

[0045] Exemplarily, as shown in FIG. 7, similar to the first end portion 24a according to the above embodiment, the second end portion 24b includes a third sub-end portion 242b and a fourth sub-end portion 243b. The extension width of the third sub-end portion 242b in the X direction of the figure is wider than the extension width of the intermediate portion 241 in the X direction of the figure, and the extension width of the fourth sub-end portion 243b in the X direction of the figure is wider than the extension width of the third sub-end portion 242b in the X direction of the figure. Note that the first end portion 24a may have the same shape as or a different shape from the second end portion 24b, but the embodiments of the present invention are not limited thereto. The second sub-end portion 243a is further installed to include the third sub-end portion 242b and the fourth sub-end portion 243b. By extending the second end portion 24b to the gate end of the passive region bb and adjusting the width of the gate corresponding to both end corners of the source / drain, the shape distortion of the gate corresponding to both end corners of the source / drain due to light diffraction is corrected, the stability of the gate is improved, and the influence of the gate deformation on the power and frequency of the semiconductor device is suppressed. In addition, the first end portion 24a and the second end portion 24b are installed at both ends of the gate to increase the contact area between the gate end metal and the substrate, improve the adhesion between the gate metal and the substrate, prevent the dropout of a part of the gate metal during manufacturing and testing, and reduce the contact resistance of the gate metal. Furthermore, the increased gate end area facilitates the interconnection between the gate metals of the device, improves the sealing efficiency of the device, and further improves the performance stability of the semiconductor device.

[0046] Based on the above embodiments, combining FIGS. 3, 6 and 7, preferably, in the first direction, the extension width L1 of the first sub-end 242a, the extension width L2 of the second sub-end 243a, the extension width L3 of the third sub-end 242b, the extension width L4 of the fourth sub-end 243b, and the extension width D of the middle part 241 satisfy 1.2×D≦L1≦30×D, 2.4×D≦L2≦60×D, 1.2×D≦L3≦30×D, 2.4×D≦L4≦60×D.

[0047] Exemplarily, it is described by taking as an example that the gate 24 includes a first end 24a and a second end 24b. As shown in FIG. 7, the extension width L1 of the first sub-end 242a extending to the passive region bb satisfies 1.2×D≦L1≦30×D, and the extension width of the third sub-end 242b extending to the passive region bb is set to satisfy 1.2×D≦L3≦30×D. By reasonably setting the extension widths of the first sub-end 242a and the third sub-end 242b extending to the passive region bb, it is ensured that at the first sub-end 242a extending to the passive region bb, the gate 24 corresponding to the two end corner portions of the source-drain is appropriately corrected, and the problem of the decrease in the width of the gate due to light diffraction can be suppressed or completely eliminated. Furthermore, without excessive correction, the problem of the increase in the width of the gate 24 corresponding to the two end corner portions of the source-drain caused by excessive correction is not generated, and the widths of the gates 24 located within the active region aa are made the same or approximately the same.

[0048] Furthermore, the extension width L2 of the second sub-end 243a extending to the passive region bb is wider than L1, satisfies 2.4×D≦L2≦60×D with the extension width D of the middle part, and the extension width L4 of the fourth sub-end 243b extending to the passive region bb is wider than L3, satisfies 2.4×D≦L4≦60×D with the extension width D of the middle part. By doing so, it is ensured that the contact area between the gate and the substrate is relatively large, the adhesiveness between the gate metal and the substrate is improved, the falling off of the gate is prevented, and further, without excessively occupying the area of the substrate, the influence on the integration efficiency of the device is suppressed, excellent adhesiveness between the gate 24 and the substrate is ensured, and further, the stability of the structure and the performance of the semiconductor device is ensured.

[0049] Note that L1 may be equal to 1.2×D, 1.5×D, 2×D, 3×D, 3.5×D, 5×D, 10×D, 15×D, or 30×D, L2 may be equal to 2.4×D, 3×D, 3.5×D, 5×D, 10×D, 15×D, 30×D, or 60×D, and L2 > L1. L3 may be equal to 1.2×D, 1.5×D, 2×D, 3×D, 3.5×D, 5×D, 10×D, 15×D, or 30×D, L4 may be equal to 2.4×D, 3×D, 3.5×D, 5×D, 10×D, 15×D, 30×D, or 60×D, and L4 > L3. In the embodiments of the present invention, specific numerical values are not enumerated, and the specific correspondence between the extension widths of the first end portion 24a and the second end portion 24b extending to the passive region bb is not limited, but as long as the stability of the structure of the gate 24 and the performance stability are satisfied, and the performance stability of the semiconductor device is further ensured.

[0050] Preferably, FIG. 8 is a diagram showing a cross-sectional configuration of a semiconductor device according to an embodiment of the present invention. As shown in FIG. 8, based on the above embodiment, the semiconductor device 20 according to the embodiment of the present invention further includes a field plate structure 26 located on one side of the gate 24 away from the substrate 21, and a plate capacitor is formed by the field plate structure 26 and the gate 24.

[0051] Exemplarily, at least the extension widths of the first end portion and / or the second end portion located in the passive region bb in the second direction (shown in FIG. 7) are wider than the extension width of the intermediate portion in the second direction, so as to increase the overall area of the gate 24. Since a plate capacitor is formed by the gate 24 and the field plate structure 26 located on the gate 24, the gate 24 serves as one capacitor substrate of the plate capacitor, and by increasing the area of the gate 24, the capacitance value of the plate capacitor can be increased, the regulation range of the capacitance of the gate can be increased, and the performance of the semiconductor device can be further optimized.

[0052] Continuing with further reference to that shown in FIG. 8, the semiconductor device 20 according to an embodiment of the present invention may further include a protective layer 7. The protective layer 27 is located on a side away from the substrate 21 of the field plate structure 26, and seals and protects the semiconductor device 20.

[0053] Continuing with further reference to that shown in FIG. 8, the semiconductor device 20 according to an embodiment of the present invention may further include a multilayer semiconductor layer 22. The multilayer semiconductor layer 22 may further include a nucleation layer 221 located on the substrate 10, a buffer layer 222 located on a side away from the substrate 21 of the nucleation layer 221, a channel layer 223 located on a side away from the nucleation layer 221 of the buffer layer 222, and a barrier layer 224 located on a side away from the buffer layer 222 of the channel layer 223. The barrier layer 224 and the channel layer 223 form a heterojunction structure, and 2DEG is formed at the interface of the heterojunction.

[0054] Exemplarily, the materials of the nucleation layer 221 and the buffer layer 222 may be nitrides, specifically, GaN, AlN or other nitrides. The nucleation layer 221 and the buffer layer 222 are compatible with the material of the substrate 10 of the substrate and the epitaxial channel layer 223. The material of the channel layer 223 may be GaN or other semiconductor materials, for example, InAlN. The barrier layer 224 is located above the channel layer 223. The material of the barrier layer 224 may be any semiconductor material that can form a heterojunction structure with the channel layer 223 and includes a gallium-based compound semiconductor material or a nitride semiconductor material.

[0055] The gallium nitride RF device formed by the semiconductor device structure of the present invention improves the power and frequency of the gallium nitride RF device on the premise of maintaining the stability of the performance of the semiconductor device, and is more applicable to the high-frequency 5G communication field.

[0056] In addition, the embodiments of the present invention improve the output power of the semiconductor device from the perspective of the structural design of the semiconductor device. The semiconductor device may include, but is not limited to, a high-power gallium nitride high electron mobility transistor (HEMT) operating in a high-voltage and high-current environment, a transistor with a silicon-on-insulator (SOI) structure on an insulating substrate, a gallium arsenide (GaAs)-based transistor, a metal-oxide-semiconductor field-effect transistor (MOSFET), a metal-insulator-semiconductor field-effect transistor (MISFET), a double heterojunction field-effect transistor (DHFET), a junction field-effect transistor (JFET), a metal-semiconductor field-effect transistor (MESFET), a metal-insulator-semiconductor heterojunction field-effect transistor (MISHFET), or other field-effect transistors.

[0057] According to the same inventive concept, the embodiments of the present invention further provide a manufacturing method of a semiconductor device for manufacturing the semiconductor device according to the above embodiments. FIG. 9 is a flowchart showing the manufacturing method of the semiconductor device according to the embodiments of the present invention. As shown in FIG. 9, the manufacturing method of the semiconductor device according to the embodiments of the present invention includes the following steps. S110: Provide a substrate.

[0058] Exemplarily, the material of the substrate may be Si, SiC, gallium nitride, or sapphire, or may be other materials suitable for the growth of gallium nitride. As the manufacturing method of the substrate, there may be atmospheric pressure chemical vapor deposition method, sub-atmospheric pressure chemical vapor deposition method, metal organic chemical vapor deposition method, reduced pressure chemical vapor deposition method, high density plasma chemical vapor deposition method, ultra-high vacuum chemical vapor deposition method, plasma enhanced chemical vapor deposition method, catalytic chemical vapor deposition method, hybrid physical chemical vapor deposition method, rapid thermal chemical vapor deposition method, vapor phase epitaxy method, pulsed laser deposition method, atomic layer epitaxy method, molecular beam epitaxy method, sputtering method, or evaporation method.

[0059] S120: On one side of the substrate, a source, a gate, and a drain are manufactured. The gate is located between the source and the drain. The gate includes a first end portion and an intermediate portion. The intermediate portion, the source, and the drain are all located in the active region. The first end portion is located in the passive region. The first end portion includes a first sub-end portion and a second sub-end portion. In the first direction, the extension width of the first sub-end portion is wider than the extension width of the intermediate portion, and the extension width of the second sub-end portion is wider than the extension width of the first end portion. The first direction is parallel to the direction from the source to the drain.

[0060] Specifically, as shown in FIGS. 1 and 2, a source 23, a gate 24, and a drain 25 are manufactured and arranged in a first direction (the illustrated X direction). The source 23, the gate 24, and the drain 25 extend in the illustrated Y direction. The gate 24 is positioned between the source 23 and the drain 25. Note that the X direction in the figure is parallel to the direction from the source 23 to the drain 25, and the Y direction is perpendicular to the X direction. The semiconductor device 20 includes an active region aa and a passive region bb surrounding the active region aa. The gate 24 sequentially includes a first end portion 24a and an intermediate portion 241. The intermediate portion 241, the source 23, and the drain 25 are all located in the active region aa. The first end portion 24a is located in the passive region bb. Note that the first end portion 24a includes a first sub-end portion 242a and a second sub-end portion 243a that are both located within the passive region bb. Note that a two-dimensional electron gas, electrons, or holes exist within the active region aa, which is the active operating region of the semiconductor chip. The passive region bb is a region that participates in the operation of the device outside the active region but whose operating state is not affected by an external circuit.

[0061] As shown in FIGS. 1 and 2, by making the extension width of the first sub-end portion 242a located in the passive region bb in the X direction of the figure wider than the extension width of the intermediate portion 241 in the X direction of the figure, the first sub-end portion 242a with a wider extension width contributes to the penetration of the developer from the first sub-end portion 242a to the intermediate portion 241, reducing the difficulty of photolithography development of the gate 24, and it is possible to correct the shape distortion of the gate corresponding to the both-end corner portions of the source and drain due to light diffraction, significantly reducing the difficulty of development, ensuring that the shape of the gate corresponding to the both-end corner portions of the source and drain is the same as the shape of the intermediate portion 241 or reducing the difference in shape between the two, ensuring the stability of the structure and performance of the gate 24, further suppressing the influence of gate deformation on the power and frequency of the semiconductor device, and ensuring the stability of the performance of the semiconductor device.

[0062] Furthermore, as shown in FIGS. 1 and 2, the extension width of the second sub-end portion 243a located within the passive region bb in the X direction of the figure is made wider than the extension width of the first sub-end portion 242a in the X direction of the figure, and further wider than the extension width of the intermediate portion 241 in the X direction of the figure. According to such a structural design, the extension width of the gate end is widened, the contact area between the gate end metal and the substrate is increased, the adhesiveness between the gate metal and the substrate is improved, a part of the gate metal from falling off during manufacturing and testing is prevented, and the contact resistance of the gate metal is reduced. Furthermore, due to the increased gate end area, the interconnection between the gate metals of the device is facilitated, the sealing efficiency of the device is improved, and further the stability of the performance of the semiconductor device is improved.

[0063] Preferably, the semiconductor device according to the embodiment of the present invention may further include a multilayer semiconductor layer. Correspondingly, the manufacturing method further includes a step of manufacturing a multilayer semiconductor layer on one side of the substrate. Specifically, the multilayer semiconductor layer may be a semiconductor material of a III-V group compound. A 2DEG is formed within the multilayer semiconductor layer.

[0064] To summarize the above, in the method for manufacturing a semiconductor device according to an embodiment of the present invention, the first end portion of the gate is extended into the passive region, the first end portion located in the passive region includes a first sub-end portion and a second sub-end portion, and the extension width of the first sub-end portion and the second sub-end portion located in the passive region in the direction from the source to the drain is made wider than the extension width of the intermediate portion in the direction from the source to the drain, and the extension width of the second sub-end portion is made wider than the extension width of the first sub-end portion. By doing so, at least the extension width of the first end portion located in the passive region is wide, and the first end portion of the gate with a wide extension width contributes to the penetration of the developer from the end portion to the intermediate portion, and the shape distortion of the gate corresponding to the both end corner portions of the source and the drain due to light diffraction can be corrected, the difficulty of development can be significantly reduced, and it is ensured that the shape of the gate corresponding to the both end corner portions of the source and the drain is the same as the shape of the intermediate portion 241 or the difference between the two shapes is reduced, the stability of the gate structure and the performance stability are ensured, the influence of the gate deformation on the power and frequency of the semiconductor device can be further suppressed, the performance stability of the semiconductor device is ensured, and it is applicable to fields such as RF / microwaves and power electronics.

[0065] Note that what has been described above is only the preferred embodiments of the present invention and the technical principles applied. As will be understood by those skilled in the art, the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the protection scope of the present invention. Therefore, although the present invention has been described in more detail by the above embodiments, the present invention is not limited to the above embodiments, and can include many other equivalent embodiments without departing from the concept of the present invention, and the protection scope of the present invention is determined by the appended claims.

Claims

1. A semiconductor device, including an active region and a passive region surrounding the active region, a substrate, further including a source, a drain located on one side of the substrate, and a gate located between the source and the drain, the gate including a first end portion and an intermediate portion, the intermediate portion, the source, and the drain are all located in the active region, the first end portion is located in the passive region, the first end portion includes a first sub-end portion and a second sub-end portion, in a first direction, the extension width of the first sub-end portion is wider than the extension width of the intermediate portion, and the extension width of the second sub-end portion is wider than the extension width of the first sub-end portion, the first direction is parallel to the direction from the source to the drain, at least one side edge profile of the first sub-end portion close to the source and / or the drain includes a first curve, and the center of the circle corresponding to the arc where any two points of the first curve are located is located on the same side of the first curve, at least one side edge profile of the second sub-end portion close to the source and / or the drain includes a second curve, and the center of the circle corresponding to the arc where any two points of the second curve are located is located on the same side of the second curve, at least one side edge profile of the first sub-end portion close to the source and / or the drain further includes a third curve smoothly connected to the first curve, and the third curve is located on the side of the first curve close to the passive region, the centers of the circles corresponding to the arcs where any two points of the first curve and any two points of the third curve are located are located on different sides of the edge profile respectively, the first curve includes a first curve start point and a first curve end point, the second curve includes a second curve start point and a second curve end point, and the third curve includes a third curve start point and a third curve end point, the first curve end point overlaps with the third curve start point, the bending directions of the first sub-end portion and the second sub-end portion are different, and the extending direction of the connecting line between the third curve end point and the second curve start point is parallel to the first direction, the first curve start point is the connection point between the intermediate portion and the first sub-end portion, the second curve start point is the connection point between the first sub-end portion and the second sub-end portion, characterized in that it is a semiconductor device.

2. The first sub-end portion curves towards the source side and / or the drain side, The semiconductor device according to claim 1, wherein the second sub-end portion curves towards the source side and / or the drain side. **Claim 3** The distance W1 between the bending end point of the first sub-end portion and the boundary of the active region satisfies 2 μm ≤ W1 ≤ 10 μm, The semiconductor device according to claim 2, wherein the distance W2 between the bending end point of the second sub-end portion and the boundary of the active region satisfies 10 μm ≤ W2 ≤ 50 μm. **Claim 4** The first curve includes a first point and a second point, The second point is located on a side closer to the passive region of the first point, The semiconductor device according to claim 1, wherein the radius of curvature corresponding to the second point is larger than the radius of curvature corresponding to the first point. **Claim 5** The gate further includes a second end portion, In the second direction, the first end portion, the intermediate portion, and the second end portion are sequentially arranged, and the second end portion is located in the passive region, The second direction is perpendicular to the first direction, The second end portion includes a third sub-end portion, The semiconductor device according to claim 1, wherein in the first direction, the extension width of the third sub-end portion is wider than the extension width of the intermediate portion. **Claim 6** The second end portion further includes a fourth sub-end portion, The fourth sub-end portion is located on a side away from the active region of the third sub-end portion and is in contact with and connected to the third sub-end portion, The semiconductor device according to claim 5, wherein in the first direction, the extension width of the fourth sub-end portion is wider than the extension width of the third sub-end portion. **Claim 7** In the first direction, the extension widths L1 of the first sub-end portion, L2 of the second sub-end portion, L3 of the third sub-end portion, L4 of the fourth sub-end portion, and the extension width D of the intermediate portion satisfy 1. 2×D ≤ L1 ≤ 30×D, 2. 4×D ≤ L2 ≤ 60×D, 1. 2×D ≤ L3 ≤ 30×D, 2. 4×D ≤ L4 ≤ 60×D The semiconductor device according to claim 6, characterized by the above. **Claim 8** The semiconductor device according to claim 2, wherein the third curve end point of the second sub-end portion is away from the first curve end point of the first sub-end portion and is located on a side away from the intermediate portion. **Claim 9** The first curve includes a first curve start point and a first curve end point, The second curve includes a second curve start point and a second curve end point, The semiconductor device according to claim 1, wherein the second curve starting point is located on one side away from the first curve starting point and away from the middle portion.

10. A method for manufacturing a semiconductor device for manufacturing the semiconductor device according to any one of claims 1 to 7 includes: providing a substrate; manufacturing a source, a drain, and a gate located between the source and the drain on one side of the substrate. The gate includes a first end portion and a middle portion. The middle portion, the source, and the drain are all located in the active region. The first end portion is located in the passive region. The first end portion includes a first sub-end portion and a second sub-end portion. In a first direction, an extension width of the first sub-end portion is wider than an extension width of the middle portion, and an extension width of the second sub-end portion is wider than the extension width of the first sub-end portion. The first direction is parallel to a direction from the source to the drain, which is a feature of the method for manufacturing a semiconductor device.

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