Epitaxial Structure of Semiconductor Device, Method for Manufacturing the Same, and Semiconductor Device

Abstract

Examples of the present invention disclose an epitaxial structure for a semiconductor device, a manufacturing method thereof, and a semiconductor device, the epitaxial structure of the semiconductor device including a substrate and an epitaxial layer located on one side of the substrate, the epitaxial layer including at least a first sub-epitaxial layer group, the first sub-epitaxial layer group including a first sub-epitaxial layer and a second sub-epitaxial layer that are stacked one on top of the other, the first sub-epitaxial layer including a plurality of first dislocation pits in a surface away from the substrate, sidewalls of the first dislocation pits intersecting both a plane in which the first sub-epitaxial layer is located and a first direction, and the sidewalls of the first dislocation pits being at least covered by the second sub-epitaxial layer. In the embodiment of the present invention, most of the dislocations in the second sub-epitaxial layer originally extending upward along the first direction change their extending direction at the first dislocation pits, and the dislocations are bent. Therefore, most of the dislocations extending upward along the first direction are reduced, the uniformity of the epitaxial layer is improved, the crystal quality and product yield are improved, and the cost is reduced.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductor technology, and in particular, to an epitaxial structure of a semiconductor device, a method for manufacturing the same, and a semiconductor device.

Background Art

[0002] Currently, in the manufacture of GaN-based optoelectronic devices and power devices, SiC, Si, and sapphire are mainly used as substrates. Since there are thermal and lattice mismatches between the GaN epitaxial layer and the substrate, many dislocations occur, and due to the thermal mismatch stress and lattice mismatch strain caused during epitaxial growth, the epitaxial wafer is deformed. As a result, the uniformity of the epitaxial layer decreases, the yield of epitaxial products decreases, and the cost increases.

[0003] The most direct way to improve the GaN crystal quality is to use a GaN substrate of the same kind. However, due to the limitations of the physical properties of GaN itself, the growth of GaN bulk single crystals is very difficult and has not yet been put into practical use. As another method for optimizing the quality of GaN, optimizing process conditions is common. However, in practice, although the GaN crystal quality is improved by optimizing the process, it is known that there is a leakage problem. Therefore, conventional methods for improving crystal quality often lead to other problems and have limitations in the degree of improvement of crystal quality.

Summary of the Invention

Problems to be Solved by the Invention

[0004] Embodiments of the present invention provide an epitaxial structure of a semiconductor device, a method for manufacturing the same, and a semiconductor device to provide an epitaxial structure with good epitaxial uniformity, high product yield, and low cost.

Means for Solving the Problems

[0005] In a first aspect, an embodiment of the present invention is an epitaxial structure of a semiconductor device, a substrate, an epitaxial layer located on one side of the substrate, the epitaxial layer at least includes a first sub-epitaxial layer group, the first sub-epitaxial layer group includes a first sub-epitaxial layer and a second sub-epitaxial layer provided in a stacked manner, the second sub-epitaxial layer is located on the side of the first sub-epitaxial layer far from the substrate, the surface of the first sub-epitaxial layer far from the substrate includes a plurality of first dislocation pits, the side walls of the first dislocation pits intersect both the plane where the first sub-epitaxial layer is located and a first direction, the first direction is parallel to the direction from the first sub-epitaxial layer to the second sub-epitaxial layer, and the second sub-epitaxial layer covers at least the side walls of the first dislocation pits, and provides an epitaxial structure of a semiconductor device.

[0006] Optionally, along the first direction, the depth of the first dislocation pit is h, and the thickness of the first sub-epitaxial layer is H1, where 1 / 20H1 ≦ h ≦ 1 / 2H1.

[0007] Optionally, 5nm ≦ h ≦ 60nm, and H1 > 100nm.

[0008] Optionally, along the first direction, the depth of the first dislocation pit is h, and the thickness of the second sub-epitaxial layer is H2, H2 > h.

[0009] Optionally, one or more of AlN, GaN, AlGaN, and InGaN are included in both the first sub-epitaxial layer and the second sub-epitaxial layer.

[0010] Optionally, on the surface of the first sub-epitaxial layer far from the substrate, a plurality of first dislocation pits formed by corrosion with a corrosive gas are included. Along the first direction, the depth of the first dislocation pits is h, The corrosive gas includes chlorine gas, Both the first sub-epitaxial layer and the second sub-epitaxial layer contain GaN. The ventilation time of the chlorine gas is t1, where 1 / 3h ≤ t1 ≤ h, or The first sub-epitaxial layer and the second sub-epitaxial layer contain AlN and / or AlGaN. The ventilation time of the chlorine gas is t2, where 2 / 3h ≤ t2 ≤ 2h.

[0011] Optionally, the epitaxial layer further includes a second sub-epitaxial layer group located on the side far from the substrate in the first sub-epitaxial layer group, The second sub-epitaxial layer group includes the second sub-epitaxial layer and a third sub-epitaxial layer located on the side far from the substrate in the second sub-epitaxial layer, On the surface of the second sub-epitaxial layer far from the substrate, a plurality of second dislocation pits are included. The side walls of the second dislocation pits intersect both the plane where the second sub-epitaxial layer is located and the first direction, and the side walls of the second dislocation pits are at least covered by the third sub-epitaxial layer.

[0012] In a second aspect, an embodiment of the present invention is a method for fabricating an epitaxial structure of a semiconductor device for fabricating the epitaxial structure described in the first aspect, including Preparing a substrate, Fabricating a first sub-epitaxial layer group on one side of the substrate, Here, fabricating a first sub-epitaxial layer group on one side of the substrate includes Fabricating a first sub-epitaxial layer on one side of the substrate, Forming a plurality of first dislocation pits on the surface of the first sub-epitaxial layer far from the substrate, wherein the side walls thereof intersect both the plane where the first sub-epitaxial layer is located and the first direction, and the first direction is parallel to the direction from the first sub-epitaxial layer toward the second sub-epitaxial layer, Providing a method for fabricating an epitaxial structure of a semiconductor device, including fabricating a second sub-epitaxial layer on the side of the first sub-epitaxial layer far from the substrate, covering at least the side walls of the first dislocation pits.

[0013] Optionally, the manufacturing method further includes: Fabricating a second sub-epitaxial layer group on the side of the first sub-epitaxial layer group far from the substrate, Here, fabricating a second sub-epitaxial layer group on the side of the first sub-epitaxial layer group far from the substrate includes: Forming a plurality of second dislocation pits on the surface of the second sub-epitaxial layer far from the substrate, wherein the side walls of the second dislocation pits intersect both the plane where the second sub-epitaxial layer is located and the first direction, Fabricating a third sub-epitaxial layer on the side of the second sub-epitaxial layer far from the substrate, the third sub-epitaxial layer covering at least the side walls of the second dislocation pits, and the second sub-epitaxial layer group including the second sub-epitaxial layer and the third sub-epitaxial layer.

[0014] In a third aspect, an embodiment of the present invention is a semiconductor device including the epitaxial structure described in the first aspect. The epitaxial structure includes a substrate, a nucleation layer, a first sub-epitaxial layer group, a channel layer, a spacer layer, a barrier layer, and a cap layer sequentially located on one side of the substrate. The semiconductor device further includes: A source and a drain located on the side of the barrier layer far from the substrate, Provided is a semiconductor device further including a gate located on the side of the cap layer far from the substrate and positioned between the source and the drain.

Advantages of the Invention

[0015] In an embodiment of the present invention, an epitaxial layer includes at least a first sub-epitaxial layer group composed of a first sub-epitaxial layer and a second sub-epitaxial layer. On the surface of the first sub-epitaxial layer far from the substrate, a plurality of first dislocation pits are included. The side walls of the first dislocation pits intersect both the plane where the first sub-epitaxial layer is located and the first direction, and the second sub-epitaxial layer is provided so as to at least cover the side walls of the first dislocation pits. Thus, the second sub-epitaxial layer grows along the side walls of the first dislocation pits, and most of the dislocations that originally extended upward along the first direction in the second sub-epitaxial layer change their extension directions at the first dislocation pits and bend. Therefore, most of the dislocations extending upward along the first direction are reduced, the uniformity of the epitaxial layer is enhanced, the crystal quality and product yield are improved, and the cost is reduced.

Brief Description of the Drawings

[0016] To more clearly explain the technical solutions in the embodiments of the present invention or the prior art, the drawings required for explaining the embodiments or the prior art are briefly introduced below. Obviously, the drawings described below are some specific embodiments of the present invention. Those skilled in the art can expand and extend to other structures and drawings according to the basic concepts of the device structures, driving methods, and manufacturing methods disclosed and suggested by various embodiments of the present invention, and they should undoubtedly be included within the scope of the claims of the present invention.

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Embodiments for Carrying Out the Invention

[0017] In order to make the objectives, technical solutions and advantages of the present invention more clear, the following will clearly and completely describe the technical solutions of the present invention through embodiments with reference to the drawings in the embodiments of the present invention. However, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the basic concepts disclosed and suggested by the embodiments of the present invention, other embodiments obtained by those skilled in the art shall all be included within the protection scope of the present invention.

[0018] Since there are thermal and lattice mismatches between the GaN epitaxial layer and the substrate, many dislocations are generated in the epitaxial layer, and most of the dislocations extend upward along the direction from the substrate to the epitaxial layer. As a result, the uniformity of the epitaxial layer decreases, the yield of the epitaxial product decreases, and the cost increases. To solve the above problems, an embodiment of the present invention provides an epitaxial structure of a semiconductor device, including a substrate and an epitaxial layer located on one side of the substrate. The epitaxial layer at least includes a first sub-epitaxial layer group, and the first sub-epitaxial layer group includes a first sub-epitaxial layer and a second sub-epitaxial layer which are stacked. The second sub-epitaxial layer is located on the side of the first sub-epitaxial layer far from the substrate. The surface of the first sub-epitaxial layer far from the substrate includes a plurality of first dislocation pits, and the side walls of the first dislocation pits intersect both the plane where the first sub-epitaxial layer is located and a first direction. The first direction is parallel to the direction from the first sub-epitaxial layer to the second sub-epitaxial layer. The epitaxial layer includes the second sub-epitaxial layer that at least covers the side walls of the first dislocation pits.

[0019] In an embodiment of the present invention, the epitaxial layer at least includes a first sub-epitaxial layer group composed of a first sub-epitaxial layer and a second sub-epitaxial layer. The surface of the first sub-epitaxial layer far from the substrate includes a plurality of first dislocation pits, and the side walls of the first dislocation pits intersect both the plane where the first sub-epitaxial layer is located and a first direction. The second sub-epitaxial layer is provided so as to at least cover the side walls of the first dislocation pits. Thus, the second sub-epitaxial layer grows along the side walls of the first dislocation pits. Most of the dislocations that originally extended upward along the first direction in the second sub-epitaxial layer change their extension directions at the first dislocation pits and bend. Therefore, most of the dislocations extending upward along the first direction are reduced, the uniformity of the epitaxial layer is improved, the crystal quality and the product yield are enhanced, and the cost is reduced.

[0020] The above is the core idea of the present invention. Hereinafter, with reference to the drawings in the embodiments of the present invention, the technical solutions in the embodiments of the present invention will be described in detail.

[0021] Exemplarily, FIG. 1 is a structural schematic diagram of an epitaxial structure of a semiconductor device according to an embodiment of the present invention. As shown in FIG. 1, the epitaxial structure of the semiconductor device according to this embodiment includes a substrate 100 and an epitaxial layer 200 located on one side of the substrate. The epitaxial layer 200 at least includes a first sub-epitaxial layer group 220. The first sub-epitaxial layer group 220 includes a first sub-epitaxial layer 221 and a second sub-epitaxial layer 222 provided in a stacked manner. The second sub-epitaxial layer 222 is located on the side of the first sub-epitaxial layer 221 far from the substrate 100. The surface of the first sub-epitaxial layer 221 far from the substrate 100 includes a plurality of first dislocation pits 201. The side walls of the first dislocation pits 201 intersect both the plane where the first sub-epitaxial layer 221 is located and the first direction Y. The first direction Y is parallel to the direction from the first sub-epitaxial layer 221 to the second sub-epitaxial layer 222. The epitaxial layer 200 further includes that the side walls of the first dislocation pits 201 are at least covered by the second sub-epitaxial layer 222.

[0022] Specifically, referring to FIG. 1, the epitaxial structure of the semiconductor device according to this embodiment includes a substrate 100 and an epitaxial layer 200. Exemplarily, the substrate 100 may be made of one or a combination of gallium nitride, aluminum gallium nitride, indium gallium nitride, aluminum indium gallium nitride, indium phosphide, gallium arsenide, silicon carbide, diamond, sapphire, germanium, silicon, or any other material on which a group III nitride can be grown. The epitaxial layer 200 may include a III-V compound semiconductor material. The epitaxial layer 200 at least includes a first sub-epitaxial layer group 220 composed of a first sub-epitaxial layer 221 and a second sub-epitaxial layer 222 provided in a stacked manner. By means of dry etching, wet etching, or the like, the dislocations on the surface of the first sub-epitaxial layer 221 far from the substrate 100 are etched to form dislocation pits, so that a first sub-epitaxial layer 221 including a plurality of first dislocation pits 201 can be formed. When a direction parallel to the direction from the first sub-epitaxial layer 221 to the second sub-epitaxial layer 222 is defined as a first direction Y, and a direction parallel to the plane where the first sub-epitaxial layer 221 is located is defined as an X direction, the side walls of the first dislocation pits 201 intersect both the X direction and the first direction Y.

[0023] There are many dislocations on the surface of the first sub-epitaxial layer 221 far from the substrate 100. During etching, the positions where the dislocations on the surface of the first sub-epitaxial layer 221 are located are preferentially etched, and the dislocations are etched to form dislocation pits. As shown in FIG. 1, along the first direction Y, the width of the first dislocation pits 201 gradually increases, that is, it forms an inverted triangular shape with a wide upper part and a narrow lower part. It should be noted that in FIG. 1, an example where the first dislocation pits 201 are equilateral triangles is described, but the shape of the first dislocation pits 201 formed by the actual process may be other irregular inverted triangles.

[0024] When the second sub-epitaxial layer 222 is continuously grown on the first sub-epitaxial layer 221 including a plurality of first dislocation pits 201, along the first direction Y, since the first dislocation pits 201 form inverse triangles, the second sub-epitaxial layer 222 will grow along the side walls of the first dislocation pits 201. Most of the dislocations that originally extended upward along the first direction Y in the second sub-epitaxial layer 222 will have their extension directions changed at the first dislocation pits 201 and the dislocations will bend to extend leftward or rightward. The dislocations extending leftward and the dislocations extending rightward will join together to form a similar semi-circular ring, so that the dislocations disappear. As a result, most of the dislocations extending upward along the first direction Y are reduced, the uniformity of the epitaxial layer is enhanced, the crystal quality and product yield are improved, and the cost is reduced.

[0025] It should be noted that the embodiments of the present invention do not limit the formation method of the dislocation pits. A plurality of first dislocation pits are formed on the surface of the first sub-epitaxial layer far from the substrate, and the second sub-epitaxial layer is grown along the side walls of the first dislocation pits to bend the dislocations and change the extension directions of most of the dislocations in the second sub-epitaxial layer. Any formation method of the dislocation pits that can achieve this is included within the protection scope of the present invention.

[0026] Also, the second sub-epitaxial layer 222 needs to cover at least the side walls of the first dislocation pits 201. That is, in order to grow the second sub-epitaxial layer 222 along the side walls of the first dislocation pits 201 and change the extension directions of the dislocations, only the side walls of the first dislocation pits 201 may be covered by the second sub-epitaxial layer 222. Or, referring to FIG. 1, in order to facilitate the growth of subsequent film layers and further improve the crystal quality, the first dislocation pits 201 may be filled by the second sub-epitaxial layer 222 so as to become flat.

[0027] The epitaxial structure of a semiconductor device according to an embodiment of the present invention includes an epitaxial layer that at least includes a first sub-epitaxial layer group composed of a first sub-epitaxial layer and a second sub-epitaxial layer. On the surface of the first sub-epitaxial layer far from the substrate, a plurality of first dislocation pits are included. The side walls of the first dislocation pits intersect both the plane where the first sub-epitaxial layer is located and the first direction, and the second sub-epitaxial layer is provided so that the side walls of the first dislocation pits are at least covered. Thus, the second sub-epitaxial layer grows along the side walls of the first dislocation pits, and most of the dislocations that originally extended upward along the first direction in the second sub-epitaxial layer change their extension directions at the first dislocation pits and bend. Therefore, most of the dislocations extending upward along the first direction are reduced, the uniformity of the epitaxial layer is enhanced, the crystal quality and product yield are improved, and the cost is reduced.

[0028] Optionally, along the first direction Y, the depth of the first dislocation pit 201 is h, and the thickness of the first sub-epitaxial layer 221 is H1, where 1 / 20H1≦h≦1 / 2H1.

[0029] Referring to FIG. 1, in order for the dislocations in the second sub-epitaxial layer 222 to be bent at the first dislocation pit 201 and most of the dislocations extending upward along the first direction Y to be reduced, and the uniformity of the epitaxial layer 200 to be enhanced and the crystal quality to be significantly improved, along the first direction Y, the depth h of the first dislocation pit 201 and the thickness H1 of the first sub-epitaxial layer 221 need to satisfy 1 / 20H1≦h≦1 / 2H1.

[0030] Furthermore, 5nm≦h≦60nm, and H1>100nm.

[0031] In addition to the above embodiments, when the depth h of the first dislocation pit 201 along the first direction Y satisfies 5 nm ≤ h ≤ 60 nm, an epitaxial layer 200 with good crystal quality can be obtained. If the first dislocation pit 201 is too shallow, i.e., h < 5 nm, lateral epitaxial growth is already completed before most dislocations bend, so the dislocation density is not significantly improved. On the other hand, if the first dislocation pit 201 is too deep, i.e., h > 60 nm, it becomes difficult to fill the first dislocation pit 201 flat by subsequent epitaxy, and finally, the surface of the epitaxial layer 200 becomes very poor. Usually, the thicker the epitaxial layer 200, the better the crystal quality. By setting the thickness H1 of the first sub-epitaxial layer 221 along the first direction Y to satisfy H1 > 100 nm, the crystal quality can be further improved.

[0032] Optionally, along the first direction Y, the depth of the first dislocation pit 201 is h, the thickness of the second sub-epitaxial layer 222 is H2, and H2 > h.

[0033] As shown in FIG. 1, along the first direction Y, the depth h of the first dislocation pit 201 and the thickness H2 of the second sub-epitaxial layer 222 satisfy H2 > h. In the embodiment of the present invention, by setting the thickness H2 of the second sub-epitaxial layer 222 to be greater than the depth h of the first dislocation pit 201, when the second sub-epitaxial layer 222 grows, the first dislocation pit 201 is filled to be flat, a relatively flat surface is obtained, the growth of subsequent film layers becomes easy, and the quality of the epitaxial layer 200 can be improved.

[0034] Optionally, one or more of AlN, GaN, AlGaN, and InGaN are included in both the first sub-epitaxial layer 221 and the second sub-epitaxial layer 222.

[0035] In an embodiment of the present invention, the first sub-epitaxial layer 221 and the second sub-epitaxial layer 222 may be set to use the same material to further improve the crystal quality, or the first sub-epitaxial layer 221 and the second sub-epitaxial layer 222 may be set to use different materials. Those skilled in the art can set according to the actual situation, and the embodiments of the present invention are not limited thereto. Exemplarily, the materials of the first sub-epitaxial layer 221 and the second sub-epitaxial layer 222 may be a combination of one or more of AlN, GaN, AlGaN, and InGaN. In other embodiments, other common epitaxial layer materials may also be used.

[0036] Referring to FIG. 1, further, on the surface of the first sub-epitaxial layer 221 far from the substrate 100, a plurality of first dislocation pits 201 formed by corrosion with a corrosive gas are included. Along the first direction Y, the depth of the first dislocation pit 201 is h. Forming dislocation pits using a corrosive gas involves, after the first sub-epitaxial layer 221 has grown and before introducing the corrosive gas, Cavity completely exhausting the hydrogen gas inside and then introducing the corrosive gas after the hydrogen gas has been completely exhausted. The corrosive gas includes chlorine gas. GaN is included in both the first sub-epitaxial layer 221 and the second sub-epitaxial layer 222. The ventilation time of the chlorine gas is t1, where 1 / 3h ≤ t1 ≤ h. Or, AlN and / or AlGaN is included in the first sub-epitaxial layer 221 and the second sub-epitaxial layer 222, and the ventilation time of the chlorine gas is t2, where 2 / 3h ≤ t2 ≤ 2h.

[0037] In an embodiment of the present invention, by means of ventilating the corrosive gas, a plurality of first dislocation pits 201 are formed on the surface of the first sub-epitaxial layer 221 far from the substrate 100. By setting the materials of the first sub-epitaxial layer 221 and the second sub-epitaxial layer 222, the type of the corrosive gas, and controlling the ventilation time of the corrosive gas, the depth h of the first dislocation pit 201 along the first direction Y can be adjusted. Therefore, the dislocations are bent, most of the dislocations extending upward along the first direction Y are reduced, the uniformity of the epitaxial layer 200 is improved, and the crystal quality is improved.

[0038] Exemplarily, in both the first sub-epitaxial layer 221 and the second sub-epitaxial layer 222, when GaN is included and a plurality of first dislocation pits 201 are formed by corrosion on the surface of the first sub-epitaxial layer 221 far from the substrate 100 using chlorine gas as a corrosive gas, the ventilation time t1 of the chlorine gas and the depth h of the first dislocation pits 201 along the first direction Y satisfy 1 / 3h ≦ t1 ≦ h. Here, the unit of t1 is seconds and the unit of h is nanometers. It should be noted that in the relational expression of 1 / 3h ≦ t1 ≦ h, t1 and h are only numerically related and have a dimensionless relationship.

[0039] Continuing to refer to FIG. 1, exemplarily, in both the first sub-epitaxial layer 221 and the second sub-epitaxial layer 222, a combination of either one or both of AlN and AlGaN is included, and when a plurality of first dislocation pits 201 are formed by corrosion on the surface of the first sub-epitaxial layer 221 far from the substrate 100 using chlorine gas as a corrosive gas, the ventilation time t2 of the chlorine gas and the depth h of the first dislocation pits 201 along the first direction Y satisfy 2 / 3h ≦ t2 ≦ 2h. Here, the unit of t2 is seconds and the unit of h is nanometers. In the relational expression of 2 / 3h ≦ t1 ≦ 2h, t2 and h are only numerically related and have a dimensionless relationship. It should be noted that , after the first sub-epitaxial layer has grown and before introducing chlorine gas, it is necessary to completely exhaust H 2 inside the cavity, and introduce chlorine gas only after completely exhausting H 2 .

[0040] It should be noted that the above embodiments only illustrate the numerical relationship between the ventilation time of the corrosive gas and the depth h of the first dislocation pit 201 along the first direction Y by taking the example that the corrosive gas is chlorine gas and the first sub-epitaxial layer 221 and the second sub-epitaxial layer 222 contain GaN, or contain AlN and / or AlGaN. It is not limited. The corrosive gas may be other gases such as hydrogen chloride, etc. The first sub-epitaxial layer 221 and the second sub-epitaxial layer 222 may be other common epitaxial materials. Both the type of the corrosive gas and the materials of the first sub-epitaxial layer 221 and the second sub-epitaxial layer 222 affect the numerical relationship between the ventilation time of the corrosive gas and the depth h of the first dislocation pit 201 along the first direction Y. When the corrosive gas and / or the materials of the epitaxial layer are different, the numerical relationship between the ventilation time of the corrosive gas and the depth h of the first dislocation pit 201 along the first direction Y is also different. Those skilled in the art can determine the specific numerical relationship according to actual experimental statistics and analysis. The embodiments of the present invention do not limit the type of the corrosive gas, the materials of the first sub-epitaxial layer 221 and the second sub-epitaxial layer 222, and the numerical relationship between the ventilation time of the corrosive gas and the depth h of the first dislocation pit 201 along the first direction Y.

[0041] The embodiments of the present invention adopt a method of ventilating a corrosive gas during epitaxial growth, It is only necessary to exhaust the hydrogen gas inside the cavity before introducing the corrosive gas, to form a plurality of first dislocation pits on the surface of the first sub-epitaxial layer far from the substrate by corrosion with the corrosive gas. The whole process is carried out in the system and there is no need to take it out of the system. Therefore, more contaminants and defects are not taken in, the cleanliness of the product is guaranteed, and the process and the growth process are simplified. by the corrosive gas formed by corrosion of the corrosive gas, and the whole process is carried out in the system and there is no need to take it out of the system. Therefore, more contaminants and defects are not taken in, the cleanliness of the product is guaranteed, and the process and the growth process are simplified.

[0042] FIG. 2 is a structural schematic diagram of an epitaxial structure of another semiconductor device according to an embodiment of the present invention. As shown in FIG. 2, optionally, the epitaxial layer 200 may further include a second sub-epitaxial layer group 230 located on the side far from the substrate 100 in the first sub-epitaxial layer group 220. The second sub-epitaxial layer group 230 includes a second sub-epitaxial layer 222 and a third sub-epitaxial layer 223. The third sub-epitaxial layer 223 is located on the side far from the substrate 100 in the second sub-epitaxial layer 222. A plurality of second dislocation pits 202 are included on the surface of the second sub-epitaxial layer 222 on the side far from the substrate 100. The sidewalls of the second dislocation pits 202 intersect both the plane where the second sub-epitaxial layer 222 is located and the first direction Y. The sidewalls of the second dislocation pits 202 are at least covered by the third sub-epitaxial layer 223.

[0043] Exemplarily, referring to FIG. 2, the epitaxial layer 200 may further include a second sub-epitaxial layer group 230, and the second sub-epitaxial layer group 230 includes a second sub-epitaxial layer 222 and a third sub-epitaxial layer 223 which are provided in a stacked manner. During epitaxial growth, by introducing a corrosive gas or the like, the dislocations on the surface of the first sub-epitaxial layer 221 far from the substrate 100 are corroded to form dislocation pits, and a first sub-epitaxial layer 221 including a plurality of first dislocation pits 201 can be formed. When the second sub-epitaxial layer 222 is continuously grown, since the first dislocation pits 201 form an inverted triangle along the first direction Y, the second sub-epitaxial layer 222 will grow along the side walls of the first dislocation pits 201. Most of the dislocations that originally extended upward along the first direction Y in the second sub-epitaxial layer 222 will change their extension directions at the first dislocation pits 201 and bend, and extend leftward or rightward. The dislocations extending leftward and the dislocations extending rightward are joined together to form a similar semi-circular ring, so that the dislocations disappear. As a result, most of the dislocations extending upward along the first direction Y are reduced. After the first dislocation pits 201 are filled by the second sub-epitaxial layer 222 and a relatively flat surface is formed, by introducing a corrosive gas or the like, the dislocations on the surface of the second sub-epitaxial layer 222 far from the substrate 100 are corroded to form dislocation pits, and a second sub-epitaxial layer 222 including a plurality of second dislocation pits 202 can be formed. Then, the third sub-epitaxial layer 223 can be continuously grown. Since the second dislocation pits 202 form an inverted triangle along the first direction Y, the third sub-epitaxial layer 223 will similarly grow along the side walls of the second dislocation pits 202. Most of the dislocations that originally extended upward along the first direction Y in the third sub-epitaxial layer 223 will change their extension directions at the second dislocation pits 202 and bend, and extend to both the left and right sides. Therefore, the dislocations disappear. As a result, most of the dislocations extending upward along the first direction Y are further reduced.Two blocking barriers composed of the first sub-epitaxial layer group 220 and the second sub-epitaxial layer group 230 form a double block, significantly reducing a large number of dislocations extending upward along the first direction Y. As a result, the crystal quality and product yield are significantly improved, and the cost is reduced.

[0044] Furthermore, the side wall of the second dislocation pit 202 is at least covered by the third sub-epitaxial layer 223. That is, the third sub-epitaxial layer 223 is grown along the side wall of the second dislocation pit 202. To change the extending direction of the dislocations, only the side wall of the second dislocation pit 202 is covered by the third sub-epitaxial layer 223, or, referring to FIG. 2, to facilitate the growth of subsequent film layers and further improve the crystal quality, the second dislocation pit 202 is filled by the third sub-epitaxial layer 223 so as to be flattened.

[0045] It should be noted that this embodiment only describes an example in which the epitaxial layer 200 includes the first sub-epitaxial layer group 220 and the second sub-epitaxial layer group 230, and is not limiting. Along the first direction Y, the epitaxial layer 200 may further include a third sub-epitaxial layer group, a fourth sub-epitaxial layer group, a fifth sub-epitaxial layer group, etc. provided in sequence. Taking the third sub-epitaxial layer group as an example, the third sub-epitaxial layer group is located on the side far from the substrate 100 in the second sub-epitaxial layer group 230. The third sub-epitaxial layer group includes a third sub-epitaxial layer 223 and a fourth sub-epitaxial layer provided in a stacked manner. On the surface of the third sub-epitaxial layer 223 on the side far from the substrate 100, a plurality of third dislocation pits are included. The side walls of the third dislocation pits intersect both the plane where the third sub-epitaxial layer is located and the first direction. The side walls of the third dislocation pits are at least covered by the fourth sub-epitaxial layer. In this way, along the first direction Y, a multiple barrier is formed. Through the blocking by each barrier, a large number of dislocations extending upward along the first direction Y can be significantly reduced. As a result, the crystal quality and product yield are significantly improved, and the cost is reduced. Also, along the first direction Y, for any dislocation pit in the epitaxial layer 200, its depth h and the thickness H1 of the film layer where the dislocation pit is located satisfy 1 / 20H1 ≦ h ≦ 1 / 2H1, and preferably 5nm ≦ h ≦ 60nm, H1 > 100nm. For the thickness H2 of the film layer on the side far from the substrate 100 in the film layer where the dislocation pit is located, all satisfy H2 > h. And the shape of the dislocation pit formed by corrosion, the material of the film layer, and the numerical relationship between the corrosive gas to be ventilated and the depth of the dislocation pit described in any embodiment of the present invention are all applicable to this embodiment. It should be noted that in the process of forming dislocation pits using a corrosive gas in this application, before introducing the corrosive gas each time, it is necessary to completely exhaust the hydrogen gas inside the cavity.

[0046] FIG. 3 is a structural schematic diagram of an epitaxial structure of still another semiconductor device according to an embodiment of the present invention. As shown in FIG. 3, in addition to the above embodiment, the epitaxial layer 200 includes a nucleation layer 210 located on the side closer to the substrate 100 in the first sub-epitaxial layer 221, a channel layer 240 located on the side farther from the substrate 100 in the second sub-epitaxial layer 222, a spacer layer 250 located on the side farther from the substrate 100 in the channel layer 240, and a barrier layer 260 located on the side farther from the substrate 100 in the spacer layer 250, where the barrier layer 260 forms a heterojunction structure with the channel layer 240, and further includes a cap layer 270 located on the side farther from the substrate 100 in the barrier layer 260.

[0047] Referring to FIG. 3, along the first direction Y, the epitaxial layer 200 includes a nucleation layer 210, a first sub-epitaxial layer 221, a second sub-epitaxial layer 222, a channel layer 240, a spacer layer 250, a barrier layer 260, and a cap layer 270 that are sequentially stacked and provided.

[0048] The nucleation layer 210 affects parameters such as the crystal quality, surface morphology, and electrical characteristics of other film layers located above the nucleation layer 210 in the epitaxial layer 200. The nucleation layer 210 mainly functions to align the material of the substrate 100 and the semiconductor material layer in the heterojunction structure of the epitaxial layer 200.

[0049] On the surface of the first sub-epitaxial layer 221 that is far from the substrate 100, a plurality of first dislocation pits 201 are included. The second sub-epitaxial layer 222 grows along the sidewalls of the first dislocation pits 201. Most of the dislocations that originally extended upward along the first direction Y in the second sub-epitaxial layer 222 change their extension directions at the first dislocation pits 201 and bend, so that most of the dislocations that extend upward along the first direction Y are reduced. As a result, the uniformity of the epitaxial layer is enhanced, the crystal quality and product yield are improved, and the cost is reduced. Here, each of the first sub-epitaxial layer 221 and the second sub-epitaxial layer 222 may be a combination of one or more of common epitaxial layers such as AlN, GaN, AlGaN, and InGaN.

[0050] The channel layer 240 may be a GaN channel layer. The channel layer 240 is for improving the interface quality in the two-dimensional electron gas channel to obtain better two-dimensional electron gas concentration and mobility.

[0051] The spacer layer 250 may be an AlN spacer layer. The spacer layer 250 can increase the barrier height, enhance the confinement of the two-dimensional electron gas, reduce alloy scattering, and improve the mobility.

[0052] The barrier layer 260 may be an AlGaN barrier layer. The barrier layer 260 forms a heterojunction structure with the channel layer 240, enabling the channel layer 240 to provide a channel for the movement of the two-dimensional electron gas.

[0053] The main role of the cap layer 270 is to reduce surface levels, reduce surface leakage of subsequent semiconductor devices, suppress current collapse, and improve the performance and reliability of the epitaxial structure and semiconductor devices. Optionally, the material of the cap layer 270 is a group III nitride, preferably p-type doped gallium nitride (P-GaN). The P-GaN structure can effectively reduce the barrier height of the AlGaN layer.

[0054] Based on the same inventive concept, embodiments of the present invention further provide a method for fabricating an epitaxial structure of a semiconductor device capable of fabricating the epitaxial structure of a semiconductor device according to any embodiment of the present invention. FIG. 4 is a flowchart of a method for fabricating an epitaxial structure of a semiconductor device according to an embodiment of the present invention, and FIG. 5 is a flowchart of fabricating a first sub-epitaxial layer group on one side of a substrate in an embodiment of the present invention. As shown in FIGS. 4 and 5, the fabrication method includes the following steps S100 to S200.

[0055] S100 is to prepare a substrate.

[0056] The fabrication method and material of the substrate are not limited. Exemplarily, the fabrication method of the substrate may be atmospheric pressure chemical vapor deposition, reduced pressure chemical vapor deposition, metal organic chemical vapor deposition, low pressure chemical vapor deposition, high density plasma chemical vapor deposition, ultra-high vacuum chemical vapor deposition, plasma enhanced chemical vapor deposition, catalytic chemical vapor deposition, hybrid physical chemical vapor deposition, rapid thermal chemical vapor deposition, vapor phase epitaxy, pulsed laser deposition, ion layer epitaxy, molecular beam epitaxy, sputtering or evaporation. The material of the substrate may be one or a combination of gallium nitride, aluminum gallium nitride, indium gallium nitride, aluminum indium gallium nitride, indium phosphide, gallium arsenide, silicon carbide, diamond, sapphire, germanium, silicon, or any other material capable of growing group III nitrides. S200 is to fabricate a first sub-epitaxial layer group on one side of the substrate.

[0057] Here, fabricating a first sub-epitaxial layer group on one side of the substrate includes the following steps S210 to S230. S210 is to fabricate a first sub-epitaxial layer on one side of the substrate. S220 forms a plurality of first dislocation pits on the surface of the first sub-epitaxial layer on the side far from the substrate, where the side walls of the pits intersect both the plane where the first sub-epitaxial layer is located and the first direction, and the first direction is parallel to the direction from the first sub-epitaxial layer to the second sub-epitaxial layer. During epitaxial growth, in-situ corrosion can be performed by methods such as introducing a corrosive gas such as chlorine gas into the MOCVD (Metal-Organic Chemical Vapor Deposition) system. Usually, due to corrosion, dislocations in the epitaxy are corroded to form dislocation pits, so a plurality of first dislocation pits are formed on the surface of the first sub-epitaxial layer on the side far from the substrate. After the first sub-epitaxial layer has grown and before introducing the corrosive gas, completely exhaust the hydrogen gas inside the cavity and then introduce the corrosive gas after the hydrogen gas has been completely exhausted. S230 fabricates a second sub-epitaxial layer that at least covers the side walls of the first dislocation pits on the side of the first sub-epitaxial layer far from the substrate.

[0058] During the next epitaxial growth, the second sub-epitaxial layer begins to grow along the side walls of the dislocation pits, lateral epitaxy occurs, and since dislocations bend during lateral epitaxy, most of the dislocations extending upward along the first direction are reduced, playing a role in improving the crystal quality.

[0059] The method for fabricating an epitaxial structure of a semiconductor device according to an embodiment of the present invention is such that the epitaxial layer includes at least a first sub-epitaxial layer group composed of a first sub-epitaxial layer and a second sub-epitaxial layer. On the surface of the first sub-epitaxial layer far from the substrate, a plurality of first dislocation pits are included. The side walls of the first dislocation pits intersect both the plane where the first sub-epitaxial layer is located and the first direction, and the second sub-epitaxial layer is provided so as to at least cover the side walls of the first dislocation pits. Thus, the second sub-epitaxial layer grows along the side walls of the first dislocation pits, and most of the dislocations that originally extended upward along the first direction in the second sub-epitaxial layer change their extension directions at the first dislocation pits and bend. Therefore, most of the dislocations extending upward along the first direction are reduced, the uniformity of the epitaxial layer is enhanced, the crystal quality and product yield are improved, and the cost is reduced.

[0060] FIG. 6 is a flowchart of a method for fabricating an epitaxial structure of another semiconductor device according to an embodiment of the present invention, and FIG. 7 is a flowchart of fabricating a second sub-epitaxial layer group on the side far from the substrate in the first sub-epitaxial layer group in the embodiment of the present invention. Referring to FIGS. 6 and 7, optionally, the fabrication method further includes step S300.

[0061] S300 is to fabricate a second sub-epitaxial layer group on the side far from the substrate in the first sub-epitaxial layer group.

[0062] Here, fabricating the second sub-epitaxial layer group on the side far from the substrate in the first sub-epitaxial layer group includes the following steps S310 to S320. S310 is to form a plurality of second dislocation pits on the surface of the second sub-epitaxial layer far from the substrate, and the side walls of the second dislocation pits intersect both the plane where the second sub-epitaxial layer is located and the first direction. After the first dislocation pit is filled by the second sub-epitaxial layer and a relatively flat surface is formed, in-situ corrosion is performed again by introducing a corrosive gas again, and the dislocations on the surface of the second sub-epitaxial layer far from the substrate are etched to form dislocation pits, thereby forming a second sub-epitaxial layer including a plurality of second dislocation pits. Thereafter, it is possible to continuously grow a third sub-epitaxial layer. After the second sub-epitaxial layer has grown and before introducing the corrosive gas, completely exhaust the hydrogen gas inside the cavity and then introduce the corrosive gas after the hydrogen gas has been completely exhausted. S320 is a third sub-epitaxial layer that at least covers the sidewall of the second dislocation pit on the side of the second sub-epitaxial layer far from the substrate. In the second sub-epitaxial layer group, a third sub-epitaxial layer including the second sub-epitaxial layer and the third sub-epitaxial layer is fabricated.

[0063] Since the second dislocation pits form an inverted triangle along the first direction, the third sub-epitaxial layer starts to grow along the sidewall of the second dislocation pit. Most of the dislocations that originally extended upward along the first direction in the third sub-epitaxial layer change their extending direction and bend at the second dislocation pit, and extend leftward or rightward. As a result, the dislocations disappear, and as a result, a large number of dislocations extending upward along the first direction are further reduced.

[0064] This embodiment has described an example of two in-situ corrosions. However, the corrosion of the epitaxial layer may be performed one or more times. For example, after etching the first sub-epitaxial layer, the second sub-epitaxial layer is grown. Then, the surface of one side of the second sub-epitaxial layer is etched. Next, the third sub-epitaxial layer is grown. After etching the surface of one side of the third sub-epitaxial layer, the fourth sub-epitaxial layer is grown. Repeating one or more times in this way, multiple blockages are formed, and a large number of dislocations extending upward along the first direction are significantly reduced, and the crystal quality and product yield are significantly improved.

[0065] In this embodiment, the epitaxial layer includes a first sub-epitaxial layer, a second sub-epitaxial layer, and a third sub-epitaxial layer that are stacked. On the surface of the first sub-epitaxial layer far from the substrate, a plurality of first dislocation pits are included. The second sub-epitaxial layer grows along the sidewalls of the first dislocation pits. On the surface of the second sub-epitaxial layer far from the substrate, a plurality of second dislocation pits are included. The third sub-epitaxial layer grows along the sidewalls of the second dislocation pits. Thereby, the direction of the dislocations that extended upward along the first direction in the epitaxial layer is changed, the dislocations are bent, and two blocking barriers are formed by the first sub-epitaxial layer group and the second sub-epitaxial layer group, a double blocking is formed, and a large number of dislocations extending upward along the first direction can be significantly reduced. As a result, the crystal quality and product yield are significantly improved, and the cost is reduced.

[0066] FIG. 8 is a flowchart of a method for fabricating an epitaxial structure of still another semiconductor device according to an embodiment of the present invention. Referring to FIG. 8, in addition to the above embodiment, the fabrication method may further include the following steps S110 to S700. S110 is to fabricate a nucleation layer on one side of the substrate. S200 is to fabricate a first sub-epitaxial layer group on the side of the nucleation layer far from the substrate. S300 is to fabricate a second sub-epitaxial layer group on the side of the first sub-epitaxial layer group far from the substrate. S400 is to fabricate a channel layer on the side of the second sub-epitaxial layer group far from the substrate. S500 is to fabricate a spacer layer on the side of the channel layer far from the substrate. S600 is to fabricate a barrier layer that forms a hetero-junction structure with the channel layer on the side of the spacer layer far from the substrate. S700 is to fabricate a cap layer on the side of the barrier layer far from the substrate.

[0067] According to an embodiment of the present invention, a method for fabricating an epitaxial structure of a semiconductor device aligns the material of a substrate and a semiconductor material layer in a hetero-junction structure of an epitaxial layer by a nucleation layer. By a first sub-epitaxial layer group and a second sub-epitaxial layer group, the extending direction of dislocations in epitaxy is changed, the dislocations are bent, a large number of dislocations extending upward along a first direction are reduced, the crystal quality and product yield are improved. By a channel layer, the interface quality in a two-dimensional electron gas channel is improved, and better two-dimensional electron gas concentration and mobility are obtained. By a spacer layer, the barrier is heightened, the confinement of the two-dimensional electron gas is enhanced, alloy scattering is reduced, and the mobility is improved. By a barrier layer, a hetero-junction structure is formed together with the channel layer, a channel for the movement of the two-dimensional electron gas is formed. By a cap layer, surface levels are reduced, surface leakage of subsequent semiconductor devices is reduced, and current collapse is suppressed. As a result, the performance and reliability of the epitaxial structure and the semiconductor device are improved.

[0068] Based on the same inventive concept, an embodiment of the present invention further provides a semiconductor device including an epitaxial structure of a semiconductor device according to any embodiment of the present invention. FIG. 9 is a schematic structural diagram of a semiconductor device according to an embodiment of the present invention. As shown in FIG. 9, the epitaxial structure of the semiconductor device includes a substrate 100, a nucleation layer 210, a first sub-epitaxial layer group 220, a channel layer 240, a spacer layer 250, a barrier layer 260, and a cap layer 270 that are sequentially located on one side of the substrate 100. The semiconductor device further includes a source 300 and a drain 400 located on the side of the barrier layer 260 far from the substrate 100, and a gate 500 located on the side of the cap layer 270 far from the substrate 100, where the gate 500 is located between the source 300 and the drain 400.

[0069] Exemplarily, the source 300 and the drain 400 are located on the side far from the substrate 100 in the barrier layer 260, and the source 300 and the drain 400 respectively form an ohmic contact with the barrier layer 260. The gate 500 is located between the source 300 and the drain 400 and on the side far from the substrate 100 in the cap layer 270, and the gate 500 forms a Schottky contact with the cap layer 270.

[0070] The semiconductor device according to an embodiment of the present invention includes, but is not limited to, a high-power gallium nitride high electron mobility transistor (abbreviated as HEMT) that operates in a high-voltage and high-current environment, a transistor having a silicon-on-insulator (SOI) structure on an insulating substrate, a gallium arsenide (GaAs)-based transistor, and a metal-oxide-semiconductor field-effect transistor (abbreviated as MOSFET), a metal-insulator-semiconductor field-effect transistor (abbreviated as MISFET), a double heterojunction field-effect transistor (abbreviated as DHFET), a junction field-effect transistor (abbreviated as JFET), a metal-semiconductor field-effect transistor (abbreviated as MESFET), a metal-insulator-semiconductor heterojunction field-effect transistor (abbreviated as MISHFET), or other field-effect transistors.

[0071] The semiconductor device according to an embodiment of the present invention uses a first group of sub-epitaxial layers to change the extending direction of dislocations in epitaxy, bend the dislocations, and reduce a large number of dislocations that extend upward along a first direction, improving the crystal quality and product yield. The nucleation layer aligns the material of the substrate and the semiconductor material layer in the hetero-junction structure of the epitaxial layer. The channel layer improves the interface quality in the two-dimensional electron gas channel, obtaining better two-dimensional electron gas concentration and mobility. The spacer layer raises the barrier, enhances the confinement of the two-dimensional electron gas, reduces alloy scattering, and improves the mobility. The barrier layer forms a hetero-junction structure together with the channel layer to form a channel for the movement of the two-dimensional electron gas. The cap layer reduces surface levels, reduces surface leakage of subsequent semiconductor devices, and suppresses current collapse. As a result, the performance and reliability of the epitaxial structure and the semiconductor device are improved.

[0072] It should be noted that what is described above is only a preferred embodiment of the present invention and the technical principles applied. As will be understood by those skilled in the art, the present invention is not limited to the specific embodiments described herein. For those skilled in the art, various obvious changes, readjustments, mutual combinations, and substitutions can be made without departing from the protection scope of the present invention. Therefore, although the present invention has been described in relatively detail by the above embodiments, the present invention is not limited to the above embodiments, and can further include more other equivalent embodiments without departing from the concept of the present invention. The scope of the present invention is defined by the appended claims.

Claims

1. An epitaxial structure of a semiconductor device, comprising: a substrate; an epitaxial layer located on one side of the substrate, wherein the epitaxial layer at least includes a first sub-epitaxial layer group; the first sub-epitaxial layer group includes a first sub-epitaxial layer with a stacked thickness of H1 and a second sub-epitaxial layer with a thickness of H2; the second sub-epitaxial layer is located on the side of the first sub-epitaxial layer far from the substrate, and the surface of the first sub-epitaxial layer on the side far from the substrate includes a plurality of first dislocation pits; taking the depth of the first dislocation pit as h, the side wall thereof intersects both the plane where the first sub-epitaxial layer is located and a first direction, and the first direction is parallel to the direction from the first sub-epitaxial layer to the second sub-epitaxial layer; the depth h, the thicknesses H1 and H2 satisfy: 5 nm ≤ h ≤ 60 nm, H1 > 100 nm, H2 > h, 1 / 20 H1 ≤ h ≤ 1 / 2 H1 ; the second sub-epitaxial layer at least covers the side wall of the first dislocation pit and bends the dislocation through the first dislocation pit; An epitaxial structure of a semiconductor device, characterized by the above.

2. The epitaxial structure according to claim 1, wherein at least one of the first sub-epitaxial layer and the second sub-epitaxial layer includes one or more of AlN, GaN, AlGaN, and InGaN.

3. The surface of the first sub-epitaxial layer on the side far from the substrate includes a plurality of first dislocation pits formed by corrosion with a corrosive gas. Along the first direction, the depth of the first dislocation pit is h. The corrosive gas includes chlorine gas. Both the first sub-epitaxial layer and the second sub-epitaxial layer include GaN, and the ventilation time of the chlorine gas is t1, where 1 / 3 h ≤ t1 ≤ h, or the first sub-epitaxial layer and the second sub-epitaxial layer include AlN and / or AlGaN, and the ventilation time of the chlorine gas is t2, where 2 / 3 h ≤ t2 ≤ 2 h. The epitaxial structure according to claim 2, characterized by the above.

4. The epitaxial layer further includes a second sub-epitaxial layer group located on the side farther from the substrate in the first sub-epitaxial layer group. The second sub-epitaxial layer group includes the second sub-epitaxial layer and a third sub-epitaxial layer located on the side farther from the substrate in the second sub-epitaxial layer. The surface of the second sub-epitaxial layer on the side farther from the substrate includes a plurality of second dislocation pits, and the side walls of the second dislocation pits intersect both the plane where the second sub-epitaxial layer is located and the first direction. The epitaxial structure according to claim 1, characterized in that the side walls of the second dislocation pits are at least covered by the third sub-epitaxial layer.

5. A method for manufacturing an epitaxial structure of a semiconductor device for manufacturing the epitaxial structure according to any one of claims 1 to 4, comprising: Preparing a substrate; Forming a first sub-epitaxial layer group on one side of the substrate, wherein forming a first sub-epitaxial layer group on one side of the substrate includes: Forming a first sub-epitaxial layer on one side of the substrate; Forming a plurality of first dislocation pits on the surface of the first sub-epitaxial layer on the side farther from the substrate, wherein the side walls of the first dislocation pits intersect both the plane where the first sub-epitaxial layer is located and the first direction, and the first direction is parallel to the direction from the first sub-epitaxial layer to the second sub-epitaxial layer; Forming a second sub-epitaxial layer on the side farther from the substrate in the first sub-epitaxial layer to at least cover the side walls of the first dislocation pits. A method for manufacturing an epitaxial structure of a semiconductor device, characterized by the above.

6. The manufacturing method further includes: Forming a second sub-epitaxial layer group on the side farther from the substrate in the first sub-epitaxial layer group, wherein forming a second sub-epitaxial layer group on the side farther from the substrate in the first sub-epitaxial layer group includes: Forming a plurality of second dislocation pits on the surface of the second sub-epitaxial layer on the side farther from the substrate, wherein the side walls of the second dislocation pits intersect both the plane where the second sub-epitaxial layer is located and the first direction. A third sub-epitaxial layer that covers at least the sidewall of the second dislocation pit on the side far from the substrate in the second sub-epitaxial layer, and producing a third sub-epitaxial layer including the second sub-epitaxial layer and the third sub-epitaxial layer in the second sub-epitaxial layer group, the manufacturing method according to claim 5, characterized in that it includes the above.

7. A semiconductor device, including the epitaxial structure according to any one of claims 1 to 4, wherein the epitaxial structure includes a substrate, a nucleation layer, a first sub-epitaxial layer group, a channel layer, a spacer layer, a barrier layer, and a cap layer that are sequentially located on one side of the substrate. The semiconductor device is a source and a drain located on the side far from the substrate in the barrier layer, and a gate located on the side far from the substrate in the cap layer, the gate being located between the source and the drain. A semiconductor device characterized by the above.

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