Semiconductor element

Abstract

To provide a semiconductor element capable of selecting an appropriate resistance value without increasing the number of series.SOLUTION: A semiconductor element includes: a first resistance layer; a second resistance layer spaced from the first resistance layer and having a resistance value different from that of the first resistance layer; a first external connection electrode electrically connected to one end side of the first resistance layer; a second external connection electrode provided apart from the first external connection electrode and electrically connected to one end side of the second resistance layer; and a protection film for covering the first and second external connection electrodes and having a first opening and a second opening that expose parts of top surfaces of the first and the second external connection electrodes, respectively. Planar patterns of the first and the second openings have different shapes from each other.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a semiconductor device used for a gate resistor element of a switching element or the like.

Background Art

[0002] In a semiconductor integrated circuit (IC) or the like, a semiconductor device (resistor device) provided with a resistor layer having a polycrystalline silicon (polysilicon) thin film is known. In this semiconductor device, two electrodes are connected to both ends of the resistor layer on the upper surface side of the resistor layer, and bonding wires are respectively joined to the two electrodes. For this reason, the chip size becomes large and two bonding wires are required.

[0003] Therefore, Patent Documents 1 and 2 disclose a vertical semiconductor device in which one end of the resistor layer is connected to one electrode on the upper surface side of the resistor layer, and the other end of the resistor layer is ohmically connected to the semiconductor substrate via a relay wiring, and current flows in the vertical direction. By using a vertical semiconductor device, the chip size can be reduced compared to a horizontal semiconductor device, and the number of bonding wires connected to the electrodes can be reduced.

[0004] The semiconductor devices described in Patent Documents 1 and 2 can be used, for example, as gate resistor elements of insulated gate bipolar transistors (IGBTs) in semiconductor modules. When two IGBT chips are arranged, as the semiconductor devices described in Patent Documents 1 and 2, a structure in which two resistor layers are provided on one chip corresponding to the two IGBT chips can be adopted. In this case, by arranging two resistor layers having the same resistance value in line symmetry, 180° chip rotation during assembly can be allowed.

[0005] Further, Patent Document 3 discloses a semiconductor integrated circuit device that converts a digital signal into an analog signal or an analog signal into a digital signal by a resistance division method, including 2n - 2 first resistance means of the same resistance value connected in series, a first precision trimming means connected to one end of the serially connected first resistance means to improve trimming accuracy, a second precision trimming means connected to the other end of the serially connected first resistance means to improve trimming accuracy, and a selection switch connected in parallel to each connection part of the first resistance means and the first and second precision trimming means, thereby providing a resistance division circuit. The resistance division circuit is provided with a selection switch connected in parallel to each connection part of the first resistance means and the first and second precision trimming means.

Prior Art Documents

Patent Documents

[0006]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0007] The resistance values of the semiconductor elements described in Patent Documents 1 and 2 need to be designed to appropriate values for each semiconductor module on which the semiconductor elements are mounted. In some cases, in order to fully exhibit the performance of the IGBT chip, it is necessary to finely set the resistance values of the semiconductor elements described in Patent Documents 1 and 2, and there is a problem that the number of series increases.

[0008] In view of the above problems, an object of the present invention is to provide a semiconductor element capable of selecting an appropriate resistance value without increasing the number of series.

Means for Solving the Problems

[0009] One aspect of the present invention is a semiconductor element comprising: (a) a first resistance layer; (b) a second resistance layer provided separately from the first resistance layer and having a resistance value different from that of the first resistance layer; (c) a first external connection electrode electrically connected to one end side of the first resistance layer; (d) a second external connection electrode provided separately from the first external connection electrode and electrically connected to one end side of the second resistance layer; and (e) a protective film covering the first and second external connection electrodes and having first and second openings that partially expose the upper surfaces of the first and second external connection electrodes, wherein the planar patterns of the first and second openings have different shapes from each other.

Advantages of the Invention

[0010] According to the present invention, it is possible to provide a semiconductor element capable of selecting an appropriate resistance value without increasing the number of series.

Brief Description of the Drawings

[0011]

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Embodiments for Carrying Out the Invention

[0012] Hereinafter, each embodiment of the present invention will be described with reference to the drawings. In the description of the drawings, the same or similar parts are denoted by the same or similar reference numerals, and redundant explanations are omitted. However, the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thicknesses of the respective layers, etc. may be different from the actual ones. Also, there are portions where the dimensional relationships and ratios are different among the drawings. Further, each of the embodiments shown below is an example of an apparatus and a method for embodying the technical idea of the present invention, and the technical idea of the present invention does not specify the material, shape, structure, arrangement, etc. of the constituent parts as follows.

[0013] Also, the definitions of the directions such as up and down in the following description are merely selections for convenience of explanation and do not limit the technical idea of the present invention. For example, if the object is rotated 90° and observed, up and down are read as left and right, and if it is rotated 180° and observed, up and down are read in reverse. Similarly, the relationship between "front" and "back" is also defined with reversed terms when rotated 180°.

[0014] (First Embodiment) <Semiconductor Device> As shown in FIG. 1, the semiconductor element according to the first embodiment of the present invention is a resistance element (resistance chip) having a rectangular planar pattern with the direction in which a pair of first external connection electrodes 5a and second external connection electrodes 5b and relay wiring 5c are arranged (the left - right direction in FIG. 1) as the longitudinal direction. The chip size of the semiconductor element according to the first embodiment is, for example, about 3.0 mm × 2.5 mm. The pair of first external connection electrodes 5a and second external connection electrodes 5b and the relay wiring 5c are covered with a protective film (passivation film) 7. Therefore, in FIG. 1, the pair of first external connection electrodes 5a and second external connection electrodes 5b and the relay wiring 5c below the protective film 7 are schematically shown by broken lines.

[0015] The first external connection electrode 5a and the second external connection electrode 5b have substantially the same shape as each other. The first external connection electrode 5a and the second external connection electrode 5b are provided in parallel with each other with a space therebetween. The first external connection electrode 5a and the second external connection electrode 5b have a rectangular planar pattern with the longitudinal direction in the up - down direction in FIG. 1. For example, the length of the first external connection electrode 5a and the second external connection electrode 5b is about 2.1 mm, the width is about 1.0 mm, and the interval is about 0.5 mm or more.

[0016] The relay wiring 5c is provided between the first external connection electrode 5a and the second external connection electrode 5b. The relay wiring 5c also has a rectangular planar pattern with the longitudinal direction in the up - down direction in FIG. 1. The relay wiring 5c is provided on the center line CL passing through the center point CP of the chip.

[0017] The first external connection electrode 5a, the second external connection electrode 5b, and the relay wiring 5c are line - symmetric with respect to the center line CL passing through the center point CP of the chip on the planar pattern, and are rotation - symmetric about the center point CP of the chip twice. Note that the first external connection electrode 5a, the second external connection electrode 5b, and the relay wiring 5c do not necessarily have to be line - symmetric with respect to the center line CL passing through the center point CP of the chip on the planar pattern. Also, the first external connection electrode 5a, the second external connection electrode 5b, and the relay wiring 5c do not necessarily have to be rotation - symmetric about the center point CP of the chip twice on the planar pattern.

[0018] The protective film 7 is provided with a first opening 7a that exposes a part of the upper surface of the first external connection electrode 5a and a second opening 7b that exposes a part of the upper surface of the second external connection electrode 5b. The first opening 7a and the second opening 7b are provided in parallel with each other at a distance. The first opening 7a and the second opening 7b have different shapes and sizes.

[0019] The first opening 7a shown on the left side of FIG. 1 has a rectangular planar pattern with a length L1 in the vertical direction of FIG. 1 and a width W1 in the horizontal direction of FIG. 1. For example, the length L1 of the first opening 7a is about 2.0 mm, and the width W1 is about 0.9 mm. The second opening 7b shown on the right side of FIG. 1 has a rectangular planar pattern with a length L2 in the vertical direction of FIG. 1 and a width W2 in the horizontal direction of FIG. 1. In the example of FIG. 1, the length L1 of the first opening 7a is longer than the length L2 of the second opening 7b. The width W1 of the first opening 7a is substantially the same as the width W2 of the second opening 7b.

[0020] The diagonal length L11 of the first opening 7a, which is the distance between the upper left corner P1 and the lower right corner P4 of the first opening 7a, is longer than the diagonal length L12 of the second opening 7b, which is the distance between the upper right corner P6 and the lower left corner P7 of the second opening 7b. In order to distinguish the first opening 7a from the second opening 7b, it is preferable that the difference between the diagonal length L11 of the first opening 7a and the diagonal length L12 of the second opening 7b is 50 μm or more.

[0021] In addition, if the shapes of the first opening 7a and the second opening 7b are different, the magnitudes of the width W1 of the first opening 7a and the width W2 of the second opening 7b, and the magnitudes of the length L1 of the first opening 7a and the length L2 of the second opening 7b are not particularly limited. For example, the width W1 of the first opening 7a may be longer than the width W2 of the second opening 7b, or may be shorter than the width W2 of the second opening 7b. Also, the length L1 of the first opening 7a may be the same as the length L2 of the second opening 7b, or may be shorter than the length L2 of the second opening 7b.

[0022] The first opening 7a and the second opening 7b are provided in a shape and position that are asymmetric with respect to the center line CL passing through the center point CP of the chip on the planar pattern and are also asymmetric with respect to the center point CP of the chip. That is, since the first opening 7a and the second opening 7b are different in shape and size from each other, they are not line-symmetric with respect to the center line CL passing through the center point CP of the chip, nor are they rotationally symmetric (point-symmetric) about the center point CP of the chip twice.

[0023] Portions of the first external connection electrode 5a and the second external connection electrode 5b that are respectively exposed from the first opening 7a and the second opening 7b serve as mounting pad regions to which external connection means such as bonding wires can be connected. In FIG. 1, effective connection regions 10a and 10b where the bonding wires inside the first opening 7a and the second opening 7b can be effectively connected are schematically shown by two-dot chain lines. For example, the effective connection region 10a is about 1.3 mm × 0.7 mm or less. The area of the effective connection region 10b is smaller than the area of the effective connection region 10a.

[0024] A first resistance layer 3a is provided between the first external connection electrode 5a and the relay wiring 5c so as to partially overlap the first external connection electrode 5a and the relay wiring 5c below the first external connection electrode 5a and the relay wiring 5. A second resistance layer 3b is provided between the second external connection electrode 5b and the relay wiring 5c so as to partially overlap the second external connection electrode 5b and the relay wiring 5c below the second external connection electrode 5b and the relay wiring 5c. In FIG. 1, the first resistance layer 3a and the second resistance layer 3b are schematically shown by broken lines.

[0025] The first resistance layer 3a and the second resistance layer 3b have different resistance values from each other. The first resistance layer 3a and the second resistance layer 3b have different shapes and sizes from each other on the planar pattern. The first resistance layer 3a has a rectangular planar pattern with the vertical direction in FIG. 1 being the length L3 and the horizontal direction in FIG. 1 being the width W3. The second resistance layer 3b has a rectangular planar pattern with the vertical direction in FIG. 1 being the length L4 and the horizontal direction in FIG. 1 being the width W4. The length L3 of the first resistance layer 3a is longer than the length L4 of the second resistance layer 3b. The width W3 of the first resistance layer 3a is substantially the same as the width W4 of the second resistance layer 3b. The resistance value of the first resistance layer 3a is smaller than the resistance value of the second resistance layer 3b.

[0026] Note that it is only necessary for the first resistance layer 3a and the second resistance layer 3b to have different resistance values from each other, and the comparison of the length L3 of the first resistance layer 3a and the length L4 of the second resistance layer 3b, and the comparison of the width W3 of the first resistance layer 3a and the width W4 of the second resistance layer 3b are not particularly limited. For example, the length L3 of the first resistance layer 3a may be the same as the length L4 of the second resistance layer 3b, or may be shorter than the length L4 of the second resistance layer 3b. Also, the width W3 of the first resistance layer 3a may be wider than the width W4 of the second resistance layer 3b, or may be narrower than the width W4 of the second resistance layer 3b.

[0027] As shown in FIG. 2, the semiconductor device according to the first embodiment includes a semiconductor substrate 1 of the first conductivity type (n - -type), lower insulating films 2a and 2b, a first resistance layer 3a, and a second resistance layer 3b. The lower insulating films 2a and 2b are provided on the semiconductor substrate 1. The first resistance layer 3a and the second resistance layer 3b are provided on the lower insulating films 2a and 2b.

[0028] The semiconductor device according to the first embodiment can be used as a gate resistance element of an insulated gate semiconductor device such as an insulated gate bipolar transistor (IGBT) or a MIS transistor. When the semiconductor device according to the first embodiment is used as a gate resistance element, depending on the required specifications, the thickness of the semiconductor substrate 1 is, for example, about 250 μm to 450 μm, and the resistivity of the semiconductor substrate 1 is usually selected to be a relatively low value. As the semiconductor substrate 1, for example, a silicon (Si) substrate or the like can be used.

[0029] In FIG. 2, although different reference numerals are given to the lower insulating films 2a and 2b, the lower insulating films 2a and 2b may be an integral member that is continuous at the back or the like in FIG. 2. Although not shown, on the upper part of the semiconductor substrate 1, a contact region having a lower specific resistance than the semiconductor substrate 1 and having a first conductivity type (n + type) is provided between the lower insulating films 2a and 2b. When a semiconductor substrate 1 of a second conductivity type (p - type) is used, a semiconductor region having a lower specific resistance than the semiconductor substrate 1 and having a second conductivity type (p + type) may be provided as a contact region on the upper part of the semiconductor substrate 1.

[0030] As the lower insulating films 2a and 2b, for example, a field insulating film having a thickness of about 600 nm to 1000 nm can be used. As the lower insulating films 2a and 2b, a silicon oxide film (SiO2 film), a silicon nitride film (Si3N4 film), or a composite film thereof can be used. As the lower insulating films 2a and 2b, an insulating film formed by a chemical vapor deposition (CVD) method using a gas of an organosilicon compound such as tetraethoxysilane (TEOS) may be used. By increasing the thickness of the lower insulating films 2a and 2b, the parasitic capacitance can be reduced.

[0031] The thicknesses of the first resistance layer 3a and the second resistance layer 3b are, for example, about 400 nm to 600 nm. The sheet resistances of the first resistance layer 3a and the second resistance layer 3b are, for example, about 100 Ω / sq to 200 Ω / sq. The resistance values of the first resistance layer 3a and the second resistance layer 3b can be controlled by adjusting the thicknesses of the first resistance layer 3a and the second resistance layer 3b, the lengths L3 and L4 (in the vertical direction in FIG. 1) of the first resistance layer 3a and the second resistance layer 3b, the widths W3 and W4 (in the horizontal direction in FIG. 1) of the first resistance layer 3a and the second resistance layer 3b, and the materials of the first resistance layer 3a and the second resistance layer 3b.

[0032] As the first resistance layer 3a and the second resistance layer 3b, for example, polycrystalline silicon (doped polysilicon: DOPOS) doped with n-type impurities can be used. n-type DOPOS can be formed by ion-implanting impurity elements such as phosphorus (P) and boron (B) into polysilicon, or by depositing polysilicon by CVD while adding impurity elements from the gas phase using doping gas. When DOPOS is used for the first resistance layer 3a and the second resistance layer 3b, the resistance values of the first resistance layer 3a and the second resistance layer 3b can also be controlled by adjusting the addition amount of the impurity elements added to the polysilicon.

[0033] The temperature coefficients of the first resistance layer 3a and the second resistance layer 3b are preferably 0 ppm / °C, or the first resistance layer 3a and the second resistance layer 3b have a negative temperature coefficient. Thereby, an increase in the resistance value during high-temperature operation can be suppressed. For example, when the semiconductor element according to the first embodiment is applied to the gate resistance of an IGBT, the on-state loss of the IGBT can be suppressed. The temperature coefficient of DOPOS can be controlled by adjusting the dose amount when ion-implanting impurities into polysilicon. For example, if the dose amount is about 7.0×10 15 cm -2 or less, the temperature coefficient of DOPOS can be made 0 ppm / °C or less. Note that the temperature coefficients of the first resistance layer 3a and the second resistance layer 3b are not necessarily limited to 0 ppm / °C or less, and the first resistance layer 3a and the second resistance layer 3b may have a positive temperature coefficient.

[0034] The first resistance layer 3a and the second resistance layer 3b are not limited to DOPOS, and may be a film of a nitride of a transition metal such as tantalum nitride (TaN x ), or a laminated film of a high-melting-point metal film laminated in the order of chromium (Cr)-nickel (Ni)-manganese (Mn). The first resistance layer 3a and the second resistance layer 3b may use thin films such as silver palladium (AgPd) and ruthenium oxide (RuO2). Although different from the structure shown in FIG. 2, it is also possible to realize the first resistance layer 3a and the second resistance layer 3b with a p-type diffusion layer or an n-type diffusion layer formed on the semiconductor surface.

[0035] An interlayer insulating film 4 is provided so as to cover the lower insulating films 2a and 2b, the first resistance layer 3a, and the second resistance layer 3b. The thickness of the interlayer insulating film 4 is, for example, about 1000 nm to 2000 nm. As the interlayer insulating film 4, a silicon oxide film (SiO2 film) without impurities called an "NSG film", a silicon oxide film with phosphorus added (PSG film), a silicon oxide film with boron added (BSG film), etc. can be used. Further, a single-layer film of a silicon oxide film with phosphorus and boron added (BPSG film) or a silicon nitride film (Si3N4 film), or a composite film selected and combined from among these can also be adopted as the interlayer insulating film 4. For example, the interlayer insulating film 4 can be composed of a composite film in which an NSG film of about 500 nm to 800 nm and a PSG film of about 400 nm to 800 nm are laminated. The NSG film has a function of suppressing resistance variation. Also, the PSG film has a function of ensuring the strength of wire bonding.

[0036] On the interlayer insulating film 4, a pair of first external connection electrodes 5a and second external connection electrodes 5b and a relay wiring 5c are provided. The first external connection electrode 5a is located above the lower insulating film 2a, and the horizontal position of the end portion of the first external connection electrode 5a overlaps with one end of the first resistance layer 3a in the depth direction. The second external connection electrode 5b is located above the lower insulating film 2b, and the horizontal position of the end portion of the second external connection electrode 5b overlaps with one end of the second resistance layer 3b in the depth direction. The relay wiring 5c is provided so as to be sandwiched between the pair of first external connection electrodes 5a and second external connection electrodes 5b, extending from above the lower insulating film 2a to above the lower insulating film 2b so that the cross-sectional structure shown in FIG. 2 is close to a T-shape.

[0037] The first external connection electrode 5a is connected to one end of the first resistance layer 3a via a contact region 6a. To the other end of the first resistance layer 3a, a resistance layer connection terminal, which is one end of the relay wiring 5c, is connected via a contact region 6b. The second external connection electrode 5b is connected to one end of the second resistance layer 3b via a contact region 6c. To the other end of the second resistance layer 3b, a resistance layer connection terminal, which is the other end of the relay wiring 5c, is connected via a contact region 6d.

[0038] The substrate connection terminal, which is the central end of the relay wiring 5c, is connected to the n-type contact 6e provided on the upper part of the semiconductor substrate 1 via the contact region 6e. + The semiconductor substrate 1 is ohmically connected to a contact region (not shown) with low contact resistance. A counter electrode 9 is provided on the back surface of the semiconductor substrate 1. That is, the first resistance layer 3a and the second resistance layer 3b are connected in series to the semiconductor substrate 1 via relay wiring 5c, and a vertical semiconductor element is realized in which the first external connection electrode 5a and the counter electrode 9, and the second external connection electrode 5b and the counter electrode 9 function as resistors.

[0039] The pair of first and second external connection electrodes 5a, 5b, and relay wiring 5c have a thickness of, for example, about 3 μm. The pair of first and second external connection electrodes 5a, 5b, and relay wiring 5c can be made of, for example, a laminate film of titanium / titanium nitride (Ti / TiN) as a barrier metal of about 100 nm to 130 nm, aluminum-silicon (Al-Si) of about 3 μm, and TiN / Ti as an anti-reflection film of about 35 nm to 55 nm. Instead of Al-Si, Al, Al alloys such as Al-Cu-Si and Al-Cu, etc. may be used. The first and second external connection electrodes 5a, 5b exposed from the first and second openings 7a, 7b of the protective film 7 become pad regions, to which bonding wires of about 200 μm to 400 μm in diameter made of metal such as aluminum (Al) can be connected.

[0040] A guard ring layer 5d is provided on the interlayer insulating film 4. The guard ring layer 5d is made of the same material as the pair of first and second external connection electrodes 5a and 5b and the relay wiring 5c. The guard ring layer 5d is provided, for example, in a ring shape on the outer periphery of the chip. The guard ring layer 5d is ohmic-connected to the semiconductor substrate 1 via contact regions 6f and 6g.

[0041] A protective film 7 is provided on a pair of first external connection electrodes 5a and second external connection electrodes 5b and a relay wiring 5c. The protective film 7 is provided with a first opening 7a and a second opening 7b, respectively. As the protective film 7, for example, as shown in FIG. 3, it can be composed of a three-layer structure of a first protective film 71, a second protective film 72, and a third protective film 73. The first protective film 71 can be composed of an oxide film such as a TEOS film. The second protective film can be composed of a Si3N4 film. The third protective film 73 can be composed of a polyimide film.

[0042] For example, by sequentially depositing a first protective film 71 made of a TEOS film and a second protective film 72 made of a Si3N4 film by a CVD method or the like, and applying a third protective film 73 made of a polyimide film, a protective film 7 having a three-layer structure is formed. Subsequently, by photolithography technology, etching technology, etc., a part of the third protective film 73 is selectively removed to form an opening in which the upper surface of the second protective film 72 is exposed. Next, by photolithography technology, etching technology, etc., a part of the second protective film 72 and the first protective film 71 are selectively removed sequentially to form a first opening 7a and a second opening 7b in which a part of the upper surfaces of the first external connection electrode 5a and the second external connection electrode 5b are exposed. As a result, as shown in FIG. 3, at the end of the second opening 7b, the third protective film 73 recedes and the first protective film 71 and the second protective film 72 protrude. The end of the first opening 7a shown in FIGS. 1 and 2 also has the same structure as the end of the second opening 7b shown in FIG. 3.

[0043] As shown in FIG. 2, a counter electrode 9 is provided on the lower surface of the semiconductor substrate 1. The counter electrode 9 can be composed of, for example, a single-layer film made of gold (Au), or a metal film laminated in the order of titanium (Ti), nickel (Ni), and gold (Au). The outermost layer of the counter electrode 9 can be composed of a material that can be soldered. The counter electrode 9 is fixed to a metal plate or the like by soldering or the like.

[0044] As shown in FIG. 2, the semiconductor element according to the first embodiment is based on a structure in which resistance layer connection terminals forming both ends of a T-shaped relay wiring 5c are connected to a first resistance layer 3a and a second resistance layer 3b. And the substrate connection terminal, which is the terminal on the central side of the T-shaped relay wiring 5c, is an n provided on the semiconductor substrate 1+ It is ohmically connected to a type contact region (not shown) with low contact resistance to form a vertical semiconductor element. Therefore, one external connection region (pad region) for mounting, which is composed of the first external connection electrode 5a connected to the first resistance layer 3a, is assigned to the first resistance layer 3a. Also, one external connection region (pad region) for mounting, which is composed of the second external connection electrode 5b connected to the second resistance layer 3b, is assigned to the second resistance layer 3b.

[0045] Therefore, according to the semiconductor element according to the first embodiment, the number of bonding wires per one of the first resistance layer 3a and the second resistance layer 3b is one, and the number of bonding wires can be reduced as compared with a horizontal semiconductor element. Further, as compared with a horizontal semiconductor element, the occupied area of the external connection region (pad region) for mounting on the upper surface side can be reduced, so that the chip size can be reduced.

[0046] For example, in a semiconductor module using the semiconductor element according to the first embodiment as a gate resistance element of an IGBT, when increasing the current capacity of the IGBT, in order to increase the chip size of the IGBT, the two-chip arrangement of the IGBT may be changed to a one-chip arrangement. In this case, when using a structure in which two resistance layers having the same resistance value are provided in one chip, like the vertical semiconductor elements described in Patent Documents 1 and 2, the bonding wire is connected to only one of the upper surface side electrodes of the two resistance layers. On the other hand, depending on the semiconductor module, it may be necessary to finely set the resistance value of the mounted semiconductor element, the number of series of the semiconductor elements increases, and it may become difficult to select an appropriate resistance value. Therefore, in the semiconductor element according to the first embodiment, the first resistance layer 3a and the second resistance layer 3b having different resistance values from each other are formed in one chip, enabling selection of an appropriate resistance value.

[0047] <Bonding Device> Next, a bonding apparatus used in the assembly process of the semiconductor device according to the first embodiment will be described. As shown in FIG. 4, the bonding apparatus includes a bonding unit 40, a position adjustment unit 30, an input device 45, and an output device 46. The bonding unit 40 includes a holding unit 41 and a head unit 42. The holding unit 41 holds the semiconductor device according to the first embodiment. For example, the semiconductor device according to the first embodiment is held by the holding unit 41 in a state where it is bonded to an insulating circuit board using a bonding member such as solder. The head unit 42 performs wire bonding on the semiconductor device according to the first embodiment held by the holding unit 41.

[0048] The position adjustment unit 30 includes an imaging unit 31, an image processing unit 32, an identification unit 33, a selection unit 34, and a storage unit 35. The imaging unit 31 captures a planar pattern of the semiconductor device according to the first embodiment as shown in, for example, FIG. 1, and acquires an image. The image processing unit 32 performs image processing on the image acquired by the imaging unit 31.

[0049] Based on the contrast difference between the metal surfaces of the first external connection electrodes 5a and 5b located at the ends of the first opening 7a and the second opening 7b shown in FIG. 1 and the protective film 7, the image processing unit 32 can automatically recognize the corner points P1 to P4 of the rectangular planar pattern of the first opening 7a and the corner points P5 to P8 of the rectangular planar pattern of the second opening 7b, and designate them as reference points (feature points). For example, using the image acquired by the imaging unit 31, the image processing unit 32 designates the positions of the corner points P1 and P4 of the first opening 7a and the positions of the corner points P6 and P7 of the second opening 7b as reference points, and registers the coordinates of the reference points P1, P4, P6, and P7 in the storage unit 35.

[0050] The identification unit 33 identifies the type of the semiconductor element according to the first embodiment based on the image processing result by the image processing unit 32. The image processing unit 32 detects (calculates) the diagonal lengths L11 which is the distance between the base points P1 and P4, and L12 which is the distance between the base points P6 and P7 as the target diagonal lengths. The identification unit 33 calculates the differences between the detected target diagonal lengths L11 and L12 and the reference diagonal lengths registered in advance in the storage unit 35 respectively. When any of the calculated differences is less than a predetermined threshold (prescribed value), the identification unit 33 identifies it as a conforming product conforming to the type of the semiconductor element according to the first embodiment. When at least any one of the differences is equal to or greater than the threshold, the identification unit 33 identifies it as a non-conforming product not conforming to the type of the semiconductor element according to the first embodiment. For example, there may be a case where semiconductor elements of a type different from that of the semiconductor element according to the first embodiment are mixed in, and it becomes possible to prevent the misidentification of such semiconductor elements of different types.

[0051] When imaging by the imaging unit 31, if the semiconductor element according to the first embodiment is bonded to an insulating circuit board or the like via a bonding member and the semiconductor element is tilted due to the non-uniformity of the thickness of the bonding member, an error occurs in the coordinates of the base points recognized by the image processing unit 32, and an error occurs in the target diagonal lengths calculated by the identification unit 33. Therefore, although it depends on the bonding apparatus, for example, if the difference in the distance between the base points is 50 μm or more, it can be recognized as different planar patterns. Thus, the threshold for comparison with the difference can be set to about 50 μm.

[0052] The identification unit 33 identifies the first opening 7a and the second opening 7b based on the diagonal lengths L11 and L12 calculated by the image processing unit 32. For example, by setting the difference between the diagonal lengths L11 and L12 to 50 μm or more, the first opening 7a and the second opening 7b can be identified. Note that the identification unit 33 may identify the first opening 7a and the second opening 7b based on only one of the diagonal lengths L11 and L12.

[0053] The selection unit 34 selects the first resistance layer 3a or the second resistance layer 3b having an appropriate resistance value based on the performance of the semiconductor module on which the semiconductor element according to the first embodiment is mounted. The selection unit 34 selects, as a wire bonding target, the pad region among the pad regions composed of the first external connection electrode 5a and the second external connection electrode 5b exposed in the first opening 7a and the second opening 7b, which is connected to the selected first resistance layer 3a or second resistance layer 3b. For example, when the resistance value of the first resistance layer 3a is appropriate, the selection unit 34 selects the pad region composed of the first external connection electrode 5a connected to the first resistance layer 3a.

[0054] The storage unit 35 stores the image acquired by the imaging unit 31, the image processing result by the image processing unit 32, the identification result by the identification unit 33, the selection result by the selection unit 34, and the like. The input device 45 receives an input operation by an operator and transmits it to the position adjustment unit 30. The output device 46 displays the image, data, etc. output from the position adjustment unit 30 to the operator.

[0055] <Method for mounting a semiconductor module> Next, with reference to the flowchart of FIG. 5, an example of an assembly method of the semiconductor element according to the first embodiment will be described. Here, the case where the semiconductor element according to the first embodiment is used as a gate resistance element of an IGBT is illustrated. The resistance chip, which is the semiconductor element according to the first embodiment, is joined together with the IGBT chip on an insulating circuit board via a joining member such as solder.

[0056] In step S100, the reference diagonal length of the semiconductor element according to the first embodiment is registered. For example, a chip (reference chip) for reference, which is a semiconductor element according to the first embodiment, is supplied to the bonding apparatus shown in FIG. 4 and placed on the holding portion 41 of the bonding unit 40. The imaging unit 31 of the position adjustment unit 30 images the reference chip and acquires an image. The image processing unit 32 designates the positions of the reference points P1, P4, P6, and P7 shown in FIG. 1 using the image acquired by the imaging unit 31 and registers them in the storage unit 35. Further, the image processing unit 32 detects the diagonal length L11 between the reference points P1 and P4 and the diagonal length L12 between the reference points P6 and P7, and registers them in the storage unit 35 as the reference diagonal length. Note that the reference diagonal length may be registered in the storage unit 35 in advance.

[0057] In step S101, a chip (target chip) that is a wire bonding target and is a semiconductor element according to the first embodiment is supplied to the bonding apparatus shown in FIG. 4. In step S102, the target chip is placed on the holding portion 41 of the bonding unit 40. The imaging unit 31 of the position adjustment unit 30 images the target chip and acquires an image. The image processing unit 32 designates the positions of the reference points P1, P4, P6, and P7 shown in FIG. 1 using the image acquired by the imaging unit 31 and registers them in the storage unit 35. In step S103, the image processing unit 32 calculates the diagonal length L11 between the reference points P1 and P4 and the diagonal length L12 between the reference points P6 and P7, and registers them in the storage unit 35 as the target diagonal length.

[0058] In step S104, the discrimination unit 33 calculates the difference between the target diagonal length and the reference diagonal length. When the difference between the target diagonal length and the reference diagonal length is equal to or greater than a predetermined threshold value (for example, 50 μm), the discrimination unit 33 proceeds to step S105 and discriminates it as a misaligned and mixed defective product. On the other hand, if the difference is less than the threshold value, it is discriminated as a non-defective product and the process proceeds to step S106. Note that the procedure of discriminating the type of the target chip in step S104 and discriminating whether the target chip is a non-defective product may be omitted.

[0059] In step S106, the identification unit 33 identifies the first opening 7a and the second opening 7b based on the diagonal lengths L11 and L12 calculated by the image processing unit 32. Based on the first opening 7a and the second opening 7b identified by the identification unit 33, the selection unit 34 selects, from among the two pad regions composed of the first external connection electrode 5a and the second external connection electrode 5b that are exposed in the first opening 7a and the second opening 7b, the pad region to be wire-bonded. The head unit 42 of the bonding unit 40 performs wire bonding on the pad region selected by the selection unit 34.

[0060] <Comparative Example> Here, a semiconductor element according to the comparative example will be described. As shown in FIG. 6, the semiconductor element according to the comparative example is different from the semiconductor element according to the first embodiment shown in FIG. 1 in that the first resistance layer 3a and the second resistance layer 3b have the same size and the same resistance value. Further, the semiconductor element according to the comparative example is different from the semiconductor element according to the first embodiment shown in FIG. 1 in that the first opening 7a and the second opening 7b have the same shape and size. That is, the semiconductor element according to the comparative example is line-symmetric with respect to the center line CL passing through the center point CP of the chip on the planar pattern and is rotationally symmetric twice with respect to the center point CP of the chip.

[0061] In the semiconductor element according to the comparative example, the upper left corner P1 of the first opening 7a and the lower right corner P8 of the second opening 7b are used as the reference points. Then, by detecting the diagonal length L13 between the reference points P1 and P8, the type of the semiconductor element according to the comparative example is identified. In the semiconductor element according to the comparative example, 180° chip rotation during assembly is allowed, and the same resistance value is obtained regardless of whether wire bonding is performed on the first external connection electrode 5a or the second external connection electrode 5b.

[0062] On the other hand, according to the semiconductor device according to the first embodiment of the present invention, since the first resistance layer 3a and the second resistance layer 3b have different resistance values, when assembling the semiconductor module, the first resistance layer 3a or the second resistance layer 3b having a resistance value suitable for the performance of a switching device such as an IGBT can be selected. Further, since the first opening 7a and the second opening 7b have different shapes, the first opening 7a and the second opening 7b can be easily identified, and one having an appropriate resistance value can be selected from the first resistance layer 3a and the second resistance layer 3b.

[0063] For example, when each chip arranged on one insulating circuit board is the same and the current specification is changed by changing the number of insulating circuit boards mounted on one semiconductor module, and the optimum chip resistance values are different, among the two pad regions composed of the first external connection electrode 5a and the second external connection electrode 5b, it becomes possible to cope by changing the pad region for wire bonding. Therefore, an appropriate resistance value can be selected without increasing the number of series of semiconductor devices.

[0064] (Second Embodiment) The planar pattern of the semiconductor device according to the second embodiment of the present invention is common to the planar pattern of the semiconductor device according to the first embodiment shown in FIG. 1 as shown in FIG. However, in the assembling process of the semiconductor device according to the second embodiment of the present invention, the locations serving as the bases of the first opening 7a and the second opening 7b are different from those in the first embodiment.

[0065] In the second embodiment of the present invention, taking the upper left corner P1 of the first opening 7a and the lower right corner P8 of the second opening 7b as bases respectively, the diagonal length L13 of the bases P1 and P8 is detected. Further, taking the lower left corner P3 of the first opening 7a and the upper right corner P6 of the second opening 7b as bases, the diagonal length L14 of the bases P3 and P6 is detected. Then, based on the diagonal lengths L13 and L14, the first opening 7a and the second opening 7b are identified, and among the two pad regions composed of the first external connection electrode 5a and the second external connection electrode 5b exposed from the first opening 7a and the second opening 7b, the pad region for wire bonding is selected. Since other configurations of the second embodiment of the present invention are the same as those of the first embodiment, duplicate descriptions are omitted.

[0066] According to the second embodiment of the present invention, even when detecting the diagonal lengths L13 and L14 across the first opening 7a and the second opening 7b, the first opening 7a and the second opening 7b can be identified, and one having an appropriate resistance value from the first resistance layer 3a and the second resistance layer 3b can be selected.

[0067] (Third Embodiment) The planar pattern of the semiconductor element according to the third embodiment of the present invention is common to the planar pattern of the semiconductor element according to the first embodiment shown in FIG. 1 as shown in FIG. 8. However, in the assembly process of the semiconductor element according to the third embodiment of the present invention, the locations serving as the bases of the first opening 7a and the second opening 7b are different from those of the first embodiment.

[0068] In the third embodiment of the present invention, taking the upper right corner P2 and the lower left corner P3 of the first opening 7a as bases respectively, the diagonal length L15 of the bases P1 and P3 is detected. Further, taking the upper left corner P5 and the lower right corner P8 of the second opening 7b as bases, the diagonal length L16 of the bases P5 and P8 is detected. Then, based on the diagonal lengths L15 and L16, the first opening 7a and the second opening 7b are identified, and among the two pad regions composed of the first external connection electrode 5a and the second external connection electrode 5b exposed from the first opening 7a and the second opening 7b, the pad region for wire bonding is selected. Since other configurations of the third embodiment of the present invention are the same as those of the first embodiment, duplicate descriptions are omitted.

[0069] According to the third embodiment of the present invention, even when detecting the diagonal lengths L15 and L16 in directions different from those in the first embodiment, the first opening 7a and the second opening 7b can be identified, and one having an appropriate resistance value can be selected from the first resistance layer 3a and the second resistance layer 3b.

[0070] (Fourth Embodiment) The planar pattern of the semiconductor element according to the fourth embodiment of the present invention is common to the planar pattern of the semiconductor element according to the first embodiment shown in FIG. 1 as shown in FIG. 9. However, in the assembling process of the semiconductor element according to the fourth embodiment of the present invention, the locations serving as the bases of the first opening 7a and the second opening 7b are different from those in the first embodiment.

[0071] In the fourth embodiment of the present invention, the diagonal length L11 of the bases P1 and P4 is detected with the upper left corner P1 and the lower right corner P4 of the first opening 7a as the bases, respectively. Also, the diagonal length L16 of the bases P5 and P8 is detected with the upper left corner P5 and the lower right corner P8 of the second opening 7b as the bases. Then, based on the diagonal lengths L11 and L16, the first opening 7a and the second opening 7b are identified, and among the two pad regions composed of the first external connection electrode 5a and the second external connection electrode 5b exposed from the first opening 7a and the second opening 7b, the pad region for wire bonding is selected. Since other configurations of the fourth embodiment of the present invention are the same as those in the first embodiment, redundant descriptions are omitted.

[0072] According to the fourth embodiment of the present invention, even when detecting the diagonal length L11 in the same direction as in the first embodiment in the first opening 7a and detecting the diagonal length L16 in a direction different from that in the first embodiment in the second opening 7b, the first opening 7a and the second opening 7b can be identified, and one having an appropriate resistance value can be selected from the first resistance layer 3a and the second resistance layer 3b.

[0073] (Fifth Embodiment) As shown in FIG. 10, the semiconductor device according to the fifth embodiment of the present invention differs from the semiconductor device according to the first embodiment shown in FIG. 1 in that convex portions (auxiliary patterns) 71a and 71b are provided in the planar pattern of the second opening 7b. The convex portion 71a is provided at the upper right corner P6 of the second opening 7b. The convex portion 71a has a rectangular planar pattern with a length L21 and a width W21. The convex portion 71b is provided at the lower left corner P7 of the second opening 7b. The convex portion 71b has a rectangular planar pattern with a length L22 and a width W22.

[0074] The convex portions 71a and 71b may have the same shape as each other or different shapes from each other. The convex portions 71a and 71b are not limited to a rectangular planar pattern, and may be, for example, a triangular or stepped planar pattern. Also, the corners P9 and P10 of the convex portions 71a and 71b can be used as reference points, but the position used as the reference point is not particularly limited and can be appropriately selected according to the shape of the convex portions 71a and 71b. Also, in FIG. 10, the case where the convex portions 71a and 71b are provided in the second opening 7b is illustrated, but convex portions may be provided in the first opening 7a. Also, the number of convex portions provided in the first opening 7a and the second opening 7b can be appropriately selected.

[0075] As shown in FIG. 11, the convex portion 71a is constituted by a portion extending toward the second opening 7b side of the first protective film 71. Similarly, the convex portion 71b shown in FIG. 10 is also constituted by a portion extending toward the second opening 7b side of the first protective film 71. The convex portions 71a and 71b can be formed by changing an etching mask for selectively removing a part of the first protective film 71 when opening the second opening 7b. Also, as shown in FIG. 12, in addition to the first protective film 71, a second protective film 72 may be provided so as to extend toward the second opening 7b side, and convex portions 71a and 72a composed of the extending portions of the first protective film 71 and the second protective film 72 may be formed.

[0076] In the assembly process of the semiconductor device according to the fifth embodiment of the present invention, as shown in FIG. 10, taking the upper left corner P1 and the lower right corner P4 of the first opening 7a as reference points, the diagonal length L11 between the reference points P1 and P4 is detected. Further, taking the corner P9 of the upper right convex portion 71a and the corner P10 of the lower left convex portion 71b of the second opening 7b as reference points, the diagonal length L18 between the reference points P9 and P10 is detected. Then, based on the diagonal lengths L11 and L18, the first opening 7a and the second opening 7b are identified, and among the two pad regions composed of the first external connection electrode 5a and the second external connection electrode 5b exposed from the first opening 7a and the second opening 7b, the pad region for wire bonding is selected. Since other configurations of the fifth embodiment of the present invention are the same as those of the first embodiment, duplicate explanations are omitted.

[0077] According to the fifth embodiment of the present invention, since it is necessary to secure the effective connection regions 10a and 10b inside the first opening 7a and the second opening 7b, there is a limit to reducing the sizes of the first opening 7a and the second opening 7b. However, by providing the convex portions 71a and 71b on at least one of the first opening 7a and the second opening 7b, the first opening 7a and the second opening 7b can have different shapes from each other without reducing their sizes. Therefore, the first opening 7a and the second opening 7b can be identified, and one having an appropriate resistance value can be selected from the first resistance layer 3a and the second resistance layer 3b. (Sixth Embodiment) The semiconductor device according to the sixth embodiment of the present invention is common to the semiconductor device according to the fifth embodiment of the present invention shown in FIG. 10 in that a convex portion 71a is provided at the upper right corner P6 of the second opening 7b as shown in FIG. 13. However, the semiconductor device according to the sixth embodiment of the present invention is different from the semiconductor device according to the fifth embodiment of the present invention shown in FIG. 10 in that no convex portion is provided at the lower left corner P7 of the second opening 7b.

[0078] In the assembly process of the semiconductor device according to the sixth embodiment of the present invention, as shown in FIG. 13, with the upper left corner P1 and the lower right corner P4 of the first opening 7a as reference points, the diagonal length L11 between the reference points P1 and P4 is detected. Further, with the corner P9 of the convex portion 71a in the upper right of the second opening 7b and the lower left corner P7 as reference points, the diagonal length L19 between the reference points P9 and P7 is detected. Then, based on the diagonal lengths L11 and L19, the first opening 7a and the second opening 7b are identified, and among the two pad regions composed of the first external connection electrode 5a and the second external connection electrode 5b exposed from the first opening 7a and the second opening 7b, the pad region for wire bonding is selected. Since other configurations of the sixth embodiment of the present invention are the same as those of the fifth embodiment, duplicate explanations are omitted.

[0079] According to the sixth embodiment of the present invention, even when one convex portion 71a is provided in the second opening 7b, the first opening 7a and the second opening 7b can have different shapes from each other. Therefore, the first opening 7a and the second opening 7b can be identified, and one having an appropriate resistance value can be selected from the first resistance layer 3a and the second resistance layer 3b. Thus, the position and number of the convex portions provided in the first opening 7a and the second opening 7b can be appropriately selected.

[0080] (Seventh Embodiment) The semiconductor device according to the seventh embodiment of the present invention is common to the semiconductor device according to the sixth embodiment shown in FIG. 13 in that a convex portion 71a is provided at the upper right corner P6 of the second opening 7b as shown in FIG. 14. However, the semiconductor device according to the seventh embodiment of the present invention is different from the semiconductor device according to the sixth embodiment shown in FIG. 13 in that a convex portion 71c is further provided at the lower left corner P3 of the first opening 7a.

[0081] In the assembly process of the semiconductor device according to the sixth embodiment of the present invention, as shown in FIG. 14, with the corner P9 of the convex portion 71a in the upper right of the second opening 7b and the corner P11 of the convex portion 71c in the lower left of the first opening 7a as reference points, the diagonal length L20 between the reference points P9 and P11 extending across the first opening 7a and the second opening 7b is detected. Then, based on the diagonal length L20, the first opening 7a and the second opening 7b are identified, and among the two pad regions composed of the first external connection electrode 5a and the second external connection electrode 5b exposed from the first opening 7a and the second opening 7b, the pad region for wire bonding is selected. Since other configurations of the seventh embodiment of the present invention are the same as those of the sixth embodiment, duplicate descriptions are omitted.

[0082] According to the seventh embodiment of the present invention, even when convex portions 71a and 71c are provided in the first opening 7a and the second opening 7b respectively, and the diagonal length L20 between the reference points P9 and P11 extending across the first opening 7a and the second opening 7b is detected with the corners P9 and P11 of the convex portions 71a and 71c as reference points, the first opening 7a and the second opening 7b can be identified, and one having an appropriate resistance value from the first resistance layer 3a and the second resistance layer 3b can be selected.

[0083] (Other Embodiments) As described above, the present invention has been described by the first to seventh embodiments, but the discussions and drawings forming a part of this disclosure should not be understood as limiting the present invention. Various alternative embodiments, examples, and operation techniques will be apparent to those skilled in the art from this disclosure.

[0084] For example, in the first to seventh embodiments, the case of detecting the diagonal lengths L11 to L20 of the first opening 7a and the second opening 7b is illustrated, but the present invention is not limited thereto. For example, as in the semiconductor element according to the first embodiment shown in FIG. 1, when the length L1 of the first opening 7a and the length L2 of the second opening 7b are different from each other, the length L1 of the first opening 7a, which is the distance between the base points, may be detected with the corner P1 and the corner P3, or the corner P2 and the corner P4 of the first opening 7a as the base points. Further, the length L2 of the second opening 7b, which is the distance between the base points, may be detected with the corner P5 and the corner P7, or the corner P6 and the corner P8 of the second opening 7b as the base points. Then, the first opening 7a and the second opening 7b may be identified based on the length L1 of the first opening 7a and the length L2 of the second opening 7b.

[0085] Also, although not shown, when the width W1 of the first opening 7a and the width W2 of the second opening 7b are different from each other, the width W1 of the first opening 7a, which is the distance between the base points, may be detected with the corner P1 and the corner P2, or the corner P3 and the corner P4 of the first opening 7a as the base points. Further, the width W2 of the second opening 7b, which is the distance between the base points, may be detected with the corner P5 and the corner P6, or the corner P7 and the corner P8 of the second opening 7b as the base points. Then, the first opening 7a and the second opening 7b may be identified based on the width W1 of the first opening 7a and the width W2 of the second opening 7b.

[0086] Also, as the semiconductor element according to the first to seventh embodiments, a semiconductor element having a vertical structure connected to the semiconductor substrate 1 via the relay wiring 5c as shown in FIGS. 1 and 2 is illustrated, but a semiconductor element having a horizontal structure may also be used. In the case of a semiconductor element having a horizontal structure, the relay wiring 5c may be omitted, and the third external connection electrode and the fourth external connection electrode connected to the first resistance layer 3a and the second resistance layer 3b, respectively, may be provided on the upper surface side of the chip.

[0087] In addition, as an example of the semiconductor device according to the first to seventh embodiments, a case where two resistance layers, namely, a first resistance layer 3a and a second resistance layer 3b, are provided has been exemplified. However, it may have three or more resistance layers having different resistance values from each other. Then, an external connection electrode may be provided on the upper surface side of the chip for each resistance layer, and the shapes and sizes of the openings for exposing a part of the external connection electrodes may be made different from each other.

[0088] In addition, the configurations disclosed in the first to seventh embodiments can be appropriately combined within a range where no contradiction occurs. Thus, the present invention naturally includes various embodiments not described herein. Therefore, the technical scope of the present invention is defined only by the invention-specific matters according to the appropriate claims based on the above description.

Explanation of Reference Numerals

[0089] 1... Semiconductor substrate 2a, 2b... Lower insulating film 3a... First resistance layer 3b... Second resistance layer 4... Interlayer insulating film 5a... First external connection electrode 5b... Second external connection electrode 5c... Relay wiring 5d... Guard ring layer 6a to 6g... Contact region 7... Protective film 9... Opposing electrode 10a, 10b... Effective connection region 30... Position adjustment unit 31... Imaging unit 32... Image processing unit 33... Identification unit 34... Selection unit 35... Storage unit 40... Bonding unit 41... Holding unit 42... Head unit 45... Input device 46... Output device 71... First protective film 71a, 71b, 71c, 72a... Protrusion 72... Second protective film 73… The third protective film CL… Center line CP… Center point L11~L20… Diagonal length P1~P11… Corners

Claims

1. a first resistance layer, a second resistance layer provided at a distance from the first resistance layer and having a resistance value different from that of the first resistance layer, a first external connection electrode electrically connected to one end side of the first resistance layer, a second external connection electrode provided at a distance from the first external connection electrode and electrically connected to one end side of the second resistance layer, a protective film covering the first and second external connection electrodes and having a first opening and a second opening that respectively expose a part of the upper surfaces of the first and second external connection electrodes, comprising a semiconductor device, wherein the planar patterns of the first and second openings are different in shape from each other.

2. The semiconductor device according to claim 1, wherein the planar patterns of the first and second openings are asymmetric with respect to the center point of the region enclosing the first and second external connection electrodes and asymmetric with respect to the center line between the first and second external connection electrodes.

3. The semiconductor device according to claim 1 or 2, wherein the planar patterns of the first and second openings are rectangular, and the diagonal length of the first opening is different from the diagonal length of the second opening.

4. The semiconductor device according to claim 3, wherein the difference between the diagonal length of the first opening and the diagonal length of the second opening is 50 μm or more.

5. The semiconductor device according to claim 1 or 2, wherein a convex portion is provided at at least one corner of the first and second openings.

6. an insulating layer provided under the first and second resistance layers, a semiconductor substrate provided under the insulating layer, relay wirings electrically connected to the other end sides of the first and second resistance layers respectively and ohmically connected to the semiconductor substrate, a counter electrode provided under the semiconductor substrate, The semiconductor device according to any one of claims 1 to 5, further comprising.

7. The semiconductor device according to claim 2, wherein the planar patterns of the first and second external connection electrodes are rotationally symmetric about the center point twice and line-symmetric about the center line.

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