Amplifier circuit

Abstract

To provide an amplifier circuit in which fluctuations in input offset voltages occurring when an input bias current is fluctuated are reduced without affecting high-frequency noise tolerance.SOLUTION: In an amplifier circuit 1A, a differential amplifier circuit 10 has non-inverting input IN+2 connected to a non-inverting input terminal IN+1 and inverting input IN-2 connected to an inverting input terminal IN-1. A first current source I1 supplies a cancel current Icncsl1 to the non-inverting input IN+2, and a second current source I2 supplies a cancel current Icncl2 to the inverting input IN-2. A first ESD protective resistance R1 is connected between a first connection point N1 between the first current source I1 and the non-inverting input IN+2, and the non-inverting input terminal IN+1. A second ESD protective resistance R2 is connected between a second connection point N2 between the second current source I2 and the inverting input IN-2, and the non-inverting input terminal IN-1. A low-pass filter 11A is provided between the first connection point N1 and the non-inverting input IN+2 and between the second connection point N2 and the inverting input IN-2.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to an amplifier circuit.

Background Art

[0002] In an amplifier circuit such as a comparator or a measurement amplifier, when a high-frequency signal (hereinafter, high-frequency noise) that greatly exceeds the unity gain frequency is applied to the input terminal of the amplifier circuit, the DC input offset voltage of the amplifier circuit fluctuates. Patent Document 1 is cited as a technique for suppressing this fluctuation of the input offset voltage.

[0003] The amplifier circuit of Patent Document 1 is provided with a low-pass filter. This low-pass filter removes the high-frequency noise applied to the input terminal of the amplifier circuit. In addition to the high-frequency noise, there is an input bias current in the characteristics of the amplifier circuit. The input bias current is the current flowing into the input terminal of the amplifier circuit or the current flowing out from the input terminal. Patent Document 2 is cited as a technique for reducing this input bias current.

[0004] The amplifier circuit of Patent Document 2 is provided with an input bias current copy circuit that generates a canceling current having a current value equal to the input bias current. By supplying the canceling current generated from this input bias current copy circuit to the input terminal of the amplifier circuit, the input bias current and the canceling current cancel each other out, and the input bias current can be reduced.

[0005] As an amplifier circuit that combines the technologies of Patent Document 1 and Patent Document 2 described above, for example, the one shown in FIG. 12 can be considered. As shown in the figure, the conventional amplifier circuit 100 includes a differential amplifier circuit 101, a low-pass filter 102, and current sources I10 and I20 as an input bias current copy circuit. The low-pass filter 102 is composed of resistors R10, R11 and capacitors C10, C11. The current sources I10 and I20 are provided on the differential amplifier circuit 101 side rather than the low-pass filter 102, and supply cancellation currents Icncl1 and Icncl2 to the input of the differential amplifier circuit 101. Further, in the amplifier circuit 100 shown in FIG. 12, the resistors R10 and R11 of the low-pass filter 102 protect the differential amplifier circuit 101 and the current sources I10 and I20 from ESD (Electro-Static Discharge: electrostatic discharge / surge).

[0006] According to the amplifier circuit 100 shown in FIG. 12 described above, when adjusting the cancellation currents Icncl1 and Icncl2 to make the input bias current zero, of the amplifier circuit there was a problem that the input offset voltage fluctuated greatly. Therefore, of the amplifier circuit it became difficult to adjust the input offset voltage.

Prior Art Documents

Patent Documents

[0007]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0008] The present invention has been made in view of the above circumstances, and its object is to provide an amplifier circuit that reduces fluctuations in the input offset voltage that occur when the input bias current is varied without affecting high-frequency noise resistance. of the amplifier circuit ​

Means for Solving the Problem

[0009] The inventors of the present invention have found that when a resistor constituting a low-pass filter is connected to a location where the current fluctuates greatly due to the fluctuation of the cancellation current, the voltage drop due to the resistor fluctuates greatly, and the input offset voltage fluctuates greatly, as the reason why the input offset voltage fluctuates greatly according to the fluctuation of the cancellation current, and thus the present invention has been achieved.

[0010] In order to achieve the above-described object, the amplifier circuit according to the present invention is characterized by the following [1] to [8]. [1] A non-inverting input terminal, An inverting input terminal, non A differential amplifier circuit that amplifies the voltage difference supplied to the inverting input and the inverting input, A first current source that supplies a cancellation current to the non-inverting input of the differential amplifier circuit to reduce the input bias current, flowing into or flowing out of the non-inverting input terminal A second current source that supplies a cancellation current to the inverting input of the differential amplifier circuit to reduce the input bias current, flowing into or flowing out of the inverting input terminal the non-inverting input of the differential amplifier circuit, and the inverting input of the differential amplifier circuit, and A first ESD protection resistor connected between the non-inverting input terminal and, the inverting input of the differential amplifier circuit, and A second ESD protection resistor connected between the inverting input terminal and, the first ESD protection resistor and the second ESD protection resistor, and A low-pass filter connected between the non-inverting input and the inverting input of the differential amplifier circuit, the first current source is connected between the first ESD protection resistor and the low-pass filter the second current source is connected between the second ESD protection resistor and the low-pass filter It is an amplifier circuit. [2] In the amplifier circuit according to [1], The low-pass filter, the first ESD protection resistor A third resistor connected between and the non-inverting input of the differential amplifier circuit, the second ESD protection resistor A fourth resistor connected between and the inverting input of the differential amplifier circuit, It is an amplifier circuit. [3] In the amplifier circuit described in [2], the low-pass filter includes a first capacitor connected between the third resistor and the non-inverting input of the differential amplifier circuit and ground, and a second capacitor connected between the fourth resistor and the inverting input of the differential amplifier circuit and ground. It is an amplifier circuit. [4] In the amplifier circuit described in [2] or [3], the low-pass filter includes a third capacitor connected between the third resistor and the non-inverting input of the differential amplifier circuit and between the fourth resistor and the inverting input of the differential amplifier circuit. It is an amplifier circuit. [5] In the amplifier circuit described in [1], the low-pass filter the first ESD protection resistor includes a first inductor connected between and the non-inverting input of the differential amplifier circuit, the second ESD protection resistor and a second inductor connected between and the inverting input of the differential amplifier circuit. It is an amplifier circuit. [6] In the amplifier circuit described in [5], the low-pass filter includes a first capacitor connected between the first inductor and the non-inverting input of the differential amplifier circuit and ground, and a second capacitor connected between the second inductor and the inverting input of the differential amplifier circuit and ground. It is an amplifier circuit. [7] In the amplifier circuit described in [5] or [6], the low-pass filter includes a third capacitor connected between the first inductor and the non-inverting input of the differential amplifier circuit and between the second inductor and the inverting input of the differential amplifier circuit. It is an amplifier circuit. [8] A non-inverting input terminal, An inverting input terminal, non A differential amplification circuit that amplifies the voltage difference supplied to the inverting input and the inverting input, Supplying a cancellation current to the non-inverting input of the differential amplification circuit, flowing into or flowing out of the non-inverting input terminal A first current source that reduces the input bias current, Supplying a cancellation current to the inverting input of the differential amplification circuit, flowing into or flowing out of the inverting input terminal A second current source that reduces the input bias current, A first ESD protection resistor connected between a first connection point between the first current source and the non-inverting input of the differential amplification circuit and the non-inverting input terminal, A second ESD protection resistor connected between a second connection point between the second current source and the inverting input of the differential amplification circuit and the inverting input terminal, A first inductor connected between the first ESD protection resistor and the first connection point, and the A second inductor connected between the second ESD protection resistor and the second connection point, and a low-pass filter having the same, No resistor is connected between the first ESD protection resistor and the first connection point No resistor is connected between the second ESD protection resistor and the second connection point It is an amplifier circuit.

Effect of the Invention

[0011] According to the present invention, it is possible to provide an amplifier circuit that does not affect high-frequency noise resistance and reduces fluctuations in the input offset voltage that occur when the input bias current is varied.

[0012] The present invention has been briefly described above. Further, the details of the present invention will be further clarified by reading through the embodiments for carrying out the invention described below (hereinafter referred to as "embodiments") with reference to the accompanying drawings.

Brief Description of the Drawings

[0013]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

BEST MODE FOR CARRYING OUT THE INVENTION

[0014] (First Embodiment) A specific first embodiment of the present invention will be described below with reference to FIGS. 1 and 2.

[0015] As shown in the figure, the amplifier circuit 1A includes a non-inverting input terminal IN+1, an inverting input terminal IN-1, a VCC power supply terminal T VCC and a VEE power supply terminal T VEE and an output terminal T VOUTand includes: The amplification circuit 1A includes a differential amplification circuit 10, a first current source I1, a second current source I2, a first ESD protection resistor R1, a second ESD protection resistor R2, a low-pass filter 11A, and ESD protection diodes D1 to D4.

[0016] The VCC power supply terminal T VCC is supplied with a VCC power supply that serves as a positive power supply. The VEE power supply terminal T VEE is supplied with a VEE power supply that serves as a ground. The differential amplification circuit 10 has a non-inverting input IN+2 connected to the non-inverting input terminal IN+1 and an inverting input IN-2 connected to the inverting input terminal IN-1, and amplifies the voltage difference supplied to the non-inverting input IN+2 and the inverting input IN-2 and outputs it from the output terminal T VOUT

[0017] A specific example of the differential amplification circuit 10 is shown in FIG. 2. As shown in the figure, the differential amplification circuit 10 includes transistors Q1, Q2, resistors R5, R6, and a constant current source I3. The transistors Q1, Q2 are composed of NPN-type transistors, and their emitters are connected to each other. The collector of transistor Q1 is connected to the VCC power supply terminal T VCC via resistor R5, and the collector of transistor Q2 is connected to the VCC power supply terminal T VCC via resistor R6. Also, the emitters of the commonly connected transistors Q1, Q2 are connected to the VEE power supply terminal T VEE via the constant current source I3. The base of transistor Q1 becomes the non-inverting input IN+2, and the base of transistor Q2 becomes the inverting input IN-2.

[0018] According to the differential amplification circuit 10 described above, since the sum of the collector currents of transistors Q1 and Q2 is constant by the constant current circuit I3, the collector current ratio of transistors Q1 and Q2 becomes a value corresponding to the voltage difference supplied to the non-inverting input IN+2 and the inverting input IN-2. Therefore, a voltage corresponding to the voltage difference supplied to the non-inverting input IN+2 and the inverting input IN-2 is generated between the connection point voltage of the collector of transistor Q1 and resistor R5 and the connection point voltage of the collector of transistor Q2 and resistor R6.​

[0019] Also, resistors R5 and R6 are composed of variable resistors. The resistance values of these resistors R5 and R6 are Amplifier circuit 1A pre-adjusted at the time of shipment or the like so that the input offset voltage of

[0020] As shown in FIG. 1, the first current source I1 supplies a cancellation current Icncl1 to the non-inverting input IN+2 of the differential amplifier circuit 10 to reduce the input bias current. The second current source I2 supplies a cancellation current Icncl2 to the inverting input IN−2 of the differential amplifier circuit 10 to reduce the input bias current.

[0021] A specific example of the first current source I1 and the second current source I2 is shown in FIG. 2. As shown in the figure, the first current sources I1 and I2 each include a tracking transistor Q3, a variable current source I4, and a current mirror circuit 12 composed of transistors Q41 and Q42. The tracking transistor Q3 is composed of the same NPN-type transistor as transistors Q1 and Q2. The tracking transistor Q3 is provided so that the collector-emitter voltage is equal to the collector-emitter voltages of transistors Q1 and Q2.

[0022] The variable current source I4 is provided between the emitter of the tracking transistor Q3 and the VEE power supply terminal T VEE and. The variable current source I4 is a constant current source whose current is adjustable, and is pre-adjusted at the time of shipment or the like so that the same current as the collector current of transistors Q1 and Q2 flows when the voltage value of the non-inverting input IN+2 = the voltage value of the inverting input IN−2. In this way, by making the collector-emitter voltage and collector current of the tracking transistor Q3 equal to the collector-emitter voltage and collector current of transistors Q1 and Q2, a current equal to the base current of transistors Q1 and Q2 can flow through the base of the tracking transistor Q3.

[0023] Transistors Q41 and Q42 are composed of PNP transistors, with their bases connected to each other, and the base is connected to the collector of transistor Q41. Also, for transistors Q41 and Q42, their emitters are connected to the VCC power supply terminal T VCC . The collector of transistor Q41 is connected to the base of tracking transistor Q3. The collector of transistor Q42 of the first current source I1 is connected to the non-inverting input IN+2 (i.e., the base of transistor Q1). The collector of transistor Q42 of the second current source I2 is connected to the inverting input IN-2 (i.e., connected to the base of transistor Q2).

[0024] A collector current equal to the base current of tracking transistor Q3, i.e., the base currents of transistors Q1 and Q2, flows through transistor Q41. This collector current is copied to the collector current of transistor Q42. Then, the collector current flowing through transistor Q42 can be supplied to the bases of transistors Q1 and Q2 as cancellation currents Icncl1 and Icncl2 to cancel the base currents flowing through transistors Q1 and Q2.

[0025] The first ESD protection resistor R1 is connected between the first connection point N1 between the first current source I1 and the non-inverting input IN+2 of the differential amplifier circuit 10 and the non-inverting input terminal IN+1. The second ESD protection resistor R2 is connected between the second connection point N2 between the second current source I2 and the inverting input IN-2 of the differential amplifier circuit 10 and the inverting input terminal IN-1. The first and second ESD protection resistors R1 and R2 are resistors for protecting the differential amplifier circuit 10 and the first and second current sources I1 and I2 from overcurrent due to ESD, and have a relatively small resistance value of about 100Ω, for example. The resistance values of the first ESD protection resistors R1 and R2 are lower than those of the resistors R3 and R4 of the low-pass filter 11A described later.

[0026] The low-pass filter 11A is provided between the first connection point N1 and the second connection point N2, and the non-inverting input IN+2 and the inverting input IN-2 of the differential amplifier circuit 10, and blocks high-frequency noise input to the differential amplifier circuit 10. The low-pass filter 11A has a resistor R3 (third resistor), a resistor R4 (fourth resistor), a capacitor C1 (first capacitor), and a capacitor C2 (second capacitor). The resistor R3 is connected between the first connection point N1 and the non-inverting input IN+2 of the differential amplifier circuit 10. The resistor R4 is connected between the second connection point N2 and the inverting input IN-2 of the differential amplifier circuit 10. The capacitor C1 is connected between the resistor R3 and the non-inverting input IN+2 and the VEE power supply terminal T VEE (ground). The capacitor C2 is connected between the resistor R4 and the inverting input IN-2 and the VEE power supply terminal T VEE (ground).

[0027] According to the above-described low-pass filter 11A, the cut-off frequency of the signal input to the non-inverting input IN+2 is determined by the series resistance value of the first ESD protection resistor R1 and the resistor R3 and the capacitance of the capacitor C1. Also, the cut-off frequency of the signal input to the inverting input IN-2 is determined by the series resistance value of the second ESD protection resistor R2 and the resistor R4 and the capacitance of the capacitor C2.

[0028] For example, in order to have filter characteristics equivalent to those of the conventional example shown in FIG. 12, the series resistance value of the first ESD protection resistor R1 and the resistor R3 is made equal to the resistor R10 in FIG. 12, and the capacitance of the capacitor C1 is made equal to the capacitor C10. Also, the series resistance value of the second ESD protection resistor R2 and the resistor R4 is made equal to the resistor R11 in FIG. 12, and the capacitance of the capacitor C2 is made equal to the capacitor C11 in FIG. 12. In the present embodiment, the first and second ESD protection resistors R1 are set to about 100 Ω, and the resistors R3 and R4 are set to about 900 Ω.

[0029] The ESD protection diode D1 has its anode connected between the resistor R1 and the non-inverting input terminal IN+1, and its cathode connected to the VCC power supply terminal T VCC is connected. The ESD protection diode D2 has its anode connected to the VEE power supply terminal TVEE is connected, and the cathode is connected between the resistor R1 and the non-inverting input terminal IN+1. The ESD protection diode D3 has its anode connected between the resistor R2 and the inverting input terminal IN-1, and its cathode connected to the VCC power supply terminal T VCC is connected. The ESD protection diode D4 has its anode connected to the VEE power supply terminal T VEE is connected, and the cathode is connected between the resistor R2 and the inverting input terminal IN-1. These ESD protection diodes D1~D4 protect the differential amplifier circuit 10, the first and second current sources I1, I2 from overvoltage due to ESD.

[0030] In the above-described amplifier circuit 1A, the currents flowing between the first connection point N1 and the non-inverting input IN+2 of the differential amplifier circuit 10 and between the second connection point N2 and the inverting input IN-2 of the differential amplifier circuit 10 are the cancellation currents Icncl1, I cncl2 change little due to their variations. Conversely, the currents flowing between the first connection point N1 and the non-inverting input terminal IN+1 and between the second connection point N2 and the inverting input terminal IN-1 are the cancellation currents Icncl1, I cncl2 change greatly due to their variations.

[0031] In this embodiment, at locations where the change in the flowing current is large (between the first connection point N1 and the non-inverting input terminal IN+1, and between the second connection point N2 and the inverting input terminal IN-1) due to the variations in the cancellation currents Icncl1, Icncl2, relatively small first and second ESD protection resistors R1, R2 with a resistance value of about 100Ω are connected. Thereby, even if the cancellation currents Icncl1, Icncl2 vary, the variation in the voltage drop across the first and second ESD protection resistors R1, R2 is also small, and the variation in the input offset voltage can be reduced.

[0032] Also, in the present embodiment, relatively large resistors R3 and R4 with a resistance value of about 900 Ω are connected to locations where the change in the flowing current is small (between the first connection point N1 and the non-inverting input IN+2, and between the second connection point N2 and the inverting input IN-2) due to the fluctuations in the cancellation currents Icncl1 and Icncl2. As a result, even if the cancellation currents Icncl1 and Icncl2 fluctuate, the fluctuations in the current flowing through the resistors R3 and R4 are small, and the fluctuations in the voltage drop across the resistors R3 and R4 are also small, enabling the reduction of fluctuations in the input offset voltage. Moreover, even if the resistance values of the resistors R3 and R4 are set large, the fluctuations in the input offset voltage can be reduced, so that the low-pass filter 11A can have the same high-frequency noise tolerance as the conventional one.

[0033] Next, in order to confirm the above-described effects, the present inventors fabricated the amplifier circuit 100 of the conventional example shown in FIG. 12 and the amplifier circuit 1A of the example shown in FIGS. 1 and 2, and measured the input offset voltage with respect to the fluctuation amount of the input bias current for each. The results are shown in FIG. 3. As shown in the figure, it was found that the amplifier circuit 1A of the present example can more effectively suppress the fluctuation of the input offset voltage with respect to the fluctuations of the cancellation currents Icncl1 and Icncl2 (input bias current). As a result, after adjusting the input offset voltage to 0 by adjusting the resistors R5 and R6, even if the cancellation currents Icncl1 and Icncl2 are adjusted and varied, the fluctuation of the input offset voltage can be suppressed, and the adjustment of the input offset voltage can be easily performed.

[0034] Next, the present inventors measured the high-frequency noise rejection ratio EMIRR with respect to frequency for the amplifier circuit 100 of the conventional example shown in FIG. 12 and the amplifier circuit 1A of the example shown in FIGS. 1 and 2. The results are shown in FIG. 4. As shown in the figure, it was found that the characteristics of the amplifier circuit 100 of the conventional example and the amplifier circuit 1A of the present example match, and the same high-frequency noise tolerance as the conventional one can be obtained.

[0035] (Second Embodiment) Next, the amplifier circuit 1B of the second embodiment will be described with reference to FIG. 5. In FIG. 5, parts equivalent to the amplifier circuit 1A described in the first embodiment with respect to FIG. 1 are denoted by the same reference numerals, and detailed descriptions thereof are omitted. A major difference between the first embodiment and the second embodiment lies in the configuration of the low-pass filter 11B.

[0036] In the second embodiment, the low-pass filter 11B is composed of a resistor R3, a resistor R4, and a capacitor C3 (third capacitor). The resistor R3 is connected between the first connection point N1 and the non-inverting input IN+2 of the differential amplifier circuit 10. The resistor R4 is connected between the second connection point N2 and the inverting input IN−2 of the differential amplifier circuit 10. The capacitor C3 is connected between between the resistor R3 and the non-inverting input IN+2 of the differential amplifier circuit 10 and between the resistor R4 and the inverting input IN−2 of the differential amplifier circuit 10. The amplifier circuit 1B of the second embodiment can obtain the same effects as the amplifier circuit 1A of the first embodiment.

[0037] (Third Embodiment) Next, the amplifier circuit 1C of the third embodiment will be described with reference to FIG. 6. In FIG. 6, parts equivalent to the amplifier circuit 1A already described in the first embodiment with respect to FIG. 1 are denoted by the same reference numerals, and detailed descriptions thereof are omitted. A major difference between the first embodiment and the third embodiment lies in the configuration of the low-pass filter 11C. In the third embodiment, the low-pass filter 11C has a capacitor C3 in addition to the resistors R3, R4, and capacitors C1, C2 described in the first embodiment. The capacitor C3 is connected between between the resistor R3 and the capacitor C1 and between the resistor R4 and the capacitor C2. The amplifier circuit 1C of the third embodiment can obtain the same effects as the amplifier circuit 1A of the first embodiment.

[0038] (Reference Example) Next, the amplifier circuit 1D of the reference example will be described with reference to FIG. 7. In FIG. 7, parts equivalent to the amplifier circuit 1A already described in the first embodiment with respect to FIG. 1 are denoted by the same reference numerals, and detailed descriptions thereof are omitted. A major difference between the first to third embodiments and the reference example is that the amplifier circuit 1D of the reference example is configured such that the first and second ESD protection resistors R1 and R2 are not inserted. In the first to third embodiments, the smaller the resistance values of the first and second ESD protection resistors R1 and R2, the more the variation in the input offset voltage can be reduced. If the configuration is such that the first and second ESD protection resistors R1 and R2 are not inserted as in the reference example, the variation in the input offset voltage can be further reduced. Note that the differential amplifier circuit 10 is protected against overcurrent due to ESD by the resistors R3 and R4 that constitute the low-pass filters 11A to 11C.

[0039] However, when ESD is applied from the non-inverting input terminal IN+1 and the inverting input terminal IN-1, the resistors R3 and R4 of the low-pass filters 11A to 11C cannot protect the first and second current sources I1 and I2 against overcurrent. Therefore, the amplifier circuit 1D of the reference example needs to include resistors R7 and R8. The resistor R7 is connected between the first current source I1 and the first connection point N1. The resistor R8 is connected between the second current source I2 and the second connection point N2. Thereby, when ESD is applied from the non-inverting input terminal IN+1 and the inverting input terminal IN-1, the first and second current sources I1 and I2 can be protected by the resistors R7 and R8.

[0040] (Fourth Embodiment) Next, the amplifier circuit 1E of the fourth embodiment will be described with reference to FIG. 8. In FIG. 8, parts equivalent to the amplifier circuit 1A described in the first embodiment described above with respect to FIG. 1 are denoted by the same reference numerals, and detailed descriptions thereof are omitted. A major difference between the first embodiment and the fourth embodiment lies in the configuration of the low-pass filter 11E. In the second embodiment, the low-pass filter 11E includes inductors L1, L2 and capacitors C1, C2. The inductor L1 (first inductor) is connected between the first connection point N1 and the non-inverting input IN+2 of the differential amplifier circuit 10. The inductor L2 (second inductor) is connected between the second connection point N2 and the inverting input IN−2 of the differential amplifier circuit 10. The capacitor C1 is connected between the inductor L1 and the non-inverting input IN+2 and between the VEE power supply terminal T VEE and. The capacitor C2 is connected between the inductor L2 and the inverting input IN−2 and between the VEE power supply terminal T VEE and. Regarding the amplifier circuit 1E of the fourth embodiment, since the low-pass filter 11E is composed of the inductors L1, L2, it is possible to further reduce the variation in the input offset voltage compared to the case where it is composed of the resistors R3, R4 as in the first to third embodiments.

[0041] Regarding the high-frequency noise resistance, the low-pass filter composed of the inductor L and the capacitor C can attenuate signals with frequencies higher than the cut-off frequency more steeply than the low-pass filter composed of the resistor R and the capacitor C. The amplifier circuit 1E of the fourth embodiment using the low-pass filter composed of the inductor L and the capacitor C can achieve excellent high-frequency noise resistance.

[0042] (Fifth Embodiment) Next, the amplifier circuit 1F of the fifth embodiment will be described with reference to FIG. 9. In FIG. 9, parts equivalent to the amplifier circuit 1E described in the fourth embodiment above with respect to FIG. 8 are denoted by the same reference numerals, and detailed descriptions thereof are omitted. The major difference between the fourth embodiment and the fifth embodiment lies in the configuration of the low-pass filter 11F. In the fifth embodiment, the low-pass filter 11F is composed of inductors L1, L2, and a capacitor C3. The inductor L1 is connected between the first connection point N1 and the non-inverting input IN+2 of the differential amplifier circuit 10. The inductor L2 is connected between the second connection point N2 and the inverting input IN−2 of the differential amplifier circuit 10. The capacitor C3 is connected between the resistor R3 and the non-inverting input IN+2 of the differential amplifier circuit 10 and between the resistor R4 and the inverting input IN−2 of the differential amplifier circuit 10. The amplifier circuit 1F of the fifth embodiment can also achieve the same effect as the amplifier circuit 1E of the fourth embodiment.

[0043] (Sixth Embodiment) Next, the amplifier circuit 1G of the sixth embodiment will be described with reference to FIG. 10. In FIG. 10, parts equivalent to 1E already described in the fourth embodiment above with respect to FIG. 8 are denoted by the same reference numerals, and detailed descriptions thereof are omitted. The major difference between the fourth embodiment and the sixth embodiment lies in the configuration of the low-pass filter 11G. In the sixth embodiment, the low-pass filter 11G has, in addition to the inductors L1, L2, capacitors C1, C2 as in the fourth embodiment, a capacitor C3. The capacitor C3 is connected between the inductor L1 and the capacitor C1 and between the inductor L2 and the capacitor C2. The amplifier circuit 1G of the sixth embodiment can also achieve the same effect as the amplifier circuit 1E of the fourth embodiment.

[0044] (Seventh Embodiment) Next, the amplifier circuit 1H of the seventh embodiment will be described with reference to FIG. 11. Parts equivalent to 1E to 1G that have already been described in the fourth to sixth embodiments with respect to FIG. 1 are denoted by the same reference numerals, and detailed descriptions thereof are omitted. A major difference between the first embodiment and the fourth to sixth embodiments lies in the positions of the low-pass filters 11E, 11F, or 11G. In the fourth to sixth embodiments, the low-pass filters 11E to 11G were provided between the first and second connection points N1, N2 and the non-inverting input IN+2 and inverting input IN−2 of the differential amplifier circuit 10. In contrast, in the seventh embodiment, the low-pass filters 11E to 11G are provided between the non-inverting input terminal IN+1, inverting input terminal IN−1, and the first and second connection points N1, N2.

[0045] The currents flowing between the non-inverting input terminal IN+1, inverting input terminal IN−1, and the first and second connection points N1, N2 vary greatly in response to variations in the cancellation currents Icncl1 and Icncl2 as described above. However, since the low-pass filters 11E to 11G are composed of the inductors L1 and L2, large fluctuations in voltage drop do not occur, and the input offset does not vary significantly. Therefore, the amplifier circuit 1H of the seventh embodiment can achieve the same effects as the amplifier circuits 1E to 1G of the fourth to sixth embodiments.

[0046] Note that the present invention is not limited to the above-described embodiments, and can be appropriately modified, improved, etc. In addition, the materials, shapes, dimensions, numbers, arrangement locations, etc. of the respective components in the above-described embodiments are arbitrary as long as the present invention can be achieved, and are not limited.

[0047] The transistors Q1 and Q2 constituting the differential amplifier circuit 10 of the amplifier circuits 1A to 1G described above were composed of NPN transistors, but this is not restrictive. The transistors Q1 and Q2 may be changed to PNP transistors. In this case, the tracking transistor Q3 also needs to be changed from an NPN transistor to a PNP transistor, and the transistors Q41 and Q42 constituting the current mirror circuit 12 also need to be changed from PNP transistors to NPN transistors.

Explanation of Symbols

[0048] Amplifier circuits 1A to 1C, 1E to 1H Differential amplifier circuit 10 Capacitor C1 (First capacitor) Capacitor C2 (Second capacitor) Capacitor C3 (Third capacitor) First current source I1 Second current source I2 Canceling current Icncl1 Canceling current Icncl2 Non-inverting input terminal IN+1 Inverting input terminal IN-1 Non-inverting input IN+2 Inverting input IN-2 Inductor L1 (First inductor) Inductor L2 (Second inductor) First connection point N1 Second connection point N2 First ESD protection resistor R1 Second ESD protection resistor R2 Resistor R3 (Third resistor) Resistor R4 (Fourth resistor) Low-pass filters 11A to 11C, 11E to 11G

Claims

1. A non-inverting input terminal, an inverting input terminal, a differential amplifier circuit that amplifies a voltage difference supplied to the non-inverting input and the inverting input, a first current source that supplies a cancellation current to the non-inverting input of the differential amplifier circuit to reduce an input bias current flowing into or flowing out of the non-inverting input terminal, a second current source that supplies a cancellation current to the inverting input of the differential amplifier circuit to reduce an input bias current flowing into or flowing out of the inverting input terminal, a first ESD protection resistor connected between the non-inverting input of the differential amplifier circuit and the non-inverting input terminal, a second ESD protection resistor connected between the inverting input of the differential amplifier circuit and the inverting input terminal, a low-pass filter connected between the first ESD protection resistor and the second ESD protection resistor and the non-inverting input and the inverting input of the differential amplifier circuit, the first current source is connected between the first ESD protection resistor and the low-pass filter, the second current source is connected between the second ESD protection resistor and the low-pass filter, an amplifier circuit.

2. In the amplifier circuit according to Claim 1, the low-pass filter includes a third resistor connected between the first ESD protection resistor and the non-inverting input of the differential amplifier circuit, and a fourth resistor connected between the second ESD protection resistor and the inverting input of the differential amplifier circuit, an amplifier circuit.

3. In the amplifier circuit according to Claim 2, the low-pass filter includes a first capacitor connected between the third resistor and the non-inverting input of the differential amplifier circuit and ground, and a second capacitor connected between the fourth resistor and the inverting input of the differential amplifier circuit and ground, an amplifier circuit.

4. In the amplifier circuit according to Claim 2 or 3, the low-pass filter includes a third capacitor connected between the third resistor and the non-inverting input of the differential amplifier circuit and the fourth resistor and the inverting input of the differential amplifier circuit, an amplifier circuit.

5. In the amplifier circuit according to Claim 1, the low-pass filter includes a first inductor connected between the first ESD protection resistor and the non-inverting input of the differential amplifier circuit, and a second inductor connected between the second ESD protection resistor and the inverting input of the differential amplifier circuit, an amplifier circuit.

6. In the amplifier circuit according to claim 5, the low-pass filter includes a first capacitor connected between the first inductor and the non-inverting input of the differential amplifier circuit and ground, and a second capacitor connected between the second inductor and the inverting input of the differential amplifier circuit and ground, amplifier circuit.

7. In the amplifier circuit according to claim 5 or 6, the low-pass filter includes a third capacitor connected between the first inductor and the non-inverting input of the differential amplifier circuit and between the second inductor and the inverting input of the differential amplifier circuit, amplifier circuit.

8. a non-inverting input terminal, an inverting input terminal, a differential amplifier circuit that amplifies the voltage difference supplied to the non-inverting input and the inverting input, a first current source that supplies a cancellation current to the non-inverting input of the differential amplifier circuit to reduce the input bias current flowing into or flowing out of the non-inverting input terminal, a second current source that supplies a cancellation current to the inverting input of the differential amplifier circuit to reduce the input bias current flowing into or flowing out of the inverting input terminal, a first ESD protection resistor connected between a first connection point between the first current source and the non-inverting input of the differential amplifier circuit and the non-inverting input terminal, a second ESD protection resistor connected between a second connection point between the second current source and the inverting input of the differential amplifier circuit and the inverting input terminal, a first inductor connected between the first ESD protection resistor and the first connection point, and the a second inductor connected between the second ESD protection resistor and the second connection point, and a low-pass filter having the same, no resistor is connected between the first ESD protection resistor and the first connection point, no resistor is connected between the second ESD protection resistor and the second connection point, amplifier circuit.

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