Imaging device and driving method

Abstract

This image capture apparatus is provided with a plurality of pixels and a voltage supply circuit. Each of the plurality of pixels comprises a pixel electrode, an opposing electrode, a photoelectric conversion layer positioned between the pixel electrode and the opposing electrode, and an electron blocking layer positioned between the pixel electrode and the photoelectric conversion layer. The electron blocking layer includes a first layer including a first material, and a second layer including a second material and doped with an acceptor impurity. The first layer is in contact with the pixel electrode. The second layer is positioned between the first layer and the photoelectric conversion layer. The voltage supply circuit is electrically connected to the opposing electrode, supplies a first voltage between the opposing electrode and the pixel electrode in a first period, and supplies a second voltage different from the first voltage between the opposing electrode and the pixel electrode in a second period.

Description

Technical Field

[0001] The present disclosure relates to an imaging device and a method for driving pixels.

Background Art

[0002] Organic semiconductor materials have physical properties and functions that are not present in conventional inorganic semiconductor materials such as silicon, and are actively studied as semiconductor materials that can realize new semiconductor devices and electronic devices.

[0003] For example, a photoelectric conversion element using an organic semiconductor material as a photoelectric conversion material has been studied. The photoelectric conversion element can be used as an imaging device or the like by taking out electrons or holes generated by photoelectric conversion as signal charges. In the photoelectric conversion element in an imaging device or the like, it is desired to efficiently extract the charges generated by photoelectric conversion to the electrodes and prevent the backflow of charges from the electrodes.

[0004] In response to such demands, for example, Patent Document 1 and Patent Document 2 propose a method of using a charge blocking layer in a photoelectric conversion element. The charge blocking layer prevents the backflow of charges from the electrodes when a bias voltage is applied in the photoelectric conversion element, and also has a function of increasing the efficiency of charge extraction by selectively transporting electrons or holes generated by photoelectric conversion to the electrodes.

[0005] In Patent Document 1, in order to efficiently extract charges, a photoelectric conversion element in which an electrode, an electron blocking layer, a hole transport auxiliary layer, a donor layer made of a donor material, an acceptor layer made of an acceptor material, an electron transport auxiliary layer, a hole blocking layer, and an electrode are laminated in this order is proposed. In the photoelectric conversion element described in Patent Document 1, the ionization potentials of the electron blocking layer, the hole transport auxiliary layer, and the donor layer decrease in this order.

[0006] In Patent Document 2, in order to efficiently extract charges, a photoelectric conversion element is proposed which has an electron blocking layer between the electrode and the photoelectric conversion layer, and the absolute value of the ionization potential of the electron blocking layer has a maximum value from the electrode interface toward the photoelectric conversion layer. As one form in Patent Document 2, a method is disclosed in which the band of the electron blocking layer is bent into a convex shape upward by using a layer with a high impurity concentration for the electron blocking layer.

[0007] In addition, as a photosensor, a CMOS (Complementary Metal Oxide Semiconductor) type image sensor having a photodiode is widely used. The CMOS type image sensor has features such as low power consumption and the ability to access each pixel. In a CMOS type image sensor having a photodiode, generally, a so-called rolling shutter in which exposure and signal charge readout are sequentially performed for each row of the pixel array is adopted as the signal readout method.

[0008] In a rolling shutter, the timings of the start and end of exposure are different for each row of the pixel array. Therefore, when imaging a fast-moving object, a distorted image may be obtained as the image of the object, or when using a flash, a difference in brightness may occur within the image. Due to such circumstances, in recent years, there has been a rising demand for a so-called global shutter function in which the start and end of exposure are performed at the same timing for all pixels in the pixel array.

[0009] For example, in Patent Document 3, as a method for realizing a global shutter function using a photoelectric conversion element using an organic material thin film, a first bias voltage for moving the signal charge generated in the photoelectric conversion material to the pixel electrode is applied to the electrodes connected to both ends of the photoelectric conversion element, and a second bias voltage for suppressing the movement of electrons and holes at the timing of reading out the moved signal charge by the signal detection circuit is applied.

Prior Art Documents

Patent Documents

[0010] [Patent Document 1] Japanese Patent No. 5969843 [Patent Document 2] International Publication No. 2017 / 163923 [Patent Document 3] Japanese Unexamined Patent Application Publication No. 2018 - 92990 [Summary of the Invention] [Problems to be Solved by the Invention]

[0011] When applying two types of bias voltages during imaging as in the global shutter function disclosed in Patent Document 3, an improvement in the signal - to - noise (S / N) ratio is desired.

[0012] Therefore, the present disclosure provides an imaging device and the like that can improve the S / N ratio during imaging. [Means for Solving the Problems]

[0013] An imaging device according to an aspect of the present disclosure includes a plurality of pixels and a voltage supply circuit. Each of the plurality of pixels includes a pixel electrode, a counter electrode, a photoelectric conversion layer located between the pixel electrode and the counter electrode and generating electrons and holes, and an electron blocking layer located between the pixel electrode and the photoelectric conversion layer. The electron blocking layer includes a first layer containing a first material and a second layer containing a second material and doped with acceptor impurities. The first layer is in contact with the pixel electrode. The second layer is located between the first layer and the photoelectric conversion layer. The voltage supply circuit is electrically connected to the counter electrode, supplies a first voltage between the counter electrode and the pixel electrode in a first period, and supplies a second voltage different from the first voltage between the counter electrode and the pixel electrode in a second period. When the first voltage is supplied between the counter electrode and the pixel electrode, the potential difference between the counter electrode and the pixel electrode becomes a first potential difference, and when the second voltage is supplied between the counter electrode and the pixel electrode, the potential difference between the counter electrode and the pixel electrode becomes a second potential difference.

[0014] A driving method according to an aspect of the present disclosure is a driving method for a plurality of pixels in the above imaging device, including applying a voltage that makes the potential of the counter electrode with respect to the pixel electrode a positive potential between the counter electrode and the pixel electrode, and applying a voltage that makes the potential of the counter electrode with respect to the pixel electrode a negative potential between the counter electrode and the pixel electrode.

Advantages of the Invention

[0015] According to an imaging device or the like according to an aspect of the present disclosure, the S / N ratio during imaging can be improved.

Brief Description of the Drawings

[0016]

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Figure 9

Embodiments for Carrying Out the Invention

[0017] (Findings Leading to an Aspect of the Present Disclosure) As described above, when applying two types of bias voltages as in the global shutter function disclosed in Patent Document 3, an improvement in the S / N ratio is desired. The improvement in the S / N ratio can be achieved, for example, by satisfying the following two points. The first point is to efficiently extract signal charges while suppressing the movement of charges opposite to the signal charges to the photoelectric conversion layer at the timing when a first bias voltage for moving the signal charges to the pixel electrode is applied to the photoelectric conversion element. The second point is that the amount of charge movement from the pixel electrode, which becomes noise, to the photoelectric conversion element is minimized at the timing when a second bias voltage for suppressing the movement of electrons and holes is applied to the photoelectric conversion element. The first bias voltage and the second bias voltage are, for example, voltages having different polarities.

[0018] However, Patent Document 3 does not disclose an effective photoelectric conversion element configuration for improving the S / N ratio. Further, neither Patent Document 1 nor Patent Document 2 describes the application of the configurations disclosed in these documents when applying two types of bias voltages to the photoelectric conversion element, and there is no mention of an effective photoelectric conversion element configuration for improving the S / N ratio.

[0019] The present disclosure has been made based on such findings, and provides an imaging device or the like that improves the S / N ratio during imaging when applying two types of bias voltages with different polarities.

[0020] (Summary of the Present Disclosure) The summary of one aspect of the present disclosure is as follows.

[0021] An imaging device according to one aspect of the present disclosure includes a plurality of pixels and a voltage supply circuit. Each of the plurality of pixels includes a pixel electrode, a counter electrode, a photoelectric conversion layer that is located between the pixel electrode and the counter electrode and generates electrons and holes, and an electron blocking layer that is located between the pixel electrode and the photoelectric conversion layer. The electron blocking layer includes a first layer containing a first material and a second layer containing a second material and doped with acceptor impurities. The first layer is in contact with the pixel electrode, and the second layer is located between the first layer and the photoelectric conversion layer. The voltage supply circuit is electrically connected to the counter electrode, supplies a first voltage between the counter electrode and the pixel electrode in a first period, and supplies a second voltage different from the first voltage between the counter electrode and the pixel electrode in a second period. When the first voltage is supplied between the counter electrode and the pixel electrode, the potential difference between the counter electrode and the pixel electrode becomes a first potential difference, and when the second voltage is supplied between the counter electrode and the pixel electrode, the potential difference between the counter electrode and the pixel electrode becomes a second potential difference.

[0022] As a result, the voltage supply circuit can apply both a voltage that makes the potential of the counter electrode with respect to the pixel electrode positive and a voltage that makes it negative between the counter electrode and the pixel electrode. Therefore, when a voltage that makes the potential of the counter electrode with respect to the pixel electrode positive is applied between the counter electrode and the pixel electrode, since the pixel has a two-layer electron blocking layer including the first layer and the second layer, the electron blocking layer becomes a resistance to electrons, and injection of electrons from the pixel electrode into the photoelectric conversion layer can be suppressed. Further, when a voltage that makes the potential of the counter electrode with respect to the pixel electrode negative is applied between the counter electrode and the pixel electrode, the energy band bends in the second layer and the photoelectric conversion layer, so that the electric field applied to the first layer in contact with the pixel electrode becomes small. Therefore, backflow of holes from the pixel electrode into the photoelectric conversion layer can be suppressed. Thus, noise is reduced. Furthermore, since the second layer is doped with acceptor impurities, the resistance to holes in the second layer decreases. When a voltage that makes the potential of the counter electrode with respect to the pixel electrode positive is applied between the counter electrode and the pixel electrode, holes generated in the photoelectric conversion layer easily move from the photoelectric conversion layer to the pixel electrode, and the holes can be efficiently extracted. Therefore, the imaging device according to this aspect can improve the S / N ratio during imaging.

[0023] Further, for example, the photoelectric conversion efficiency of the plurality of pixels in the first period may be different from the photoelectric conversion efficiency of the plurality of pixels in the second period.

[0024] As a result, even if a first voltage and a second voltage are selected such that the change in current density differs according to the amount of light incident on the photoelectric conversion layer in the first period and the second period, since the imaging device has an electron blocking layer as described above, the S / N ratio during imaging can be improved.

[0025] Further, for example, the imaging device may operate in a global shutter mode in which all exposure periods of the plurality of pixels are unified. The exposure period is a period for accumulating one of the electrons and the holes generated in the photoelectric conversion layer.

[0026] In this way, since all pixels can be exposed at the same timing, it is possible to improve the S / N ratio during imaging while suppressing phenomena such as distortion of the image of an object peculiar to a rolling shutter.

[0027] Further, for example, the first period may be an exposure period, and the second period may be a non-exposure period that is a period other than the exposure period during the operation of the imaging device.

[0028] In this way, a global shutter method in which the second period is a non-exposure period for signal reading can be realized.

[0029] Further, for example, when the second voltage is supplied between the counter electrode and the pixel electrode, electrons and holes in the photoelectric conversion layer may recombine.

[0030] In this way, since a second voltage for recombining electrons and holes is supplied during the second period, by setting the second period, which is a non-exposure period, as a signal reading period, the current density generated from the photoelectric conversion layer during the non-exposure period becomes less likely to be affected by the amount of light incident on the photoelectric conversion layer.

[0031] Further, for example, when the first voltage is supplied between the counter electrode and the pixel electrode, photosensitivity may be generated in the photoelectric conversion layer.

[0032] In this way, since a voltage for generating sensitivity is supplied to the first electrode during the first period, which is the exposure period, the S / N ratio during imaging can be improved.

[0033] Further, for example, the voltage supply circuit may selectively apply a voltage that makes the potential of the counter electrode with respect to the pixel electrode a positive potential or a negative potential between the counter electrode and the pixel electrode.

[0034] Thus, even when a voltage that makes the potential of the counter electrode with respect to the pixel electrode positive or negative is selectively applied between the counter electrode and the pixel electrode, the imaging device can improve the S / N ratio during imaging because it has an electron blocking layer as described above.

[0035] Also, for example, the thickness of the first layer may be thinner than the thickness of the second layer.

[0036] Thereby, since the second layer where holes easily move is thicker than the first layer, holes can be extracted more efficiently.

[0037] Also, for example, the thickness of the first layer may be thicker than the thickness of the second layer.

[0038] Thereby, injection of electrons from the pixel electrode into the photoelectric conversion layer and backflow of holes from the pixel electrode into the photoelectric conversion layer can be further suppressed.

[0039] Also, for example, the second layer may be in contact with the photoelectric conversion layer.

[0040] Thereby, since the photoelectric conversion layer can be directly laminated on the second layer, pixels of the imaging device can be manufactured efficiently.

[0041] Also, for example, the electron blocking layer may further include a third layer located between the second layer and the photoelectric conversion layer and containing a third material.

[0042] Thereby, injection of electrons from the pixel electrode into the photoelectric conversion layer and backflow of holes from the pixel electrode into the photoelectric conversion layer can be further suppressed.

[0043] Also, for example, the second layer may contain a counter anion.

[0044] Thereby, the doping state of the electron blocking layer is stabilized.

[0045] Further, for example, the thickness of the first layer may be 10 nm or more.

[0046] Thereby, injection of electrons from the pixel electrode into the photoelectric conversion layer and backflow of holes from the pixel electrode into the photoelectric conversion layer can be further suppressed.

[0047] Further, for example, the carrier density in the first layer is less than 1E16 / cm 3 , that is, less than 1×10 16 cm -3 and may be less.

[0048] Thereby, injection of electrons from the pixel electrode into the photoelectric conversion layer and backflow of holes from the pixel electrode into the photoelectric conversion layer can be further suppressed.

[0049] Further, for example, the thickness of the second layer may be 10 nm or more.

[0050] Thereby, injection of electrons from the pixel electrode into the photoelectric conversion layer can be further suppressed. Further, even if the second layer is thick, since it is doped with acceptor impurities, it is difficult to inhibit the movement of holes from the photoelectric conversion layer to the lower electrode.

[0051] Further, for example, the carrier density in the second layer is 1E16 / cm 3 or more, that is, 1×10 16 cm -3 or more and may be.

[0052] Thereby, the resistance to holes in the second layer is further reduced, and holes can be extracted more efficiently.

[0053] A driving method according to an aspect of the present disclosure is a driving method for a plurality of pixels in the imaging device, including applying a voltage in which the potential of the counter electrode with respect to the pixel electrode becomes a positive potential between the counter electrode and the pixel electrode, and applying a voltage in which the potential of the counter electrode with respect to the pixel electrode becomes a negative potential between the counter electrode and the pixel electrode.

[0054] Thus, in the driving method according to one aspect of the present disclosure, a voltage at which the potential of the counter electrode with respect to the pixel electrode becomes a positive potential or a negative potential is selectively applied between the counter electrode and the pixel electrode. Since the pixel includes an electron blocking layer including a first layer and a second layer as described above, even when such a driving method is performed, injection of electrons from the pixel electrode into the photoelectric conversion layer and backflow of holes from the pixel electrode into the photoelectric conversion layer can be suppressed, and holes can be efficiently extracted. Therefore, the driving method according to this aspect can improve the S / N ratio during imaging.

[0055] Hereinafter, embodiments will be described with reference to the drawings.

[0056] Note that each of the embodiments described below shows general or specific examples. The numerical values, shapes, components, arrangement positions and connection forms of the components, steps, order of steps, etc. shown in the following embodiments are merely examples and are not intended to limit the present disclosure. In addition, among the components in the following embodiments, components not described in the independent claims are described as optional components. Also, each drawing is not necessarily drawn precisely. Therefore, for example, scales in each drawing do not necessarily match. Also, in each drawing, substantially the same configurations are denoted by the same reference numerals, and duplicate descriptions may be omitted or simplified.

[0057] In addition, in this specification, terms indicating the relationship between elements, terms indicating the shape of elements, and numerical ranges are not expressions representing only a strict meaning, but are expressions meaning substantially equivalent ranges, for example, including a difference of about several percent.

[0058] In this specification, the terms "upper" and "lower" do not refer to the upward (vertically upward) and downward (vertically downward) directions in absolute spatial recognition, but are used as terms defined by a relative positional relationship based on the stacking order in a stacked configuration. Specifically, the light-receiving side of the imaging device is defined as "upper", and the side opposite to the light-receiving side is defined as "lower". Note that terms such as "upper" and "lower" are only used to specify the mutual arrangement between members and are not intended to limit the posture of the imaging device during use. Also, the terms "upper" and "lower" are applicable not only when two components are spaced apart from each other and there is another component between the two components, but also when the two components are in close contact with each other and the two components are in contact.

[0059] (Embodiment) [Photoelectric conversion element] The photoelectric conversion element included in the imaging device according to this embodiment will be described with reference to FIG. 1. The photoelectric conversion element according to this embodiment is a charge readout type photoelectric conversion element.

[0060] FIG. 1 is a schematic cross-sectional view showing an example of the photoelectric conversion element 10 according to this embodiment. The photoelectric conversion element 10 is supported on a support substrate 1, and includes an upper electrode 6 and a lower electrode 2 which are a pair of electrodes, a photoelectric conversion layer 5 located between the upper electrode 6 and the lower electrode 2, and an electron blocking layer 7 located between the lower electrode 2 and the photoelectric conversion layer 5. The electron blocking layer 7 has a multilayer structure in which a plurality of electron blocking layers are stacked. The electron blocking layer 7 is located between the lower electrode 2 and the photoelectric conversion layer 5, and includes an electron blocking layer 3 in contact with the lower electrode 2 and an electron blocking layer 4 located between the electron blocking layer 3 and the photoelectric conversion layer 5 and doped with acceptor impurities. In this embodiment, the lower electrode 2 is an example of a pixel electrode when the photoelectric conversion element 10 is used in an imaging device, and the upper electrode 6 is an example of a counter electrode when the photoelectric conversion element 10 is used in an imaging device. Also, the electron blocking layer 3 is an example of the first layer, and the electron blocking layer 4 is an example of the second layer.

[0061] Hereinafter, each component of the photoelectric conversion element 10 according to the present embodiment will be described.

[0062] The support substrate 1 may be any substrate used for supporting a general photoelectric conversion element, and may be, for example, a glass substrate, a quartz substrate, a semiconductor substrate, or a plastic substrate.

[0063] The lower electrode 2 is formed of a metal, a metal nitride, a metal oxide, or polysilicon provided with conductivity. Examples of metals include aluminum, copper, titanium, and tungsten. Examples of methods for imparting conductivity to polysilicon include doping with impurities.

[0064] The upper electrode 6 is, for example, a transparent electrode formed of a transparent conductive material. The material of the upper electrode 6 is, for example, a transparent conductive oxide (TCO: Transparent Conducting Oxide). Examples of TCO include ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), AZO (Aluminum-doped Zinc Oxide), FTO (Fluorine-doped Tin Oxide), SnO2, and TiO2. Note that the upper electrode 6 may be appropriately fabricated by using a single or a combination of a plurality of metal materials such as TCO, aluminum (Al), and gold (Au) according to a desired transmittance.

[0065] Note that the materials of the lower electrode 2 and the upper electrode 6 are not limited to the above-described conductive materials, and other materials may be used.

[0066] For fabricating the lower electrode 2 and the upper electrode 6, various methods are used depending on the materials used. For example, when using ITO, methods such as an electron beam method, a sputtering method, a resistance heating evaporation method, a chemical reaction method such as a sol-gel method, or coating with a dispersion of indium tin oxide may be used. In this case, after forming the ITO film, further UV-ozone treatment, plasma treatment, or the like may be performed for fabricating the lower electrode 2 and the upper electrode 6.

[0067] The photoelectric conversion layer 5 is made of, for example, an organic semiconductor material. As a method for manufacturing the photoelectric conversion layer 5, for example, a wet method such as a coating method by spin coating or the like, or a dry method such as a vacuum evaporation method can be used. The vacuum evaporation method is a method of vaporizing the material of the layer by heating under vacuum and depositing it on a substrate. Further, the photoelectric conversion layer 5 is, for example, a mixed film having a bulk heterostructure including a donor organic semiconductor material and an acceptor organic semiconductor material. The photoelectric conversion layer 5 may be a laminated film in which a plurality of films each composed of a donor organic semiconductor material and an acceptor organic semiconductor material are laminated. Hereinafter, the donor organic semiconductor material and the acceptor organic semiconductor material will be specifically exemplified.

[0068] Examples of the donor organic semiconductor material include triarylamine compounds, benzidine compounds, pyrazoline compounds, styrylamine compounds, hydrazone compounds, triphenylmethane compounds, carbazole compounds, polysilane compounds, thiophene compounds, phthalocyanine compounds, naphthalocyanine compounds, subphthalocyanine compounds, cyanine compounds, merocyanine compounds, oxonol compounds, polyamine compounds, indole compounds, pyrrole compounds, pyrazole compounds, polyarylene compounds, condensed aromatic carbocyclic compounds (for example, naphthalene derivatives, anthracene derivatives, phenanthrene derivatives, tetracene derivatives, pyrene derivatives, perylene derivatives, fluoranthene derivatives, etc.) and metal complexes having a nitrogen-containing heterocyclic compound as a ligand.

[0069] Examples of the acceptor organic semiconductor material include fullerenes (for example, C60 fullerene, C70 fullerene, etc.), fullerene derivatives (for example, PCBM (phenyl C 61 methyl butyrate) and ICBA (indenyl C 60Bis addition compounds (etc.), condensed aromatic carbocyclic compounds (e.g., naphthalene derivatives, anthracene derivatives, phenanthrene derivatives, tetracene derivatives, pyrene derivatives, perylene derivatives, fluoranthene derivatives, etc.), 5- to 7-membered heterocyclic compounds containing a nitrogen atom, an oxygen atom, or a sulfur atom (e.g., pyridine, pyrazine, pyrimidine, pyridazine, triazine, quinoline, quinoxaline, quinazoline, phthalazine, cinnoline, isoquinoline, pteridine, acridine, phenazine, phenanthroline, tetrazole, pyrazole, imidazole, thiazole, oxazole, indazole, benzimidazole, benzodiazole, benzoxazole, benzothiazole, carbazole, purine, triazolopyridazine, triazolopyrimidine, tetrazaindene, oxadiazole, imidazopyridine, pyrrolidine, pyrrolopyridine, thiadiazolopyridine, dibenzazepine, and tribenzazepine, etc.), metal complexes having a polyarylene compound, a fluorene compound, a cyclopentadiene compound, a silyl compound, and a nitrogen-containing heterocyclic compound as ligands, and the like can be mentioned.

[0070] Note that the donor-type organic semiconductor material and the acceptor-type organic semiconductor material are not limited to the above examples. Any organic compound that can be formed into a film as the photoelectric conversion layer 5 by either a dry or a wet method, whether a low-molecular organic compound or a high-molecular organic compound, may be used as the material constituting the photoelectric conversion layer 5.

[0071] In addition, semiconductor materials other than the above donor-type organic semiconductor material and acceptor-type organic semiconductor material may be used in the photoelectric conversion layer 5. The semiconductor material may be, for example, a silicon semiconductor, a compound semiconductor, a quantum dot, a perovskite material, a carbon nanotube, etc., or a mixture of any two or more of these.

[0072] The photoelectric conversion element 10 according to this embodiment includes an electron blocking layer 7 including an electron blocking layer 3 and an electron blocking layer 4 doped with acceptor impurities. The electron blocking layer 7 transports the holes generated in the photoelectric conversion layer 5 to the lower electrode 2. Further, the electron blocking layer 7 has a function of suppressing the transport of electrons generated in the photoelectric conversion layer 5 to the lower electrode 2 and the movement of electrons from the lower electrode 2. The electron blocking layer 3 is in contact with the lower electrode 2. The electron blocking layer 4 is in contact with the electron blocking layer 3 and is not in contact with the lower electrode 2.

[0073] Further, the electron blocking layer 4 is in contact with the photoelectric conversion layer 5. Thereby, since the photoelectric conversion layer 5 can be directly laminated on the electron blocking layer 4, the photoelectric conversion element 10 can be efficiently manufactured.

[0074] Since the photoelectric conversion element 10 has the electron blocking layer 3 and the electron blocking layer 4, the following effects can be obtained. For example, when a voltage for extracting charges is applied between the upper electrode 6 and the lower electrode 2, the signal charges can be efficiently extracted while suppressing the injection of charges opposite to the signal charges from the lower electrode 2 into the photoelectric conversion layer 5. For example, the extraction efficiency of the signal charges can be increased as compared with the case where the photoelectric conversion element 10 has only the electron blocking layer 3 having the same thickness as the total thickness of the electron blocking layer 3 and the electron blocking layer 4. On the other hand, when a voltage for stopping the charge extraction is applied between the upper electrode 6 and the lower electrode 2, the backflow of charges from the lower electrode 2 to the photoelectric conversion layer 5 can be suppressed, and the noise signals that adversely affect the S / N ratio can be reduced. Therefore, the photoelectric conversion element 10 can improve the S / N ratio during imaging. In this embodiment, the signal charges are positive charges, for example, holes, and the charges opposite to the signal charges are negative charges, for example, electrons. Hereinafter, the details of the electron blocking layer 3 and the electron blocking layer 4 will be described.

[0075] The electron blocking layer 3 contains a first material as a main component. The electron blocking layer 3 is composed of, for example, the first material. The electron blocking layer 4 contains a second material as a main component and is doped with acceptor impurities. The electron blocking layer 4 is composed of, for example, the second material doped with acceptor impurities.

[0076] The first material and the second material may be the same material or different materials. The first material and the second material are, for example, organic semiconductor materials. As the organic semiconductor materials of the first material and the second material, for example, the materials exemplified as the organic semiconductor materials used for the above-mentioned photoelectric conversion layer 5 are used. The first material and the second material are not limited to organic semiconductor materials, and may be semiconductor materials such as oxide semiconductors or nitride semiconductors, or composite materials containing at least one of these.

[0077] For the acceptor impurities, for example, a compound that accepts electrons from the second material is used.

[0078] The method for forming the electron blocking layer 3 is not particularly limited. The electron blocking layer 3 is formed, for example, by depositing the first material or by dissolving the first material in a solvent and coating it.

[0079] The method for forming the electron blocking layer 4 is not particularly limited. The electron blocking layer 4 is formed, for example, by co-evaporating a second material and an acceptor impurity. Examples of the acceptor impurity used for film formation by co-evaporation include acceptor inorganic materials such as molybdenum trioxide, or acceptor organic materials such as 2,3,6,7,10,11-Hexacyano-1,4,5,8,9,12-hexaazatriphenylene (HATCN). Further, the electron blocking layer 4 is formed, for example, by dissolving a second material and an acceptor impurity in a solvent and applying the solution. Examples of the acceptor impurity used for film formation by application include compounds such as triarylboron compounds, metal halides, Lewis acids, organic acids, onium salts, salts of arylamine and metal halide, and salts of arylamine and Lewis acid. These compounds may be used alone or in combination of two or more kinds.

[0080] Further, the electron blocking layer 4 may contain a counter anion. Thereby, when the film is formed by coating, the doping state of the second material is stabilized. The counter anion is contained, for example, in the compound used as the acceptor impurity to be doped. Specific examples of the compound used as the acceptor impurity containing a counter anion include onium salts substituted with organic groups such as 4-Isopropyl-4’-methyldiphenyliodonium Tetrakis(pentafluorophenyl)borate and Triphenylsulfonium Tetrafluoroborate.

[0081] The concentration of acceptor impurities in the electron blocking layer 4 only needs to be higher than that in the electron blocking layer 3 and is not particularly limited. The concentration of acceptor impurities in the electron blocking layer 4 is, for example, a concentration that realizes the following carrier density. As a specific example, it is 0.1% by mass or more and 50% by mass or less with respect to the second material in the electron blocking layer 4. The carrier density in the doped electron blocking layer 4 is, from the viewpoint of efficiently extracting holes, which are signal charges, and improving the S / N ratio, for example, 1E16 / cm 3 or more, that is, 1×10 16 cm -3 or more, and may be 1E17 / cm 3 or more, that is, 1×10 17 cm -3 or more.

[0082] Further, in order to suppress the injection of electrons from the lower electrode 2 into the photoelectric conversion layer 5 and the backflow of holes from the lower electrode 2 into the photoelectric conversion layer 5, the electron blocking layer 3, for example, substantially does not contain acceptor impurities and is not doped with acceptor impurities. Specifically, the carrier density of the electron blocking layer 3 is, for example, less than 1E16 / cm 3 that is, less than 1×10 16 cm -3 less than.

[0083] The thickness of the electron blocking layer 3 is, for example, 10 nm or more. Thereby, the injection of electrons from the lower electrode 2 into the photoelectric conversion layer 5 and the backflow of holes from the lower electrode 2 into the photoelectric conversion layer 5 can be further suppressed. Also, the thickness of the electron blocking layer 3 is, for example, 200 nm or less. Thereby, a decrease in the extraction efficiency of signal charges can be suppressed.

[0084] Also, as shown in FIG. 1, the thickness of the electron blocking layer 3 may be thinner than the thickness of the electron blocking layer 4. Thereby, since the electron blocking layer 4 where holes are likely to move is thick, holes can be extracted more efficiently. Also, the thickness of the electron blocking layer 3 may be half or less of the thickness of the electron blocking layer 4.

[0085] Note that the thickness of the electron blocking layer 3 may be greater than the thickness of the electron blocking layer 4. Thereby, injection of electrons from the lower electrode 2 into the photoelectric conversion layer 5 and backflow of holes from the lower electrode 2 into the photoelectric conversion layer 5 can be further suppressed. Also, the thickness of the electron blocking layer 3 may be the same as the thickness of the electron blocking layer 4.

[0086] The thickness of the electron blocking layer 4 is, for example, 10 nm or more. Thereby, as the electron blocking layer 4 becomes thicker, injection of electrons from the lower electrode 2 into the photoelectric conversion layer 5 can be suppressed. Also, even if the electron blocking layer 4 becomes thicker, since the acceptor impurity is doped, the resistance to holes does not easily increase, so it is difficult to inhibit the movement of holes from the photoelectric conversion layer 5 to the lower electrode 2. The thickness of the electron blocking layer 4 is, for example, 500 nm or less.

[0087] Note that the photoelectric conversion element 10 may further include a hole blocking layer located between the upper electrode 6 (not shown in FIG. 1) and the photoelectric conversion layer 5. The hole blocking layer transports electrons generated in the photoelectric conversion layer 5 to the upper electrode 6. Also, the hole blocking layer suppresses transport of holes generated in the photoelectric conversion layer 5 to the upper electrode 6 and movement of holes from the upper electrode 6. For example, an organic semiconductor material is used for the hole blocking layer.

[0088] FIG. 2 is an exemplary energy band diagram of the photoelectric conversion element 10 shown in FIG. 1. In FIG. 2, the energy bands of each layer are shown as rectangles.

[0089] The photoelectric conversion layer 5 generates pairs of electrons and holes inside when irradiated with light. The generated pairs of electrons and holes are separated into electrons and holes at the interface between the donor-type organic semiconductor material and the acceptor-type organic semiconductor material of the photoelectric conversion layer 5. The electrons and holes move toward the lower electrode 2 side or the upper electrode 6 side according to the electric field, respectively. Here, among the pairs of electrons and holes generated by absorbing light, the material that donates electrons to the other material is called the donor material, and the material that accepts electrons is called the acceptor material. When two different types of organic semiconductor materials are used for the photoelectric conversion layer 5, which becomes the donor material and which becomes the acceptor material is generally determined by the relative positions of the energy levels of the highest occupied molecular orbital (HOMO) and the lowest unoccupied molecular orbital (LUMO) of the two types of organic semiconductor materials at the contact interface. Among the rectangles indicating the energy bands in Fig. 2, the upper end is the energy level of the LUMO, and the lower end is the energy level of the HOMO. As shown in Fig. 2, among the donor-type organic semiconductor material and the acceptor-type organic semiconductor material included in the photoelectric conversion layer 5, the one with the shallower energy level of the LUMO that accepts electrons becomes the donor material 5A, and the one with the deeper energy level becomes the acceptor material 5B. The donor-type organic semiconductor material is the donor material 5A, and the acceptor-type organic semiconductor material is the acceptor material 5B. In this specification, it is expressed that the higher the energy level located above in Fig. 2, the shallower it is, and the lower the energy level located below in Fig. 2, the deeper it is. That is, the shallower the energy level, the smaller the energy difference from the vacuum level, and the deeper the energy level, the larger the energy difference from the vacuum level.

[0090] Also, in Fig. 2, the Fermi level of the electron blocking layer 4 doped with acceptor impurities is shown by a dashed line.

[0091] Also, for example, as shown in Fig. 2, when the photoelectric conversion element 10 is used in an imaging device, the lower electrode 2 is electrically connected to a charge storage node described later.

[0092] In addition, the energy levels of the HOMOs of the electron blocking layer 3 and the electron blocking layer 4 are, for example, such that the difference from the energy level of the HOMO of the donor material 5A is 0.5 eV or less. Thereby, the photoelectric conversion element 10 can achieve both efficient hole extraction and suppression of the backflow of holes from the lower electrode 2 to the photoelectric conversion layer 5. Further, the energy level of the HOMO of the electron blocking layer 3 is, for example, such that the difference from the energy level of the HOMO of the electron blocking layer 4 is 0.5 eV or less. Thereby, it is possible to achieve both efficient hole extraction and suppression of the injection of electrons from the lower electrode 2 to the photoelectric conversion layer 5.

[0093] In addition, the energy levels of the LUMOs of the electron blocking layer 3 and the electron blocking layer 4 are shallower than, for example, the energy level of the LUMO of the acceptor material 5B of the photoelectric conversion layer 5. Further, the Fermi level of the electron blocking layer 4 is, for example, such that the difference from the energy level of the HOMO of the donor material 5A is 0.5 eV or less.

[0094] An energy band configuration as shown in FIG. 2 can be realized, for example, by selecting the materials for each layer based on the energy bands of the respective materials of each layer exemplified above.

[0095] FIG. 3 is an exemplary energy band diagram of the photoelectric conversion element 10 when a reverse bias voltage is applied between the lower electrode 2 and the upper electrode 6. Further, FIG. 4 is an exemplary energy band diagram of the photoelectric conversion element 10 when a forward bias voltage is applied between the lower electrode 2 and the upper electrode 6. In this specification, the voltage applied to the photoelectric conversion element 10, specifically, the voltage applied between the lower electrode 2 and the upper electrode 6 is referred to as the bias voltage. Also, the voltage when a voltage higher than that of the lower electrode 2 is applied to the upper electrode 6 is the reverse bias voltage, and the voltage when a voltage lower than that of the lower electrode 2 is applied to the upper electrode 6 is the forward bias voltage. Hereinafter, the reverse bias voltage may be referred to as the reverse bias, and the forward bias voltage may be referred to as the forward bias.

[0096] For example, when an imaging device using the photoelectric conversion element 10 accumulates signal charges, in the state shown in FIG. 3, electron-hole pairs are generated in the photoelectric conversion layer 5. Thereafter, since a voltage higher than that of the lower electrode 2 is applied to the upper electrode 6, holes move to the lower electrode 2 and electrons move to the upper electrode 6, and holes are accumulated in the charge storage node. Since the electron blocking layer 4 is doped with acceptor impurities and has high hole conductivity, in other words, since the resistance to holes is low, it is difficult to inhibit the transport of holes. Therefore, even if the electron blocking layer 4 is provided in the photoelectric conversion element 10, holes efficiently move to the lower electrode 2. Further, due to the influence of the reverse bias voltage, electrons tend to flow from the lower electrode 2 to the photoelectric conversion layer 5. However, since the photoelectric conversion element 10 includes the electron blocking layer 7 having a two-layer structure of the electron blocking layer 3 and the electron blocking layer 4, compared with the case of a single-layer electron blocking layer, there is a high effect of suppressing the injection of electrons from the lower electrode 2 to the photoelectric conversion layer 5.

[0097] Also, for example, when an imaging device using the photoelectric conversion element 10 reads out signal charges, holes accumulated in the charge storage node are read out through the lower electrode 2 in the state shown in FIG. 4. Although electrons generated in the photoelectric conversion layer 5 tend to flow to the lower electrode 2 due to the influence of the forward bias voltage, since the photoelectric conversion element 10 includes an electron blocking layer 7 having a two-layer structure of an electron blocking layer 3 and an electron blocking layer 4, compared with the case of a single-layer electron blocking layer, the effect of suppressing the injection of electrons from the photoelectric conversion layer 5 to the lower electrode 2 is high. Further, the reverse flow rate of holes from the lower electrode 2 to the photoelectric conversion layer 5 due to the influence of the forward bias voltage depends on, for example, the electric field applied to the electron blocking layer 3 in which holes are less mobile than in the electron blocking layer 4. As shown in FIG. 4, the energy band bends in the electron blocking layer 4 doped with acceptor impurities and the photoelectric conversion layer 5, so that the electric field applied to the electron blocking layer 3 becomes small. As a result, when reading out the signal charges, the reverse flow of holes accumulated in the charge storage node from the lower electrode 2 to the photoelectric conversion layer 5 is suppressed. For example, when the electron blocking layer 4 is not provided, since the energy band of the electron blocking layer 3 in FIG. 4 slopes upward to the right, the energy level of HOMO, which becomes a barrier to the movement of holes, slopes upward to the right and the photoelectric conversion layer 5 side becomes shallow, and the effect of suppressing the reverse flow of holes accumulated in the charge storage node is reduced.

[0098] As described above, the photoelectric conversion element 10 provided in the imaging device according to the present embodiment includes an electron blocking layer 7 including the above-described electron blocking layer 3 and electron blocking layer 4. Thereby, in the method of reading out holes collected from the lower electrode 2, when a forward bias voltage is applied between the lower electrode 2 and the upper electrode 6, the photoelectric conversion element 10 can effectively suppress the reverse flow of holes from the lower electrode 2 to the photoelectric conversion layer 5 during signal reading. Further, when a reverse bias voltage is applied between the lower electrode 2 and the upper electrode 6, the photoelectric conversion element 10 can efficiently extract holes while suppressing the injection of electrons from the lower electrode 2 to the photoelectric conversion layer 5.

[0099] Note that the electron blocking layer 7 has a stacked structure of two layers, i.e., the electron blocking layer 3 and the electron blocking layer 4, but is not limited thereto. The electron blocking layer 7 may include an electron blocking layer other than the electron blocking layer 3 and the electron blocking layer 4. FIG. 5 is a schematic cross-sectional view showing a photoelectric conversion element 11, which is another example of the photoelectric conversion element 10 according to the present embodiment.

[0100] The photoelectric conversion element 11 has the same configuration as the photoelectric conversion element 10, except that it includes an electron blocking layer 7A instead of the electron blocking layer 7. The electron blocking layer 7A includes an electron blocking layer 8 and an electron blocking layer 9 in addition to the electron blocking layer 3 and the electron blocking layer 4 included in the electron blocking layer 7. The electron blocking layer 8 is an example of the third layer. By including the electron blocking layer 8 and the electron blocking layer 9 in the electron blocking layer 7A, injection of charges opposite to the signal charges from the lower electrode 2 to the photoelectric conversion layer 5 and backflow of the signal charges from the lower electrode 2 to the photoelectric conversion layer 5 can be further suppressed. Note that, of the electron blocking layer 8 and the electron blocking layer 9, one may not be included in the electron blocking layer 7A.

[0101] The electron blocking layer 8 is located between the electron blocking layer 4 and the photoelectric conversion layer 5. The electron blocking layer 8 contains a third material as a main component. The electron blocking layer 8 is, for example, made of the third material. The electron blocking layer 8 may be doped with acceptor impurities.

[0102] The electron blocking layer 9 is located between the electron blocking layer 4 and the electron blocking layer 3. The electron blocking layer 9 contains a fourth material as a main component. The electron blocking layer 9 is, for example, made of the fourth material. The electron blocking layer 9 may be doped with acceptor impurities.

[0103] The third material and the fourth material are, for example, the materials exemplified in the description of the first material and the second material. The third material and the fourth material may each be the same material as at least one of the above-described first material and the second material, or may each be a different material.

[0104] [Imaging device] FIG. 6 is a diagram showing an example of a circuit configuration of an imaging device 100 including a photoelectric conversion unit 10A using the photoelectric conversion element 10 shown in FIG. 2. FIG. 7 is a schematic cross-sectional view showing an example of a device structure of a pixel 24 in the imaging device 100 according to the present embodiment.

[0105] As shown in FIGS. 6 and 7, the imaging device 100 according to the present embodiment includes a semiconductor substrate 40 which is an example of a substrate, a charge detection circuit 35 provided on the semiconductor substrate 40, a photoelectric conversion unit 10A provided on the semiconductor substrate 40, and a pixel 24 including a charge storage node 34 electrically connected to the charge detection circuit 35 and the photoelectric conversion unit 10A. The photoelectric conversion unit 10A of the pixel 24 includes the above-described photoelectric conversion element 10. The photoelectric conversion unit 10A has an upper electrode 6, a lower electrode 2, a photoelectric conversion layer 5, and an electron blocking layer 7 including an electron blocking layer 3 and an electron blocking layer 4. Note that the photoelectric conversion unit 10A may include another photoelectric conversion element such as a photoelectric conversion element 11 instead of the photoelectric conversion element 10.

[0106] The charge storage node 34 is electrically connected to the lower electrode 2 of the photoelectric conversion unit 10A and stores the charge obtained by the photoelectric conversion unit 10A. The charge storage node 34 is also referred to as a charge storage region. The charge detection circuit 35 detects the charge stored in the charge storage node 34. Note that the charge detection circuit 35 provided on the semiconductor substrate 40 may be provided on the semiconductor substrate 40 or may be directly provided in the semiconductor substrate 40.

[0107] As shown in FIG. 6, the imaging device 100 includes a plurality of pixels 24 and peripheral circuits. The imaging device 100 is, for example, an organic image sensor realized by a one-chip integrated circuit, and has a pixel array PA including a plurality of pixels 24 arranged two-dimensionally. The imaging device 100 is, for example, an imaging device that operates in a global shutter method in which the exposure periods of all the plurality of pixels 24 are unified. That is, the imaging device 100 has a global shutter function. Details of the exposure period will be described later.

[0108] The plurality of pixels 24 are arranged two-dimensionally, that is, in the row direction and the column direction, on the semiconductor substrate 40 to form a photosensitive region that is a pixel region. In FIG. 6, an example in which the pixels 24 are arranged on a 2×2 matrix is shown. Note that in FIG. 6, for the sake of illustration, the illustration of a circuit (for example, a pixel electrode control circuit) for individually setting the sensitivity of the pixel 24 is omitted. Further, the imaging device 100 may be a line sensor. In that case, the plurality of pixels 24 may be arranged one-dimensionally. In this specification, the row direction and the column direction refer to the directions in which the rows and columns extend, respectively. That is, the vertical direction, which is the vertical direction in FIG. 6, is the column direction, and the horizontal direction, which is the horizontal direction in FIG. 6, is the row direction.

[0109] As shown in FIGS. 6 and 7, each pixel 24 includes a photoelectric conversion unit 10A and a charge storage node 34 electrically connected to a charge detection circuit 35. The charge detection circuit 35 includes an amplification transistor 21, a reset transistor 22, and an address transistor 23.

[0110] The photoelectric conversion unit 10A includes a lower electrode 2 provided as a pixel electrode and an upper electrode 6 provided as a counter electrode. The photoelectric conversion unit 10A includes the photoelectric conversion element 10 described above. A predetermined bias voltage is applied to the upper electrode 6 via the counter electrode signal line 26.

[0111] The lower electrode 2 is connected to the gate electrode 21G of the amplification transistor 21, and the signal charges collected by the lower electrode 2 are accumulated in the charge storage node 34 located between the lower electrode 2 and the gate electrode 21G of the amplification transistor 21. In the present embodiment, the signal charges are holes.

[0112] The signal charges accumulated in the charge storage node 34 are applied as a voltage corresponding to the amount of the signal charges to the gate electrode 21G of the amplification transistor 21. The amplification transistor 21 amplifies this voltage and is selectively read out as a signal voltage by the address transistor 23. The reset transistor 22 has its source / drain electrode connected to the lower electrode 2 and resets the signal charges accumulated in the charge storage node 34. In other words, the reset transistor 22 resets the potentials (voltages) of the gate electrode 21G of the amplification transistor 21 and the lower electrode 2.

[0113] In order to selectively perform the operations described above in the plurality of pixels 24, the imaging device 100 has a power supply wiring 31, a vertical signal line 27, an address signal line 36, and a reset signal line 37, and these lines are respectively connected to each pixel 24. Specifically, the power supply wiring 31 is connected to the source / drain electrode of the amplification transistor 21, the vertical signal line 27 is connected to the source / drain electrode of the address transistor 23. The address signal line 36 is connected to the gate electrode 23G of the address transistor 23. Also, the reset signal line 37 is connected to the gate electrode 22G of the reset transistor 22.

[0114] The peripheral circuit includes a voltage supply circuit 19, a vertical scanning circuit 25, a horizontal signal readout circuit 20, a plurality of column signal processing circuits 29, a plurality of load circuits 28, and a plurality of differential amplifiers 32.

[0115] The voltage supply circuit 19 is electrically connected to the upper electrode 6 via the counter electrode signal line 26. The voltage supply circuit 19 supplies a voltage that creates a potential difference between the upper electrode 6 and the lower electrode 2 by applying a voltage to the upper electrode 6. For example, the voltage supply circuit 19 supplies a first voltage to the upper electrode 6 during a first period such as an exposure period described later, and supplies a second voltage different from the first voltage during a second period such as a non-exposure period. For example, the voltage supply circuit 19 selectively applies a voltage that makes the potential of the upper electrode 6 with respect to the lower electrode 2 a positive potential or a negative potential between the upper electrode 6 and the lower electrode 2. That is, of the first voltage and the second voltage, one is a voltage that makes the potential of the upper electrode 6 with respect to the lower electrode 2 a positive potential, and the other is a voltage that makes the potential of the upper electrode 6 with respect to the lower electrode 2 a negative potential. For example, the voltage supply circuit 19 applies a first voltage that makes the potential of the upper electrode 6 with respect to the lower electrode 2 a positive potential during the exposure period described later between the upper electrode 6 and the lower electrode 2. Also, for example, the voltage supply circuit 19 applies a second voltage that makes the potential of the upper electrode 6 with respect to the lower electrode 2 a negative potential during the non-exposure period described later between the upper electrode 6 and the lower electrode 2.

[0116] The vertical scanning circuit 25 is connected to the address signal line 36 and the reset signal line 37, selects a plurality of pixels 24 arranged in each row in row units, reads out the signal voltage, and resets the potential of the lower electrode 2. The power supply wiring 31, which is a source follower power supply, supplies a predetermined power supply voltage to each pixel 24. The horizontal signal readout circuit 20 is electrically connected to a plurality of column signal processing circuits 29. The column signal processing circuit 29 is electrically connected to the pixels 24 arranged in each column via the vertical signal line 27 corresponding to each column. The load circuit 28 is electrically connected to each vertical signal line 27. The load circuit 28 and the amplification transistor 21 form a source follower circuit.

[0117] A plurality of differential amplifiers 32 are provided corresponding to each column. The negative input terminal of the differential amplifier 32 is connected to the corresponding vertical signal line 27. Also, the output terminal of the differential amplifier 32 is connected to the pixel 24 via the feedback line 33 corresponding to each column.

[0118] The vertical scanning circuit 25 applies, via the address signal line 36, a row selection signal for controlling the on and off of the address transistor 23 to the gate electrode 23G of the address transistor 23. Thereby, the row to be read is scanned and selected. A signal voltage is read from the pixel 24 of the selected row to the vertical signal line 27. Further, the vertical scanning circuit 25 applies, via the reset signal line 37, a reset signal for controlling the on and off of the reset transistor 22 to the gate electrode 22G of the reset transistor 22. Thereby, the row of the pixel 24 to be the target of the reset operation is selected. The vertical signal line 27 transmits the signal voltage read from the pixel 24 selected by the vertical scanning circuit 25 to the column signal processing circuit 29.

[0119] The column signal processing circuit 29 performs noise suppression signal processing typified by correlated double sampling and analog-digital conversion (AD conversion).

[0120] The horizontal signal readout circuit 20 sequentially reads signals from a plurality of column signal processing circuits 29 to a horizontal common signal line (not shown).

[0121] The differential amplifier 32 is connected to the drain electrode of the reset transistor 22 via the feedback line 33. Therefore, the differential amplifier 32 receives the output value of the address transistor 23 at the negative terminal. The differential amplifier 32 performs a feedback operation so that the gate potential of the amplification transistor 21 becomes a predetermined feedback voltage. At this time, the output voltage value of the differential amplifier 32 is 0V or a positive voltage near 0V. The feedback voltage means the output voltage of the differential amplifier 32.

[0122] As shown in FIG. 7, the pixel 24 includes a semiconductor substrate 40, a charge detection circuit 35, a photoelectric conversion unit 10A, and a charge storage node 34 (see FIG. 6).

[0123] The semiconductor substrate 40 may be an insulating substrate or the like provided with a semiconductor layer on the surface on which the photosensitive region is formed. The semiconductor substrate 40 is, for example, a p-type silicon substrate. The semiconductor substrate 40 has impurity regions 21D, 21S, 22D, 22S, and 23S, and an element isolation region 41 for electrical isolation between the pixels 24. The impurity regions 21D, 21S, 22D, 22S, and 23S are, for example, n-type regions. Here, the element isolation region 41 is provided between the impurity region 21D and the impurity region 22D. Thereby, leakage of the signal charge accumulated in the charge storage node 34 is suppressed. Note that the element isolation region 41 is formed, for example, by performing ion implantation of an acceptor under predetermined implantation conditions.

[0124] The impurity regions 21D, 21S, 22D, 22S, and 23S are, for example, diffusion regions formed in the semiconductor substrate 40. As shown in FIG. 7, the amplification transistor 21 includes the impurity region 21S, the impurity region 21D, and the gate electrode 21G. The impurity regions 21S and 21D function as, for example, the source region and the drain region of the amplification transistor 21, respectively. A channel region of the amplification transistor 21 is formed between the impurity regions 21S and 21D.

[0125] Similarly, the address transistor 23 includes the impurity region 23S, the impurity region 21S, and the gate electrode 23G connected to the address signal line 36. In this example, the amplification transistor 21 and the address transistor 23 are electrically connected to each other by sharing the impurity region 21S. The impurity region 23S functions as, for example, the source region of the address transistor 23. The impurity region 23S has a connection to the vertical signal line 27 shown in FIG. 6.

[0126] The reset transistor 22 includes the impurity regions 22D and 22S, and the gate electrode 22G connected to the reset signal line 37. The impurity region 22S functions as, for example, the source region of the reset transistor 22. The impurity region 22S has a connection to the reset signal line 37 shown in FIG. 6.

[0127] An interlayer insulating layer 50 is laminated on the semiconductor substrate 40 so as to cover the amplification transistor 21, the address transistor 23, and the reset transistor 22.

[0128] In addition, a wiring layer (not shown in FIG. 7) may be disposed in the interlayer insulating layer 50. The wiring layer is formed of a metal such as copper, for example, and may include, as part thereof, wirings such as the above-described vertical signal line 27. The number of insulating layers in the interlayer insulating layer 50 and the number of layers included in the wiring layer disposed in the interlayer insulating layer 50 can be arbitrarily set.

[0129] In the interlayer insulating layer 50, a contact plug 53 connected to the gate electrode 21G of the amplification transistor 21, a contact plug 54 connected to the impurity region 22D of the reset transistor 22, a contact plug 51 connected to the lower electrode 2, and a wiring 52 connecting the contact plug 51, the contact plug 54, and the contact plug 53 are disposed. Thereby, the impurity region 22D of the reset transistor 22 is electrically connected to the gate electrode 21G of the amplification transistor 21. In the configuration illustrated in FIG. 7, the contact plugs 51, 53, and 54, the wiring 52, the gate electrode 21G of the amplification transistor 21, and the impurity region 22D of the reset transistor 22 constitute at least a part of the charge storage node 34.

[0130] The charge detection circuit 35 detects the signal charge captured by the lower electrode 2 and outputs a signal voltage. The charge detection circuit 35 includes the amplification transistor 21, the reset transistor 22, and the address transistor 23, and is formed on the semiconductor substrate 40.

[0131] The amplification transistor 21 includes an impurity region 21D and an impurity region 21S that are formed in the semiconductor substrate 40 and function as a drain region and a source region, respectively, a gate insulating layer 21X formed on the semiconductor substrate 40, and a gate electrode 21G formed on the gate insulating layer 21X.

[0132] The reset transistor 22 is formed in the semiconductor substrate 40 and includes an impurity region 22D and an impurity region 22S that function as a drain region and a source region, respectively, a gate insulating layer 22X formed on the semiconductor substrate 40, and a gate electrode 22G formed on the gate insulating layer 22X.

[0133] The address transistor 23 is formed in the semiconductor substrate 40 and includes an impurity region 21S and an impurity region 23S that function as a drain region and a source region, respectively, a gate insulating layer 23X formed on the semiconductor substrate 40, and a gate electrode 23G formed on the gate insulating layer 23X. In the impurity region 21S, the amplification transistor 21 and the address transistor 23 are connected in series.

[0134] The above-described photoelectric conversion unit 10A is disposed on the interlayer insulating layer 50. In other words, in the present embodiment, a plurality of pixels 24 constituting the pixel array PA are formed on the semiconductor substrate 40. The plurality of pixels 24 two-dimensionally arranged on the semiconductor substrate 40 form a photosensitive region. The distance (i.e., pixel pitch) between two adjacent pixels 24 may be, for example, about 2 μm.

[0135] The photoelectric conversion unit 10A has the structure of the above-described photoelectric conversion element 10. The lower electrode 2 is individually provided corresponding to each of the plurality of pixels 24. Further, the electron blocking layer 3, the electron blocking layer 4, the photoelectric conversion layer 5, and the upper electrode 6 are commonly provided for each of the plurality of pixels 24. At least one of the electron blocking layer 3, the electron blocking layer 4, the photoelectric conversion layer 5, and the upper electrode 6 may be individually provided corresponding to each of the plurality of pixels 24.

[0136] Above the photoelectric conversion unit 10A, a color filter 60 is formed, and a microlens 61 is formed above the color filter 60. The color filter 60 is formed, for example, as an on-chip color filter by patterning. As the material of the color filter 60, a photosensitive resin in which a dye or a pigment is dispersed is used. The microlens 61 is formed, for example, as an on-chip microlens. As the material of the microlens 61, an ultraviolet-sensitive material or the like is used.

[0137] For the manufacture of the imaging device 100, a general semiconductor manufacturing process can be used. In particular, when a silicon substrate is used as the semiconductor substrate 40, the imaging device 100 can be manufactured by utilizing various silicon semiconductor processes.

[0138] FIG. 8 is a diagram showing an example of the schematic current-voltage (I-V) characteristics of the photoelectric conversion unit 10A. In FIG. 8, the thick solid line graph shows the exemplary I-V characteristics of the photoelectric conversion unit 10A when a voltage is applied between the lower electrode 2 and the upper electrode 6 in a state where light is irradiated. Note that in FIG. 8, an example of the I-V characteristics of the photoelectric conversion unit 10A when a voltage is applied between the lower electrode 2 and the upper electrode 6 in a state where no light is irradiated is also shown by a thick dashed line. Similar to the above, the voltage at which the potential of the upper electrode 6 with respect to the lower electrode 2 becomes a positive potential is the reverse bias voltage, and the voltage at which it becomes a negative potential is the forward bias voltage, and the following description will be made.

[0139] As shown in FIG. 8, the photocurrent characteristics of the photoelectric conversion unit 10A according to the present embodiment are generally characterized by a first voltage range, a second voltage range, and a third voltage range.

[0140] In the first voltage range, the dependence of the current flowing through the photoelectric conversion unit 10A on the voltage applied between the lower electrode 2 and the upper electrode 6 and the amount of incident light on the photoelectric conversion layer 5 is small. That is, in the first voltage range, it can be considered that the difference between the current value flowing when there is light incident on the photoelectric conversion layer 5 and the current value flowing when there is no light incident is small. In the first voltage range, even if pairs of holes and electrons are generated by the incidence of light on the photoelectric conversion layer 5, since the absolute value of the voltage applied between the lower electrode 2 and the upper electrode 6 is not large, the holes and electrons, even if separated, recombine via trap levels or the like while being transported in the photoelectric conversion layer 5.

[0141] The first voltage range includes the region of the forward bias voltage. That is, the energy band diagram shown in FIG. 4 described above corresponds to the energy band diagram when a voltage in the first voltage range is applied between the lower electrode 2 and the upper electrode 6 in the photoelectric conversion unit 10A. Since the photoelectric conversion unit 10A has the electron blocking layer 3 and the electron blocking layer 4, as described with reference to FIG. 4, the photoelectric conversion unit 10A can suppress the reverse flow of holes, which are signal charges from the lower electrode 2 to the photoelectric conversion layer 5, compared to the case where it does not have these or has only one of them. Also, compared to the case where the positions of the electron blocking layer 3 and the electron blocking layer 4 are reversed with respect to the photoelectric conversion unit 10A, since the electron blocking layer 3, which is not the electron blocking layer 4 where holes are likely to move, is in contact with the lower electrode 2, the number of holes flowing from the lower electrode 2 to the photoelectric conversion layer 5 can be reduced. For example, when the electron blocking layer 4 is in contact with the lower electrode 2, there is a possibility that holes may easily flow backward from the lower electrode 2 to the photoelectric conversion layer 5 due to the influence of the doped acceptor impurities. Thus, when a forward bias voltage is applied to the photoelectric conversion unit 10A, it is important that the photoelectric conversion unit 10A not only has the electron blocking layer 3 and the electron blocking layer 4 doped with acceptor impurities, but also has a configuration in which the electron blocking layer 3 and the electron blocking layer 4 are laminated in such an order that the electron blocking layer 3 is in contact with the lower electrode 2.

[0142] Further, the second voltage range in FIG. 8 is a voltage range of a reverse bias voltage, and is a region where the absolute value of the output current density increases as the reverse bias voltage increases. That is, the second voltage range is a region where the current value increases in accordance with the amount of incident light on the photoelectric conversion layer 5 and the increase in the bias voltage applied between the lower electrode 2 and the upper electrode 6.

[0143] The energy band diagram shown in FIG. 3 described above corresponds to the energy band diagram when a voltage in the second voltage range is applied between the lower electrode 2 and the upper electrode 6 in the photoelectric conversion unit 10A. Therefore, since the photoelectric conversion unit 10A has the electron blocking layer 3 and the electron blocking layer 4, while suppressing the injection of electrons from the lower electrode 2 into the photoelectric conversion layer 5, the photoelectric conversion layer 5 can efficiently extract holes, which are signal charges generated by photoelectric conversion.

[0144] Further, the third voltage range in FIG. 8 is a forward bias voltage range in which the absolute value of the forward bias voltage is larger than the forward bias voltage range in the first voltage range, and is a region where the output current density increases as the forward bias voltage increases. That is, the third voltage range is a region where the current increases in accordance with the increase in the bias voltage applied between the lower electrode 2 and the upper electrode 6 even without light incidence on the photoelectric conversion layer 5. Specifically, it is a region where the amount of movement of holes from the lower electrode 2 to the photoelectric conversion layer 5 increases as the bias voltage increases. The energy band diagram shown in FIG. 4 described above also corresponds to the energy band diagram when a voltage in the third voltage range is applied between the lower electrode 2 and the upper electrode 6 in the photoelectric conversion unit 10A. Since the photoelectric conversion unit 10A has the electron blocking layer 3 and the electron blocking layer 4, as described above, the reverse flow of holes from the lower electrode 2 to the photoelectric conversion layer 5 can be suppressed. Therefore, at a relatively low (i.e., close to 0 V) bias voltage, the current hardly increases. As a result, the third voltage range becomes narrow and the first voltage range becomes wide. Thus, although details will be described later, the imaging device 100 can expand the width of the dynamic range.

[0145] [Operation of Imaging Device] Next, the operation of the imaging device 100 will be described with reference to FIGS. 6 and 9. Specifically, an example of a driving method for a plurality of pixels 24 will be described. The driving method for the plurality of pixels 24 includes a first step and a second step, which will be described below. Here, the case where holes are used as signal charges as described above will be explained. Note that the operation of the imaging device 100 is not limited to the example described below.

[0146] The voltage supply circuit 19 shown in FIG. 6 supplies different voltages to the upper electrode 6 between an exposure period, which is an example of the first period, and a non-exposure period, which is an example of the second period, via the counter electrode signal line 26. Specifically, the voltage supply circuit 19 selectively applies a voltage that makes the potential of the upper electrode 6 with respect to the lower electrode 2 a positive potential or a negative potential between the upper electrode 6 and the lower electrode 2 during the exposure period and the non-exposure period. In this specification, the "exposure period" means a period for accumulating, as signal charges, either holes or electrons generated by photoelectric conversion in the charge storage node 34. That is, the "exposure period" may be referred to as the "charge accumulation period". Also, in this specification, a period other than the exposure period during the operation of the imaging device is referred to as the "non-exposure period". The "non-exposure period" may be a period in which the incidence of light to the photoelectric conversion unit 10A is blocked, or a period in which the photoelectric conversion unit 10A is irradiated with light but no charge is substantially accumulated in the charge storage node 34.

[0147] FIG. 9 is a timing chart showing an example of the voltage V2 supplied to the upper electrode 6 of the photoelectric conversion unit 10A and the timing of operations in each row of the pixel array PA of the imaging device 100. For clarity, FIG. 9 shows only the change in the voltage V2 and the timing of exposure and signal readout for each row in the pixel array PA indicated by R0 to R7. The upper side of FIG. 9 is a graph showing an example of the temporal change in the voltage V2. Also, the lower side of FIG. 9 is a graph schematically showing an example of the timing of the readout period, exposure period, and non-exposure period. In the lower side of FIG. 9, the rectangle with a dot pattern indicates the readout period R. Also, the white rectangle indicates the exposure period E. Also, the rectangle with a dot pattern and the rectangle with a hatched pattern indicate the non-exposure period N.

[0148] First, in the initial state, the potential difference between the lower electrode 2 and the upper electrode 6 of the photoelectric conversion unit 10A, that is, the bias voltage applied to the photoelectric conversion unit 10A, is set to a value within the first voltage range. Here, it is assumed that the voltage V2 supplied from the voltage supply circuit 19 to the upper electrode 6 is the reference voltage Vb. Also, assuming the voltage of the charge storage node 34 is Vc, it is assumed that Vc is in a state reset to the reference voltage Vb. The reference voltage Vb is, for example, about 0V to 1V. In this case, if the voltage applied to the photoelectric conversion unit 10A is the bias voltage Vo, then since V2 = Vo + Vc, Vo = 0.

[0149] Next, the operation during the exposure period E will be described. At the start of the exposure period E, the voltage supply circuit 19 supplies the upper electrode 6 with a voltage Va which is an example of the first voltage within the second voltage range, that is, a reverse bias voltage, so that a voltage within the second voltage range is applied to the photoelectric conversion unit 10A. That is, as a first step, the voltage supply circuit 19 applies a voltage between the upper electrode 6 and the lower electrode 2 such that the potential of the upper electrode 6 with respect to the lower electrode 2 becomes a positive potential. For example, when the photoelectric conversion layer 5 is made of an organic semiconductor material, the voltage Va is a voltage of several V to at most about 10V. As a result, holes in an amount corresponding to the amount of incident light on the photoelectric conversion layer 5 are accumulated as signal charges in the charge storage node 34 of each pixel 24. Thus, during the exposure period E, the voltage supply circuit 19 supplies the upper electrode 6 with the voltage Va that causes recombination of electrons and holes in the photoelectric conversion layer 5.

[0150] Next, the operation during the non-exposure period N will be described. After the end of the exposure period E, the voltage supply circuit 19 supplies the upper electrode 6 with a reference voltage Vb which is an example of the second voltage as the voltage V2 so that a voltage within the first voltage range is applied to the photoelectric conversion unit 10A. In the charge storage node 34 of each pixel 24, holes corresponding to the amount of light incident on the photoelectric conversion layer 5 during the exposure period E are accumulated, and the value of the voltage Vc varies depending on the pixel 24. Since Vo = V2 - Vc, in the pixel 24 where the voltage Vc has not changed without being exposed, the bias voltage Vo also becomes zero. However, in the pixel 24 where the voltage Vc has changed, the bias voltage Vo does not become zero. Specifically, holes are accumulated in the charge storage node 34 during the exposure period E, and the voltage Vc of the charge storage node 34 rises from the reference voltage Vb before the exposure period E. Therefore, by the voltage supply circuit 19 supplying the reference voltage Vb as the voltage V2 to the upper electrode 6, the bias voltage Vo becomes a forward bias voltage. That is, as a second step, the voltage supply circuit 19 applies a voltage between the upper electrode 6 and the lower electrode 2 such that the potential of the upper electrode 6 with respect to the lower electrode 2 becomes a negative potential. Thus, during the non-exposure period N, the voltage supply circuit 19 supplies the upper electrode 6 with the reference voltage Vb that causes recombination of electrons and holes in the photoelectric conversion layer 5.

[0151] When a voltage range with a sufficiently wide width of the first voltage range is ensured, even if the value of the voltage Vc varies among the respective pixels 24, the voltage V2 can be set so that the bias voltage Vo applied to the photoelectric conversion unit 10A in the pixel 24 falls within the first voltage range. The variation in the value of the voltage Vc corresponds to the width of the dynamic range. For example, if the width of the first voltage range is 0.5 V or more, in an imaging device with a conversion gain of 50 μV / e - a dynamic range of 80 dB or more corresponding to the human eye can be ensured.

[0152] As described above, in a state where a bias voltage in the first voltage range is applied to the photoelectric conversion unit 10A, even when light enters the pixel 24, holes hardly move to the charge storage node 34. Further, holes accumulated in the charge storage node 34 hardly discharge to the lower electrode 2, and holes supplied from the voltage supply circuit 19 hardly flow into the charge storage node 34 through the lower electrode 2. That is, the voltage supply circuit 19 supplies a voltage to the upper electrode 6 so that the photoelectric conversion efficiencies of the plurality of pixels 24, specifically, the photoelectric conversion efficiencies of the photoelectric conversion units 10A of the plurality of pixels 24, are different between the exposure period and the non-exposure period.

[0153] Therefore, in the non-exposure period N, the holes in each pixel 24 are maintained and held in an amount corresponding to the amount of incident light to the photoelectric conversion layer 5. That is, the holes in each pixel 24 can be held without resetting the holes in the charge storage node 34 unless light is incident on the photoelectric conversion layer 5 again. For this reason, even when a sequential readout operation is performed row by row in the non-exposure period N, no new hole accumulation occurs during the readout operation. Therefore, even when the global shutter operation described later is performed, rolling distortion does not occur like a rolling shutter. Therefore, the global shutter function can be realized with a simple pixel circuit such as the pixel 24 without providing a transfer transistor and an additional storage capacitor. Since the pixel circuit is simple, the imaging device 100 can advantageously miniaturize the pixel 24.

[0154] Next, the global shutter operation of the imaging device 100 will be described with reference to FIG. 9.

[0155] As described above, in the imaging device 100, during the non-exposure period N, the voltage supply circuit 19 supplies the upper electrode 6 with a reference voltage Vb such that the bias voltage Vo applied to the photoelectric conversion unit 10A is within the first voltage range. That is, during the non-exposure period N, the second step described above is performed. When holes are accumulated in the charge storage node 34, the reference voltage Vb is, as described above, for example, below the voltage Vc of the charge storage node 34. Also, as shown in FIG. 9, the imaging device 100 sequentially performs signal reading at the timing of the reading period R of each row from R0 to R7 during the non-exposure period N. Also, for example, during the reading period R, after the signal reading, the holes accumulated in the charge storage node 34 are also reset.

[0156] Also, as described above, during the exposure period E, the voltage supply circuit 19 supplies the upper electrode 6 with a voltage Va such that the bias voltage Vo applied to the photoelectric conversion unit 10A is within the second voltage range. That is, during the exposure period E, the first step described above is performed. Also, the start and end timings of the exposure period E are the same for all rows from R0 to R7. That is, while sequentially performing signal reading, a global shutter function is realized.

[0157] From the above, according to the present embodiment, the photoelectric conversion unit 10A of the imaging device 100 has an electron blocking layer 3 and an electron blocking layer 4. Also, the driving method of the photoelectric conversion unit 10A includes a first step and a second step. Thereby, in the first step in which a reverse bias voltage is applied to the photoelectric conversion unit 10A performed during the exposure period E and the like, the imaging device 100 can efficiently extract holes while suppressing the injection of electrons from the lower electrode 2 into the photoelectric conversion layer 5. Also, in the second step in which a forward bias voltage is applied to the photoelectric conversion unit 10A performed during the non-exposure period N and the like, the imaging device 100 can suppress the backflow of holes from the lower electrode 2. Therefore, the imaging device 100 can improve the S / N ratio at the time of imaging even when applying forward and reverse bias voltages to the photoelectric conversion unit 10A, such as when realizing a global shutter function.

[0158] Hereinafter, the photoelectric conversion element and the like used in the imaging device according to the present disclosure will be specifically described with reference to examples. However, the present disclosure is not limited to the following examples in any way.

[0159] [Example 1] (Adjustment of Solution) The materials used for the electron blocking layer 3 and the electron blocking layer 4 were adjusted according to the following procedure. VNPB (N4,N4'-Di(naphthalen-1-yl)-N4,N4'-bis(4-vinylphenyl)biphenyl-4,4'-diamine, manufactured by LUMTEC) was weighed, and chlorobenzene was added as a solvent to prepare a first solution with a concentration of 10 mg / ml. Subsequently, 10 mg of a dopant (4-Isopropyl-4'-Methyldiphenyliodonium Tetrakis(Pentafluorophenyl)Borate) was weighed, and 1000 mL of chlorobenzene was added to prepare a second solution. 0.03 ml of the solution 2 was added to 1 ml of the solution 1 to prepare a third solution.

[0160] (Fabrication of Photoelectric Conversion Element) A photoelectric conversion element was fabricated according to the following procedure. The first solution was dropped onto a 0.7-mm-thick quartz glass with 150-nm ITO patterned thereon, and a coating film was formed by spin coating. Subsequently, the substrate on which the film was formed using a hot plate was heated at 200 °C for 50 minutes. Thereby, an un-doped and cross-linked electron blocking layer 3 was fabricated. Next, the third solution was dropped onto the electron blocking layer 3, and a coating film was formed by spin coating. Subsequently, the substrate on which the film was formed using a hot plate was heated at 200 °C for 50 minutes. Thereby, an electron blocking layer 4 doped with acceptor impurities and cross-linked was fabricated on the electron blocking layer 3. The thicknesses of the obtained electron blocking layers 3 and 4 were approximately 50 nm each.

[0161] Next, on the electron blocking layer 4, as materials for the photoelectric conversion layer, subphthalocyanine, which is a donor-type organic semiconductor material, and C60 fullerene, which is an acceptor-type organic semiconductor material, were co-evaporated by vacuum evaporation so that the weight ratio was 1:9, thereby forming a photoelectric conversion layer. Note that the film thickness of the photoelectric conversion layer obtained at this time was approximately 500 nm. Also, as the subphthalocyanine, subphthalocyanine having boron (B) as the central metal and chloride ions coordinated to B as ligands was used.

[0162] Next, an ITO film was formed as the upper electrode on the photoelectric conversion layer by sputtering to a film thickness of 30 nm, and then an Al2O3 film was formed on the upper electrode by atomic layer deposition as a sealing film, thereby obtaining the photoelectric conversion element of Example 1.

[0163] [Comparative Example 1] In the production of the photoelectric conversion element, a photoelectric conversion element of Comparative Example 1 was obtained using the same steps as in Example 1, except that the electron blocking layer 4 was not formed.

[0164] [Comparative Example 2] In the production of the photoelectric conversion element, a photoelectric conversion element of Comparative Example 2 was obtained using the same steps as in Example 1, except that the first solution was used for both the electron blocking layer 3 and the electron blocking layer 4.

[0165] [Comparative Example 3] In the production of the photoelectric conversion element, a photoelectric conversion element of Comparative Example 3 was obtained using the same steps as in Example 1, except that the third solution was used instead of the first solution for the electron blocking layer 3 and the first solution was used instead of the third solution for the electron blocking layer 4.

[0166] (Measurement of Dark Current) For the obtained photoelectric conversion element, the dark current was measured. A B1500A semiconductor device parameter analyzer (manufactured by Keysight Technologies) was used for the measurement. More specifically, the dark current was measured when a forward bias of -0.2 V was applied to the upper electrode with reference to the ITO electrode on the glass substrate side under a nitrogen atmosphere. The relative dark current, which is the ratio of the dark current to Comparative Example 1, was calculated using the following formula (1). (Relative dark current) = (Dark current value of each photoelectric conversion element) ÷ (Dark current value of Comparative Example 1) (1)

[0167] (Measurement of spectral sensitivity) For the photoelectric conversion elements in Example 1 and Comparative Examples 1 to 3, the spectral sensitivity was measured. Specifically, in a glove box under a nitrogen atmosphere, the photoelectric conversion element was introduced into a measurement jig that could be sealed, and the spectral sensitivity was measured using a spectral sensitivity measuring device (manufactured by a spectrometer). At that time, the external quantum efficiency with respect to light of 450 nm was measured under the condition of applying a reverse bias of 5 V. The relative external quantum efficiency, which is the ratio of the quantum efficiency to Comparative Example 1, was calculated using the following formula (2). (Relative external quantum efficiency) = (External quantum efficiency of each photoelectric conversion element) ÷ (External quantum efficiency of Comparative Example 1) (2)

[0168] (Evaluation results) Table 1 shows the results of the relative dark current and relative external quantum efficiency of the photoelectric conversion elements in Example 1 and Comparative Examples 1 to 3. As shown in Table 1, in Example 1, a low dark current was obtained because the charge injection from the electrode during forward bias was small. Also, a high external quantum efficiency was obtained because the resistance of the electron blocking layer was low due to doping. In Comparative Example 2, although a low dark current was obtained, the external quantum efficiency was low because the resistance of the electron blocking layer was high. In Comparative Example 3, although a high external quantum efficiency was obtained, the dark current was high because charge was easily injected from the electrode during forward bias.

Table 1

[0169] As described above, by the method of the present disclosure, a small dark current and a high external quantum efficiency during forward bias can be achieved simultaneously, and a global shutter function with a high S / N ratio can be realized.

[0170] As described above, the imaging device according to the present disclosure has been described based on the embodiments. However, the present disclosure is not limited to these embodiments. Without departing from the gist of the present disclosure, various modifications conceived by those skilled in the art to the embodiments and examples, as well as other forms constructed by combining some components in the embodiments and examples, are also included in the scope of the present disclosure.

Industrial Applicability

[0171] The photoelectric conversion element according to the present disclosure is useful for image sensors and the like used in various imaging devices typified by digital cameras.

Explanation of Signs

[0172] 1 Support substrate 2 Lower electrode 3, 4, 7, 7A, 8, 9 Electron blocking layer 5 Photoelectric conversion layer 5A Donor material 5B Acceptor material 6 Upper electrode 10, 11 Photoelectric conversion element 10A Photoelectric conversion section 19 Voltage supply circuit 20 Horizontal signal readout circuit 21 Amplification transistor 22 Reset transistor 23 Address transistor 21G, 22G, 23G Gate electrode 21D, 21S, 22D, 22S, 23S Impurity region 21X, 22X, 23X Gate insulating layer 24 Pixel 25 Vertical scanning circuit 26 Counter electrode signal line 27 Vertical signal line 28 Load circuit 29 Column signal processing circuit 31 Power supply wiring 32 Differential amplifier 33 Feedback line 34 Charge storage node 35 Charge detection circuit 36 Address signal line 37 Reset signal line 40 Semiconductor substrate 41 Element isolation region 50 Interlayer insulation layer 51, 53, 54 Contact plug 52 Wiring 60 Color filter 61 Microlens 100 Imaging device

Claims

1. A plurality of pixels, a voltage supply circuit, and includes, each of the plurality of pixels, a pixel electrode, a counter electrode, a photoelectric conversion layer located between the pixel electrode and the counter electrode, which generates electrons and holes, a charge blocking layer located between the pixel electrode and the photoelectric conversion layer, and includes, the charge blocking layer contains impurities, the impurity concentration of the second region including the second surface on the photoelectric conversion layer side of the charge blocking layer is higher than the impurity concentration of the first region including the first surface on the pixel electrode side in the charge blocking layer, the voltage supply circuit supplies a first voltage that gives a first potential difference between the counter electrode and the pixel electrode in a first period, and supplies a second voltage that gives a second potential difference different from the first potential difference between the counter electrode and the pixel electrode in a second period, the charge blocking layer, a first layer containing a first material, a second layer containing a second material and doped with impurities, and includes, the first layer is in contact with the pixel electrode and has the first region, the second layer is located between the first layer and the photoelectric conversion layer and has the second region, an imaging device.

2. The photoelectric conversion efficiency of the plurality of pixels in the first period is different from the photoelectric conversion efficiency of the plurality of pixels in the second period, The imaging device according to claim 1.

3. The imaging device operates in a global shutter mode in which all exposure periods of the plurality of pixels are unified, The exposure period is a period for accumulating one of the electrons and holes generated in the photoelectric conversion layer, The imaging device according to claim 1 or 2.

4. The first period is the exposure period, The second period is a non-exposure period that is a period other than the exposure period during the operation of the imaging device, The imaging device according to claim 3.

5. When the second voltage is supplied between the counter electrode and the pixel electrode, the electrons and holes in the photoelectric conversion layer recombine, The imaging device according to claim 4.

6. When the first voltage is supplied between the counter electrode and the pixel electrode, the sensitivity of photoelectric conversion occurs in the photoelectric conversion layer, The imaging device according to claim 4 or 5.

7. The voltage supply circuit selectively applies a voltage that makes the potential of the counter electrode with respect to the pixel electrode positive or negative between the counter electrode and the pixel electrode, The imaging device according to any one of claims 1 to 6.

8. The thickness of the first layer is thinner than the thickness of the second layer. The imaging device according to any one of claims 1 to 7.

9. The thickness of the first layer is thicker than the thickness of the second layer. The imaging device according to any one of claims 1 to 7.

10. The second layer is in contact with the photoelectric conversion layer. The imaging device according to any one of claims 1 to 9.

11. The charge blocking layer further includes a third layer located between the second layer and the photoelectric conversion layer and containing a third material. The imaging device according to any one of claims 1 to 9.

12. The second layer contains a counter anion. The imaging device according to any one of claims 1 to 11.

13. The thickness of the first layer is 10 nm or more. The imaging device according to any one of claims 1 to 12.

14. The carrier density in the first layer is less than 1×10 １６ cm －３ minus The imaging device according to any one of claims 1 to 13.

15. The thickness of the second layer is 10 nm or more. The imaging device according to any one of claims 1 to 14.

16. The carrier density in the second layer is 1×10 １６ cm －３ or more. The imaging device according to any one of claims 1 to 15.

17. The charge blocking layer is an electron blocking layer. The photoelectric conversion layer contains an acceptor material. The energy level of the LUMO (Lowest-Undoccupied-Molecular-Orbital) of the electron blocking layer is smaller than the energy level of the LUMO of the acceptor material. The imaging device according to any one of claims 1 to 16.

18. The impurity is an acceptor impurity. The imaging device according to any one of claims 1 to 17.

19. Furthermore, an amplification transistor is provided. The pixel electrode is connected to the gate electrode of the amplification transistor. The imaging device according to any one of claims 1 to 18.

20. A driving method for a plurality of pixels in the imaging device according to any one of claims 1 to 19, applying a voltage between the counter electrode and the pixel electrode such that the potential of the counter electrode with respect to the pixel electrode becomes a positive potential, and applying a voltage between the counter electrode and the pixel electrode such that the potential of the counter electrode with respect to the pixel electrode becomes a negative potential. Driving method.

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