Solar cell and method for manufacturing solar cell

Abstract

Provided is a solar cell with improved reliability. In the solar cell, a textured structure having a pyramid-shaped microrelief structure is formed on the back surface side of a semiconductor substrate 11. In a first region-side boundary region of a second region on the back surface side of the semiconductor substrate 11, each slanting face of each pyramid 11A has a first slanting face SF1 from a pyramid foot 1A to a halfway point 2A, and a second slanting face SF2 from the halfway point 2A to a pyramid peak 3A. The slope of the second slanting face SF2 is gentler than the slope of the first slanting face SF1. The minimum angle θ formed by the straight line from the pyramid foot 1A to the pyramid peak 3A and the straight line from the pyramid foot 1A to the bending point of the halfway point 2A is 8 < θ ≤ 30. The pyramids 11A occupy 0.01-50% (inclusive) of the area of the back surface, and the thickness of a second semiconductor layer 35, 33 on the second slanting face SF2 is larger than the thickness of the second semiconductor layer 35, 33 on the first slanting face SF1.

Description

Technical Field

[0001] The present invention relates to a back-contact type solar cell and a method for manufacturing the same.

Background Art

[0002] As solar cells using a semiconductor substrate, there are a double-sided electrode type solar cell in which electrodes are formed on both the light-receiving surface side and the back surface side, and a back-contact type solar cell in which electrodes are formed only on the back surface side. In the double-sided electrode type solar cell, since an electrode is formed on the light-receiving surface side, sunlight is blocked by this electrode. On the other hand, in the back-contact type solar cell, since no electrode is formed on the light-receiving surface side, the light reception rate of sunlight is higher than that of the double-sided electrode type solar cell. Patent Document 1 discloses a back-contact type solar cell.

[0003] The solar cell described in Patent Document 1 includes a semiconductor substrate having a textured structure with a pyramidal fine concavo-convex structure formed on both the light-receiving surface side and the back surface side. The slope of the pyramid on the back surface side has a first slope from the mountain foot to the middle part and a second slope from the middle part to the mountain top, and the second slope has a different inclination angle from the first slope. Thereby, in the light that has entered the semiconductor substrate from the light-receiving surface side, even when the light reflected by the first slope, for example, passes through to the outside, the light reflected by the second slope is less likely to pass through to the outside. Therefore, the photoelectric conversion efficiency of the solar cell can be improved.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] By the way, in a back electrode type solar cell, it is desired to improve the reliability resulting from the exposure of the semiconductor layer between electrodes with different polarities.

[0006] An object of the present invention is to provide a solar cell with improved reliability and a method for manufacturing the same.

Means for Solving the Problems

[0007] The solar cell according to the present invention is a back electrode type solar cell including a semiconductor substrate, a first semiconductor layer and a first electrode layer sequentially laminated on a first region which is a part of the other main surface side opposite to one main surface side of the semiconductor substrate, and a second semiconductor layer and a second electrode layer sequentially laminated on a second region which is another part of the other main surface side of the semiconductor substrate, wherein a texture structure having a pyramidal fine concavo-convex structure is formed on at least the other main surface side of the semiconductor substrate, and in a boundary region on the first region side in the second region on the other main surface side of the semiconductor substrate, the slope of the pyramid has a first slope from the foot of the mountain to the middle part and a second slope from the middle part to the top of the mountain, the inclination of the second slope is gentler than the inclination of the first slope, in a cross section orthogonal to the foot of the mountain passing through the top of the mountain, the minimum angle θ [°] formed by a first virtual straight line from the foot of the mountain to the top of the mountain and a second virtual straight line from the foot of the mountain to the bending point of the middle part is 8 < θ ≦ 30, the pyramid occupies 0.01% or more and 50% or less of the area of the other main surface, the film thickness of the second semiconductor layer on the second slope is thicker than the film thickness of the second semiconductor layer on the first slope.

[0008] Another solar cell according to the present invention includes a semiconductor substrate, a first semiconductor layer and a first electrode layer sequentially stacked on a first region which is a part of the other main surface side opposite to one main surface side of the semiconductor substrate, and a second semiconductor layer and a second electrode layer sequentially stacked on a second region which is another part of the other main surface side of the semiconductor substrate, and is a back electrode type solar cell, wherein a texture structure having a pyramidal fine concavo-convex structure is formed on at least the other main surface side of the semiconductor substrate, and at a boundary region on the first region side in the second region on the other main surface side of the semiconductor substrate, the slope of the pyramid has a first slope from the foot of the mountain to the middle part and a second slope from the middle part to the peak, the inclination of the second slope is gentler than the inclination of the first slope, at least a part of the first slope is sequentially stacked with the first semiconductor layer and the second semiconductor layer, the film thickness of the second semiconductor layer on the second slope is thicker than the film thickness of the second semiconductor layer on the first slope.

[0009] The manufacturing method of the solar cell according to the present invention is a manufacturing method of a back contact type solar cell including a semiconductor substrate, a first semiconductor layer and a first electrode layer sequentially stacked on a first region which is a part of the other main surface side opposite to one main surface side of the semiconductor substrate, and a second semiconductor layer and a second electrode layer sequentially stacked on a second region which is another part of the other main surface side of the semiconductor substrate, the method including: forming a texture structure having a pyramidal fine concavo-convex structure on at least the other main surface side of the semiconductor substrate; forming a first semiconductor layer material film which is a material film of the first semiconductor layer on the other main surface side of the semiconductor substrate; forming a resist on the material film of the first semiconductor layer in the first region; removing the material film of the first semiconductor layer in the second region using the resist as a mask to form the patterned first semiconductor layer in the first region, and removing the resist, which is a first semiconductor layer forming step; and forming the patterned second semiconductor layer in the second region, which is a second semiconductor layer forming step. In the resist forming step, the resist is formed in the first region by printing and curing a printing material containing a resin material using a pattern printing method, and a bleeding film formed by bleeding of the printing material is formed on a first slope from a skirt to a middle part of the pyramid in a boundary region (bleeding region of the printed resist) on the first region side in the second region. In the first semiconductor layer forming step, by etching the material film of the first semiconductor layer using the resist and the bleeding film at its periphery as a mask, in a boundary region on the first region side in the second region, the slope of the pyramid has a first slope from a skirt to a middle part and a second slope from the middle part to a peak, the inclination of the second slope is gentler than the inclination of the first slope, in a cross section passing through the peak and orthogonal to the skirt, a minimum angle θ [°] formed by a first virtual straight line from the skirt to the peak and a second virtual straight line from the skirt to a bending point of the middle part is 8 < θ ≤ 30, the pyramid occupies 0.01% or more and 50% or less of the area of the other main surface, Form the pyramid. In the second semiconductor layer forming step, in the boundary region (bleed-out region of the printing resist) on the first region side in the second region, form the second semiconductor layer in which the film thickness on the second slope is thicker than the film thickness on the first slope.

[0010] Another method for manufacturing a solar cell according to the present invention is a method for manufacturing a back electrode type solar cell including a semiconductor substrate, a first semiconductor layer and a first electrode layer sequentially laminated on a first region which is a part of the other main surface side opposite to one main surface side of the semiconductor substrate, and a second semiconductor layer and a second electrode layer sequentially laminated on a second region which is another part of the other main surface side of the semiconductor substrate, the method including: forming a texture structure having a pyramid-shaped fine concavo-convex structure on at least the other main surface side of the semiconductor substrate; forming a first semiconductor layer material film which is a material film of the first semiconductor layer on the other main surface side of the semiconductor substrate; forming a resist on the material film of the first semiconductor layer in the first region; removing the material film of the first semiconductor layer in the second region using the resist as a mask to form the patterned first semiconductor layer in the first region, and removing the resist, which is a first semiconductor layer forming step; and forming the patterned second semiconductor layer in the second region, which is a second semiconductor layer forming step. In the resist forming step, by printing and curing a printing material containing a resin material using a pattern printing method, form the resist in the first region and form a bleed-out film formed by bleeding of the printing material on a first slope from the foot to the middle of the pyramid in the boundary region on the first region side in the second region. In the first semiconductor layer forming step, by etching the material film of the first semiconductor layer using the resist and the bleed-out film at its periphery as a mask, in the boundary region on the first region side in the second region, The slope of the pyramid has a first slope from the foot to the middle and a second slope from the middle to the top. The inclination of the second slope is gentler than the inclination of the first slope. At least a part of the first inclined surface is laminated with the first semiconductor layer. The pyramid is formed. In the second semiconductor layer forming step, in the boundary region on the first region side in the second region, the second semiconductor layer is formed on the first semiconductor layer on the first inclined surface, and the second semiconductor layer having a thickness thicker than that of the first inclined surface is formed on the second inclined surface.

Advantages of the Invention

[0011] According to the present invention, it is possible to improve the reliability of the solar cell.

Brief Description of the Drawings

[0012]

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[0013] Hereinafter, an example of an embodiment of the present invention will be described with reference to the accompanying drawings. In each drawing, the same or corresponding parts will be denoted by the same reference numerals. Also, for the sake of convenience, hatching, member reference numerals, etc. may be omitted, but in such a case, other drawings shall be referred to.

[0014] [First Embodiment] (Solar Cell) FIG. 1 is a view of a solar cell according to the first embodiment as seen from the back side. The solar cell 1 shown in FIG. 1 is a back-contact type (also referred to as a back-contact type or a back-junction type) solar cell. The solar cell 1 includes a semiconductor substrate 11 having two main surfaces, and has a first region 7 and a second region 8 on the main surfaces of the semiconductor substrate 11.

[0015] The first region 7 has a so-called comb shape, and has a plurality of finger portions 7f corresponding to comb teeth and a bus bar portion 7b corresponding to a support portion of the comb teeth. The bus bar portion 7b extends in a first direction (X direction) along one side portion of the semiconductor substrate 11, and the finger portions 7f extend from the bus bar portion 7b in a second direction (Y direction) intersecting the first direction (X direction).

[0016] Similarly, the second region 8 has a so-called comb shape, and includes a plurality of finger portions 8f corresponding to comb teeth and a bus bar portion 8b corresponding to a support portion of the comb teeth. The bus bar portion 8b extends in the first direction (X direction) along the other side portion of the semiconductor substrate 11 that faces one side portion, and the finger portions 8f extend from the bus bar portion 8b in the second direction (Y direction).

[0017] The finger portion 7f and the finger portion 8f are alternately provided in the first direction (X direction). Note that the first region 7 and the second region 8 may be formed in a stripe shape.

[0018] FIG. 2 is a cross-sectional view taken along line II-II of the solar cell in FIG. 1. As shown in FIG. 2, the solar cell 1 is a heterojunction solar cell. The solar cell 1 includes a semiconductor substrate 11, an intrinsic semiconductor layer 13 and an optical adjustment layer 15 that are sequentially laminated on one main surface of the semiconductor substrate 11, which is the light-receiving side of the main surfaces. Further, the solar cell 1 includes an intrinsic semiconductor layer 23, a first conductivity type semiconductor layer 25, and a first electrode layer 27 that are sequentially laminated on a part (first region 7) of the other main surface of the semiconductor substrate 11, which is the back surface side opposite to the light-receiving surface. Further, the solar cell 1 includes an intrinsic semiconductor layer 33, a second conductivity type semiconductor layer 35, and a second electrode layer 37 that are sequentially laminated on another part (second region 8) of the back surface side of the semiconductor substrate 11. Further, as will be described later, in the vicinity of the boundary between the first region 7 and the second region 8, the region including both the first conductivity type semiconductor layer 25 and the second conductivity type semiconductor layer 35 is the second region 8. Hereinafter, the intrinsic semiconductor layer 23 and the first conductivity type semiconductor layer 25 are also referred to as the first semiconductor layer, and the intrinsic semiconductor layer 33 and the second conductivity type semiconductor layer 35 are also referred to as the second semiconductor layer.

[0019] The semiconductor substrate 11 is formed of a crystalline silicon material such as single-crystalline silicon or polycrystalline silicon. The semiconductor substrate 11 is, for example, an n-type semiconductor substrate in which an n-type dopant is doped into a crystalline silicon material. Note that the semiconductor substrate 11 may be, for example, a p-type semiconductor substrate in which a p-type dopant is doped into a crystalline silicon material. Examples of the n-type dopant include phosphorus (P). Examples of the p-type dopant include boron (B). The semiconductor substrate 11 functions as a photoelectric conversion substrate that absorbs incident light from the light-receiving surface side and generates optical carriers (electrons and holes).

[0020] By using crystalline silicon as the material of the semiconductor substrate 11, the dark current is relatively small, and a relatively high output (stable output regardless of illuminance) can be obtained even when the intensity of the incident light is low.

[0021] The semiconductor substrate 11 has a pyramidal fine concavo-convex structure called a texture structure on the back surface side. Thereby, the recovery efficiency of the light that has passed through without being absorbed by the semiconductor substrate 11 is increased.

[0022] Also, the semiconductor substrate 11 may have a pyramidal fine concavo-convex structure called a texture structure on the light-receiving surface side. Thereby, the reflection of the incident light on the light-receiving surface is reduced, and the light confinement effect in the semiconductor substrate 11 is improved.

[0023] The intrinsic semiconductor layer 13 is formed on the light-receiving surface side of the semiconductor substrate 11. The intrinsic semiconductor layer 23 is formed in the first region 7 on the back surface side of the semiconductor substrate 11. The intrinsic semiconductor layer 33 is formed in the second region 8 on the back surface side of the semiconductor substrate 11. The intrinsic semiconductor layers 13, 23, and 33 are formed of a material mainly composed of, for example, intrinsic (i-type) amorphous silicon. The intrinsic semiconductor layers 13, 23, and 33 function as so-called passivation layers, suppress the recombination of carriers generated in the semiconductor substrate 11, and increase the recovery efficiency of carriers.

[0024] The optical adjustment layer 15 is formed on the intrinsic semiconductor layer 13 on the light-receiving surface side of the semiconductor substrate 11. The optical adjustment layer 15 functions as an antireflection layer that prevents reflection of incident light and also functions as a protective layer that protects the light-receiving surface side of the semiconductor substrate 11 and the intrinsic semiconductor layer 13. The optical adjustment layer 15 is formed of an insulator material such as silicon oxide (SiO), silicon nitride (SiN), or a composite thereof such as silicon oxynitride (SiON).

[0025] The first-conductivity-type semiconductor layer 25 is formed on the intrinsic semiconductor layer 23, that is, in the first region 7 on the back surface side of the semiconductor substrate 11. The first-conductivity-type semiconductor layer 25 is formed of, for example, an amorphous silicon material. The first-conductivity-type semiconductor layer 25 is a p-type semiconductor layer in which, for example, a p-type dopant (e.g., boron (B) described above) is doped into an amorphous silicon material.

[0026] The second-conductivity-type semiconductor layer 35 is formed on the intrinsic semiconductor layer 33, that is, in the second region 8 on the back surface side of the semiconductor substrate 11. The second-conductivity-type semiconductor layer 35 is formed of, for example, an amorphous silicon material. The second-conductivity-type semiconductor layer 35 is an n-type semiconductor layer in which, for example, an n-type dopant (e.g., phosphorus (P) described above) is doped into an amorphous silicon material. Note that the first-conductivity-type semiconductor layer 25 may be an n-type semiconductor layer and the second-conductivity-type semiconductor layer 35 may be a p-type semiconductor layer.

[0027] The first electrode layer 27 is formed on the first-conductivity-type semiconductor layer 25, and the second electrode layer 37 is formed on the second-conductivity-type semiconductor layer 35. The first electrode layer 27 has a transparent electrode layer 28 and a metal electrode layer 29 laminated in order on the first-conductivity-type semiconductor layer 25. The second electrode layer 37 has a transparent electrode layer 38 and a metal electrode layer 39 laminated in order on the second-conductivity-type semiconductor layer 35.

[0028] The transparent electrode layers 28 and 38 are formed of a transparent conductive material. Examples of the transparent conductive material include ITO (Indium Tin Oxide, a composite oxide of indium oxide and tin oxide) and ZnO (Zinc Oxide). The metal electrode layers 29 and 39 are formed of a conductive paste material containing metal powder such as silver or copper.

[0029] FIG. 3 is an enlarged cross-sectional view of the boundary region III between the first region 7 and the second region 8 shown in FIG. 2. FIG. 4A is an enlarged cross-sectional view of the back surface of the semiconductor substrate 11 in a part VA of the boundary region 8A (the bleeding region of the pattern printing resist to be described later) on the first region 7 side in the second region 8 shown in FIG. 3, and FIG. 5A is an enlarged cross-sectional view of the semiconductor layers 35 and 33 in a part VA of the boundary region 8A (the bleeding region of the pattern printing resist to be described later) on the first region 7 side in the second region 8 shown in FIG. 3. Further, FIG. 4B is an enlarged cross-sectional view of the back surface of the semiconductor substrate 11 in a part VB other than the boundary region 8A in the second region 8 shown in FIG. 3, and FIG. 5B is an enlarged cross-sectional view of the semiconductor layers 35 and 33 in a part VB other than the boundary region 8A in the second region 8 shown in FIG. 3.

[0030] As shown in FIGS. 3 and 4A, a plurality of pyramids 11A each composed of four slopes are formed in the boundary region 8A (the bleeding region of the pattern printing resist) on the first region 7 side in the second region 8 on the back surface side of the semiconductor substrate 11.

[0031] Each slope of the pyramid 11A has a first slope SF1 from the base 1A to the middle 2A and a second slope SF2 from the middle 2A to the apex 3A. The first slope SF1 and the second slope SF2 have different inclination angles with the inflection point of the middle 2A as the boundary. The inclination of the second slope SF2 is gentler than that of the first slope SF1.

[0032] In a cross section passing through the apex 3A and orthogonal to the base 1A (that is, the cross section shown in FIG. 4A), the minimum angle θ [°] formed by a first virtual straight line L1 from the base 1A to the apex 3A and a second virtual straight line L2 from the base 1A to the inflection point of the middle 2A satisfies 8 < θ ≦ 30.

[0033] Such a pyramid 11A occupies 0.01% or more and 50% or less of the area of the back surface of the semiconductor substrate 11.

[0034] On the other hand, as shown in FIGS. 3 and 4B, in the region other than the boundary region 8A in the second region 8 on the back surface side of the semiconductor substrate 11, a plurality of pyramids 11B each composed of four slopes are formed. In FIG. 4B, for comparison, the first slope SF1 and the second slope SF2 of the above-described pyramid 11A are shown by broken lines.

[0035] Each slope of the pyramid 11B has a third slope SF3 without a bending point from the foot of the mountain 1B to the peak of the mountain 3B. The inclination of the third slope SF3 is gentler than the inclination of the first slope SF1 described above.

[0036] Thereby, the following relationship holds for the inclinations of the first slope SF1 and the second slope SF2 of the pyramid 11A. Inclination of the second slope SF2 < Inclination of the first slope SF1

[0037] As shown in FIG. 5A, in the boundary region 8A (bleed-out region of the pattern printing resist) on the first region 7 side in the second region 8 on the back surface side of the semiconductor substrate 11, the film thicknesses of the second intrinsic semiconductor layer 33 and the second conductivity type semiconductor layer 35 (second semiconductor layer) on the second slope SF2 of the pyramid 11A are thicker than the film thicknesses of the second intrinsic semiconductor layer 33 and the second conductivity type semiconductor layer 35 (second semiconductor layer) on the first slope SF1 of the pyramid 11A.

[0038] The value obtained by dividing the film thicknesses of the second intrinsic semiconductor layer 33 and the second conductivity type semiconductor layer 35 (second semiconductor layer) on the second slope SF2 of the pyramid 11A by the film thicknesses of the second intrinsic semiconductor layer 33 and the second conductivity type semiconductor layer 35 (second semiconductor layer) on the first slope SF1 of the pyramid 11A is preferably 1.02 or more and 1.80 or less, more preferably 1.03 or more and 1.60 or less, and still more preferably 1.05 or more and 1.40 or less.

[0039] Here, the film thickness of the semiconductor layer is the film thickness in the direction orthogonal to the slope of the pyramid of the semiconductor substrate 11. The film thickness at the first slope SF1 is measured at the midpoint PA1 between the foot of the mountain 1A and the inflection point (midriff) 2A, and the film thickness at the second slope SF2 is measured at the midpoint PA2 between the peak 3A of the pyramid and the inflection point (midriff) 2A. When there are two or more inflection points, the inflection point closest to the peak is used for film thickness measurement.

[0040] In a back-contact type solar cell, a first semiconductor region and a second semiconductor region exist on the back surface, and they have an adjacent structure. The existence of the boundary between the first semiconductor region and the second semiconductor region on the back surface is a structure peculiar to the back-contact type solar cell. The structure around the boundary region greatly affects the reliability of the solar cell. Even if the area is small in the boundary region, it has the structure of the pyramid A described above, and by having the film thickness ratio between the first slope SF1 and the second slope SF2, the reliability can be improved.

[0041] On the other hand, as shown in FIG. 5B, in the region other than the boundary region 8A in the second region 8 on the back surface side of the semiconductor substrate 11, since there is no inflection like that of the pyramid 11A on the third slope SF3 of the pyramid 11B, among the three points PB1, PB2, and PB3 that divide the foot of the mountain 1B and the peak 3B of the third slope SF3 into four equal parts, the film thicknesses of the first point PB3 and the third point PB1 from the peak 3B are measured.

[0042] As a result, the following relationship holds for the film thicknesses of the second semiconductor layers 35 and 33 on the first slope SF1 and the second slope SF2 of the pyramid 11A, and the film thickness of the second semiconductor layer on the third slope SF3 of the pyramid 11B. Film thickness of the second semiconductor layers 35 and 33 on the second slope SF2 / Film thickness of the second semiconductor layers 35 and 33 on the first slope SF1 > Film thickness of the second semiconductor layer at the midpoint PB3 between the midpoint PB2 between the foot of the mountain 1B and the peak 3B of the third slope SF3 and the peak 3B / Film thickness of the second semiconductor layer at the midpoint PB1 between the midpoint PB2 between the foot of the mountain 1B and the peak 3B of the third slope SF3 and the foot of the mountain 1B

[0043] As shown in FIG. 3, the boundary region 8A on the side of the first region 7 in the second region 8 is located between the transparent electrode layer 28 of the first electrode layer 27 and the transparent electrode layer 38 of the second electrode layer 37, and may be located under the transparent electrode layer 28 of the first electrode layer 27 in the transparent electrode layer 38 of the second electrode layer 37.

[0044] (Method for manufacturing a solar cell)

[0045] Hereinafter, with reference to FIGS. 6A to 6H, a method for manufacturing the solar cell 1 according to the first embodiment will be described. FIG. 6A is a diagram showing a first semiconductor layer material film forming step and a lift-off layer forming step in the method for manufacturing a solar cell according to the first embodiment, and FIGS. 6B to 6D are diagrams showing a first semiconductor layer forming step in the method for manufacturing a solar cell according to the first embodiment. Further, FIG. 6E is a diagram showing a second semiconductor layer material film forming step in the method for manufacturing a solar cell according to the first embodiment, and FIG. 6F is a diagram showing a second semiconductor layer forming step in the method for manufacturing a solar cell according to the first embodiment. Further, FIG. 6G is a diagram showing an electrode layer forming step in the method for manufacturing a solar cell according to the first embodiment, and FIG. 6H is a diagram showing an optical adjustment layer forming step in the method for manufacturing a solar cell according to the first embodiment.

[0046] First, at least on the back surface side of the semiconductor substrate 11, anisotropic etching is performed to form a texture structure having a pyramid-shaped fine concavo-convex structure. Examples of the etching solution include an alkaline solution such as an aqueous potassium hydroxide solution.

[0047] Next, as shown in FIG. 6A, for example, using the CVD method (chemical vapor deposition method), an intrinsic semiconductor layer material film 23Z and a first conductivity type semiconductor layer material film 25Z are sequentially laminated (film-formed) on the entire back surface side of the semiconductor substrate 11 (first semiconductor layer material film forming step).

[0048] Further, for example, using the CVD method, an intrinsic semiconductor layer 13 is laminated (film-formed) on the entire light-receiving surface side of the semiconductor substrate 11. Note that the film-forming order of the intrinsic semiconductor layer material film 23Z and the first conductivity type semiconductor layer material film 25Z and the intrinsic semiconductor layer 13 is not limited.

[0049] Also, the intrinsic semiconductor layer 13 on the light-receiving surface side may be formed in a later second semiconductor layer material film forming step. In this case, the intrinsic semiconductor layer on the light-receiving surface side formed at this stage may be removed in a later first semiconductor layer forming step. Alternatively, an intrinsic semiconductor layer may not be formed on the light-receiving surface side at this stage, that is, there may be no intrinsic semiconductor layer forming step at this stage.

[0050] Next, for example, using a CVD method, a lift-off layer (sacrificial layer) 41 is laminated (formed) on the entire back surface side of the semiconductor substrate 11, specifically, on the entire surface of the first conductivity type semiconductor layer material film 25Z (lift-off layer forming step). The lift-off layer 41 is formed of a material such as silicon oxide (SiO), silicon nitride (SiN), or a composite thereof such as silicon oxynitride (SiON).

[0051] Next, as shown in FIGS. 6B to 6D, by removing the intrinsic semiconductor layer material film 23Z, the first conductivity type semiconductor layer material film 25Z, and the lift-off layer 41 in the second region 8 on the back surface side of the semiconductor substrate 11 using a pattern printing resist, a patterned intrinsic semiconductor layer 23, a first conductivity type semiconductor layer 25, and a lift-off layer 41 are formed in the first region 7 (first semiconductor layer forming step).

[0052] Specifically, as shown in FIG. 6B, a pattern printing resist 90 is formed on the entire back surface side of the first region 7 of the semiconductor substrate 11 and on the entire light-receiving surface side of the semiconductor substrate 11 using a pattern printing method (resist forming step).

[0053] Pattern printing means a printing method in which, unlike the photolithography method, a patterned resist (printing material) is directly attached to the resist attachment surface, such as press printing like screen printing or gravure printing, or ejection printing like inkjet printing, without forming a resist film (non-patterned resist film) before patterning and then undergoing processes such as exposure and development.

[0054] Thus, in the patterning of the first conductivity type semiconductor layer (the first patterning), by using a pattern printing resist by a pattern printing method, the exposure and development processes can be reduced as compared with the case of using a photoresist by a spin coating method (photolithography method), and the manufacturing process of the solar cell can be simplified.

[0055] The pattern printing resist 90 is obtained by printing and curing a printing material containing a resin material and an inorganic material. At this time, a part of the printing material oozes out from the printing material printed in the first region 7. The printing material may contain a solvent component, and the curing process may be not only by heating but also by curing with light. Further, in the curing process, it is not always necessary for the resin component to be cured by crosslinking or the like, and it means that the shape is maintained at room temperature and the solvent resistance is obtained due to the increase in viscosity accompanying the volatilization of the solvent, that is, it becomes a state having a function as a resist.

[0056] FIG. 7A is an enlarged view of a boundary region VIIA between the first region 7 and the second region 8 shown in FIG. 6B. As shown in FIG. 7A, the oozed resist material covers the troughs of the pyramids 11A in a boundary region 8A (the oozing region of the pattern printing resist) on the first region 7 side in the second region 8.

[0057] More specifically, as shown in FIG. 8, the oozing film 90A formed by the oozing of the printing material is formed so as to cover a first slope SF1 from the foot 1A to the middle part 2A of the pyramid 11A in a boundary region 8A (the oozing region of the pattern printing resist) on the first region 7 side in the second region 8.

[0058] Here, the film thickness of the pattern printing resist 90 is 3 μm or more and 50 μm or less, while the height of the pyramid 11A is 0.1 μm or more and 15 μm or less. The height of the pyramid is the height from the foot to the top, and the film thickness of the pattern printing resist 90 is the film thickness from the foot of the pyramid.

[0059] Thereafter, as shown in FIG. 6C, by using the pattern printed resist 90 and the bleeding film 90A at its periphery as a mask to etch the lift-off layer 41, the first conductivity type semiconductor layer material film 25Z, and the intrinsic semiconductor layer material film 23Z in the second region 8, a patterned intrinsic semiconductor layer 23, a first conductivity type semiconductor layer 25, and a lift-off layer 41 are formed in the first region 7.

[0060] Examples of the etching solution for the lift-off layer 41 include acidic solutions such as a mixed solution of ozone dissolved in hydrofluoric acid or a mixed solution of hydrofluoric acid and nitric acid. Examples of the etching solution for the p-type semiconductor layer material film also include acidic solutions such as a mixed solution of ozone dissolved in hydrofluoric acid or a mixed solution of hydrofluoric acid and nitric acid, and examples of the etching solution for the n-type semiconductor layer material film include alkaline solutions such as an aqueous potassium hydroxide solution.

[0061] FIG. 7B is an enlarged view of the boundary region VIIB between the first region 7 and the second region 8 shown in FIG. 6C. As shown in FIG. 7B, in the boundary region 8A (the bleeding region of the pattern printed resist) on the first region 7 side in the second region 8 covered with the bleeding film 90A, most of the lift-off layer 41, the first conductivity type semiconductor layer material film 25Z, and the intrinsic semiconductor layer material film 23Z are etched by under-etching.

[0062] FIGS. 4A and 8 described above correspond to an enlarged cross-sectional view of a part IVA of the boundary region 8A on the first region 7 side in the second region 8 shown in FIG. 7B, and FIG. 4B described above corresponds to an enlarged cross-sectional view of a part IVB other than the boundary region 8A in the second region 8 shown in FIG. 7B.

[0063] As shown in FIGS. 4A and 8, in the boundary region 8A (the bleeding region of the pattern printed resist) on the first region 7 side in the second region 8 on the back side of the semiconductor substrate 11, the skirt side of the pyramid 11A covered by the bleeding film 90A is not etched, and the top side not covered by the bleeding film 90A is etched.

[0064] As a result, each slope of the pyramid 11A has a first slope SF1 from the mountain foot 1A to the middle part 2A and a second slope SF2 from the middle part 2A to the mountain top 3A. The first slope SF1 and the second slope SF2 have different inclination angles with the inflection point of the middle part 2A as the boundary. The inclination of the second slope SF2 is gentler than that of the first slope SF1.

[0065] In a cross-section orthogonal to the mountain foot 1A passing through the mountain top 3A (that is, the cross-section shown in FIGS. 4A and 8), the minimum angle θ [°] formed by the first virtual straight line L1 from the mountain foot 1A to the mountain top 3A and the second virtual straight line L2 from the mountain foot 1A to the inflection point of the middle part 2A satisfies 8 < θ ≤ 30.

[0066] Such a pyramid 11A occupies 0.01% or more and 50% or less of the area of the back surface of the semiconductor substrate 11.

[0067] On the other hand, as shown in FIG. 4B, in the region other than the boundary region 8A in the second region 8 on the back surface side of the semiconductor substrate 11, the pyramid 11B is not covered by the bleeding film 90A, so it is etched as a whole.

[0068] As a result, each slope of the pyramid 11B has a third slope SF3 without an inflection point from the mountain foot 1B to the mountain top 3B. In the pyramid 11B, since the slope is etched as a whole, the inclination of the third slope SF3 is steeper than that of the first slope SF1.

[0069] Thereafter, as shown in FIG. 6D, the pattern printing resist 90 is removed. Examples of the etching solution for the pattern printing resist 90 include an alkaline solution such as an aqueous potassium hydroxide solution.

[0070] In this way, by adopting an inexpensive alkaline solution as the solution for removing the pattern printing resist in the patterning (first patterning) of the first conductivity type semiconductor layer 25, the cost of the solar cell can be reduced.

[0071] In the first semiconductor layer formation step, patterning of the first conductivity type semiconductor layer 25 may be performed so as to leave part or all of the intrinsic semiconductor layer material film 23Z in the second region 8 on the back side of the semiconductor substrate 11.

[0072] Next, both sides of the semiconductor substrate 11 are cleaned (first cleaning step). In the first cleaning step, for example, after ozone treatment, hydrofluoric acid treatment is performed. The hydrofluoric acid treatment includes not only hydrofluoric acid but also treatment with a mixture containing other types of acids (for example, hydrochloric acid in the first cleaning step) in hydrofluoric acid.

[0073] Next, as shown in FIG. 6E, for example, using a CVD method, an intrinsic semiconductor layer material film 33Z and a second conductivity type semiconductor layer material film 35Z are sequentially laminated (film formation) on the entire back side of the semiconductor substrate 11 (second semiconductor layer material film formation step).

[0074] Next, as shown in FIG. 6F, using a lift-off method using a lift-off layer (sacrificial layer), on the back side of the semiconductor substrate 11, the intrinsic semiconductor layer material film 33Z and the second conductivity type semiconductor layer material film 35Z in the first region 7 are removed, thereby forming a patterned intrinsic semiconductor layer 33 and a second conductivity type semiconductor layer 35 in the second region 8 (second semiconductor layer formation step).

[0075] Specifically, by removing the lift-off layer 41, the intrinsic semiconductor layer material film 33Z and the second conductivity type semiconductor layer material film 35Z on the lift-off layer 41 are removed, and an intrinsic semiconductor layer 33 and a second conductivity type semiconductor layer 35 are formed in the second region 8. As a removal solution for the lift-off layer 41, for example, an acidic solution such as hydrofluoric acid is used.

[0076] In this way, by adopting a lift-off method using a lift-off layer (sacrificial layer) in the patterning (second patterning) of the second conductivity type semiconductor layer 35, simplification of the manufacturing process of the solar cell becomes possible.

[0077] FIG. 7C is an enlarged cross-sectional view of a boundary region VII C between a first region 7 and a second region 8 shown in FIG. 6G. FIG. 5A described above corresponds to an enlarged cross-sectional view of a part VA of a boundary region 8A on the first region 7 side in the second region 8 shown in FIG. 7C, and FIG. 5B described above corresponds to an enlarged cross-sectional view of a part VB other than the boundary region 8A in the second region 8 shown in FIG. 7C.

[0078] As shown in FIGS. 7C and 5A, in a boundary region 8A (bleed-out region of a pattern printing resist) on the first region 7 side in the second region 8 on the back surface side of the semiconductor substrate 11, the film thicknesses of the second intrinsic semiconductor layer 33 and the second conductivity type semiconductor layer 35 (second semiconductor layer) on the second inclined surface SF2 are formed thicker than the film thicknesses of the second intrinsic semiconductor layer 33 and the second conductivity type semiconductor layer 35 (second semiconductor layer) on the first inclined surface SF1. It is presumed that this is due to the fact that the gentler the inclination, the thicker the film thickness of the stacked semiconductor layer.

[0079] In addition, in the first semiconductor layer forming step, when all of the intrinsic semiconductor layer material film 23Z in the second region 8 on the back surface side of the semiconductor substrate 11 remains, in the second semiconductor layer material film forming step and the second semiconductor layer forming step, the intrinsic semiconductor layer material film may not be laminated (film formed), and the second conductivity type semiconductor layer 35 may be patterned. Further, in the first semiconductor layer forming step, when a part of the intrinsic semiconductor layer material film 23Z in the second region 8 on the back surface side of the semiconductor substrate 11 remains, in the second semiconductor layer material film forming step and the second semiconductor layer forming step, the intrinsic semiconductor layer material film may be laminated (film formed) by the removed amount, and the intrinsic semiconductor layer and the second conductivity type semiconductor layer 35 may be patterned.

[0080] Next, as shown in FIG. 6G, a first electrode layer 27 and a second electrode layer 37 are formed on the back surface side of the semiconductor substrate 11 (electrode layer forming step).

[0081] Specifically, for example, using a PVD method (physical vapor deposition method) such as a sputtering method, a transparent electrode layer material film is laminated (formed into a film) on the entire back surface side of the semiconductor substrate 11. Then, for example, by using an etching method using an etching paste to remove a part of the transparent electrode layer material film, patterned transparent electrode layers 28 and 38 are formed. As the etching solution for the transparent electrode layer material film, for example, hydrochloric acid or an aqueous solution of ferric chloride is used.

[0082] Thereafter, for example, by using a pattern printing method or a coating method to form a metal electrode layer 29 on the transparent electrode layer 28 and a metal electrode layer 39 on the transparent electrode layer 38, a first electrode layer 27 and a second electrode layer 37 are formed.

[0083] The above-described FIG. 3 corresponds to an enlarged cross-sectional view of a boundary region III between a first region 7 and a second region 8 shown in FIG. 6G. As shown in FIG. 3, a boundary region 8A on the first region 7 side in the second region 8 is located between the transparent electrode layer 28 of the first electrode layer 27 and the transparent electrode layer 38 of the second electrode layer 37, and may be located under the transparent electrode layer 28 of the first electrode layer 27 in the transparent electrode layer 38 of the second electrode layer 37.

[0084] Next, as shown in FIG. 6H, an optical adjustment layer 15 is laminated (formed into a film) on the entire light-receiving surface side of the semiconductor substrate 11. Through the above steps, the back electrode type solar cell 1 according to the first embodiment is completed.

[0085] As described above, according to the solar cell 1 and its manufacturing method of the first embodiment, in the boundary region 8A on the first region 7 side in the second region 8, that is, between the transparent electrode layers 28 and 38, the film thicknesses of the second intrinsic semiconductor layer 33 and the second conductivity type semiconductor layer 35 (second semiconductor layer) on the second inclined surface SF2 of the pyramid 11A are thick. Thereby, the reliability of the solar cell 1 can be improved. In addition, the passivation performance is improved, and the performance (for example, Voc) of the solar cell 1 can be improved.

[0086] Further, according to the solar cell 1 and its manufacturing method of the first embodiment, the boundary region 8A on the side of the first region 7 in the second region 8 is located between the transparent electrode layer 28 of the first electrode layer 27 and the transparent electrode layer 38 of the second electrode layer 37, and is located below the transparent electrode layer 38 of the second electrode layer 37 on the side of the transparent electrode layer 28 of the first electrode layer 27. Thereby, even if there are manufacturing variations or the like, in the second region 8 between the transparent electrode layers 28 and 38, the pyramid 11A having a thick film thickness of the second intrinsic semiconductor layer 33 and the second conductivity type semiconductor layer 35 (second semiconductor layer) on the second slope SF2 is arranged, and the reliability and performance of the solar cell 1 can be improved.

[0087] Further, according to the manufacturing method of the solar cell of the first embodiment, in the patterning of the first conductivity type semiconductor layer (first patterning), by using a pattern printing resist by a pattern printing method, while simplifying the manufacturing process of the solar cell, by utilizing the bleeding film of the resin material in the pattern printing resist, as described above, the improvement of the reliability and performance of the solar cell 1 can be realized.

[0088] In addition, in a flat semiconductor substrate that does not have a pyramid-shaped fine concavo-convex structure (texture structure), even if a pattern printing resist by a pattern printing method is used, almost no bleeding of the resin material in the pattern printing resist occurs. That is, the characteristics of the solar cell 1 of the first embodiment described above can be realized by a combination of the use of a semiconductor substrate having a pyramid-shaped fine concavo-convex structure (texture structure) and the use of a pattern printing resist by a pattern printing method.

[0089] Further, according to the solar cell 1 and its manufacturing method of the first embodiment, by adjusting the size of the pyramid and / or the components and viscosity of the pattern printing resist, the bleeding width of the resin material in the pattern printing resist can be adjusted. Thereby, the optimization design of the characteristics of the solar cell 1 of the first embodiment described above becomes easy.

[0090] (Modification example) FIG. 9 is a cross-sectional view of a solar cell according to a modified example of the first embodiment, and is a cross-sectional view corresponding to line II-II in FIG. 1. Further, FIG. 10 is an enlarged cross-sectional view of a boundary region X between the first region 7 and the second region 8 shown in FIG. 9.

[0091] As shown in FIGS. 9 and 10, a boundary region 8A on the first region 7 side in the second region 8 is located between the transparent electrode layer 28 of the first electrode layer 27 and the transparent electrode layer 38 of the second electrode layer 37, and may not be located under the transparent electrode layer 38 of the second electrode layer 37. Thereby, since the pyramid 11A having a thick film thickness of the second intrinsic semiconductor layer 33 and the second conductivity type semiconductor layer 35 (second semiconductor layer) on the second inclined surface SF2 is not located under the transparent electrode layer 38 of the second electrode layer 37, an increase in resistance can be suppressed, and a decrease in carrier extraction efficiency can be suppressed.

[0092] In the above-described first embodiment, as shown in FIGS. 3 and 5A, in the boundary region 8A (bleed-out region of the pattern printing resist) on the first region 7 side in the second region 8, a form in which the first intrinsic semiconductor layer 23 and the first conductivity type semiconductor layer 25 (first semiconductor layer) do not remain due to under-etching was exemplified. In the following second embodiment, as shown in FIGS. 13 and 15A described later, in the boundary region 8A (bleed-out region of the pattern printing resist) on the first region 7 side in the second region 8, a form in which the first intrinsic semiconductor layer 23 and the first conductivity type semiconductor layer 25 (first semiconductor layer) remain on the first inclined surface SF1 of the pyramid 11A depending on the degree of under-etching will be exemplified.

[0093] [Second Embodiment] (Solar Cell) FIG. 11 is a view of the solar cell according to the second embodiment as seen from the back side. The solar cell 1 shown in FIG. 11 is a back-contact type (also referred to as a back-contact type or a back-junction type) solar cell. The solar cell 1 includes a semiconductor substrate 11 having two main surfaces, and has a first region 7 and a second region 8 on the main surfaces of the semiconductor substrate 11.

[0094] The first region 7 has a so-called comb shape, and includes a plurality of finger portions 7f corresponding to comb teeth and a bus bar portion 7b corresponding to a support portion of the comb teeth. The bus bar portion 7b extends in a first direction (X direction) along one side portion of the semiconductor substrate 11, and the finger portions 7f extend from the bus bar portion 7b in a second direction (Y direction) intersecting the first direction (X direction).

[0095] Similarly, the second region 8 has a so-called comb shape, and includes a plurality of finger portions 8f corresponding to comb teeth and a bus bar portion 8b corresponding to a support portion of the comb teeth. The bus bar portion 8b extends in the first direction (X direction) along the other side portion of the semiconductor substrate 11 facing one side portion, and the finger portions 8f extend from the bus bar portion 8b in the second direction (Y direction).

[0096] The finger portions 7f and the finger portions 8f are alternately provided in the first direction (X direction). Note that the first region 7 and the second region 8 may be formed in a stripe shape.

[0097] FIG. 12 is a cross-sectional view taken along line II-II in the solar cell of FIG. 11. As shown in FIG. 12, the solar cell 1 is a heterojunction solar cell. The solar cell 1 includes a semiconductor substrate 11, an intrinsic semiconductor layer 13 and an optical adjustment layer 15 laminated in order on one main surface of the semiconductor substrate 11, which is a light-receiving side main surface. Further, the solar cell 1 includes an intrinsic semiconductor layer 23, a first conductivity type semiconductor layer 25, and a first electrode layer 27 laminated in order on a part (first region 7) on the back surface side, which is the other main surface of the semiconductor substrate 11 opposite to the light-receiving surface. Further, the solar cell 1 includes an intrinsic semiconductor layer 33, a second conductivity type semiconductor layer 35, and a second electrode layer 37 laminated in order on another part (second region 8) on the back surface side of the semiconductor substrate 11. Further, as will be described later, in the vicinity of the boundary between the first region 7 and the second region 8, the region including both the first conductivity type semiconductor layer 25 and the second conductivity type semiconductor layer 35 is the second region 8. Hereinafter, the intrinsic semiconductor layer 23 and the first conductivity type semiconductor layer 25 are also referred to as the first semiconductor layer, and the intrinsic semiconductor layer 33 and the second conductivity type semiconductor layer 35 are also referred to as the second semiconductor layer.

[0098] The semiconductor substrate 11 is formed of a crystalline silicon material such as single-crystalline silicon or polycrystalline silicon. The semiconductor substrate 11 is, for example, an n-type semiconductor substrate doped with an n-type dopant in a crystalline silicon material. Note that the semiconductor substrate 11 may be, for example, a p-type semiconductor substrate doped with a p-type dopant in a crystalline silicon material. Examples of the n-type dopant include phosphorus (P). Examples of the p-type dopant include boron (B). The semiconductor substrate 11 functions as a photoelectric conversion substrate that absorbs incident light from the light-receiving surface side to generate optical carriers (electrons and holes).

[0099] By using crystalline silicon as the material of the semiconductor substrate 11, the dark current is relatively small, and a relatively high output (stable output regardless of illuminance) can be obtained even when the intensity of the incident light is low.

[0100] The semiconductor substrate 11 has a pyramidal fine concavo-convex structure called a texture structure on the back surface side. Thereby, the recovery efficiency of the light that has passed through the semiconductor substrate 11 without being absorbed is increased.

[0101] Also, the semiconductor substrate 11 may have a pyramidal fine concavo-convex structure called a texture structure on the light-receiving surface side. Thereby, the reflection of the incident light on the light-receiving surface is reduced, and the light confinement effect in the semiconductor substrate 11 is improved.

[0102] The intrinsic semiconductor layer 13 is formed on the light-receiving surface side of the semiconductor substrate 11. The intrinsic semiconductor layer 23 is formed in the first region 7 on the back surface side of the semiconductor substrate 11. The intrinsic semiconductor layer 33 is formed in the second region 8 on the back surface side of the semiconductor substrate 11. The intrinsic semiconductor layers 13, 23, and 33 are formed of a material mainly composed of, for example, intrinsic (i-type) amorphous silicon. The intrinsic semiconductor layers 13, 23, and 33 function as so-called passivation layers, suppress the recombination of carriers generated in the semiconductor substrate 11, and increase the carrier recovery efficiency.

[0103] The optical adjustment layer 15 is formed on the intrinsic semiconductor layer 13 on the light-receiving surface side of the semiconductor substrate 11. The optical adjustment layer 15 functions as an antireflection layer for preventing reflection of incident light and also functions as a protective layer for protecting the light-receiving surface side of the semiconductor substrate 11 and the intrinsic semiconductor layer 13. The optical adjustment layer 15 is formed of an insulator material such as silicon oxide (SiO), silicon nitride (SiN), or a composite thereof such as silicon oxynitride (SiON).

[0104] The first-conductivity-type semiconductor layer 25 is formed on the intrinsic semiconductor layer 23, that is, in the first region 7 on the back surface side of the semiconductor substrate 11. The first-conductivity-type semiconductor layer 25 is formed of, for example, an amorphous silicon material. The first-conductivity-type semiconductor layer 25 is a p-type semiconductor layer in which, for example, a p-type dopant (e.g., boron (B) described above) is doped into an amorphous silicon material.

[0105] The second-conductivity-type semiconductor layer 35 is formed on the intrinsic semiconductor layer 33, that is, in the second region 8 on the back surface side of the semiconductor substrate 11. The second-conductivity-type semiconductor layer 35 is formed of, for example, an amorphous silicon material. The second-conductivity-type semiconductor layer 35 is an n-type semiconductor layer in which, for example, an n-type dopant (e.g., phosphorus (P) described above) is doped into an amorphous silicon material. Note that the first-conductivity-type semiconductor layer 25 may be an n-type semiconductor layer and the second-conductivity-type semiconductor layer 35 may be a p-type semiconductor layer.

[0106] The first electrode layer 27 is formed on the first-conductivity-type semiconductor layer 25, and the second electrode layer 37 is formed on the second-conductivity-type semiconductor layer 35. The first electrode layer 27 has a transparent electrode layer 28 and a metal electrode layer 29 laminated in order on the first-conductivity-type semiconductor layer 25. The second electrode layer 37 has a transparent electrode layer 38 and a metal electrode layer 39 laminated in order on the second-conductivity-type semiconductor layer 35.

[0107] The transparent electrode layers 28 and 38 are formed of a transparent conductive material. Examples of the transparent conductive material include ITO (Indium Tin Oxide, a composite oxide of indium oxide and tin oxide) and ZnO (Zinc Oxide). The metal electrode layers 29 and 39 are formed of a conductive paste material containing metal powder such as silver or copper.

[0108] FIG. 13 is an enlarged cross-sectional view of the boundary region III between the first region 7 and the second region 8 shown in FIG. 12. FIG. 14A is an enlarged cross-sectional view of the back surface of the semiconductor substrate 11 in a part VA of the boundary region 8A (the bleeding region of the pattern printing resist to be described later) on the first region 7 side in the second region 8 shown in FIG. 13, and FIG. 15A is an enlarged cross-sectional view of the semiconductor layer in a part VA of the boundary region 8A (the bleeding region of the pattern printing resist to be described later) on the first region 7 side in the second region 8 shown in FIG. 13. Further, FIG. 14B is an enlarged cross-sectional view of the back surface of the semiconductor substrate 11 in a part VB other than the boundary region 8A in the second region 8 shown in FIG. 13, and FIG. 15B is an enlarged cross-sectional view of the semiconductor layer in a part VB other than the boundary region 8A in the second region 8 shown in FIG. 13.

[0109] As shown in FIGS. 13 and 14A, a plurality of pyramids 11A each composed of four slopes are formed in the boundary region 8A (the bleeding region of the pattern printing resist) on the first region 7 side in the second region 8 on the back surface side of the semiconductor substrate 11.

[0110] Each slope of the pyramid 11A has a first slope SF1 from the base 1A to the middle 2A and a second slope SF2 from the middle 2A to the apex 3A. The first slope SF1 and the second slope SF2 have different inclination angles with the bending point of the middle 2A as the boundary. The inclination of the second slope SF2 is gentler than that of the first slope SF1.

[0111] In a cross section passing through the apex 3A and orthogonal to the base 1A (that is, the cross section shown in FIG. 14A), the minimum angle θ [°] formed by a first virtual straight line L1 from the base 1A to the apex 3A and a second virtual straight line L2 from the base 1A to the bending point of the middle 2A satisfies 8 < θ ≦ 30.

[0112] Such a pyramid 11A occupies 0.01% or more and 50% or less of the area of the back surface of the semiconductor substrate 11.

[0113] On the other hand, as shown in FIGS. 13 and 14B, in a region other than the boundary region 8A in the second region 8 on the back surface side of the semiconductor substrate 11, a plurality of pyramids 11B each composed of four slopes are formed. In FIG. 14B, for comparison, the first slope SF1 and the second slope SF2 of the above-described pyramid 11A are shown by broken lines.

[0114] Each slope of the pyramid 11B has a third slope SF3 without an inflection point from the foot of the mountain 1B to the peak 3B. The inclination of the third slope SF3 is gentler than the inclination of the first slope SF1 described above.

[0115] Thereby, the following relationship holds for the inclinations of the first slope SF1 and the second slope SF2 of the pyramid 11A. Inclination of the second slope SF2 < Inclination of the first slope SF1

[0116] As shown in FIG. 15A, in the boundary region 8A (the bleeding region of the pattern printing resist) on the first region 7 side in the second region 8 on the back surface side of the semiconductor substrate 11, on the first slope SF1 of the pyramid 11A, the first intrinsic semiconductor layer 23 and the first conductivity type semiconductor layer 25 (the first semiconductor layer), and the second intrinsic semiconductor layer 33 and the second conductivity type semiconductor layer 35 (the second semiconductor layer) are laminated (formed) in this order. Note that the first intrinsic semiconductor layer 23 and the first conductivity type semiconductor layer 25 (the first semiconductor layer) may be laminated on the entire first slope SF1 of the pyramid 11A, or may be laminated on at least a part (for example, on the foot of the mountain 1A side, that is, on the valley side).

[0117] On the other hand, on the second slope SF2 of the pyramid 11A, the first intrinsic semiconductor layer 23 and the first conductivity type semiconductor layer 25 (the first semiconductor layer) are not laminated (formed), and only the second intrinsic semiconductor layer 33 and the second conductivity type semiconductor layer 35 (the second semiconductor layer) are laminated (formed).

[0118] Also, in the boundary region 8A (the bleeding region of the pattern printing resist) on the side of the first region 7 in the second region 8 on the back surface side of the semiconductor substrate 11, the film thicknesses of the second intrinsic semiconductor layer 33 and the second conductivity type semiconductor layer 35 (the second semiconductor layer) on the second slope SF2 of the pyramid 11A are thicker than the film thicknesses of the second intrinsic semiconductor layer 33 and the second conductivity type semiconductor layer 35 (the second semiconductor layer) on the first slope SF1 of the pyramid 11A.

[0119] The value obtained by dividing the film thicknesses of the second intrinsic semiconductor layer 33 and the second conductivity type semiconductor layer 35 (the second semiconductor layer) on the second slope SF2 of the pyramid 11A by the film thicknesses of the second intrinsic semiconductor layer 33 and the second conductivity type semiconductor layer 35 (the second semiconductor layer) on the first slope SF1 of the pyramid 11A is preferably 1.02 or more and 1.80 or less, more preferably 1.03 or more and 1.60 or less, and even more preferably 1.05 or more and 1.40 or less.

[0120] Here, the film thickness of the semiconductor layer is the film thickness in the direction orthogonal to the slope of the pyramid of the semiconductor substrate 11. The film thickness on the first slope SF1 is measured at the midpoint PA1 between the foot of the mountain 1A and the inflection point (midriff) 2A, and the film thickness on the second slope SF2 is measured at the midpoint PA2 between the peak 3A of the pyramid and the inflection point (midriff) 2A. When there are two or more inflection points, the inflection point closest to the peak is used for film thickness measurement.

[0121] In a back contact type solar cell, a first semiconductor region and a second semiconductor region exist on the back surface, and they have an adjacent structure. The presence of the boundary between the first semiconductor region and the second semiconductor region on the back surface is a structure peculiar to the back contact type solar cell. The structure around the boundary region greatly affects the reliability of the solar cell. Even if the area in the boundary region is small, it has the structure of the pyramid A described above, and by having the film thickness ratio between the first slope SF1 and the second slope SF2, it is possible to improve the reliability.

[0122] On the other hand, as shown in FIG. 15B, in the region other than the boundary region 8A in the second region 8 on the back surface side of the semiconductor substrate 11, since there is no bend like the pyramid 11A on the third slope SF3 of the pyramid 11B, among the three points PB1, PB2, and PB3 that divide the mountain foot 1B and the mountain top 3B into four equal parts on the third slope SF3, the film thicknesses of the first point PB3 and the third point PB1 from the mountain top 3B shall be measured.

[0123] As a result, the following relationship holds for the film thicknesses of the second semiconductor layers 35 and 33 on the first slope SF1 and the second slope SF2 of the pyramid 11A, and the film thickness of the second semiconductor layer on the third slope SF3 of the pyramid 11B. Film thickness of the second semiconductor layers 35 and 33 on the second slope SF2 / Film thickness of the second semiconductor layers 35 and 33 on the first slope SF1 > Film thickness of the second semiconductor layers 35 and 33 at the midpoint PB3 between the midpoint PB2 of the mountain foot 1B and the mountain top 3B and the mountain top 3B on the third slope SF3 / Film thickness of the second semiconductor layers 35 and 33 at the midpoint PB1 between the midpoint PB2 of the mountain foot 1B and the mountain top 3B and the mountain foot 1B on the third slope SF3

[0124] As shown in FIG. 13, the boundary region 8A on the first region 7 side in the second region 8 is located between the transparent electrode layer 28 of the first electrode layer 27 and the transparent electrode layer 38 of the second electrode layer 37, and may be located below the transparent electrode layer 28 of the first electrode layer 27 in the transparent electrode layer 38 of the second electrode layer 37.

[0125] (Method for manufacturing a solar cell)

[0126] Next, with reference to FIGS. 16A to 16H, a method for manufacturing the solar cell 1 according to the second embodiment will be described. FIG. 16A is a diagram showing a first semiconductor layer material film forming step and a lift-off layer forming step in the method for manufacturing a solar cell according to the second embodiment, and FIGS. 16B to 16D are diagrams showing a first semiconductor layer forming step in the method for manufacturing a solar cell according to the second embodiment. Further, FIG. 16E is a diagram showing a second semiconductor layer material film forming step in the method for manufacturing a solar cell according to the second embodiment, and FIG. 16F is a diagram showing a second semiconductor layer forming step in the method for manufacturing a solar cell according to the second embodiment. Further, FIG. 16G is a diagram showing an electrode layer forming step in the method for manufacturing a solar cell according to the second embodiment, and FIG. 16H is a diagram showing an optical adjustment layer forming step in the method for manufacturing a solar cell according to the second embodiment.

[0127] First, at least on the back surface side of the semiconductor substrate 11, by performing anisotropic etching, a texture structure having a pyramid-shaped fine concavo-convex structure is formed. Examples of the etching solution include an alkaline solution such as an aqueous potassium hydroxide solution.

[0128] Next, as shown in FIG. 16A, for example, by using a CVD method (chemical vapor deposition method), an intrinsic semiconductor layer material film 23Z and a first conductivity type semiconductor layer material film 25Z are sequentially laminated (film formed) on the entire back surface side of the semiconductor substrate 11 (first semiconductor layer material film forming step).

[0129] Further, for example, by using a CVD method, an intrinsic semiconductor layer 13 is laminated (film formed) on the entire light receiving surface side of the semiconductor substrate 11. Note that the film forming order of the intrinsic semiconductor layer material film 23Z and the first conductivity type semiconductor layer material film 25Z and the intrinsic semiconductor layer 13 is not limited.

[0130] Further, the intrinsic semiconductor layer 13 on the light receiving surface side may be film formed in a later second semiconductor layer material film forming step. In this case, the intrinsic semiconductor layer on the light receiving surface side film formed at this stage may be removed in a later first semiconductor layer forming step. Alternatively, an intrinsic semiconductor layer may not be formed on the light receiving surface side at this stage, that is, there may be no intrinsic semiconductor layer forming step at this stage.

[0131] Next, for example, using a CVD method, a lift-off layer (sacrificial layer) 41 is laminated (formed into a film) on the entire back surface side of the semiconductor substrate 11, specifically, on the entire surface of the first conductivity type semiconductor layer material film 25Z (lift-off layer forming step). The lift-off layer 41 is formed of a material such as silicon oxide (SiO), silicon nitride (SiN), or a composite thereof such as silicon oxynitride (SiON).

[0132] Next, as shown in FIGS. 16B to 16D, by removing the intrinsic semiconductor layer material film 23Z, the first conductivity type semiconductor layer material film 25Z, and the lift-off layer 41 in the second region 8 on the back surface side of the semiconductor substrate 11 using a pattern printing resist, a patterned intrinsic semiconductor layer 23, a first conductivity type semiconductor layer 25, and a lift-off layer 41 are formed in the first region 7 (first semiconductor layer forming step).

[0133] Specifically, as shown in FIG. 16B, a pattern printing resist 90 is formed on the entire light-receiving surface side of the semiconductor substrate 11 and in the first region 7 on the back surface side of the semiconductor substrate 11 using a pattern printing method (resist forming step).

[0134] Pattern printing means a printing method in which a patterned resist (printing material) is directly adhered to a resist adhesion surface, such as screen printing or gravure printing, which are press printing methods, or inkjet printing, which is a discharge printing method, rather than a printing method such as photolithography, in which a resist film before patterning (non-patterned resist film) is formed once and then processes such as exposure and development are performed.

[0135] Thus, in the patterning of the first conductivity type semiconductor layer (first patterning), by using a pattern printing resist by the pattern printing method, the exposure and development processes can be reduced as compared with the case of using a photoresist by the spin coating method (photolithography method), and the manufacturing process of the solar cell can be simplified.

[0136] The pattern printing resist 90 is obtained by printing and curing a printing material containing a resin material and an inorganic material. At this time, a part of the printing material oozes out from the printing material printed in the first region 7. The printing material may contain a solvent component, and the curing process may be not only by heating but also by curing with light. Further, in the curing process, it is not always necessary for the resin component to be cured by crosslinking or the like, and it refers to a state in which the shape is maintained at room temperature and solvent resistance is provided due to an increase in viscosity accompanying the volatilization of the solvent, that is, a state having a function as a resist.

[0137] FIG. 17A is an enlarged view of the boundary region VIIA between the first region 7 and the second region 8 shown in FIG. 16B. As shown in FIG. 17A, the oozed resist material covers the trough of the pyramid 11A in the boundary region 8A (the oozing region of the pattern printing resist) on the first region 7 side in the second region 8.

[0138] Specifically, as shown in FIG. 18, the oozing film 90A formed by the oozing of the printing material is formed so as to cover the first inclined surface SF1 from the skirt 1A to the middle part 2A of the pyramid 11A in the boundary region 8A (the oozing region of the pattern printing resist) on the first region 7 side in the second region 8.

[0139] Here, while the film thickness of the pattern printing resist 90 is 3 μm or more and 50 μm or less, the height of the pyramid 11A is 0.1 μm or more and 15 μm or less. The height of the pyramid is the height from the skirt to the apex, and the film thickness of the pattern printing resist 90 is the film thickness from the skirt of the pyramid.

[0140] Thereafter, as shown in FIG. 16C, by etching the lift-off layer 41, the first conductivity type semiconductor layer material film 25Z, and the intrinsic semiconductor layer material film 23Z in the second region 8 using the pattern printing resist 90 and the oozing film 90A on its periphery as a mask, a patterned intrinsic semiconductor layer 23, a first conductivity type semiconductor layer 25, and a lift-off layer 41 are formed in the first region 7.

[0141] Examples of the etching solution for the lift-off layer 41 include acidic solutions such as a mixed solution obtained by dissolving ozone in hydrofluoric acid, or a mixed solution of hydrofluoric acid and nitric acid. Examples of the etching solution for the p-type semiconductor layer material film include acidic solutions such as a mixed solution obtained by dissolving ozone in hydrofluoric acid, or a mixed solution of hydrofluoric acid and nitric acid, and examples of the etching solution for the n-type semiconductor layer material film include an alkaline solution such as an aqueous potassium hydroxide solution.

[0142] FIG. 17B is an enlarged view of a boundary region VIIB between the first region 7 and the second region 8 shown in FIG. 16C. As shown in FIG. 17B, in a boundary region 8A (bleed-out region of the pattern printing resist) on the side of the first region 7 in the second region 8, the first true semiconductor layer 23 and the first conductivity type semiconductor layer 25 (first semiconductor layer) remain on a first inclined surface SF1 of a pyramid 11A covered with a bleed-out film 90A.

[0143] FIGS. 14A and 18 described above correspond to an enlarged cross-sectional view of a partial region IVA of the boundary region 8A on the side of the first region 7 in the second region 8 shown in FIG. 17B, and FIG. 14B described above corresponds to an enlarged cross-sectional view of a partial region IVB other than the boundary region 8A in the second region 8 shown in FIG. 17B.

[0144] As shown in FIGS. 14A and 18, in a boundary region 8A (bleed-out region of the pattern printing resist) on the side of the first region 7 in the second region 8 on the back surface side of the semiconductor substrate 11, the bottom side of the pyramid 11A covered with the bleed-out film 90A is not etched, and the top side not covered with the bleed-out film 90A is etched.

[0145] As a result, each inclined surface of the pyramid 11A has a first inclined surface SF1 from the bottom 1A to the middle 2A and a second inclined surface SF2 from the middle 2A to the top 3A. The first inclined surface SF1 and the second inclined surface SF2 have different inclination angles with the bending point of the middle 2A as a boundary. The inclination of the second inclined surface SF2 is gentler than the inclination of the first inclined surface SF1.

[0146] In a cross-section (i.e., the cross-sections shown in FIGS. 14A and 18) perpendicular to the mountain foot 1A passing through the mountain top 3A, the minimum angle θ [°] formed by the first virtual straight line L1 from the mountain foot 1A to the mountain top 3A and the second virtual straight line L2 from the mountain foot 1A to the bending point of the mountainside 2A is 8 < θ ≤ 30.

[0147] Such a pyramid 11A will occupy 0.01% or more and 50% or less of the area of the back surface of the semiconductor substrate 11.

[0148] On the other hand, as shown in FIG. 14B, in the region other than the boundary region 8A in the second region 8 on the back surface side of the semiconductor substrate 11, the pyramid 11B is not covered by the bleeding film 90A, so it is etched as a whole.

[0149] As a result, each slope of the pyramid 11B will have a third slope SF3 without a bending point from the mountain foot 1B to the mountain top 3B. In the pyramid 11B, since the slopes are etched as a whole, the inclination of the third slope SF3 is steeper than that of the second slope SF2.

[0150] In addition, the lift-off layer 41, the first intrinsic semiconductor layer 23, and the first conductivity type semiconductor layer 25 (the first semiconductor layer) remain on the first slope SF1 of the pyramid 11A. Note that the lift-off layer 41, the first intrinsic semiconductor layer 23, and the first conductivity type semiconductor layer 25 (the first semiconductor layer) may remain on the entire first slope SF1 of the pyramid 11A, or may remain at least partially (for example, on the mountain foot 1A side, that is, on the valley side).

[0151] Thereafter, as shown in FIG. 16D, the pattern printing resist 90 is removed. Examples of the etching solution for the pattern printing resist 90 include an alkaline solution such as an aqueous potassium hydroxide solution.

[0152] Thus, in the patterning of the first conductivity type semiconductor layer 25 (the first patterning), by adopting an inexpensive alkaline solution as the solution for removing the pattern printing resist, the cost of the solar cell can be reduced.

[0153] In the first semiconductor layer forming step, the patterning of the first conductivity type semiconductor layer 25 may be performed so as to leave part or all of the intrinsic semiconductor layer material film 23Z in the second region 8 on the back side of the semiconductor substrate 11.

[0154] Next, both sides of the semiconductor substrate 11X are cleaned (the first cleaning step). In the first cleaning step, for example, after ozone treatment, hydrofluoric acid treatment is performed. The hydrofluoric acid treatment includes not only hydrofluoric acid but also treatment with a mixture containing other types of acids (for example, hydrochloric acid in the first cleaning step) in hydrofluoric acid.

[0155] Next, as shown in FIG. 16E, for example, using the CVD method, an intrinsic semiconductor layer material film 33Z and a second conductivity type semiconductor layer material film 35Z are sequentially laminated (film formation) on the entire back side of the semiconductor substrate 11 (the second semiconductor layer material film forming step).

[0156] Next, as shown in FIG. 16F, using the lift-off method using a lift-off layer (sacrificial layer), on the back side of the semiconductor substrate 11, the intrinsic semiconductor layer material film 33Z and the second conductivity type semiconductor layer material film 35Z in the first region 7 are removed, thereby forming a patterned intrinsic semiconductor layer 33 and a second conductivity type semiconductor layer 35 in the second region 8 (the second semiconductor layer forming step).

[0157] Specifically, by removing the lift-off layer 41, the intrinsic semiconductor layer material film 33Z and the second conductivity type semiconductor layer material film 35Z on the lift-off layer 41 are removed, and the intrinsic semiconductor layer 33 and the second conductivity type semiconductor layer 35 are formed in the second region 8. As the solution for removing the lift-off layer 41, for example, an acidic solution such as hydrofluoric acid is used.

[0158] In this way, by adopting a lift-off method using a lift-off layer (sacrificial layer) in the patterning of the p-type semiconductor layer 35 (second patterning), the manufacturing process of the solar cell can be simplified.

[0159] FIG. 17C is an enlarged cross-sectional view of the boundary region VIIC between the first region 7 and the second region 8 shown in FIG. 16G. FIG. 15A described above corresponds to an enlarged cross-sectional view of a part VA of the boundary region 8A on the first region 7 side in the second region 8 shown in FIG. 17C, and FIG. 15B described above corresponds to an enlarged cross-sectional view of a part VB other than the boundary region 8A in the second region 8 shown in FIG. 17C.

[0160] As shown in FIGS. 17C and 15A, in the boundary region 8A (bleed-out region of the pattern printing resist) on the first region 7 side in the second region 8 on the back side of the semiconductor substrate 11, on the first inclined surface SF1 of the pyramid 11A, the first intrinsic semiconductor layer 23 and the n-type semiconductor layer 25 (first semiconductor layer), and the second intrinsic semiconductor layer 33 and the p-type semiconductor layer 35 (second semiconductor layer) are laminated (formed) in this order. Note that the first intrinsic semiconductor layer 23 and the n-type semiconductor layer 25 (first semiconductor layer) may be laminated on the entire first inclined surface SF1 of the pyramid 11A, or may be laminated on at least a part (for example, the mountain foot 1A side, that is, the valley part side).

[0161] On the other hand, on the second inclined surface SF2 of the pyramid 11A, the first intrinsic semiconductor layer 23 and the n-type semiconductor layer 25 (first semiconductor layer) are not laminated (formed), and only the second intrinsic semiconductor layer 33 and the p-type semiconductor layer 35 (second semiconductor layer) are laminated (formed).

[0162] Also, in the boundary region 8A (the bleeding region of the pattern printing resist) on the side of the first region 7 in the second region 8 on the back side of the semiconductor substrate 11, the film thicknesses of the second intrinsic semiconductor layer 33 and the second conductivity type semiconductor layer 35 (the second semiconductor layer) on the second inclined surface SF2 are formed thicker than the film thicknesses of the second intrinsic semiconductor layer 33 and the second conductivity type semiconductor layer 35 (the second semiconductor layer) on the first inclined surface SF1. This is presumably due to the fact that the gentler the inclination, the thicker the film thickness of the stacked semiconductor layers.

[0163] In addition, in the first semiconductor layer formation step, if all of the intrinsic semiconductor layer material film 23Z in the second region 8 on the back side of the semiconductor substrate 11 remains, in the second semiconductor layer material film formation step and the second semiconductor layer formation step, the stacking (film formation) of the intrinsic semiconductor layer material film may not be performed, and only the patterning of the second conductivity type semiconductor layer 35 may be performed. Further, in the first semiconductor layer formation step, if a part of the intrinsic semiconductor layer material film 23Z in the second region 8 on the back side of the semiconductor substrate 11 remains, in the second semiconductor layer material film formation step and the second semiconductor layer formation step, the stacking (film formation) of the intrinsic semiconductor layer material film may be performed by the removed amount, and the patterning of the intrinsic semiconductor layer and the second conductivity type semiconductor layer 35 may be performed.

[0164] Next, as shown in FIG. 16G, a first electrode layer 27 and a second electrode layer 37 are formed on the back side of the semiconductor substrate 11 (electrode layer formation step).

[0165] Specifically, for example, using a PVD method (physical vapor deposition method) such as a sputtering method, a transparent electrode layer material film is stacked (formed) on the entire back side of the semiconductor substrate 11. Then, for example, by using an etching method using an etching paste to remove a part of the transparent electrode layer material film, the patterned transparent electrode layers 28, 38 are formed. As the etching solution for the transparent electrode layer material film, for example, hydrochloric acid or an aqueous solution of ferric chloride is used.

[0166] Thereafter, for example, by using a pattern printing method or a coating method, a metal electrode layer 29 is formed on the transparent electrode layer 28, and a metal electrode layer 39 is formed on the transparent electrode layer 38, thereby forming the first electrode layer 27 and the second electrode layer 37.

[0167] The above-described FIG. 13 corresponds to an enlarged cross-sectional view of the boundary region III between the first region 7 and the second region 8 shown in FIG. 16G. As shown in FIG. 13, the boundary region 8A on the first region 7 side in the second region 8 is located between the transparent electrode layer 28 of the first electrode layer 27 and the transparent electrode layer 38 of the second electrode layer 37, and may be located under the transparent electrode layer 28 of the first electrode layer 27 in the transparent electrode layer 38 of the second electrode layer 37.

[0168] Next, as shown in FIG. 16H, an optical adjustment layer 15 is laminated (film-formed) on the entire light-receiving surface side of the semiconductor substrate 11. Through the above steps, the back electrode type solar cell 1 according to the second embodiment is completed.

[0169] As described above, according to the solar cell 1 and its manufacturing method of the second embodiment, the film thicknesses of the second intrinsic semiconductor layer 33 and the second conductivity type semiconductor layer 35 (second semiconductor layer) on the second inclined surface SF2 of the pyramid 11A in the boundary region 8A on the first region 7 side in the second region 8, that is, between the transparent electrode layers 28 and 38, are thick. Also, on the first inclined surface SF1 of the pyramid 11A in the boundary region 8A on the first region 7 side in the second region 8, that is, between the transparent electrode layers 28 and 38, the first intrinsic semiconductor layer 23 and the first conductivity type semiconductor layer 25 (first semiconductor layer) remain, so the total film thickness of the first intrinsic semiconductor layer 23 and the first conductivity type semiconductor layer 25 (first semiconductor layer) and the second intrinsic semiconductor layer 33 and the second conductivity type semiconductor layer 35 (second semiconductor layer) is thick. Thereby, the reliability of the solar cell 1 can be improved. Also, the passivation performance is improved, and the performance (e.g., Voc) of the solar cell 1 can be improved.

[0170] Also, according to the solar cell 1 and its manufacturing method of the second embodiment, the boundary region 8A on the side of the first region 7 in the second region 8 is located between the transparent electrode layer 28 of the first electrode layer 27 and the transparent electrode layer 38 of the second electrode layer 37, and is located below the transparent electrode layer 38 of the second electrode layer 37 on the side of the transparent electrode layer 28 of the first electrode layer 27. Thereby, even if there are manufacturing variations or the like, in the second region 8 between the transparent electrode layers 28 and 38, the film thicknesses of the second intrinsic semiconductor layer 33 and the second conductivity type semiconductor layer 35 (second semiconductor layer) on the second inclined surface SF2 are thick, and the total film thickness of the first intrinsic semiconductor layer 23 and the first conductivity type semiconductor layer 25 (first semiconductor layer) and the second intrinsic semiconductor layer 33 and the second conductivity type semiconductor layer 35 (second semiconductor layer) on the first inclined surface SF1 is thick, and the pyramid 11A is arranged, and the reliability and performance of the solar cell 1 can be improved.

[0171] Also, according to the manufacturing method of the solar cell of the second embodiment, in the patterning of the first conductivity type semiconductor layer (first patterning), by using a pattern printing resist by the pattern printing method, while simplifying the manufacturing process of the solar cell, by using the bleeding film of the resin material in the pattern printing resist, as described above, the improvement of the reliability and performance of the solar cell 1 can be realized.

[0172] Note that in a flat semiconductor substrate having no pyramid-shaped fine concavo-convex structure (texture structure), even if a pattern printing resist by the pattern printing method is used, almost no bleeding of the resin material in the pattern printing resist occurs. That is, the characteristics of the solar cell 1 of the second embodiment described above can be realized by the combination of the use of a semiconductor substrate having a pyramid-shaped fine concavo-convex structure (texture structure) and the use of a pattern printing resist by the pattern printing method.

[0173] Further, according to the solar cell 1 of the second embodiment and its manufacturing method, by adjusting the size of the pyramid and / or the components and viscosity of the pattern printing resist, the bleeding width of the resin material in the pattern printing resist can be adjusted. By protecting the vicinity of the valley of the pyramid in the boundary region 8A (the bleeding region of the pattern printing resist) on the first region 7 side in the second region 8 on the back side of the semiconductor substrate 11, the film thickness of the semiconductor layer in the valley where the film thickness of the semiconductor layer tends to be thin even after the first semiconductor layer patterning is increased to improve reliability, and since the first semiconductor layer laminated on the top portion is removed, an optimal structure can be obtained in which current can be collected from this top portion without significant resistance loss. As a result, the optimization design of the characteristics of the solar cell 1 of the second embodiment described above becomes easy.

[0174] (Modification example) FIG. 19 is a cross-sectional view of a solar cell according to a modification example of the second embodiment, and is a cross-sectional view corresponding to line II-II in FIG. 11. Further, FIG. 20 is an enlarged cross-sectional view of the boundary region X between the first region 7 and the second region 8 shown in FIG. 19.

[0175] As shown in FIGS. 19 and 20, the boundary region 8A on the first region 7 side in the second region 8 is located between the transparent electrode layer 28 of the first electrode layer 27 and the transparent electrode layer 38 of the second electrode layer 37, and may not be located under the transparent electrode layer 38 of the second electrode layer 37. As a result, under the transparent electrode layer 38 of the second electrode layer 37, the film thicknesses of the second intrinsic semiconductor layer 33 and the second conductivity type semiconductor layer 35 (second semiconductor layer) on the second slope SF2 are thick, and the first intrinsic semiconductor layer 23 and the first conductivity type semiconductor layer 25 (first semiconductor layer) on the first slope SF1 and the second intrinsic semiconductor layer 33 and the second conductivity type semiconductor layer 35 (second semiconductor layer) Since the pyramid 11A with a large total film thickness is not located, an increase in resistance can be suppressed, and a decrease in the carrier extraction efficiency can be suppressed.

[0176] As described above, embodiments of the present invention have been explained. However, the present invention is not limited to the above-described embodiments, and various changes and modifications are possible. For example, in the above-described embodiment, in the boundary region 8A (the bleeding region of the pattern printing resist) on the first region 7 side in the second region 8 on the back side of the semiconductor substrate 11, a pyramid 11A having one bending point in the middle 2A from the foot of the mountain 1A to the peak 3A is exemplified. However, the present invention is not limited to this, and in the boundary region (the bleeding region of the pattern printing resist) on the first region side in the second region on the back side of the semiconductor substrate, a pyramid having two or more bending points from the foot of the mountain to the peak may be used.

[0177] In this case, each slope of the pyramid has three or more slopes having different inclination angles from the foot of the mountain to the peak. As a result, in the boundary region 8A (the bleeding region of the pattern printing resist) on the first region 7 side in the second region 8 on the back side of the semiconductor substrate 11, the film thicknesses of the second intrinsic semiconductor layer 33 and the second conductivity type semiconductor layer 35 (the second semiconductor layer) on each slope are different.

Explanation of symbols

[0178] 1 Solar cell 1A, 1B Foot of the mountain 2A Middle of the mountain 3A, 3B Peak 7 First region 7b, 8b Bus bar part 7f, 8f Finger part 8 Second region 8A Boundary region in the second region 11 Semiconductor substrate 11A, 11B Pyramid 13 Intrinsic semiconductor layer 15 Optical adjustment layer 23, 33 Intrinsic semiconductor layer 23Z, 33Z Intrinsic semiconductor layer material film 25 First conductivity type semiconductor layer 25Z First conductivity type semiconductor layer material film 27 First electrode layer 28, 38 Transparent electrode layer 28Z transparent electrode layer material film 29,39 metal electrode layer 35 second conductivity type semiconductor layer 35Z second conductivity type semiconductor layer material film 37 second electrode layer 41 lift-off layer 90 pattern printing resist 90A bleeding film L1 first virtual straight line L2 second virtual straight line SF1 first inclined plane SF2 second inclined plane SF3 third inclined plane

Claims

1. A back-contact solar cell comprising a semiconductor substrate, a first semiconductor layer and a first electrode layer sequentially stacked on a first region which is a part of the other main surface side opposite to one main surface side of the semiconductor substrate, and a second semiconductor layer and a second electrode layer sequentially stacked on a second region which is another part of the other main surface side of the semiconductor substrate, wherein a texture structure having a pyramidal fine concavo-convex structure is formed at least on the other main surface side of the semiconductor substrate, in a boundary region on the first region side in the second region on the other main surface side of the semiconductor substrate, the slope of the pyramid has a first slope from the base to the middle and a second slope from the middle to the top, the inclination of the second slope is gentler than the inclination of the first slope, in a cross section orthogonal to the base through the top, the minimum angle θ [°] formed by a first virtual straight line from the base to the top and a second virtual straight line from the base to the bending point of the middle is 8 < θ ≤ 30, the pyramid occupies 0.01% or more and 50% or less of the area of the other main surface, the film thickness of the second semiconductor layer on the second slope is thicker than the film thickness of the second semiconductor layer on the first slope, the boundary region is located between the first electrode layer and the second electrode layer and is not located under the second electrode layer, a solar cell.

2. A back-contact solar cell comprising a semiconductor substrate, a first semiconductor layer and a first electrode layer sequentially stacked on a first region which is a part of the other main surface side opposite to one main surface side of the semiconductor substrate, and a second semiconductor layer and a second electrode layer sequentially stacked on a second region which is another part of the other main surface side of the semiconductor substrate, wherein a texture structure having a pyramidal fine concavo-convex structure is formed at least on the other main surface side of the semiconductor substrate, in a boundary region on the first region side in the second region on the other main surface side of the semiconductor substrate, the slope of the pyramid has a first slope from the base to the middle and a second slope from the middle to the top, the inclination of the second slope is gentler than the inclination of the first slope, at least a part of the first slope has the first semiconductor layer and the second semiconductor layer sequentially stacked thereon, the film thickness of the second semiconductor layer on the second slope is thicker than the film thickness of the second semiconductor layer on the first slope, The boundary region is located between the first electrode layer and the second electrode layer and is not located under the second electrode layer. Solar cell. **Claim 3** A method for manufacturing a back-contact solar cell including a semiconductor substrate, a first semiconductor layer and a first electrode layer sequentially stacked on a first region which is a part of the other main surface side opposite to one main surface side of the semiconductor substrate, and a second semiconductor layer and a second electrode layer sequentially stacked on a second region which is another part of the other main surface side of the semiconductor substrate, the method comprising: forming a texture structure having a pyramidal fine concavo-convex structure on at least the other main surface side of the semiconductor substrate; forming a first semiconductor layer material film for forming the first semiconductor layer on the other main surface side of the semiconductor substrate; forming a resist on the material film of the first semiconductor layer in the first region; forming a patterned first semiconductor layer in the first region by removing the material film of the first semiconductor layer in the second region using the resist as a mask, and removing the resist; forming a patterned second semiconductor layer in the second region; including In the resist forming step, a printing material containing a resin material is printed and cured using a pattern printing method to form the resist in the first region, and an overflow film formed by overflow of the printing material is formed on a first slope from the skirt to the middle of the pyramid in a boundary region (overflow region of the printed resist) on the first region side in the second region; In the first semiconductor layer forming step, by etching the material film of the first semiconductor layer using the resist and the overflow film at its periphery as a mask, in the boundary region on the first region side in the second region, the slope of the pyramid has a first slope from the skirt to the middle and a second slope from the middle to the top; the inclination of the second slope is gentler than the inclination of the first slope; in a cross section passing through the top and orthogonal to the skirt, the minimum angle θ [°] formed by a first virtual straight line from the skirt to the top and a second virtual straight line from the skirt to the bending point of the middle is 8 < θ ≤ 30; the pyramid occupies 0.01% or more and 50% or less of the area of the other main surface; forming the pyramid In the second semiconductor layer forming step, in a boundary region (bleed-out region of a printing resist) on the first region side in the second region, a second semiconductor layer is formed in which the film thickness on the second slope is thicker than the film thickness on the first slope. Method for manufacturing a solar cell.

4. A method for manufacturing a back contact type solar cell including a semiconductor substrate, a first semiconductor layer and a first electrode layer sequentially stacked on a first region which is a part of the other main surface side opposite to one main surface side of the semiconductor substrate, and a second semiconductor layer and a second electrode layer sequentially stacked on a second region which is another part of the other main surface side of the semiconductor substrate, forming a texture structure having a pyramid-shaped fine concavo-convex structure on at least the other main surface side of the semiconductor substrate; a first semiconductor layer material film forming step of forming a material film of the first semiconductor layer on the other main surface side of the semiconductor substrate; a resist forming step of forming a resist on the material film of the first semiconductor layer in the first region; a first semiconductor layer forming step of forming the patterned first semiconductor layer in the first region by removing the material film of the first semiconductor layer in the second region using the resist as a mask, and removing the resist; a second semiconductor layer forming step of forming the patterned second semiconductor layer in the second region; including In the resist forming step, by printing and curing a printing material containing a resin material using a pattern printing method, the resist is formed in the first region, and a bleed-out film formed by bleeding of the printing material is formed on a first slope from a foot to a middle portion of the pyramid in a boundary region on the first region side in the second region. In the first semiconductor layer forming step, by etching the material film of the first semiconductor layer using the resist and a bleed-out film at its periphery as a mask, in a boundary region on the first region side in the second region, the slope of the pyramid has a first slope from a foot to a middle portion and a second slope from the middle portion to a peak. The inclination of the second slope is gentler than the inclination of the first slope. At least a part of the first slope has the first semiconductor layer stacked thereon. forming the pyramid In the second semiconductor layer forming step, in the boundary region on the first region side in the second region, the second semiconductor layer is formed on the first semiconductor layer on the first inclined surface, and the second semiconductor layer having a film thickness thicker than that on the first inclined surface is formed on the second inclined surface. Method for manufacturing a solar cell.

5. The method further includes an electrode layer forming step of forming the first electrode layer in the first region and the second electrode layer in the second region. In the electrode layer forming step, the first electrode layer and the second electrode layer are formed such that the boundary region is located between the first electrode layer and the second electrode layer and is not located under the second electrode layer. The method for manufacturing a solar cell according to claim 3 or 4.

6. The method further includes an electrode layer forming step of forming the first electrode layer in the first region and the second electrode layer in the second region. In the electrode layer forming step, the first electrode layer and the second electrode layer are formed such that the boundary region is located between the first electrode layer and the second electrode layer and under the second electrode layer on the first electrode layer side. The method for manufacturing a solar cell according to claim 3 or 4.

7. After the first semiconductor layer material film forming step, the method further includes a lift-off layer forming step of forming a lift-off layer on the material film of the first semiconductor layer. In the resist forming step, the resist is formed on the lift-off layer in the first region. In the first semiconductor layer forming step, using the resist as a mask, the material film of the lift-off layer and the first semiconductor layer in the second region are removed, so that the patterned lift-off layer and the first semiconductor layer are formed in the first region, and the resist is removed. Before the second semiconductor layer forming step, the method further includes a second semiconductor layer material film forming step of forming a material film of the second semiconductor layer on the lift-off layer in the first region and in the second region. In the second semiconductor layer forming step, by removing the lift-off layer, the material film of the second semiconductor layer in the first region is removed, and the patterned second semiconductor layer is formed in the second region. The method for manufacturing a solar cell according to any one of claims 3 to 6.

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