Method for surface processing of semiconductor wafer

Abstract

To realize reduction of a process-affected layer in a planarizing process method of a surface of a semiconductor wafer using anodic oxidation.SOLUTION: A surface processing method for planarizing a surface (W1) for a semiconductor wafer (W) includes: a first type of planarization process in which an oxide is generated on the surface by anodic oxidation and such an oxide is removed, and a second type of planarization process different from the first type of planarization process. The first type of planarization process is performed under processing conditions where an oxidation rate by anodic oxidation is equal to or greater than an oxide removal rate. The second type of planarization process is a process which is performed before the first type of planarization process to remove an oxide generated on the surface by the anodic oxidation under processing conditions where the oxide removal rate is equal to or greater than the oxidation rate. Alternatively, the second type of planarization process is a process which is performed after the first type of planarization process to further planarize the surface than the first type of planarization process.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a method for processing the surface of a semiconductor wafer. [Background technology]

[0002] Patent Document 1 discloses a polishing method using anodization. This polishing method involves simultaneously or alternately performing an anodization process and a polishing process in the presence of an electrolyte, polishing the surface of a workpiece under conditions where the polishing process has a higher removal rate than the anodization process. In the anodization process, a voltage is applied to the workpiece as the anode, oxidizing the surface of the workpiece. In the polishing process, oxides formed on the surface of the workpiece are polished and removed using a fixed-abrasive polishing body, in which abrasive grains of a predetermined hardness and grain size are fixed to a substrate. Specifically, this polishing method sequentially performs a high-speed polishing process and a low-speed polishing process. The high-speed polishing process has a high material removal rate and removes scratches and deep subsurface damage introduced during manufacturing. The high-speed polishing process also includes a damage-introducing device that uniformly introduces shallow damage into the subsurface of the workpiece. The low-speed polishing process has a low material removal rate and removes oxides caused by shallow damage to achieve planarization. This makes it possible to realize a high-speed polishing process that can replace the grinding and lapping processes that were previously used in the process of slicing an ingot to produce wafers. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2021-27359 Summary of the Invention [Problem to be solved by the invention]

[0004] In the manufacturing process of a semiconductor wafer, the lead time is determined by the processing time in surface planarization (i.e., grinding or polishing). Such processing time depends on the amount of the processing-affected layer that is replaced. The processing-affected layer is a surface layer having crystal strain, scratches, etc. caused by slicing or grinding. Therefore, in order to speed up the surface planarization and shorten the lead time in the manufacturing process of a semiconductor wafer, reduction of the processing-affected layer is an issue. In this regard, the polishing method described in Patent Document 1 introduces uniformly shallow damage under the surface of the workpiece in a high-speed polishing process, and such "shallow damage" corresponds to the processing-affected layer. That is, the polishing method described in Patent Document 1 increases rather than reduces the processing-affected layer in the high-speed polishing process. In this regard, conventionally, no surface planarization method focusing on reduction of the processing-affected layer has been proposed yet.

[0005] The present invention has been made in view of the circumstances exemplified above. That is, the present invention provides a technique for reducing the processing-affected layer, for example, in a method for planarizing the surface of a semiconductor wafer that employs anodic oxidation.

Means for Solving the Problem

[0006] The surface processing method according to claim 1 is a method for planarizing the surface (W1) of a semiconductor wafer (W), comprising: a first type of planarization processing in which an oxide is generated on the surface by anodic oxidation and the oxide is removed; and a second type of planarization processing different from the first type of planarization processing; wherein the first type of planarization processing is performed under processing conditions such that the oxidation rate by anodic oxidation is equal to or higher than the oxide removal rate; the second type of planarization processing is processing for removing the oxide generated on the surface by anodic oxidation before the first type of planarization processing under processing conditions such that the oxide removal rate is equal to or higher than the oxidation rate; or processing for further planarizing the surface more than the first type of planarization processing, which is performed after the first type of planarization processing. [[ID= The surface processing method according to claim 6 is a method for planarizing the surface (W1) of a semiconductor wafer (W), comprising: performing a first type of planarization process of forming an oxide on the surface by anodic oxidation and removing such an oxide; and a second type of planarization process different from the first type of planarization process; wherein as the first type of planarization process, a surface oxidation process of forming an oxide on the surface by anodic oxidation after a grinding process as the second type of planarization process; and an oxide removal process of removing the oxide formed by the surface oxidation process; are performed. The surface processing method according to claim 7 is a method for planarizing the surface (W1) of a semiconductor wafer (W), comprising: performing a first type of planarization process of forming an oxide on the surface by anodic oxidation and removing such an oxide; and a second type of planarization process different from the first type of planarization process; wherein as the first type of planarization process, a surface oxidation process of forming an oxide on the surface by anodic oxidation after a polishing process as the second type of planarization process; and an oxide removal process of removing the oxide formed by the surface oxidation process; are performed.

[0007] In each column of the application documents, reference numerals in parentheses may be assigned to each element in some cases. In such a case, the reference numerals merely indicate an example of the correspondence relationship between the same element and the specific configuration described in the embodiments below. Therefore, the present invention is not limited by the description of the reference numerals in any way. BRIEF DESCRIPTION OF THE DRAWINGS

[0008]

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Embodiments for Carrying Out the Invention

[0009] (Embodiment) Hereinafter, embodiments of the present invention will be described with reference to the drawings. Note that for various modification examples applicable to one embodiment, if they are inserted in the middle of a series of explanations regarding the embodiment, there is a risk of hindering the understanding of the embodiment. For this reason, the modification examples will not be inserted in the middle of the series of explanations regarding the embodiment, but will be collectively explained later.

[0010] (Surface Processing Apparatus) Referring to FIG. 1, the surface processing apparatus 1 is a processing apparatus that uses a semiconductor wafer W, which is a SiC wafer, as a workpiece, and is configured to flatten, i.e., grind or polish, a processed surface W1, which is one main surface of the semiconductor wafer W. The "main surface" is a surface orthogonal to the thickness direction of a layer-like or plate-like object, and is also referred to as the "plate surface". Specifically, in the present embodiment, the surface processing apparatus 1 is configured to be able to perform polishing or grinding using anodic oxidation on the processed surface W1 of the semiconductor wafer W. That is, the surface processing apparatus 1 has a configuration as an ECMP apparatus or an ECMG apparatus. ECMP is an abbreviation for Electro-Chemical Mechanical Polishing. ECMG is an abbreviation for Electro-Chemical Mechanical Grinding.

[0011] The surface processing apparatus 1 includes a container 2, a surface processing pad 3, a driving device 4, and a power supply device 5. As will be described later, FIG. 1 and the following description using the same are simplified solely for explaining the schematic configuration and functions of the surface processing apparatus 1 according to the present embodiment, and do not necessarily match the specific apparatus configuration actually manufactured and sold. Also, for the sake of simplicity of explanation, a right-handed XYZ coordinate system is set as shown in the figure. In the present embodiment, the positive Z-axis direction indicates vertically upward, i.e., the direction opposite to the direction of the weight acting direction. Also, both the X-axis direction and the Y-axis direction, which are orthogonal to each other, indicate the horizontal direction. Hereinafter, for convenience of explanation, the positive Z-axis direction side corresponding to vertically upward may be simply referred to as "upward", or the reverse may be simply referred to as "downward".

[0012] The container 2 is formed in a bathtub shape that opens upward. The container 2 is configured to hold the semiconductor wafer W at the bottom and accommodate it while being immersed in the electrolyte S that does not contain an etchant component. The etchant component is a component (such as hydrofluoric acid, for example) that constitutes a solution having the ability to dissolve the oxide film (i.e., the SiC oxide formed in a film shape) generated on the surface to be processed W1 by anodization. The electrolyte S is, for example, an aqueous solution of sodium chloride, potassium chloride, or sodium nitrate. The surface processing pad 3 and the drive device 4 are arranged above the container 2. The container 2, the surface processing pad 3, and the drive device 4 are provided so as to be relatively movable in the vertical direction by a lifting mechanism (not shown). Further, the container 2, the surface processing pad 3, and the drive device 4 are provided so as to be relatively movable in the in-plane direction (i.e., the horizontal direction orthogonal to the rotation axis) along the surface to be processed W1 by a slide mechanism (not shown).

[0013] The surface processing pad 3 has an electrode 31 and an abrasive layer 32. The electrode 31 is a plate-shaped member made of a good conductor such as metal and is formed of, for example, a copper plate. The abrasive layer 32 is joined to the electrode 31. That is, the surface processing pad 3 has a configuration in which the electrode 31 and the abrasive layer 32 are joined in the thickness direction of the surface processing pad 3. The abrasive layer 32 is formed of an abrasive stone (such as a diamond abrasive stone, for example) that is a grinding material or a polishing material. The surface processing pad 3 is provided such that the abrasive layer 32 is disposed opposite to the surface to be processed W1 of the semiconductor wafer W with the electrolyte S interposed therebetween. Then, the surface processing pad 3 is rotationally driven by the drive device 4 in a state where the abrasive layer 32 is disposed opposite to the surface to be processed W1 with the electrolyte S interposed therebetween, so that the oxide film generated on the surface to be processed W1 by anodization can be selectively polished or ground away.

[0014] The driving device 4 is configured to rotationally drive the surface processing pad 3 around the rotation axis along the vertical direction. The power supply device 5 is provided to pass a current for anodizing the work surface W1 to be processed by the grindstone layer 32 by applying a voltage with the semiconductor wafer W, which is the workpiece, as the anode and the electrode 31 on the surface processing pad 3 as the cathode in the presence of the electrolytic solution S.

[0015] (Surface processing method) The surface processing method according to the present disclosure is a method of planarizing the work surface W1, which is the surface of the semiconductor wafer W obtained from an ingot, using the surface processing apparatus 1. The surface processing method according to the present embodiment includes a first type of planarization process and a second type of planarization process. The first type of planarization process is a planarization process that generates an oxide film on the work surface W1 by anodic oxidation and uses anodic oxidation under processing conditions such that the generation of this oxide film is not overtaken by the removal of the oxide film. The second type of planarization process is a planarization process of the work surface W1, which is different from the first type of planarization process, and is performed before or after the first type of planarization process.

[0016] (First Embodiment) Hereinafter, the surface processing method according to the first embodiment will be described. In the present embodiment, the first type of planarization process is a process of removing the oxide generated on the work surface W1 by anodic oxidation under processing conditions such that the oxidation rate by anodic oxidation is equal to or higher than the oxide removal rate. Further, in the present embodiment, as the second type of planarization process, an anodic oxidation grinding process (that is, ECMG process) of removing the oxide generated on the work surface W1 by anodic oxidation by grinding under processing conditions such that the oxide removal rate is equal to or higher than the oxidation rate, which is performed before the first type of planarization process, is included. Furthermore, the present embodiment includes a polishing process as the second type of planarization process, which is performed after the first type of planarization process and further planarizes the work surface W1 more than the first type of planarization process.

[0017] FIG. 2 shows an outline of a method for manufacturing a semiconductor wafer W including the surface processing method according to the present embodiment. Hereinafter, an outline of the method for manufacturing the semiconductor wafer W, which is a SiC wafer, will be described with reference to FIGS. 1 and 2.

[0018] As shown in FIG. 2, the method for manufacturing the semiconductor wafer W according to the present embodiment includes an ingot forming step, a wafer slicing step, a grinding step, and a polishing step, in this order. Further, the grinding step includes a high-speed ECMG processing step which is a high-speed grinding step and a finish ECMG processing step which is a low-speed grinding step or a finish grinding step. The polishing step is a CMP processing step. CMP is an abbreviation for Chemical Mechanical Polishing. Note that, in order to briefly explain the content of the present invention, the process flow diagram shown in FIG. 2 shows an outline of a series of processes for planarizing, that is, finishing to an epitaxial mirror surface, a processed surface W1 of one of a pair of main surfaces of the semiconductor wafer W. Therefore, the specific process flow diagram in the case of planarizing both surfaces of the semiconductor wafer W does not match FIG. 2. The same applies to other embodiments from FIG. 3 onwards. Also, details such as beveling, inversion, and conveyance of the outer edge portion of the semiconductor wafer W, which are necessary in the actual manufacturing process of the semiconductor wafer W but have low relevance to the content of the present invention, are omitted in this specification because providing these explanations would make the specification redundant.

[0019] The ingot forming step is a step of processing a mass of single crystal SiC grown by crystal growth into a cylindrical ingot. The wafer slicing step is a step of obtaining the semiconductor wafer W, which is a thin disk-shaped SiC wafer, from the ingot by a well-known wafer slicing method such as wire slicing or laser slicing. The grinding step is the first-stage planarization step for the processed surface W1 of the semiconductor wafer W, which is performed prior to the subsequent polishing step. Thereby, the thickness of the semiconductor wafer W is adjusted to a predetermined range, and "undulations" and relatively large irregularities generated on the processed surface W1 in the wafer slicing step are removed. The polishing step is the second-stage, that is, the final-stage planarization step for the processed surface W1 of the semiconductor wafer W, which is performed after the grinding step. Thereby, the processed surface W1 of the semiconductor wafer W is finished to an epitaxial mirror surface, which is a surface state preferable for the semiconductor device manufacturing process.

[0020] In the manufacturing process of the semiconductor wafer W, the lead time is determined by the processing time in the surface flattening process (i.e., grinding or polishing). Here, in the wafer slicing process and the grinding process, a processed affected layer is generated on the processed surface W1 of the semiconductor wafer W. The processed affected layer includes damages such as scratches, crystal strain, cracks, and residual stress in the SiC surface and its vicinity. Such a processed affected layer serves as the "substitute" in the grinding process and the polishing process. Therefore, in order to shorten the lead time in the manufacturing process of the semiconductor wafer W, reducing the processed affected layer is an issue.

[0021] Therefore, in this embodiment, ECMG processing, which is a damage-free or low-damage grinding process, is adopted in the grinding process. ECMG processing is an anodic oxidation grinding process that selectively removes the oxide generated on the processed surface W1 by anodic oxidation through grinding. Specifically, in ECMG processing, with the semiconductor wafer W as the anode and the electrode 31 as the cathode, a current is applied in the presence of the electrolytic solution S, and at the same time, the surface processing pad 3 is rotationally driven to grind the processed surface W1 to be processed while anodizing it. Anodization and grinding can be performed simultaneously or alternately. By generating a relatively soft oxide on the processed surface W1 by anodic oxidation and selectively removing the generated oxide by grinding, it is possible to satisfactorily remove the processed affected layer generated in the wafer slicing process while favorably suppressing the generation of the processed affected layer due to grinding. In particular, in this embodiment, ECMG processing is performed under processing conditions such that the oxidation rate by anodic oxidation is equal to or higher than the oxide removal rate by grinding. As a result, the processed surface W1 after ECMG processing is in a state where there is no oxide film or a little oxide film remains. Even if a little oxide film remains on the processed surface W1, such an oxide film is a relatively soft film and can be easily removed in the subsequent process.

[0022] As shown in FIG. 2 , this embodiment uses a grinding process using ECMG, which includes a first-stage high-speed grinding process, called high-speed ECMG processing, and a second-stage finish grinding process, called finish ECMG processing. The high-speed ECMG processing, which is a rough grinding process, is a surface planarization process performed before the finish ECMG processing, which is a finish grinding process, using an abrasive harder than the semiconductor wafer W under processing conditions in which the grinding rate is equal to or greater than the oxidation rate. The finish ECMG processing is a finish grinding process performed between the high-speed ECMG processing and the polishing process under processing conditions in which the oxidation rate is equal to or greater than the grinding rate. Furthermore, this embodiment uses CMP processing as a polishing process for polishing the workpiece surface W1, which is a post-processing step after the finish ECMG processing. The finish ECMG processing corresponds to a “first type of planarization process,” and the high-speed ECMG processing and polishing processes correspond to a “second type of planarization process.” According to this embodiment, the workpiece surface W1 is roughly ground at a relatively high speed with little damage by the high-speed ECMG processing. The workpiece surface W1 is then finish-ground with no or very little damage by the finish ECMG process. During this process, the remaining of the workpiece surface W1 is effectively suppressed. The workpiece surface W1 is then finished to a satisfactory epi-ready surface by the subsequent polishing process. By dividing the wafer planarization process into three steps, both high-speed planarization and high-quality can be achieved. The high-speed ECMG process and the finish ECMG process may use a common surface processing device 1, or different surface processing devices 1. For example, a common surface processing device 1 may be used, and the surface processing pad 3 may be replaced between the high-speed ECMG process and the finish ECMG process. Alternatively, the semiconductor wafer W may be transported from the surface processing device 1 for the high-speed ECMG process to the surface processing device 1 for the finish ECMG process.

[0023] High-speed ECMG machining and finishing ECMG machining are processes in which the grinding wheel layer 32 as the abrasive on the surface machining pad 3 is disposed opposite to the work surface W1, and the oxide generated on the work surface W1 by anodic oxidation is selectively removed by the grinding wheel layer 32. Here, the grinding wheel layer 32 in high-speed ECMG and finishing ECMG machining can be formed of a well-known grinding wheel material. When the grinding wheel layer 32 in both high-speed ECMG and finishing ECMG machining is formed of diamond grinding wheels, the mesh number of the grinding wheel layer 32 in finishing ECMG machining can be equal to or greater than the mesh number of the grinding wheel layer 32 in high-speed ECMG machining. Specifically, for example, the mesh number of the grinding wheel layer 32 in finishing ECMG machining is selected within the range of 400 to 30,000, and the combination can be appropriately selected according to the workpiece to be processed. For example, after performing high-speed ECMG machining at a machining speed of 1.6 μm / min using a 30,000-mesh diamond grinding wheel as the grinding wheel layer 32, finishing ECMG machining is performed at a machining speed of 0.5 μm / min to flatten the semiconductor wafer W to TTV = 3.7 μm. TTV is the abbreviation of Total Thickness Variation. At this time, the work surface W1 after machining by high-speed ECMG machining had a surface roughness of Ra = 1.0 nm, and a machining-affected layer of about 100 to 500 nm remained. On the other hand, the machining time of the finishing ECMG machining was 1 minute. In the work surface W1 after the finishing ECMG machining, almost no residual machining-affected layer was confirmed, and an oxide film of about 10 to 20 nm was generated on the work surface W1, but no distortion of the atomic arrangement occurred. The work surface W1 after machining by the finishing ECMG machining had a surface roughness of Ra = 3.2 nm due to the formation of the oxide film, and the surface roughness decreased compared with that after high-speed ECMG machining. However, by appropriately removing the oxide film in the subsequent polishing process, good flattening could be achieved.

[0024] (Second Embodiment) Next, other embodiments will be described. In the following description of other embodiments, mainly the parts different from the first embodiment will be described. Also, in the first embodiment and other embodiments, parts that are the same or equivalent to each other are denoted by the same reference numerals. Therefore, in the following description of other embodiments, with respect to the components denoted by the same reference numerals as those in the first embodiment, the description in the first embodiment can be appropriately incorporated unless there is a technical contradiction or special additional explanation.

[0025] This embodiment includes, as the second type of planarization process, anodic grinding (i.e., ECMG process) with processing conditions such that the oxide removal rate is equal to or higher than the oxidation rate, which is performed before the first type of planarization process. Also, as the second type of planarization process, it includes a polishing process that is performed after the first type of planarization process.

[0026] FIG. 3 shows an outline of a method for manufacturing a semiconductor wafer W including a surface processing method according to the present embodiment. In the present embodiment, the polishing process in the first embodiment is replaced with an ECMP process instead of a CMP process. The ECMP process is an anodic oxidation polishing process that selectively removes the oxide formed on the surface to be processed W1 by anodic oxidation by polishing. The anodic oxidation and the polishing can be performed simultaneously or alternately. In the ECMP process, as the grindstone layer 32, a soft grindstone containing relatively soft abrasive grains (for example, ceria abrasive grains or the like) can be used. According to the present embodiment, by replacing the CMP process with an ECMP, which is a polishing process with less damage, high-speed and damage-free polishing of the surface to be processed W1 can be realized. Specifically, for example, after performing high-speed ECMG processing at a processing speed of 1.6 μm / min using a diamond grindstone of No. 30000 as the grindstone layer 32, finish ECMG processing is performed at a processing speed of 0.5 μm / min. Subsequently, an ECMP process is performed at a processing speed of 0.2 μm / min using a grindstone layer 32 containing ceria abrasive grains. The TTV of the processed semiconductor wafer W is 3.7 μm, and the processing time of the ECMP process is 2.5 minutes. The surface to be processed W1 after processing has a surface roughness of Ra = 0.5 nm, and no distortion of the atomic arrangement has occurred. Note that the high-speed ECMG process, the finish ECMG process, and the ECMP process may use the same surface processing apparatus 1 or different surface processing apparatuses 1.

[0027] (Third Embodiment) FIG. 4 shows an outline of a method for manufacturing a semiconductor wafer W including a surface processing method according to the present embodiment. In the present embodiment, the ECMP processing in the second embodiment is divided into two steps: a first-step high-speed ECMP processing, i.e., rough ECMP processing, and a second-step finishing ECMP processing. By the high-speed ECMP processing, the surface to be processed W1 is quickly mirror-finished. Then, by the subsequent finishing ECMP processing, the processed altered layer is almost completely removed. In this case, in the high-speed ECMP processing, the processing conditions are set such that the polishing rate is greater than the oxidation rate, and in the rough ECMP processing, the processing conditions are set such that the polishing rate is approximately equal to the oxidation rate, so that it is possible to achieve both the polishing processing rate and the surface quality of the surface to be processed W1. Note that the high-speed ECMP processing and the finishing ECMP processing may use the same surface processing apparatus 1 or different surface processing apparatuses 1.

[0028] (Fourth Embodiment) By reducing the number of process steps and the number of devices used in the wafer planarization process, it is possible to reduce the manufacturing cost. In this regard, the method for manufacturing a semiconductor wafer W according to the present embodiment shown in FIG. 5 replaces the polishing process in the first to third embodiments with an oxide film removal process using an etchant component. That is, in the present embodiment, the first type of planarization process is a finishing ECMG process performed under processing conditions where the oxidation rate is equal to or higher than the grinding rate, and the second type of planarization process is an oxide film removal process different from grinding and polishing, which is performed after the finishing ECMG process. Thereby, it is possible to form an epitaxial surface to be processed W1 with almost no residual processed altered layer at low cost.

[0029] (Fifth Embodiment) The manufacturing method of the semiconductor wafer W according to the present embodiment shown in FIGS. 6 and 7 is to integrate the two-step ECMG process in the second embodiment into one-step ECMG process corresponding to the finish ECMG process. That is, in the present embodiment, the first type of planarization process is an ECMG process performed under processing conditions where the oxidation rate is equal to or higher than the grinding rate, and the second type of planarization process is a polishing process performed after the ECMG process, that is, an ECMP process or a CMP process. Thereby, it becomes possible to form an epitaxial workpiece surface W1 with almost no remaining machining-affected layer at low cost. In the example of FIG. 6, the ECMG process and the ECMP process may use the same surface processing apparatus 1 or different surface processing apparatuses 1.

[0030] (Sixth Embodiment) The manufacturing method according to the first embodiment shown in FIG. 2 has, as the grinding process, a high-speed ECMG process which is a rough grinding process and a finish ECMG process which is a finish grinding process. And in the finish ECMG process, the processing conditions are set so that the oxidation rate is equal to or higher than the grinding rate. However, depending on the type of the semiconductor wafer W which is the workpiece and the surface processing pad 3, etc., it may be difficult to adjust the oxidation rate and the oxide removal rate, that is, the grinding rate, in the ECMG process.

[0031] Therefore, in such cases, anodizing alone is performed after the completion of rough grinding using ECMG processing, leaving a small oxide film on the workpiece surface W1. This oxide film can then be removed by subsequent polishing and cleaning processes, resulting in a workpiece surface W1 with almost no residual work-affected layer. Figure 8 illustrates an example of such a surface processing method. In other words, in this embodiment, after grinding as a second type of planarization, a first type of planarization process is performed: a surface oxidation process, which is an anodizing process that generates oxides on the workpiece surface W1 by anodizing, and an oxide removal process that removes the oxides generated on the workpiece surface W1 by the surface oxidation process. The surface oxidation process can be performed by the surface processing device 1 using a surface processing pad 3 that does not have a grinding wheel layer 32. Alternatively, the surface processing pad 3 can be rotated without being driven by the drive device 4 during the surface oxidation process. The oxide removal process is a surface planarization process other than grinding, such as polishing, oxide dissolution, or cleaning. This can reduce the damage layer on the workpiece surface W1 of the semiconductor wafer W that is subjected to polishing. In this case, the relationship between the oxidation rate in the surface oxidation process and the oxide removal rate in the subsequent oxide removal process may be, but is not particularly limited to, oxidation rate≧oxide removal rate. Furthermore, the ECMG process as a rough grinding process can be replaced with other types of grinding processes.

[0032] Similarly, the manufacturing method according to the third embodiment shown in FIG. 4 includes two polishing processes: a high-speed ECMP process, which is a rough polishing process, and a finish ECMP process, which is a finish polishing process. However, depending on the type of workpiece (semiconductor wafer W) and the surface processing pad 3, it may be difficult to adjust the oxidation rate and oxide removal rate (i.e., the polishing rate) during ECMP. Therefore, in such cases, anodization alone is performed after the completion of the rough polishing process by ECMP, leaving a small oxide film on the workpiece surface W1. By removing the oxide film in a subsequent process, it is possible to form a workpiece surface W1 with almost no residual damage due to the workpiece surface. FIG. 9 shows an example of such a surface processing method. That is, in this embodiment, after the polishing process as a second type of planarization process, a surface oxidation process, which is an anodization process for generating oxides on the surface by anodization, and an oxide removal process for removing the oxides generated by the surface oxidation process are performed as a first type of planarization process. Note that there is no particular limitation on the magnitude relationship between the oxidation rate during the surface oxidation process and the oxide removal rate during the subsequent oxide removal process. Also, the ECMP process as a rough polishing process can be replaced by other types of polishing processes.

[0033] (Summary of the embodiment) As described above, each of the above embodiments includes at least an anodization-assisted planarization process in which an oxide film is formed on the work surface W1 by anodization, and the process conditions are such that the removal of the oxide film does not outpace the formation of the oxide film. Therefore, each of the above embodiments provides a technology for reducing the process-affected layer in a method for planarizing the work surface W1 of a semiconductor wafer W using anodization.

[0034] (Variation) The present invention is not limited to the above-described embodiments. Therefore, the above-described embodiments can be appropriately modified. Hereinafter, typical modifications will be described. In the description of the following modifications, the differences from the above-described embodiments will be mainly described. Also, in the above-described embodiments and the modifications, the same or equivalent parts are denoted by the same reference numerals. Therefore, in the description of the following modifications, with respect to the components having the same reference numerals as those in the above-described embodiments, the description in the above-described embodiments can be appropriately incorporated unless there is a technical contradiction or a special additional explanation.

[0035] The present invention is not limited to the specific apparatus configuration shown in the above-described embodiments. That is, FIG. 1 and the following description using the same are simplified solely for explaining the schematic configuration and functions of the surface processing apparatus 1 according to the present embodiment, and do not necessarily match the specific apparatus configuration actually manufactured and sold. Specifically, for example, in the above-described embodiment, the semiconductor wafer W was held on the container 2 side, while the surface processing pad 3 was rotatably held above the semiconductor wafer W. However, the present invention is not limited to such a mode. That is, there may be a configuration in which the semiconductor wafer W is held by a chuck disposed above the container 2 and rotationally driven by a driving device 4, while the surface processing pad 3 is held on the container 2 side.

[0036] The electrolytic solution S may contain an etchant component. That is, the surface processing apparatus 1 according to the present invention, and the surface processing method that can be implemented thereby, may polish or grind the surface to be processed W1 by selectively removing the oxide film generated by anodization using both the etchant and the surface processing pad 3.

[0037] There is no particular limitation on the count and material of the grindstone layer 32. That is, within the range in which the effects of the present invention can be achieved satisfactorily, the count and material of the grindstone layer 32 can be appropriately selected.

[0038] The elements constituting the above-described embodiments are not necessarily essential, except in cases where it is explicitly stated that they are particularly essential or where they are considered to be clearly essential in principle. Also, when numerical values such as the number, quantity, range, etc. of components are mentioned, the present invention is not limited to those specific numerical values, except in cases where it is explicitly stated that they are particularly essential or where they are clearly limited to specific numerical values in principle. Similarly, when the shape, direction, positional relationship, etc. of components are mentioned, the present invention is not limited to those shape, direction, positional relationship, etc., except in cases where it is explicitly stated that they are particularly essential or where they are clearly limited to specific shape, direction, positional relationship, etc. in principle.

[0039] The modification examples are not limited to the above examples. That is, for example, in addition to those exemplified above, multiple embodiments can be combined with each other as long as they do not technically conflict. Similarly, multiple modification examples can be combined with each other as long as they do not technically conflict.

Explanation of Reference Numerals

[0040] 1 Surface processing apparatus 2 Container 3 Surface processing pad 31 Electrode 32 Grinding layer 4 Driving device 5 Power supply device S Electrolyte W Semiconductor wafer W1 Work surface (surface)

Claims

1. A surface processing method for planarizing the surface (W1) of a semiconductor wafer (W), comprising: a first type of planarization process of forming an oxide on the surface by anodic oxidation and removing such an oxide; a second type of planarization process different from the first type of planarization process; and having the first type of planarization process is performed under processing conditions such that the oxidation rate by anodic oxidation is equal to or higher than the oxide removal rate; the second type of planarization process is a process of removing, under processing conditions such that the oxide removal rate is equal to or higher than the oxidation rate, the oxide formed on the surface by anodic oxidation, which is performed before the first type of planarization process or a process of further planarizing the surface after the first type of planarization process, which is more planar than the first type of planarization process is a surface processing method.

2. The first type of planarization process is an anodic oxidation grinding process performed under processing conditions such that the oxidation rate is equal to or higher than the grinding rate; the second type of planarization process is a polishing process or an oxide film removal process performed after the first type of planarization process, The surface processing method according to claim 1.

3. As the second type of planarization process, before the first type of planarization process, a high-speed grinding process of grinding the surface under processing conditions such that the grinding rate is equal to or higher than the oxidation rate by using a grinding material harder than the semiconductor wafer; after the first type of planarization process, a polishing process of polishing the surface; are performed, the first type of planarization process is a finish grinding process performed under processing conditions such that the oxidation rate is equal to or higher than the grinding rate between the high-speed grinding process and the polishing process, The surface processing method according to claim 1.

4. The polishing process is an anodic oxidation polishing process of selectively removing, by polishing, the oxide formed on the surface by anodic oxidation, The surface processing method according to claim 3.

5. The high-speed grinding process and the finish grinding process are processes of disposing the grinding wheel layer of a surface processing pad (3) having the grinding wheel layer (32) as the grinding material opposite to the surface and selectively removing, by the grinding wheel layer, the oxide formed on the surface by anodic oxidation; the grinding wheel layer in the high-speed grinding process and the finish grinding process is formed of a diamond grinding wheel; the number of meshes of the grinding wheel layer in the finish grinding process is equal to or higher than the number of meshes of the grinding wheel layer in the high-speed grinding process, The surface processing method according to claim 3 or 4.

6. The semiconductor wafer is a SiC wafer, The surface processing method according to any one of claims 1 to 5.

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