Circuit and method for providing a switched-capacitor integrator

Abstract

The integrator circuit includes an operational amplifier, a first capacitor coupled to an input of the operational amplifier, a second capacitor, and a second switch configured to electrically couple a first terminal of the second capacitor to a second terminal of the first capacitor coupled in parallel with the first capacitor such that a first terminal of the first capacitor is configured to be electrically coupled to a first terminal of the second capacitor by the first switch.

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to and benefit of U.S. patent application Ser. No. 16 / 892,193, filed June 3, 2020, which is incorporated herein by reference for all applicable purposes as if fully set forth below in its entirety.

[0002] FIELD OF THE INVENTION

[0002] This application relates generally to integrator circuits, and more particularly to switched-capacitor integrator circuits. [Background technology]

[0003]

[0003] Some systems use, for example, an integrator circuit to measure a voltage. For example, one system has a sampling capacitor disposed within a switch network. During a first phase, called the sampling phase, the switch network couples the sampling capacitor between ground and the voltage to be measured. During a second phase, called the integration phase, the switch network isolates the capacitor from ground and the voltage to be measured and instead couples it between a reference voltage and an operational amplifier (op amp) input. The output of the op amp is the integrated voltage.

[0004] However, problems can arise when measuring voltages that may be as high as the reference voltage. In particular, if the level of the reference voltage and the level of the voltage to be measured are approximately the same, the integrator may become saturated and thereby potentially be unable to provide a reliable output.

[0005]

[0005] Therefore, there is a need for a more reliable integrator, and more particularly, an integrator that is less likely to saturate when measuring voltage levels that are approximately the same as a reference voltage level. Summary of the Invention

[0006]

[0006] Various implementations are directed to circuits and methods that provide a more reliable integrator circuit. In one example, the integrator circuit may have a smaller capacitor coupled in parallel with a sampling capacitor. During the sampling phase, both the sampling capacitor and the smaller capacitor are charged. During the integration phase, a switch is closed to create a feedback loop with the amplifier, and the terminals of the smaller capacitor are swapped to subtract a portion of the sample charge on the sampling capacitor. The effect is that the dynamic range of the input signal may be compressed, thereby preventing the integrator from saturating and allowing the integrator to provide a useful and reliable output.

[0007]

[0007] According to one implementation, an integrator circuit includes an operational amplifier, a first capacitor coupled to an input of the operational amplifier, a second capacitor, and a second switch configured to electrically couple a first terminal of the second capacitor to a second terminal of the first capacitor, the second capacitor being coupled in parallel to the first capacitor such that a first terminal of the first capacitor is configured to be electrically coupled to a first terminal of the second capacitor by a first switch.

[0008]

[0008] According to another implementation, a method for operating an integrator circuit includes electrically coupling a first terminal of a first capacitor to a first terminal of a second capacitor during a sampling phase of the integrator circuit, and electrically coupling a second terminal of the first capacitor to a first terminal of the second capacitor during an integrating phase of the integrator circuit.

[0009]

[0009] According to another implementation, an integrator circuit includes an operational amplifier, a first capacitor coupled to the input of the operational amplifier, a second capacitor, and means for electrically coupling the second capacitor in parallel to the first capacitor during a sampling phase of the integrator circuit, and for reversing the polarity of the second capacitor relative to the first capacitor during an integration phase of the integrator circuit.

[0010]

[0010] According to yet another implementation, a system on chip (SOC) includes a bandgap reference generator configured to generate a bandgap voltage, and an analog to digital converter (ADC) coupled to receive the bandgap voltage from the bandgap reference generator, wherein the ADC includes an integrator circuit having a first capacitor, a second capacitor, and a second switch configured to electrically couple a first terminal of the second capacitor to a second terminal of the first capacitor, the second capacitor being coupled in parallel to the first capacitor such that a first terminal of the first capacitor is configured to be electrically coupled to a first terminal of the second capacitor by the first switch. [Brief explanation of the drawings]

[0011] [Figure 1]

[0011] FIG. 1 is a diagram of an exemplary integrator circuit, according to various implementations. [Figure 2]

[0012] 2 is a diagram of the exemplary integrator circuit of FIG. 1 according to one implementation. [Figure 3]

[0013] 3 is a diagram of an exemplary architecture for constructing the integrator circuit of FIGS. 1 and 2, according to one implementation. [Figure 4]

[0014] 4 is a diagram of the example integrator circuit of FIG. 3 during a sampling phase, according to one implementation. [Figure 5]

[0015] 4 is a diagram of the example integrator circuit of FIG. 3 during an integration phase, according to one implementation. [Figure 6]

[0016] 6 is a diagram of an exemplary curve illustrating the dynamic range compression of an input voltage that can be achieved using an integrator circuit according to the principles of FIGS. 1-5, according to one implementation. [Figure 7]

[0017] 4 is a flow diagram of an exemplary method of using an integrator circuit, according to one implementation. [Figure 8]

[0018] 1 is a diagram of a Sigma Delta modulator using an integrator circuit, according to one implementation. [Figure 9]

[0019] 1 is a diagram of a system-on-chip (SOC) implementing a sigma-delta modulator that may include an integrator circuit, according to one implementation. DETAILED DESCRIPTION OF THE INVENTION

[0012]

[0020] Various implementations provided herein include circuits and methods for providing a more reliable switched-capacitor integrator circuit. In some implementations, the switched-capacitor integrator circuit may be included in an analog-to-digital converter (ADC), although the scope of implementations is not limited to ADCs.

[0013]

[0021] One exemplary implementation includes an integrator circuit having a sampling capacitor coupled to an input of an operational amplifier (op-amp) and an additional capacitor coupled in parallel to the sampling capacitor such that a first terminal of the sampling capacitor is coupled to a first terminal of the additional capacitor by a first switch. The integrator circuit also has a second switch that couples the first terminal of the additional capacitor to a second terminal of the sampling capacitor. Thus, during the sampling phase, both the sampling capacitor and the additional capacitor can be charged. During the integration phase, the terminals of the additional capacitor are swapped, which subtracts a portion of the sample charge from the sampling capacitor.

[0014]

[0022] Continuing with this example, subtracting a portion of the sample charge causes the dynamic range of the input signal to be compressed. In this example, the input signal may be the voltage to be measured. Furthermore, the integrator circuit may use a reference voltage having a level that is approximately the same as the level of the voltage to be measured. However, because the input voltage (the voltage to be measured) has its dynamic range compressed, the highest level the input voltage reaches may be reduced by a known portion (e.g., 5%), which, in this example, is sufficient to prevent saturation of the integrator. Or, in other words, the level of the input voltage when applied to the operational amplifier may be lower than the reference voltage so that the difference between the input voltage and the reference voltage reduces or avoids saturation.

[0015]

[0023] Further, in this example, the integrator circuit may include any suitable values of capacitance for the sampling capacitor and the additional capacitor. In one example, the additional capacitor has a capacitance that is less than 10% of the sampling capacitor. However, in any particular application, the value of the additional capacitor may depend on the desired level of compression of the dynamic range of the input voltage.

[0016]

[0024] Continuing with this example, the integrator circuit may further receive a first clock signal to the first switch and a second clock signal to the second switch. The first and second clock signals may be non-overlapping. When the first clock signal is high, it corresponds to the sampling phase, and when the second clock signal is high, it corresponds to the integration phase of the integrator.

[0017]

[0025] An exemplary application of an integrator circuit includes a sigma-delta modulator with an ADC. For example, a sigma-delta modulator can be used to measure the output of a bandgap reference generator when the bandgap voltage is approximately the same level as the power rail (VDD). When the integrator circuit measures the bandgap voltage and uses VDD as the reference voltage, the principles described above compress the dynamic range of the bandgap voltage so that the voltage seen by the operational amplifier is sufficiently different from the VDD level to reduce or avoid saturation of the integrator circuit.

[0018]

[0026] Various implementations may include a method of operating an integrator circuit. For example, the method may include coupling a first terminal of a sampling capacitor to a first terminal of an additional capacitor during a sampling phase of the integrator circuit. The method may further include coupling a second terminal of a second capacitor to the first terminal of the additional capacitor during an integration phase of the integrator circuit. In this example, reversing the polarity of the additional capacitor relative to the sampling capacitor subtracts a portion of the sample charge.

[0019]

[0027] An advantage of some of the implementations described above is that they may offer improved performance relative to other integrator circuits by reducing or preventing saturation. Another advantage is that various implementations may be implemented by adding small capacitors and multiple switches, which provides a low-power solution and silicon area savings compared to solutions that attempt similar results but may add one or more operational amplifiers. Signal degradation due to dynamic range compression may be offset by increased linearity of the system. In other words, in various applications, the increased linearity may provide satisfactory operation for systems that measure input voltage levels close to the level of a reference voltage, and the loss of accuracy due to dynamic range compression may be significantly less than the loss of accuracy that would be expected from saturation.

[0020]

[0028] 1 is a diagram of an integrator circuit 100 according to one implementation. The integrator circuit 100 includes three different capacitors: Capacitor CS is a sampling capacitor that is disposed between a voltage input Vin and an inverting input to an operational amplifier (opamp) 110; Capacitor CA is an additional capacitor that is disposed in parallel with the sampling capacitor CS; and Capacitor CF is a feedback capacitor that is coupled to both the inverting input and the output of the opamp 110.

[0021]

[0029] The integrator circuit 100 also includes various switches for making and breaking connections. A first set of switches is labeled S1 and a second set of switches is labeled S2.

[0022]

[0030] Looking first at the sampling phase, the S1 switch is on, while the S2 switch is off. This creates an electrical path from the voltage input Vin to the terminal labeled Vcm. In this implementation, Vcm may refer to a common-mode voltage, which may be used as a virtual ground. In another implementation, Vcm may refer to an actual ground. In either case, in the implementation of FIG. 1, the input voltage Vin is the voltage to be measured, and Vcm is either a virtual ground or a ground. The reference voltage Vref refers to a power supply voltage, which may include voltage drain-drain (VDD). During the sampling phase, the terminal labeled Vref is isolated from the sampling capacitor CS, as well as the inverting input to the operational amplifier 110, because switch S2 is closed.

[0023]

[0031] During the sampling phase, capacitor C charges. Similarly, because an additional capacitor C is connected in parallel with sampling capacitor C, the additional capacitor C also charges. Capacitors C and C may be sized relative to one another according to the objectives of the application. As described above, capacitor C may be small compared to capacitor C so that it may subtract a portion of the sample charge from capacitor C. The subtracted portion of charge may be large enough to compress the dynamic range of the input voltage as seen at the inverting input to operational amplifier 110 to reduce or prevent saturation, yet small enough to enable integrator circuit 100 to provide an accurate output. Thus, in one example, capacitor C has a capacitance of about 10% or less of sampling capacitor C, although various applications may use different relative capacitances.

[0024]

[0032] FIG. 2 shows an exemplary integrator circuit 100 according to one implementation. FIG. 2 shows the exemplary integrator circuit 100 during the integration phase, which follows the sampling phase of FIG. 1. During the integration phase, switch S1 is turned off (open), while switch S2 is turned on (closed). When switch S1 is turned off, the input voltage and Vcm are electrically isolated or disconnected from the sampling capacitor CS. Turning on switch S2 electrically couples the switching capacitor CS to Vref and to the inverting input of the operational amplifier 110.

[0025]

[0033] Furthermore, during the integration phase, the polarity of the additional capacitor CA is reversed compared to its polarity in FIG. 1. In other words, if during the sampling phase the first terminal of capacitor CA is coupled to the first terminal of capacitor CS and the second terminal of capacitor CA is coupled to the second terminal of capacitor CS, then during the integration phase, those terminals are seen as connected: the first terminal to the second terminal and the second terminal to the first terminal. As a result, the charge stored in the additional capacitor CA during the sampling phase is discharged during the integration phase, thereby subtracting that charge from capacitor CS. The output Vout represents the integral of the input voltage Vin.

[0026]

[0034] 1 and 2 alternates between sampling and integration phases during operation according to a set of clocks, such as those described below with respect to Figures 3-5. Thus, at least when the clock is applied, the integrator circuit 100 performs alternating sampling and integration phases according to the frequency of the clock.

[0027]

[0035] FIG. 3 is a diagram of an exemplary integrator circuit 200 according to one implementation. The integrator circuit 200 illustrates one way in which the integrator circuit 100 of FIGS. 1 and 2 can be made using NMOS transistors for switches S1 and S2 and operated by clock 1 and clock 2. Switches S1 and S2 can be made using any suitable technology. For example, some implementations may use negative-channel metal-oxide-semiconductor (NMOS) transistors such that a logic 1 applied to the gate turns on the transistor. In other cases, some implementations may use positive-channel metal-oxide-semiconductor (PMOS) transistors such that a logic 0 applied to the gate turns on the transistor. While various applications may use any suitable transistor or switch technology, the clocks described below with respect to FIGS. 4 and 5 assume NMOS transistors as an example for ease of understanding. However, the scope of implementations is not limited to any switch technology. For example, some implementations may use mechanical switches or relay switches.

[0028]

[0036] Again, the sets of switches are shown as a first set of switches S1 and a second set of switches S2. In this example, switch S1 is operated according to clock 1, and switch S2 is operated according to clock 2. Note that in this example, clock 1 and clock 2 do not have overlapping areas of logic 1, but they do have overlapping areas of logic 0. Such a design reduces the chance of all of the switches being closed at the same time, which could result in a short circuit or undesired discharge of one or more of capacitors C, C, and C. Also, in this example, the integration and sampling phases are non-overlapping and separate from one another, as indicated by the 180° offset of clock 1 and clock 2.

[0029]

[0037] An additional switch is shown in FIG. 3 to illustrate one possible technique for enabling the polarization of the additional capacitor CA versus the sampling capacitor CS to be reversed. In this example implementation, the additional switch may also be operated according to either clock 1 or clock 2 as shown.

[0030]

[0038] 4 is a diagram of an exemplary integrator circuit 200 during a sampling phase. In the exemplary sampling phase, clock 1 is at logic 1, while clock 2 is at logic 0. Switch S1 is on, thereby electrically coupling an additional capacitor CA between Vcm and Vin. When switch S1 is on, switch S1 also electrically couples sampling capacitor CS between Vin and Vcm. Switch S2 is off.

[0031]

[0039] Further in this example, terminal 401 of additional capacitor CA is electrically coupled to terminal 411 of sampling capacitor CS. Both capacitor Cs and capacitor CA are charged during the sampling phase. The electrical coupling is through switch S1, which is shown closed in FIG. 4.

[0032]

[0040] 5 is a diagram of exemplary integrator circuit 200 during the integration phase. In the exemplary integration phase, clock 1 is at logic 0 and clock 2 is at logic 1. Switch S2 is on and switch S1 is off. Thus, an additional capacitor CA is electrically coupled between Vref and terminal 511 of sampling capacitor CS, which is closest to operational amplifier 110.

[0033]

[0041] Here, terminal 401 of additional capacitor CA is electrically coupled to terminal 511 of sampling capacitor CS. This electrical coupling is due to switch S2, which is shown as closed in Figure 5, being on. Thus, the polarity of additional capacitor CA is reversed with respect to sampling capacitor CS compared to the configuration shown in Figure 4. Capacitor CA subtracts charge from capacitor CS during the integration phase.

[0034]

[0042] Integrator circuit 200 alternates between sampling and integration phases, just as described above with respect to Figures 1 and 2. Although only two clock cycles are shown in Figures 4-5, it should be understood that clocks 1 and 2 may continue to run for as long as desired, thereby producing a waveform at Vout that integrates the difference Vin-Vref.

[0035]

[0043] Of course, the range of implementations is not limited to the specific implementations shown in Figures 4 and 5. For example, another implementation could use PMOS transistors as switches S1 and S2, in which case clocks 1 and 2 would be inverted. As mentioned above, the range of implementations is not limited to any switch technology.

[0036]

[0044] Furthermore, capacitors C, C, and C may be implemented in any suitable manner, such as by using NMOS capacitors, metal plate capacitors, etc. Thus, the range of implementations is not limited to any capacitor technology.

[0037]

[0045] Moreover, there are different types of op-amps, such as inverting, inverting-summing, and non-inverting. The range of implementations is not limited to any op-amp technology.

[0038]

[0046] During the sampling phase, capacitors C and C are connected in parallel. Thus, the charge stored on C is given by the following equation, where QS is the charge, and C S is the capacitance of CS.

[0039]

number

[0040]

[0047] Similarly, the charge stored in CA is given by, where q A is the charge, and C A is the capacitance of CA.

[0041]

number

[0042]

[0048] During the integration phase, the terminals of the capacitor CA are swapped, thus transferring the charge q A Q S is subtracted from Q F is the charge on the capacitor CF, and ΔQ F is the fraction of charge added to the total charge on the CF in each integration phase.

[0043]

number

[0044]

[0049] At this point, the compressed level of Vin, V EFF The concept of ΔQ is also introduced. F However, V as shown in Figure 6 EFF Note how this can be expressed in terms of

[0045]

number

[0046]

[0050] The change in charge on the feedback capacitor CF for a system omitting CA is

[0047]

number

[0048] is given by

[0049]

[0051] In the exemplary implementation of FIGS. 1-5, Vin and V EFF A difference between V and V will result in reduced or eliminated saturation in the integrator circuit. Thus, one advantage of the implementations described herein is the ability to compress the level of V to reduce or avoid saturation, along with capacitor and switch configurations that do not result in excessive silicon area in many applications.

[0050]

[0052] FIG. 6 shows V vs. V in one exemplary implementation. EFF 6 is a diagram of an example curve 600 plotting the effective input voltage V. In this example, the ratio of the additional capacitor CA to the sampling capacitor CS is 0.1. Furthermore, Vcm is the true common-mode voltage, which is equal to 1 / 2 of VDD, and the rail-to-rail input Vin is in the range of 0 to VDD. EFF Using the formula for (above) and just plugging in the given values, V EFF are equal to 95% of VDD when Vin=VDD and 5% when Vin=0, respectively.

[0051]

[0053] A flow diagram of an exemplary method 700 for operating an integrator circuit is shown in Figure 7. In one example, method 700 is performed by any of the implementations shown in Figures 1-5 by receiving at least two clock signals and operating a set of switches, such as those shown above as switch S1 and switch S2.

[0052]

[0054] In action 710, a first terminal of the sampling capacitor is electrically coupled to a first terminal of an additional capacitor during the sampling phase of the integrator circuit. An example in which an additional capacitor CA is electrically coupled in parallel to the sampling capacitor CS is shown in FIG. 4. In that example, terminal 401 of capacitor CA is electrically coupled to terminal 410 of the sampling capacitor CS. The electrical coupling may be implemented by turning on a transistor disposed in the electrical signal path. For example, a transistor (e.g., S1) may be controlled by a first clock. A second clock may turn off another transistor (e.g., S2).

[0053]

[0055] Action 710 may also include electrically coupling a second terminal of the first capacitor to a second terminal of the second capacitor during the sampling phase.

[0054]

[0056] In action 720, the second terminal of the sampling capacitor is coupled to the first terminal of the additional capacitor during the integration phase of the integrator circuit. For example, in FIG. 5, terminal 401 of additional capacitor CA is electrically coupled to terminal 511 of sampling capacitor CS. Again, the electrical coupling may be implemented by using at least two clocks to turn on a transistor (e.g., S2) and turn off another transistor (e.g., S1). The integration phase in this example includes subtracting a portion of the sample charge from sampling capacitor CS before the sample charge is integrated in the operational amplifier. Furthermore, the integration phase in this example includes discharging the sampling capacitor into a feedback loop created by feedback capacitor CF and the inverting input to the operational amplifier.

[0055]

[0057] Action 720 may also include electrically coupling the first terminal of the first capacitor to the second terminal of the second capacitor during the integration phase.

[0056]

[0058] The range of implementations is not limited to the actions shown in Figure 7. Rather, various implementations may add, omit, rearrange, or modify various actions. For example, some implementations may include repeating actions 710-720 according to the frequency of a clock.

[0057]

[0059] 8 is a diagram of an exemplary sigma-delta modulator 800, according to one implementation. The sigma-delta modulator 800 may include an integrator block 801. The integrator implementations presented in FIGS. 1-7 are implemented to convert the difference (Vin-V REF ) and thus encompasses both the "+" block 804 and the integrator block 801 in Figure 8. Furthermore, the sigma-delta modulator 800 may be used in some implementations as an analog-to-digital converter (ADC).

[0058]

[0060] The sigma-delta modulator 800 includes an integrator block 801, which is a discrete-time, switch-capacitor integrator circuit, such as those described above with respect to Figures 1-7. The integrator block 801 is configured such that the input signal Vin is input to V before the input, as shown in Figure 8. EFF where V EFF is used as an input. The output of the integrator 801 is provided to a single-bit ADC 802. The output of the ADC 802 is fed back through a digital-to-analog converter (DAC) 803. In a single-bit implementation, the ADC 802 is a comparator and the DAC 803 is a 1-bit DAC. The range of implementations also includes multi-bit modulators where the output of the ADC 802 is fed back to the DAC 803, where the DAC 803 is scaled to the appropriate resolution. The output of the ADC 802 (Vt) is EFF This is a digital output that represents the level of Vin.

[0059]

[0061] The sigma-delta modulator 800 of Figure 8 can be used in a variety of applications. One such application is described in more detail with respect to Figure 9, where the sigma-delta modulator 800 provides a measured output for a reference voltage within a system-on-chip (SOC).

[0060]

[0062] FIG. 9 is a diagram of an exemplary SOC 900 according to one implementation. In this example, the SOC 900 is implemented on a semiconductor die and includes multiple system components 910-990. Specifically, in this example, the SOC 900 includes a central processing unit (CPU) 910, which is a multi-core general-purpose processor having four processor cores, Core 0-Core 3. Of course, the scope of implementations is not limited to any particular number of cores, as other implementations may include two cores, eight cores, or any other suitable number of cores in the CPU 910. The SOC 900 further includes other system components, such as a first digital signal processor (DSP) 940, a second DSP 950, a modem 930, a graphics processing unit (GPU) 920, a video subsystem 960, a wireless local area network (WLAN) transceiver 970, and a video front-end (VFE) subsystem 980.

[0061]

[0063] The SOC 900 also includes a reference generator 990, which in this example includes a bandgap reference generator. The reference generator 990 provides reference currents and reference voltages to different components on the SOC 900. For example, each of the different components 910-980 may include various subcomponents that use reference voltages or reference currents. Examples of subcomponents that may use reference voltages or reference currents include low dropout (LDO) voltage regulators, ADCs, current-mode logic (CML) buffers, phase-locked loops (PLLs), delay-locked loops (DLLs), amplifiers, filters, serializer-deserializer physical interfaces (SERDES PHYs), and various loads. While such subcomponents are not explicitly shown in FIG. 9 , it should be understood that the SOC of FIG. 9 would be expected to include multiple subcomponents that employ reference voltages or currents.

[0062]

[0064] The SOC 900 may implement the sigma-delta modulator 800 to measure the bandgap voltage from the reference generator 990. For example, when the sigma-delta modulator 800 is implemented using an integrator circuit according to the architecture shown in FIGS. 1-5, it will input the bandgap voltage from the reference generator 990 as Vin and use VDD from a power rail as Vref. The ground can be either a common-mode voltage or a ground power rail (e.g., voltage source-source (VSS)). If the bandgap voltage from the reference generator 990 has a range similar to VDD, the integrator circuit will compress the dynamic range of the bandgap voltage to avoid integrator saturation and ensure an accurate output of the sigma-delta modulator 800.

[0063]

[0065] As those skilled in the art will by now appreciate, depending on the particular application at hand, many modifications, substitutions, and variations may be made in and to the materials, apparatus, construction, and methods of use of the devices of the present disclosure without departing from the spirit and scope of the present disclosure. In light of this, as the specific implementations shown and described herein are merely examples of the present disclosure, the scope of the present disclosure should not be limited thereto, but rather should correspond fully to the following appended claims and their functional equivalents. The inventions described in the claims of the present application as originally filed are set forth below. [C1] an operational amplifier; a first capacitor coupled to the input of the operational amplifier; a second capacitor coupled in parallel to the first capacitor such that a first terminal of the first capacitor is configured to be electrically coupled to the first terminal of the second capacitor by a first switch; a second switch configured to electrically couple the first terminal of the second capacitor to the second terminal of the first capacitor; 1. An integrator circuit comprising: [C2] The integrator circuit of C1, wherein the capacitance of the second capacitor is less than the capacitance of the first capacitor. [C3] 10. The integrator circuit of claim 1, further comprising a first clock signal applied to the first switch and a second clock signal applied to the second switch, wherein the first clock signal and the second clock signal are non-overlapping. [C4] 10. The integrator circuit of claim 9, wherein the first switch is configured to electrically couple the first terminal of the first capacitor to the first terminal of the second capacitor during a sampling phase of the integrator circuit, wherein the sampling phase includes charging the first capacitor. [C5] 10. The integrator circuit of claim 9, wherein the second switch is configured to electrically couple the first terminal of the second capacitor to the second terminal of the first capacitor during an integration phase of the integrator circuit, wherein the integration phase includes discharging the first capacitor. [C6] The integrator circuit of C5, wherein a sampling phase and the integration phase do not overlap. [C7] The integrator circuit of C1, wherein the first switch is configured to electrically couple the first terminal of the second capacitor to a voltage input of the integrator circuit. [C8] The integrator circuit of C1, wherein the second switch is configured to electrically couple the first terminal of the second capacitor to the input of the operational amplifier. [C9] 10. The integrator circuit of claim 1, further comprising a third switch, wherein the third switch is configured to electrically couple a second terminal of the second capacitor to a power rail of the integrator circuit, and wherein the third switch receives the same clock signal as the second switch. [C10] 10. The integrator circuit of claim 1, further comprising a third switch, wherein the third switch is configured to electrically couple a second terminal of the second capacitor to a reference voltage of the integrator circuit, and wherein the third switch receives the same clock signal as the second switch. [C11] 10. The integrator circuit of claim 1, further comprising a third switch, wherein the third switch is configured to electrically couple a second terminal of the first capacitor to an inverting input of the operational amplifier, and wherein the third switch receives the same clock signal as the second switch. [C12] The integrator circuit of C1, wherein the integrator circuit is included in a sigma-delta modulator. [C13] The integrator circuit of C12, wherein the sigma-delta modulator comprises an analog-to-digital converter (ADC). [C14] The integrator circuit of C12, wherein the sigma-delta modulator is configured to measure the output of a bandgap reference generator. [C15] The integrator circuit of C1, wherein the integrator circuit comprises a discrete-time switched-capacitor integrator. [C16] 1. A method of operating an integrator circuit, said method comprising: electrically coupling a first terminal of a first capacitor to a first terminal of a second capacitor during a sampling phase of the integrator circuit; electrically coupling a second terminal of the first capacitor to the first terminal of the second capacitor during an integration phase of the integrator circuit; A method comprising: [C17] The method of C16, wherein the second terminal of the first capacitor is electrically coupled to a second terminal of the second capacitor during the sampling phase. [C18] The method of C16, wherein the first terminal of the first capacitor is electrically coupled to the second terminal of the second capacitor during the integration phase. [C19] 1. An integrator circuit comprising: an operational amplifier; a first capacitor coupled to the input of the operational amplifier; a second capacitor; means for electrically coupling the second capacitor in parallel with the first capacitor during a sampling phase of the integrator circuit, and for reversing the polarity of the second capacitor relative to the first capacitor during an integration phase of the integrator circuit; 1. An integrator circuit comprising: [C20] 19. The integrator circuit of claim 19, wherein the means for electrically coupling comprises a first switch configured to couple a first terminal of the first capacitor to a first terminal of the second capacitor. [C21] The electrically coupling means a second switch configured to electrically couple the first terminal of the second capacitor to the second terminal of the first capacitor; 20. The integrator circuit of claim 19, further comprising: [C22] The integrator circuit of C21, further comprising a third switch, wherein the third switch is configured to electrically couple a second terminal of the second capacitor to a power rail of the integrator circuit, and wherein the third switch receives the same clock signal as the second switch. [C23] 2. The integrator circuit of claim 1, further comprising a third switch, wherein the third switch is configured to electrically couple a second terminal of the second capacitor to a reference voltage of the integrator circuit, and wherein the third switch receives the same clock signal as the second switch. [C24] 10. The integrator circuit of claim 9, further comprising a third switch, wherein the third switch is configured to electrically couple a second terminal of the first capacitor to an inverting input of the operational amplifier, and wherein the third switch receives the same clock signal as the second switch. [C25] The integrator circuit of C19, wherein the capacitance of the second capacitor is less than the capacitance of the first capacitor. [C26] a bandgap reference generator configured to generate a bandgap voltage; an analog-to-digital converter (ADC) coupled to receive the bandgap voltage from the bandgap reference generator, wherein the ADC includes an integrator circuit having a first capacitor, a second capacitor, and a second switch configured to electrically couple the first terminal of the second capacitor to the second terminal of the first capacitor, the second capacitor coupled in parallel with the first capacitor such that the first terminal of the first capacitor is configured to be electrically coupled to the first terminal of the second capacitor by a first switch; System on a Chip (SOC). [C27] The SOC of C26, wherein the ADC comprises a sigma-delta modulator.

Claims

1. 1. An integrator circuit comprising: an operational amplifier; a first capacitor (CS) coupled to the input of the operational amplifier; a second capacitor (CA); a first set (S1) of one or more switches configured to electrically couple a first terminal of the first capacitor to a first terminal of the second capacitor during a sampling phase of the integrator circuit; a second set (S2) of one or more switches configured to electrically couple the first terminal of the second capacitor to the second terminal of the first capacitor during an integration phase of the integrator circuit; the second capacitor (CA) is coupled in parallel to the first capacitor such that a first terminal of the first capacitor is configured to be electrically coupled to the first terminal of the second capacitor by a first set of one or more switches (S1) during a sampling phase of the integrator circuit; the second terminal of the first capacitor is electrically coupled to the second terminal of the second capacitor during the sampling phase, and the first terminal of the first capacitor is electrically coupled to the second terminal of the second capacitor during the integration phase; the sampling phase and the integration phase alternate; Integrator circuit.

2. 2. The integrator circuit of claim 1, wherein the capacitance of the second capacitor is less than the capacitance of the first capacitor.

3. 2. The integrator circuit of claim 1, further comprising: a first clock signal applied to the first set of one or more switches and a second clock signal applied to the second set of one or more switches, wherein the first clock signal and the second clock signal are non-overlapping.

4. 2. The integrator circuit of claim 1, wherein the sampling phase includes charging the first capacitor and the integration phase includes discharging the first capacitor.

5. 5. The integrator circuit of claim 4, wherein the sampling phase and the integration phase do not overlap.

6. 2. The integrator circuit of claim 1, wherein the first set of one or more switches is configured to electrically couple the first terminal of the second capacitor to a voltage input of the integrator circuit.

7. 2. The integrator circuit of claim 1, wherein the second set of one or more switches is configured to electrically couple the first terminal of the second capacitor to the input of the operational amplifier.

8. 10. The integrator circuit of claim 1, further comprising a third set of one or more switches configured to electrically couple a second terminal of the second capacitor to a power rail of the integrator circuit, and wherein the third set of one or more switches receives the same clock signal as the second set of one or more switches.

9. 10. The integrator circuit of claim 1, further comprising a third set of one or more switches, wherein the third set of one or more switches is configured to electrically couple a second terminal of the second capacitor to a reference voltage of the integrator circuit, and wherein the third set of one or more switches receives the same clock signal as the second set of one or more switches.

10. 2. The integrator circuit of claim 1, further comprising a third set of one or more switches, wherein the third set of one or more switches is configured to electrically couple a second terminal of the first capacitor to an inverting input of the operational amplifier, and wherein the third set of one or more switches receives the same clock signal as the second set of one or more switches.

11. 10. The integrator circuit of claim 1, wherein the integrator circuit is included in a sigma-delta modulator, the sigma-delta modulator comprising an analog-to-digital converter (ADC), and / or the sigma-delta modulator is configured to measure the output of a bandgap reference generator.

12. The integrator circuit of claim 1 , wherein the integrator circuit comprises a discrete-time switched-capacitor integrator.

13. 1. A method of operating an integrator circuit, said method comprising: electrically coupling a first terminal of a first capacitor to a first terminal of a second capacitor during a sampling phase of the integrator circuit; electrically coupling a second terminal of the first capacitor to the first terminal of the second capacitor during an integration phase of the integrator circuit; the second terminal of the first capacitor is electrically coupled to the second terminal of the second capacitor during the sampling phase, and the first terminal of the first capacitor is electrically coupled to the second terminal of the second capacitor during the integration phase; the sampling phase and the integration phase alternate; method.

14. a bandgap reference generator configured to generate a bandgap voltage; an analog-to-digital converter (ADC) coupled to receive the bandgap voltage from the bandgap reference generator, wherein the ADC comprises an integrator circuit according to any one of claims 1 to 12. System on a chip (SOC).

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