Buffer circuit and measurement device

Abstract

This buffer circuit comprises a first transistor that has a power source terminal to which a first voltage is applied, a control terminal which is connected to an output terminal of an operation amplifier, and an output terminal which is connected to a second input terminal of the operation amplifier. The buffer circuit comprises: a second transistor that has a power source terminal to which a second voltage is applied, a control terminal which is connected to the output terminal of the operation amplifier, and an output terminal which is connected to the second input terminal of the operation amplifier; and a control transistor that has a first connection terminal which is connected to the control terminal of the second transistor, a detection terminal which is connected to the second input terminal of the operation amplifier, and a second connection terminal which is connected to the output terminal of the operation amplifier. The second input terminal of the operation amplifier is connected to the output terminal of the buffer circuit, and when an output voltage of the buffer circuit is in the range from the first voltage to the second voltage on the basis of the potential difference between the operation amplifier and the output terminal of the buffer circuit, the control transistor switches a state between the control terminal of the second transistor and the output terminal of the operation amplifier to a conducting state.

Description

Buffer circuit and measuring device

[0001] The present invention relates to a buffer circuit that causes an operational amplifier to operate in negative feedback mode, and to a measuring device.

[0002] JP1992-118672U discloses a measuring device equipped with a constant current supply circuit for supplying a constant current to a connected device under test via a pair of current terminals.

[0003] In the constant current supply circuit, an input signal is supplied from the reference voltage generation circuit to a first input terminal of the comparison and amplification means, and the output terminal of the comparison and amplification means is connected to a control terminal of a semiconductor element. The semiconductor element functions as a buffer circuit and supplies a load current, which is an amplified output of an operational amplifier constituting the comparison and amplification means, to the device under test.

[0004] The above-mentioned buffer circuit is configured to vary the voltage applied to the device under test according to the output of the operational amplifier, with the power supply voltage applied to the power supply terminal of the semiconductor element as the upper limit. In situations where a higher voltage needs to be applied to the device under test, the power supply voltage must be increased beyond the required value.

[0005] In such a situation, for example, if an AC voltage is applied to the device under test from a buffer circuit, as the voltage applied to the device under test approaches zero, the difference between the applied voltage and the power supply voltage increases, resulting in a problem of increased power loss in the buffer circuit.

[0006] The present invention has been made in view of these problems, and has as its object to suppress power loss occurring in a buffer circuit.

[0007] In one embodiment of the present invention, a buffer circuit that operates an operational amplifier with a first input terminal receiving an input signal in a negative feedback manner includes a first transistor having a power supply terminal to which a first voltage is applied, a control terminal directly or indirectly connected to the output terminal of the operational amplifier, and an output terminal connected to the second input terminal of the operational amplifier. The buffer circuit includes a second transistor having a power supply terminal to which a second voltage is applied, a control terminal indirectly connected to the output terminal of the operational amplifier, and an output terminal connected to the second input terminal of the operational amplifier. A control transistor has a first connection terminal connected to the control terminal of the second transistor, a detection terminal connected to the second input terminal of the operational amplifier, and a second connection terminal directly or indirectly connected to the output terminal of the operational amplifier. The second input terminal of the operational amplifier is connected to the output terminal of the buffer circuit. The control transistor switches the state between the control terminal of the second transistor and the output terminal of the operational amplifier from a non-conductive state to a conductive state based on a potential difference between the output terminal of the operational amplifier and the output terminal of the buffer circuit when the output voltage of the buffer circuit is within the range from the first voltage to the second voltage.

[0008] According to the above aspect, when the output voltage of the buffer circuit is within a first range from the first voltage to the second voltage, the control transistor establishes a conductive state between the output terminal of the operational amplifier and the control terminal of the second transistor, whereby a voltage within the first range corresponding to the output level of the operational amplifier is applied from the output terminal of the second transistor to the output terminal of the buffer circuit.

[0009] On the other hand, when the output voltage of the buffer circuit falls within a second range, for example, from the reference potential to the first voltage, the control transistor causes a non-conductive state between the output terminal of the operational amplifier and the second transistor, so that a voltage within the second range corresponding to the output level of the operational amplifier is applied to the output terminal of the buffer circuit from the output terminal of the first transistor, whose control terminal is connected to the output terminal of the operational amplifier.

[0010] In this way, the output voltage range of the buffer circuit is divided into a first range covered by the operation of the second transistor powered by the second voltage, and a second range covered by the operation of the first transistor powered by the first voltage. Then, based on the output voltage of the buffer circuit, the first or second transistor operates using a power supply voltage assigned to the range of the first or second range that corresponds to the voltage value of the output voltage of the buffer circuit.

[0011] Therefore, compared to a circuit configuration in which one transistor covers the entire range of the output voltage of the buffer circuit, the difference between the power supply voltage and the output voltage is smaller, making it possible to suppress power loss occurring in the transistor during operation.

[0012] FIG. 1 is a circuit diagram showing the configuration of a buffer circuit according to a first embodiment of the present invention. FIG. 2 is an explanatory diagram illustrating operation of the buffer circuit within a low voltage range. FIG. 3 is an explanatory diagram illustrating operation of the buffer circuit within a high voltage range. FIG. 4 is a diagram illustrating an input voltage waveform in a simulation of the buffer circuit. FIG. 5 is a diagram illustrating output results of the buffer circuit. FIG. 6 is a circuit diagram showing the configuration of a buffer circuit according to a second embodiment. FIG. 7 is an explanatory diagram illustrating operation of the buffer circuit within a low voltage range. FIG. 8 is an explanatory diagram illustrating operation of the buffer circuit within a high voltage range. FIG. 9 is a circuit diagram showing the configuration of a buffer circuit according to a third embodiment. FIG. 10 is a circuit diagram showing the configuration of a buffer circuit according to a fourth embodiment. FIG. 11 is a circuit diagram showing a first modified example of a buffer circuit according to each embodiment. FIG. 12 is a circuit diagram showing a second modified example of a buffer circuit according to each embodiment. FIG. 13 is a circuit diagram showing a third modified example of a buffer circuit according to each embodiment. FIG. 14 is a circuit diagram showing a modified example of a buffer circuit according to a fifth embodiment. FIG. 15 is a circuit diagram showing a modified example of the buffer circuit shown in FIG. 14. FIG. 16 is a block diagram showing the configuration of a measurement device including a buffer circuit.

[0013] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, various embodiments of the present invention will be described with reference to the accompanying drawings. In this specification, the same or equivalent elements are designated by the same reference numerals throughout.

[0014] First Embodiment FIG. 1 is a circuit diagram showing the circuit configuration of a buffer circuit 100 according to a first embodiment.

[0015] The buffer circuit 100 includes an output circuit 20 that performs negative feedback operation on an operational amplifier 10 having a first input terminal to which an input signal is supplied, and supplies power to a load connected to an output terminal T2 of the buffer circuit 100 in accordance with the input level of the operational amplifier 10. In the buffer circuit 100, the operational amplifier 10 can suppress the amount of its own output current relative to the load current that is the current to be supplied to the load.

[0016] The buffer circuit 100 is employed, for example, as a component of a power supply device or a measuring device that supplies current to an object to be measured.

[0017] For example, a signal oscillator is connected to the input terminal T1 of the buffer circuit 100, and a resistor, an LED, or the like is connected as a load to the output terminal T2 of the buffer circuit 100. Furthermore, when the output signal of the buffer circuit 100 is used as a source signal output from a measuring device, the output terminal T2 of the buffer circuit 100 is connected to a measurement target.

[0018] The buffer circuit 100 of the first embodiment includes an operational amplifier 10 and an output circuit 20 .

[0019] The operational amplifier 10 is an error amplifier that amplifies the voltage between input signals input to a pair of input terminals. The operational amplifier 10 has an inverting input terminal (-) as a first input terminal and a non-inverting input terminal (+) as a second input terminal.

[0020] The inverting input terminal (-) of the operational amplifier 10 is connected to the input terminal T1 of the buffer circuit 100 to which the input voltage Vin is supplied, and the non-inverting input terminal (+) of the operational amplifier 10 is connected to the output terminal T2 of the buffer circuit 100. The output terminal of the operational amplifier 10 is connected to the input part of the output circuit 20, and the output part of the output circuit 20 is connected to the output terminal T2 of the buffer circuit 100.

[0021] In this way, the buffer circuit 100 constitutes a voltage follower type buffer circuit, and therefore the input voltage Vin and the output voltage Vout of the buffer circuit 100 are equal to each other.

[0022] The output circuit 20 is a buffer for the operational amplifier 10 and supplies a load current instead of the operational amplifier 10 .

[0023] The output circuit 20 has a PNP transistor 21 as a first transistor, a PNP transistor 22 as a second transistor, a control transistor 23 as a first control transistor, a resistor element 31, and a rectifier element 32. The output circuit 20 is a common-emitter circuit, and is a source output circuit that flows a current from the output terminal T2 of the buffer circuit 100 to a load.

[0024] The output circuit 20 is connected to first and second power supplies 11 and 12 for supplying power to a load connected to an output terminal T2 of the buffer circuit 100. The first power supply 11 applies a power supply voltage Vs1 as a first voltage to a PNP transistor 21, and the second power supply 12 applies a power supply voltage Vs2 as a second voltage to a PNP transistor 22.

[0025] Both the power supply voltage Vs1 and the power supply voltage Vs2 have positive voltage values ​​higher than the reference potential, which is the potential used as a reference for the buffer circuit 100, and the voltage value of the power supply voltage Vs1 is lower than the voltage value of the power supply voltage Vs2. For example, the reference potential is set to 0 [V], the power supply voltage Vs1 is set to +5 [V], and the power supply voltage Vs2 is set to +10 [V].

[0026] In the first embodiment, the first power supply 11 is referred to as a low power supply 11 , and the second power supply 12 is referred to as a high power supply 12 .

[0027] The PNP transistor 21 is a PNP type transistor. The PNP transistor 21 has an emitter terminal used as a power supply terminal, a base terminal used as a control terminal, and a collector terminal used as an output terminal. The PNP transistor 21 adjusts the current flowing between the emitter terminal and the collector terminal in accordance with the current flowing between the emitter terminal and the base terminal.

[0028] The emitter terminal of the PNP transistor 21 is connected to the low power supply 11. Therefore, the emitter terminal of the PNP transistor 21 is applied with a power supply voltage Vs1, which is lower than the power supply voltage Vs2, from the low power supply 11 as a first voltage.

[0029] The base terminal of the PNP transistor 21 is connected to the output terminal of the operational amplifier 10 via a resistive element 31. Specifically, one end of the resistive element 31 is connected to the output terminal of the operational amplifier 10, and the other end of the resistive element 31 is connected to the base terminal of the PNP transistor 21. The resistive element 31 appropriately limits the amount of base current flowing through the base terminal of the PNP transistor 21.

[0030] The collector terminal of the PNP transistor 21 is connected to the non-inverting input terminal (+) of the operational amplifier 10 via the rectifying element 32 and is also connected to the output terminal T 2 of the buffer circuit 100 .

[0031] Specifically, the anode of the rectifying element 32 is connected to the collector terminal of the PNP transistor 21 , and the cathode of the rectifying element 32 is connected to the non-inverting input terminal (+) of the operational amplifier 10 and the output terminal T 2 of the buffer circuit 100 .

[0032] That is, the rectifying element 32 is connected between the collector terminal of the PNP transistor 21 and the output terminal T2 of the buffer circuit 100 so that the forward direction of the rectifying element 32 is the same as the forward direction of the PNP transistor 21. The forward direction of the rectifying element 32 and the PNP transistor 21 refers to the direction in which current flows.

[0033] The rectifying element 32 prevents current from flowing backward to the collector terminal of the PNP transistor 21. As the rectifying element 32, for example, a Schottky barrier diode and a switching diode are used.

[0034] With this connection configuration, the PNP transistor 21 adjusts the amount of current supplied from the low power supply 11 to the output terminal T2 of the buffer circuit 100 through itself in accordance with the voltage level of the input voltage Vin to the operational amplifier 10.

[0035] That is, the PNP transistor 21 performs an ON operation to supply current to the output terminal T2 of the buffer circuit 100 within a low voltage range from a reference potential (e.g., 0 V) ​​to the power supply voltage Vs1 of the low power supply 11, within the voltage range in which the output voltage Vout of the buffer circuit 100 can change.

[0036] Next, a description will be given of the PNP transistor 22. The PNP transistor 22 of the first embodiment has the same configuration as the PNP transistor 21.

[0037] The PNP transistor 22 is a PNP transistor connected via the control transistor 23. The PNP transistor 22 has an emitter terminal used as a power supply terminal, a base terminal used as a control terminal, and a collector terminal used as an output terminal. The PNP transistor 22 adjusts the current flowing between the emitter terminal and the collector terminal in accordance with the current flowing between the emitter terminal and the base terminal.

[0038] The emitter terminal of the PNP transistor 22 is connected to the high power supply 12. Therefore, the power supply voltage Vs2 is applied to the emitter terminal of the PNP transistor 22 from the high power supply 12 as the second voltage.

[0039] The base terminal of the PNP transistor 22 is connected to the output terminal of the operational amplifier 10 via the control transistor 23. The connection configuration with the control transistor 23 will be described later.

[0040] The collector terminal of the PNP transistor 22 is connected to the non-inverting input terminal (+) of the operational amplifier 10 and also to the output terminal T 2 of the buffer circuit 100 .

[0041] With this connection configuration, the PNP transistor 22 adjusts the amount of current supplied from the high power supply 12 to the output terminal T2 of the buffer circuit 100 through itself, depending on the voltage level of the input voltage Vin to the operational amplifier 10 connected via the control transistor 23.

[0042] That is, the PNP transistor 22 performs an ON operation to supply current to the output terminal T2 of the buffer circuit 100 within the high voltage range of the output voltage Vout of the buffer circuit 100, from the power supply voltage Vs1 of the low power supply 11 to the power supply voltage Vs2 of the high power supply 12.

[0043] Next, the control transistor 23 will be described.

[0044] The control transistor 23 detects the output voltage Vout of the buffer circuit 100, and when the detected output voltage Vout exceeds the power supply voltage Vs1, adjusts the amount of current in a conductive state in which current flows between the output terminal of the operational amplifier 10 and the base terminal of the PNP transistor 22. The conductive state here also includes a state in which a small amount of current can flow between the output terminal of the operational amplifier 10 and the base terminal of the PNP transistor 22.

[0045] In the first embodiment, the control transistor 23 is an NPN transistor, and has a collector terminal used as a first connecting terminal, a base terminal used as a detection terminal, and an emitter terminal used as a second connecting terminal.

[0046] The collector terminal of the control transistor 23 is connected to the base terminal of the PNP transistor 22, and the base terminal of the control transistor 23 is connected to the output terminal T2 of the buffer circuit 100. The emitter terminal of the control transistor 23 is connected to the output terminal of the operational amplifier 10.

[0047] With this connection configuration, the control transistor 23 switches the state between the base terminal of the PNP transistor 22 and the output terminal of the operational amplifier 10 from a non-conductive state to a conductive state in which current flows, based on the potential difference between the output terminal of the operational amplifier 10 and the output terminal T2 of the buffer circuit 100.

[0048] Specifically, the control transistor 23 controls the connection between the base terminal of the PNP transistor 21 and the output terminal of the operational amplifier 10 to be conductive when the output voltage Vout of the buffer circuit 100 is at least within the high voltage range from the power supply voltage Vs1 to the power supply voltage Vs2.

[0049] The control transistor 23 of the first embodiment adjusts the current flowing between the base terminal of the PNP transistor 21 and the output terminal of the operational amplifier 10 when the voltage is within a high voltage range from a predetermined voltage value slightly lower than the power supply voltage Vs1 to the power supply voltage Vs2. The predetermined voltage value here is determined so as to enable continuous switching between the PNP transistors 21 and 22, and is set to a voltage value that is, for example, about 0.5 V lower than the power supply voltage Vs1.

[0050] On the other hand, when the output voltage Vout of the buffer circuit 100 is within a low voltage range from the reference potential to the power supply voltage Vs1, the control transistor 23 controls the state between the base terminal of the PNP transistor 22 and the output terminal of the operational amplifier 10 to be non-conductive. In this non-conductive state, the control transistor 23 is turned off.

[0051] Next, the operation of the buffer circuit 100 will be described with reference to FIGS.

[0052] Here, an example will be described in which an AC input voltage Vin is input from the input terminal T1 of the buffer circuit 100 to the inverting input terminal (-) of the operational amplifier 10, and the voltage level of the output voltage Vout of the buffer circuit 100 changes depending on the amplitude of the input voltage Vin.

[0053] First, the operation of the buffer circuit 100 when the output voltage Vout of the buffer circuit 100 indicates a voltage value within a low voltage range from the reference potential to the power supply voltage Vs1 will be described.

[0054] 2 is a diagram for explaining the operation of the buffer circuit 100 when the output voltage Vout of the buffer circuit 100 indicates a voltage value within a low voltage range. In FIG. 2 and FIG. 3, the direction of current flowing from the base terminal to the emitter terminal of a transistor is defined as positive, and the direction of current flowing from the emitter terminal to the collector terminal is defined as positive.

[0055] When the output voltage Vout of the buffer circuit 100 is within the low voltage range, a base current (-Ib1) flows from the low power supply 11 to the output terminal of the operational amplifier 10 via the base terminal of the PNP transistor 21, turning on the PNP transistor 21. Note that the base current (-Ib1) actually flows even in the high voltage range.

[0056] In this case, the relationship between the voltage drop Veb1 between the emitter terminal and base terminal of the PNP transistor 21 and the resistance value R1 of the resistive element 31 can be expressed by the following equation (1): Vop=Vs1-Veb1-(-Ib1×R1) (1) The voltage drop Veb1 is generally about 0.5 V to 0.8 V.

[0057] When the PNP transistor 21 is turned on, a collector current (-Ic1) is output as a load current from the low power supply 11 through the collector terminal of the PNP transistor 21 to the output terminal T2 of the buffer circuit 100. This increases the output voltage Vout generated at the output terminal T2 of the buffer circuit 100. The collector current (-Ic1) is generally 100 times or more larger than the base current (-Ib1).

[0058] Furthermore, the operational amplifier 10 performs a negative feedback operation until the output voltage Vout generated at the output terminal T2 connected to its non-inverting input terminal (+) converges to the voltage level of the input voltage Vin to the operational amplifier 10. This negative feedback operation maintains the output voltage Vout of the buffer circuit 100 at the voltage level of the input voltage Vin to the operational amplifier 10.

[0059] At this time, the control transistor 23 is in the OFF state because the output voltage Vout generated at the output terminal T2 connected to its base terminal is lower than the power supply voltage Vs1. As a result, the output terminal of the operational amplifier 10 and the base terminal of the PNP transistor 22 are not conductive, no base current flows through the base terminal of the PNP transistor 22, and the PNP transistor 22 is also in the OFF state. Therefore, no current is output from the high voltage power supply 12 to the output terminal T2 of the buffer circuit 100 through the PNP transistor 22.

[0060] In this way, when the output voltage Vout of the buffer circuit 100 falls within a voltage value within the low voltage range, a load current is supplied from the low power supply 11 to the output terminal T2 of the buffer circuit 100 through the PNP transistor 21 of the low power supply 11 and the high power supply 12.

[0061] At this time, the voltage Vec between the emitter terminal and the collector terminal of the PNP transistor 21 corresponds to the voltage (Vs1-Vout) between the power supply voltage Vs1 of the low power supply 11 and the output voltage Vout within the low voltage range.

[0062] In the PNP transistor 21, power (P) is consumed as heat, as shown in the following equation (2). The power consumed by this heat generation is the power loss P of the PNP transistor 21. P=-Ic1×Vec=-Ic1×(Vs1-Vout) (2)

[0063] If the power loss P becomes too large, the PNP transistor 21 may generate heat, causing malfunctions or degrading the performance of surrounding circuits. Furthermore, adopting a circuit configuration that takes heat dissipation or cooling into consideration as a countermeasure against heat generation may result in increased manufacturing costs or size. Furthermore, in devices that use batteries to supply power to components, the usable time may be shortened.

[0064] As a countermeasure to this, it is desirable to reduce the potential difference between the power supply voltage Vs1 and the output voltage Vout in order to reduce the power loss P of the PNP transistor 21. Therefore, in the first embodiment, when the output voltage Vout falls within a voltage value within a low voltage range (e.g., 0 V to +5 V) from the reference potential to the power supply voltage Vs1, the low power supply 11, which has a lower voltage value than the high power supply 12, is selected.

[0065] Therefore, the power loss P {=-Ic1×(Vs1-Vout)} of the PNP transistor 21 is reduced compared to the power loss {=-Ic1×(Vs2-Vout)} when the high power supply 12 is connected to the PNP transistor 21 and a load current is output from the high power supply 12 through the PNP transistor 21. This makes it possible to reduce the power loss of the entire buffer circuit 100 including the PNP transistor 21.

[0066] Next, the operation of the buffer circuit 100 when the output voltage Vout of the buffer circuit 100 indicates a voltage value within the high voltage range from the power supply voltage Vs1 to the power supply voltage Vs2 will be described with reference to FIG.

[0067] FIG. 3 is a diagram for explaining the operation of the buffer circuit 100 when the output voltage Vout of the buffer circuit 100 indicates a voltage value within the high voltage range.

[0068] When the output voltage Vout of the buffer circuit 100 is within the high voltage range, the output voltage Vout of the buffer circuit 100 is higher than the power supply voltage Vs1 of the low power supply 11, and therefore the PNP transistor 21 is turned off. Therefore, no current is output from the low power supply 11 to the output terminal T2 of the buffer circuit 100 through the PNP transistor 21.

[0069] On the other hand, the output voltage Vout generated at the output terminal T2 connected to the base terminal of the control transistor 23 indicates a voltage value within the high voltage range, and therefore the base current Ib3 flows toward the output terminal of the operational amplifier 10, turning the control transistor 23 into an ON state, thereby bringing the output terminal of the operational amplifier 10 and the base terminal of the PNP transistor 22 into a conductive state.

[0070] Here, we will briefly explain the conditions under which the base current Ib3 flows. First, if the voltage between the base terminal and emitter terminal of the control transistor 23 when the base current Ib3 starts to flow is Vbe3, the base terminal of the control transistor 23 is connected to the output terminal T2 of the buffer circuit 100, and the emitter terminal is connected to the output terminal of the operational amplifier 10. Therefore, the base current Ib3 flows when the relationship in the following equation (3) is established: Vout - Vop > Vbe3 (3)

[0071] By using the above equation (1), equation (3) becomes the following equation (4): Vout>Vs1+(Vbe1-Vbe3)-(-Ib1×R1) (4)

[0072] From the viewpoint of the physical properties of transistors, Vbe1 and Vbe3 are generally approximately equal in value, so if we approximate the second term on the right-hand side as (Vbe1-Vbe3)=0, we obtain the following equation (5): Vout>Vs1-(-Ib1xR1) (5)

[0073] In this way, the base current Ib3 flows when the relationship of equation (5) is established. In the first embodiment, it is preferable to set the resistance value R1 of the resistor element 31 so that the second term on the right side of equation (5) (-Ib1 × R1) is a small value less than 1 V.

[0074] As a result of the base current Ib3 flowing, a base current (-Ib2) equal to the collector current Ic3 flows from the high power supply 12 to the output terminal of the operational amplifier 10 via the base terminal of the PNP transistor 22, turning the PNP transistor 22 on.

[0075] Accordingly, a collector current (-Ic2) is output as a load current from the high power supply 12 through the collector terminal of the PNP transistor 21 toward the output terminal T2 of the buffer circuit 100. As a result, the output voltage Vout generated at the output terminal T2 of the buffer circuit 100 rises to or above the power supply voltage Vs1.

[0076] The operational amplifier 10 performs negative feedback operation until the output voltage Vout generated at the output terminal T2 connected to its non-inverting input terminal (+) converges to the voltage level of the input voltage Vin to the operational amplifier 10. This negative feedback operation maintains the output voltage Vout of the buffer circuit 100 at the voltage level of the input voltage Vin to the operational amplifier 10.

[0077] At this time, a portion of the collector current (-Ic2) flowing from the high voltage power supply 12 through the PNP transistor 22 is blocked by the rectifier element 32 so as not to flow back to the collector terminal of the PNP transistor 21. In addition, the resistor element 31 suppresses the transient forward base current (-Ib1) that flows from the power supply voltage Vs1 to the output terminal of the operational amplifier 10 mainly when switching between the PNP transistors 21 and 22.

[0078] As described above, in the buffer circuit 100, a power supply that covers a voltage range that covers the current voltage value of the output voltage Vout is selected from the low power supply 11 and the high power supply 12, and a load current is output from the output terminal T2 through the PNP transistor to which that power supply is connected. This reduces the potential difference between the power supply voltage of the selected power supply and the output voltage Vout of the buffer circuit 100, thereby reducing power loss in the buffer circuit 100.

[0079] In the first embodiment, the resistive element 31 is provided to suppress the base current (-Ib2) flowing into the base terminal of the PNP transistor 21, but in a circuit configuration in which the influence of the base current (-Ib2) flowing into the PNP transistor 21 is small, the resistive element 31 may be eliminated.

[0080] In addition, in the first embodiment, a rectifying element 32 is provided to prevent the collector current (-Ic2) from flowing back to the collector terminal of the PNP transistor 21, but in a circuit configuration in which the impact of the backflow of the collector current (-Ic2) on the PNP transistor 21 is small, the rectifying element 32 may be eliminated.

[0081] Next, the results of a simulation of the operation of buffer circuit 100 when a waveform signal is input will be described with reference to FIGS.

[0082] In the simulation of the buffer circuit 100, the reference potential is set to 0 V, the power supply voltage Vs1 is set to +5 V, the power supply voltage Vs2 is set to +10 V, and the resistive element 31 is set to 1 kΩ. In addition, a resistive element is connected between the output terminal of the operational amplifier 10 and the emitter terminal of the control transistor 23, and a capacitive element is connected between the output terminal of the operational amplifier 10 and the collector terminal of the control transistor 23. These resistive element and capacitive element are phase compensation elements for increasing the stability of the negative feedback operation, and are set to 1 kΩ and 100 pF, respectively.

[0083] FIG. 4 is a diagram showing the waveform of the input voltage Vin supplied to the input terminal T1 in a simulation of the buffer circuit 100.

[0084] An AC input voltage Vin having a frequency f is supplied to the input terminal T1 of the buffer circuit 100 as shown in the following equation (6): Vin=4×sin(2πft)+4 (6)

[0085] As shown in FIG. 4, the input voltage Vin is an input signal in which a DC component of +4 V is superimposed on an AC component {4×sin(2πft)} having a frequency f of 1 kHz and an amplitude of 4 V.

[0086] Next, the simulation results for the period from time T10 to time T12 shown in FIG. 4 will be described with reference to FIG.

[0087] 5A and 5B are diagrams showing the output results of the buffer circuit 100 when the input voltage Vin shown in the above equation (6) is supplied to the input terminal T1. Fig. 5A shows the simulation results of the output voltage Vout of the buffer circuit 100, and Fig. 5B shows the simulation results of the output current of the buffer circuit 100.

[0088] First, the output of the buffer circuit 100 during the first rising period from time T10 to time T11 will be described.

[0089] In the low voltage range R1 where the output voltage Vout of the buffer circuit 100 ranges from 0 V to +5 V, which is the same as the power supply voltage Vs1 of the low power supply 11, the control transistor 23 is in the off state, and therefore the PNP transistor 22 is also in the off state.

[0090] On the other hand, the PNP transistor 21 is in an on state, and in this state, in order to increase the output voltage Vout of the buffer circuit 100, the operational amplifier 10 reduces its own output voltage Vop and increases the base current (-Ib1) flowing from the low power supply 11 to the output terminal of the operational amplifier 10 through the base terminal of the PNP transistor 21.

[0091] Accordingly, as shown by the dotted line in FIG. 5B, the collector current (-Ic1) output from the low power supply 11 through the collector terminal of the PNP transistor 21 increases.

[0092] In this way, the PNP transistor 21 increases the current (-Ic1) flowing between the emitter terminal and the collector terminal of the PNP transistor 21 as the output voltage Vout of the buffer circuit 100 approaches the power supply voltage Vs1 from 0 [V].

[0093] Therefore, in the low voltage range R1, as the output voltage Vout of the buffer circuit 100 approaches the power supply voltage Vs1 from the reference potential, the collector current (-Ic1) output from the buffer circuit 100 through the PNP transistor 21 increases.

[0094] At this time, as shown in FIG. 5A, the output voltage Vout of the buffer circuit 100 is controlled to be equal to the input voltage Vin to the operational amplifier 10 by the negative feedback operation of the operational amplifier 10.

[0095] Furthermore, when the output voltage Vout of the buffer circuit 100 is near +5 V, the control transistor 23 is turned on, and a base current (-Ib2) flows from the high power supply 12 through the control transistor 23 and the base terminal of the PNP transistor 22 to the output terminal of the operational amplifier 10.

[0096] 5B, the control transistor 23 gradually switches the transistor that turns on when the output voltage Vout of the buffer circuit 100 reaches a predetermined voltage value slightly lower than the power supply voltage Vs1, for example, 4.5 V, from the PNP transistor 21 to the PNP transistor 22. The predetermined voltage value can be expressed by the right-hand side of the above equation (5), {Vs1-(-Ib1×R1)}.

[0097] Specifically, in the vicinity of +5 [V], the negative feedback operation of the operational amplifier 10 causes a decrease in the output voltage Vop of the operational amplifier 10, and the accompanying increase in the output voltage Vout of the buffer circuit 100 causes the voltage between the emitter terminal and the collector terminal of the control transistor 23 to increase, and the amount of base current (-Ib2) flowing into the output terminal of the operational amplifier 10 increases sharply.

[0098] Therefore, as shown in FIG. 5B, the collector current (-Ic2) output from the high voltage power supply 12 to the output terminal T2 of the buffer circuit 100 through the collector terminal of the PNP transistor 22 also increases sharply.

[0099] Next, the output of the buffer circuit 100 during the second rising period from time T11 to time T12 will be described.

[0100] When the output voltage Vout of the buffer circuit 100 is in a high voltage range Rh of +5 V to +10 V, the PNP transistor 21 is turned off, and the collector current (−Ic1) of the PNP transistor 21 stops, as shown in FIG. 5(b).

[0101] On the other hand, the PNP transistor 22 is turned on, and the increase in the output voltage Vout of the buffer circuit 100 increases the voltage between the base terminal and the emitter terminal of the control transistor 23. This increases the base current Ib3 of the control transistor 23, and increases the collector current (-Ic2) output from the high-voltage power supply 12 to the output terminal T2 of the buffer circuit 100 through the collector terminal of the PNP transistor 22.

[0102] In this way, when the output voltage Vout of the buffer circuit 100 is within the range from the power supply voltage Vs1 to the power supply voltage Vs2, the control transistor 23 flows a base current (-Ib2) between the base terminal of the PNP transistor 22 and the output terminal of the operational amplifier 10 based on the potential difference between the output terminal of the operational amplifier 10 and the output terminal T2 of the buffer circuit 100.

[0103] The PNP transistor 22 increases the current (-Ic2) flowing between the emitter terminal and the collector terminal of the PNP transistor 22 as the output voltage Vout of the buffer circuit 100 approaches the power supply voltage Vs2 from the power supply voltage Vs1.

[0104] At this time, as shown in FIG. 5A, the output voltage Vout of the buffer circuit 100 is controlled to be equal to the input voltage Vin to the operational amplifier 10 by the negative feedback operation of the operational amplifier 10.

[0105] In this way, by employing the control transistor 23, it is possible to switch between the PNP transistor 21 and the PNP transistor 22 at optimal timing as a path for supplying a load current while outputting a predetermined output voltage Vout corresponding to the input voltage Vin to the operational amplifier 10 based on the negative feedback operation of the operational amplifier 10. That is, in order to minimize the power loss P in the buffer circuit 100, the PNP transistor 21 can be operated until the output voltage Vout approaches the power supply voltage Vs1 of the low power supply 11, and the PNP transistor 22 can be operated in a voltage range above that.

[0106] Next, the effects of the first embodiment will be described.

[0107] According to the first embodiment, the buffer circuit 100 performs negative feedback operation on an operational amplifier 10 having an inverting input terminal (−) to which an input voltage Vin is supplied as an input signal. The non-inverting input terminal (+) of the operational amplifier 10 is connected to an output terminal T2 of the buffer circuit 100. The inverting input terminal (−) and the non-inverting input terminal (+) of the operational amplifier 10 are used as a first input terminal and a second input terminal, respectively.

[0108] The buffer circuit 100 includes a PNP transistor 21 as a first transistor, a PNP transistor 22 as a second transistor, and a control transistor 23. Each of the PNP transistor 21, the PNP transistor 22, and the control transistor 23 has an emitter terminal, a base terminal, and a collector terminal.

[0109] In the PNP transistor 21, the emitter terminal is used as a power supply terminal to which a power supply voltage Vs1 is applied as a first voltage, and the base terminal is used as a control terminal that is directly or indirectly connected to the output terminal of the operational amplifier 10. Furthermore, the collector terminal is connected to the non-inverting input terminal (+) of the operational amplifier 10 and is used as an output terminal that is connected to the output terminal T2 of the buffer circuit 100.

[0110] In the PNP transistor 22, the emitter terminal is used as a power supply terminal to which a power supply voltage Vs2 as a second voltage is applied, and the base terminal is used as a control terminal indirectly connected to the output terminal of the operational amplifier 10. Furthermore, the collector terminal is used as an output terminal connected to the non-inverting input terminal (+) of the operational amplifier 10.

[0111] The control transistor 23 has a collector terminal used as a first connection terminal connected to the base terminal of the PNP transistor 22, a base terminal connected to the non-inverting input terminal (+) of the operational amplifier 10 and used as a detection terminal connected to the output terminal T2 of the buffer circuit 100, and an emitter terminal used as a second connection terminal connected directly or indirectly to the output terminal of the operational amplifier 10.

[0112] Then, based on the potential difference between the output terminal of the operational amplifier 10 and the output terminal T2 of the buffer circuit 100, the control transistor 23 switches the state between the base terminal of the PNP transistor 22 and the output terminal of the operational amplifier 10 from a non-conductive state to a conductive state when the output voltage Vout of the buffer circuit 100 falls within the high voltage range from the power supply voltage Vs1 to the power supply voltage Vs2.

[0113] With this configuration, when the output voltage Vout of the buffer circuit 100 is within the high-voltage range from the power supply voltage Vs1 to the power supply voltage Vs2, the control transistor 23 establishes a conductive state between the output terminal of the operational amplifier 10 and the base terminal of the PNP transistor 22. Accordingly, the PNP transistor 22 applies a voltage within the high-voltage range corresponding to the output level of the operational amplifier 10 to the output terminal T2 of the buffer circuit 100.

[0114] On the other hand, when the output voltage Vout of the buffer circuit 100 is within a low voltage range, for example, from the reference potential to the power supply voltage Vs1, the control transistor 23 causes a non-conductive state between the output terminal of the operational amplifier 10 and the PNP transistor 22. Accordingly, the PNP transistor 21, whose base terminal is connected to the output terminal of the operational amplifier 10, applies a voltage within the low voltage range corresponding to the output level of the operational amplifier to the output terminal T2 of the buffer circuit 100.

[0115] In this way, the entire range of the output voltage Vout of the buffer circuit 100 is divided into a high voltage range covered by the operation of the PNP transistor 22 powered by the power supply voltage Vs2, and a low voltage range covered by the operation of the PNP transistor 21 powered by the power supply voltage Vs1. The buffer circuit 100 is configured so that the transistor that uses the power supply voltage assigned to the voltage range that covers the output voltage Vout of the buffer circuit 100, out of the power supply voltage Vs1 and the power supply voltage Vs2, is turned on.

[0116] Therefore, the difference between the output voltage Vout and the power supply voltage (Vs1 or Vs2) applied to the transistor in an on-state is smaller than in a circuit configuration in which a single transistor covers the entire range of the output voltage Vout of the buffer circuit 100. This makes it possible to suppress power loss occurring in the transistor in an on-state, thereby reducing power loss in the entire buffer circuit 100.

[0117] In addition, by using the control transistor 23, it is possible to create an intermediate state for maintaining the continuity of the output voltage Vout when switching between the PNP transistor 21 and the PNP transistor 22. This makes the switching more continuous than when a discontinuous switching means is used, and allows the output voltage Vout of the buffer circuit 100 to change more smoothly. In other words, by using the control transistor, it is possible to suppress fluctuations in the output voltage Vout of the buffer circuit 100 that occur when switching from one of the PNP transistors 21 and 22 to the other.

[0118] Furthermore, when the output voltage Vout of the buffer circuit 100 falls within the high voltage range from the power supply voltage Vs1 to the power supply voltage Vs2, the control transistor 23 of the first embodiment causes a current to flow between the base terminal of the PNP transistor 22 and the output terminal of the operational amplifier 10 based on the potential difference between the output terminal of the operational amplifier 10 and the output terminal T2 of the buffer circuit 100.

[0119] This configuration allows a load current to be supplied through the PNP transistor 22 in accordance with changes in the input voltage Vin to the operational amplifier 10 in the high voltage range.

[0120] In the first embodiment, the PNP transistor 21 supplies a current (-Ic1) from the low power supply 11 to a load connected to the output terminal T2 of the buffer circuit 100 in a low voltage range where the output voltage Vout of the buffer circuit 100 ranges from the reference potential to the power supply voltage Vs1. The PNP transistor 22 supplies a current (-Ic2) from the high power supply 12 to a load connected to the output terminal T2 of the buffer circuit 100 in a high voltage range where the output voltage Vout of the buffer circuit 100 ranges from the power supply voltage Vs1 to the power supply voltage Vs2.

[0121] According to this configuration, the PNP transistors 21 and 22 to which different power supply voltages Vs1 and Vs2 are applied in the buffer circuit 100 can share the entire range of the output voltage Vout of the buffer circuit 100 and supply current to the load.

[0122] In the first embodiment, the power supply voltages Vs1 and Vs2 are higher than the reference potential that the buffer circuit 100 uses as a reference, and the power supply voltage Vs2 is higher than the power supply voltage Vs1.

[0123] According to this configuration, by alternately switching between the two positive power supply voltages Vs1 and Vs2, it is possible to reproduce the positive output voltage Vout of the buffer circuit 100 in accordance with changes in the input voltage Vin to the operational amplifier 10, while reducing power loss.

[0124] The buffer circuit 100 of the first embodiment further includes a resistor element 31 having one end connected to the output terminal of the operational amplifier 10 and the other end connected to the base terminal of the PNP transistor 21 .

[0125] With this configuration, when the output voltage Vout of the buffer circuit 100 indicates a voltage value within the high voltage range, it is possible to suppress the amount of current that flows from the low power supply 11 to the output terminal of the operational amplifier 10 via the base terminal of the PNP transistor 21. As a result, it is possible to suppress malfunctions of the operational amplifier 10 and the PNP transistor 21.

[0126] The buffer circuit 100 of the first embodiment further includes a rectifying element 32. The rectifying element 32 is connected between the collector terminal of the PNP transistor 21 and the output terminal T2 of the buffer circuit 100 so that the forward direction of the rectifying element 32 is the same as the forward direction of the PNP transistor 21. The forward direction of the rectifying element 32 and the PNP transistor 21 refers to the direction in which current flows. Specifically, the anode of the rectifying element 32 is connected to the collector terminal of the PNP transistor 21, and the cathode of the rectifying element 32 is connected to the output terminal T2 of the buffer circuit 100.

[0127] With this configuration, when the output voltage Vout of the buffer circuit 100 indicates a voltage value within the high voltage range, it is possible to prevent the current output to the output terminal T2 of the buffer circuit 100 through the collector terminal of the PNP transistor 22 from flowing back to the collector terminal of the PNP transistor 21. This makes it possible to suppress malfunctions of the PNP transistor 21.

[0128] Second Embodiment FIG. 6 is a circuit diagram showing the configuration of a buffer circuit 101 according to a second embodiment.

[0129] The buffer circuit 101 corresponds to the buffer circuit 100 of the first embodiment, and includes an output circuit 20A instead of the output circuit 20 of the first embodiment. Since other configurations of the buffer circuit 101 are the same as or equivalent to those of the first embodiment, the same reference numerals as those of the first embodiment are used and the description thereof will be omitted here.

[0130] The output circuit 20A is a grounded emitter circuit, similar to the output circuit 20. However, unlike the output circuit 20, the output circuit 20A is a sink output circuit that draws current from the connected load in a direction toward the output terminal T2 of the buffer circuit 101.

[0131] The output circuit 20A is a buffer for the operational amplifier 10 and absorbs the load current instead of the operational amplifier 10.

[0132] The output circuit 20A includes an NPN transistor 21A as a first transistor, an NPN transistor 22A as a second transistor, a control transistor 23A, a resistive element 31, and a rectifying element 32.

[0133] The output circuit 20A is connected to two power supplies, a low power supply 11A and a high power supply 12A, for supplying power to a load connected to the output terminal T2 of the buffer circuit 101. For convenience, the power supply with a small absolute voltage value will be referred to as the low power supply, and the power supply with a large absolute voltage value will be referred to as the high power supply.

[0134] The low power supply 11A applies a power supply voltage Vs1A as a first voltage to the NPN transistor 21A, and the high power supply 12A applies a power supply voltage Vs2A as a second voltage to the NPN transistor 22A.

[0135] Both power supply voltage Vs1A and power supply voltage Vs2A have negative voltage values ​​lower than the reference potential of the buffer circuit 101, and the voltage value of power supply voltage Vs1A is higher than the voltage value of power supply voltage Vs2A. In other words, the absolute value of the voltage value of power supply voltage Vs1A is lower than the absolute value of the voltage value of power supply voltage Vs2A. For example, the reference potential is set to 0 [V], the power supply voltage Vs1A is set to -5 [V], and the power supply voltage Vs2A is set to -10 [V].

[0136] The NPN transistor 21A is an NPN transistor. The NPN transistor 21A has an emitter terminal used as a power supply terminal, a base terminal used as a control terminal, and a collector terminal used as an output terminal. The NPN transistor 21A adjusts the current flowing between the emitter terminal and the collector terminal in accordance with the current flowing between the emitter terminal and the base terminal.

[0137] The emitter terminal of the NPN transistor 21A is connected to the low power supply 11A, so that the power supply voltage Vs1A higher than the power supply voltage Vs2A is applied as a first voltage to the emitter terminal of the NPN transistor 21A from the low power supply 11A.

[0138] The base terminal of the NPN transistor 21A is connected to the output terminal of the operational amplifier 10 via a resistive element 31. Specifically, one end of the resistive element 31 is connected to the output terminal of the operational amplifier 10, and the other end of the resistive element 31 is connected to the base terminal of the NPN transistor 21A. The resistive element 31 appropriately limits the amount of base current flowing through the base terminal of the NPN transistor 21A.

[0139] The collector terminal of the NPN transistor 21A is connected to the non-inverting input terminal (+) of the operational amplifier 10 via the rectifying element 32 and is also connected to the output terminal T2 of the buffer circuit 101.

[0140] The rectifying element 32 is connected between the collector terminal of the NPN transistor 21A and the output terminal T2 of the buffer circuit 101 so that the forward direction of the rectifying element 32 is the same as the forward direction of the NPN transistor 21A. Specifically, the cathode of the rectifying element 32 is connected to the collector terminal of the NPN transistor 21A, and the anode of the rectifying element 32 is connected to the non-inverting input terminal (+) of the operational amplifier 10 and the output terminal T2 of the buffer circuit 101. The rectifying element 32 prevents current from flowing back to the collector terminal of the NPN transistor 21A.

[0141] With this connection configuration, the NPN transistor 21A adjusts the amount of current supplied from the output terminal T2 of the buffer circuit 101 to the low power supply 11A through itself based on the negative feedback operation of the operational amplifier 10.

[0142] That is, the NPN transistor 21A performs an ON operation to supply current from the output terminal T2 of the buffer circuit 101 to the low power supply 11A within a low voltage range on the negative side of the voltage range of the output voltage Vout of the buffer circuit 101, from the power supply voltage Vs1A of the low power supply 11A to, for example, zero.

[0143] Next, the NPN transistor 22A will be described. The NPN transistor 22A of the second embodiment has the same configuration as the NPN transistor 21A.

[0144] The NPN transistor 22A is an NPN transistor. The NPN transistor 22A has an emitter terminal used as a power supply terminal, a base terminal used as a control terminal, and a collector terminal used as an output terminal. The NPN transistor 22A adjusts the current flowing between the emitter terminal and the collector terminal in accordance with the current flowing between the emitter terminal and the base terminal.

[0145] The emitter terminal of the NPN transistor 22A is connected to the high power supply 12A, so that the power supply voltage Vs2A is applied as the second voltage from the high power supply 12A to the emitter terminal of the NPN transistor 22A.

[0146] The base terminal of the NPN transistor 22A is connected to the output terminal of the operational amplifier 10 via a control transistor 23A. The connection configuration with the control transistor 23A will be described later.

[0147] The collector terminal of the NPN transistor 22A is connected to the non-inverting input terminal (+) of the operational amplifier 10 and also to the output terminal T2 of the buffer circuit 101.

[0148] With this connection configuration, the NPN transistor 22A adjusts the amount of current supplied from the output terminal T2 of the buffer circuit 101 to the high-voltage power supply 12A through itself based on the negative feedback operation of the operational amplifier 10 connected via the control transistor 23A.

[0149] That is, the NPN transistor 22A performs an ON operation to supply current to the output terminal T2 of the buffer circuit 101 within the negative high voltage range of the voltage range of the output voltage Vout of the buffer circuit 101, from the power supply voltage Vs1A of the low power supply 11A to the power supply voltage Vs2A of the high power supply 12A.

[0150] Next, the control transistor 23A will be described.

[0151] The control transistor 23A detects the output voltage Vout of the buffer circuit 101, and when the detected output voltage Vout falls below the power supply voltage Vs1A, controls the control transistor 23A to a conductive state that allows current to flow between the output terminal of the operational amplifier 10 and the base terminal of the NPN transistor 22A.

[0152] In the second embodiment, the control transistor 23A is a PNP transistor and has a collector terminal used as a first connecting terminal, a base terminal used as a detection terminal, and an emitter terminal used as a second connecting terminal.

[0153] The collector terminal of the control transistor 23A is connected to the base terminal of the NPN transistor 22A, and the base terminal of the control transistor 23A is connected to the output terminal T2 of the buffer circuit 101. The emitter terminal of the control transistor 23A is connected to the output terminal of the operational amplifier 10.

[0154] With this connection configuration, the control transistor 23A switches the state between the base terminal of the NPN transistor 22A and the output terminal of the operational amplifier 10 from a non-conductive state to a conductive state based on the potential difference between the output terminal of the operational amplifier 10 and the output terminal T2 of the buffer circuit 101.

[0155] Specifically, when the output voltage Vout of the buffer circuit 101 is at least within the high voltage range from the power supply voltage Vs1A to the power supply voltage Vs2A, the control transistor 23A controls the connection between the base terminal of the NPN transistor 21A and the output terminal of the operational amplifier 10 to be conductive.

[0156] At this time, when the output voltage Vout of the buffer circuit 101 is within the high voltage range, the control transistor 23A passes a current between the base terminal of the PNP transistor 22 and the output terminal of the operational amplifier 10 based on the potential difference between the output terminal of the operational amplifier 10 and the output terminal T2 of the buffer circuit 101.

[0157] The NPN transistor 22A supplies a current (Ic2) from the high power supply 12A to the load connected to the output terminal T2 when the output voltage Vout of the buffer circuit 101 is in the range from the power supply voltage Vs1A to the power supply voltage Vs2A.

[0158] On the other hand, when the output voltage Vout of the buffer circuit 101 is within a low voltage range from the reference potential to the power supply voltage Vs1A, the control transistor 23A controls the connection between the base terminal of the NPN transistor 22A and the output terminal of the operational amplifier 10 to be non-conductive.

[0159] The NPN transistor 21A supplies a current (Ic1) from the low power supply 11A to the load connected to the output terminal T2 when the output voltage Vout of the buffer circuit 101 is in the range from the reference potential to the power supply voltage Vs1A.

[0160] Next, the operation of the buffer circuit 101 will be described.

[0161] Here, as in the first embodiment, an example will be described in which an AC input voltage Vin is input from the input terminal T1 of the buffer circuit 101 to the inverting input terminal (-) of the operational amplifier 10, and the voltage level of the output voltage Vout of the buffer circuit 101 changes depending on the amplitude of the input voltage Vin.

[0162] First, the operation of the buffer circuit 101 when the input voltage Vin to the operational amplifier 10 indicates a voltage value within a low voltage range from the reference potential to the power supply voltage Vs1A will be described with reference to FIG.

[0163] FIG. 7 is a diagram for explaining the operation of the buffer circuit 101 when the output voltage Vout of the buffer circuit 101 indicates a voltage value within the low voltage range.

[0164] When the output voltage Vout of the buffer circuit 101 falls within the low voltage range, a base current Ib1 flows from the output terminal of the operational amplifier 10 to the low power supply 11A via the base terminal of the NPN transistor 21A, turning on the NPN transistor 21A.

[0165] Accordingly, a collector current Ic1 flows as a load current into the low power supply 11A from the output terminal T2 of the buffer circuit 101 through the collector terminal of the NPN transistor 21A, causing the output voltage Vout generated at the output terminal T2 of the buffer circuit 101 to rise.

[0166] The operational amplifier 10 performs negative feedback operation until the output voltage Vout generated at the output terminal T2 connected to its non-inverting input terminal (+) converges to the voltage level of the input voltage Vin to the operational amplifier 10. This negative feedback operation maintains the output voltage Vout of the buffer circuit 101 at the voltage level of the input voltage Vin to the operational amplifier 10.

[0167] At this time, the control transistor 23A is in the OFF state because the output voltage Vout generated at the output terminal T2 connected to its base terminal is higher than the power supply voltage Vs1A. As a result, the output terminal of the operational amplifier 10 and the base terminal of the NPN transistor 22A are not conductive, no base current flows to the base terminal of the NPN transistor 22A, and the NPN transistor 22A is also in the OFF state. Therefore, no current flows from the output terminal T2 of the buffer circuit 100 to the high power supply 12A through the NPN transistor 22A.

[0168] In this way, when the output voltage Vout of the buffer circuit 101 is within the low voltage range, the load current is drawn from the output terminal T2 of the buffer circuit 100 to the low power supply 11A of the two power supplies through the NPN transistor 21A.

[0169] The power loss of the NPN transistor 21A in this case will be described.

[0170] In the NPN transistor 21A, a power loss P calculated using the collector current Ic1 flowing through the collector terminal and the voltage Vec between the emitter terminal and the collector terminal is dissipated as heat as shown in the following equation (7): P=Ic1×Vec=Ic1×(Vs1A−Vout) (7)

[0171] The voltage Vec between the emitter terminal and the collector terminal corresponds to the voltage {Ic1×(Vs1A−Vout)} between the power supply voltage Vs1A of the low power supply 11A and the output voltage Vout within the low voltage range.

[0172] In the second embodiment, when the output voltage Vout of the buffer circuit 101 falls within a voltage value within a low voltage range from the reference potential to the power supply voltage Vs1A (for example, 0V to -5V), the low power supply 11A that is responsible for the low voltage range is selected.

[0173] Therefore, the power loss P {Ic1×(Vs1A−Vout)} of the NPN transistor 21A is smaller than the power loss {Ic1×(Vs2A−Vout)} when the high-voltage power supply 12A is connected to the PNP transistor 21 and a load current is drawn through the PNP transistor 21. This makes it possible to reduce the power loss of the buffer circuit 101 having the NPN transistor 21A.

[0174] Next, the operation of the buffer circuit 101 when the input voltage Vin of the operational amplifier 10 indicates a voltage value within the high voltage range from the power supply voltage Vs1A to the power supply voltage Vs2A will be described with reference to FIG.

[0175] FIG. 8 is a diagram for explaining the operation of the buffer circuit 101 when the output voltage Vout of the buffer circuit 101 indicates a voltage value within the high voltage range.

[0176] When the output voltage Vout of the buffer circuit 101 is within the high voltage range, the output voltage Vout of the buffer circuit 101 is lower than the power supply voltage Vs1A of the low power supply 11A, so the NPN transistor 21A is turned off, and therefore no current flows from the output terminal T2 of the buffer circuit 101 to the low power supply 11A via the NPN transistor 21A.

[0177] On the other hand, the control transistor 23A is turned on because the output voltage Vout generated at the output terminal T2 connected to its base terminal indicates a voltage value within the high voltage range, causing a base current (-Ib3) to flow, thereby bringing the control transistor 23A into a conductive state between the output terminal of the operational amplifier 10 and the base terminal of the NPN transistor 22A.

[0178] As a result, the base current Ib2 that flows from the output terminal of the operational amplifier 10 to the base terminal of the NPN transistor 22A, which is equal to the collector current (-Ic3) of the control transistor 23A, flows into the high power supply 12A, and the NPN transistor 22A turns on.

[0179] Accordingly, the collector current Ic2 flowing through the collector terminal of the NPN transistor 21A flows as a load current from the output terminal T2 of the buffer circuit 101 to the high power supply 12A, causing the output voltage Vout generated at the output terminal T2 of the buffer circuit 101 to drop below the power supply voltage Vs1A.

[0180] The operational amplifier 10 performs negative feedback operation until the output voltage Vout generated at the output terminal T2 connected to its non-inverting input terminal (+) converges to the voltage level of the input voltage Vin to the operational amplifier 10. This negative feedback operation maintains the output voltage Vout of the buffer circuit 101 at the voltage level of the input voltage Vin to the operational amplifier 10.

[0181] At this time, the current output from the low power supply 11A is prevented from flowing back to the NPN transistor 21A by the rectifying element 32. In addition, the resistive element 31 suppresses a transient forward base current that flows from the output terminal of the operational amplifier 10 to the power supply voltage Vs1A mainly when switching between the NPN transistors 21A and 22A.

[0182] As described above, in the buffer circuit 101, a power supply having a voltage range that covers the current voltage value of the output voltage Vout is selected from the low power supply 11A and the high power supply 12A, and a load current is drawn from the output terminal T2 through the NPN transistor to which that power supply is connected. This reduces the potential difference between the power supply voltage of the selected power supply and the output voltage Vout of the buffer circuit 101, thereby reducing power loss in the buffer circuit 101.

[0183] In the second embodiment, a resistive element 31 is provided between the output terminal of the operational amplifier 10 and the base terminal of the NPN transistor 21A, but in a circuit configuration in which the influence of the inflow of the base current Ib2 into the NPN transistor 21A is small, the resistive element 31 may be eliminated.

[0184] In addition, in the second embodiment, a rectifying element 32 is provided between the collector terminal of the NPN transistor 21A and the output terminal of the buffer circuit 101, but in a circuit configuration in which the impact of backflow of current on the NPN transistor 21A is small, the rectifying element 32 may be eliminated.

[0185] Next, the effects of the second embodiment will be described.

[0186] According to the second embodiment, the buffer circuit 101, like the buffer circuit 101 of the first embodiment, performs negative feedback operation on the operational amplifier 10 having an inverting input terminal (−) to which an input voltage Vin as an input signal is supplied.

[0187] The buffer circuit 101 includes an NPN transistor 21A as a first transistor, an NPN transistor 22A as a second transistor, and a control transistor 23A. Each of the NPN transistor 21A, the NPN transistor 22A, and the control transistor 23A has an emitter terminal, a base terminal, and a collector terminal.

[0188] In the NPN transistor 21A, the emitter terminal is used as a power supply terminal to which a power supply voltage Vs1A as a first voltage is applied, and the base terminal is used as a control terminal directly or indirectly connected to the output terminal of the operational amplifier 10. Furthermore, the collector terminal is connected to the non-inverting input terminal (+) of the operational amplifier 10 and is used as an output terminal connected to the output terminal T2 of the buffer circuit 101.

[0189] In the NPN transistor 22A, the emitter terminal is used as a power supply terminal to which a power supply voltage Vs2A as a second voltage is applied, and the base terminal is used as a control terminal indirectly connected to the output terminal of the operational amplifier 10. Furthermore, the collector terminal is connected to the non-inverting input terminal (+) of the operational amplifier 10 and is used as an output terminal connected to the output terminal T2 of the buffer circuit 101.

[0190] In the control transistor 23A, the collector terminal is used as a first connection terminal connected to the base terminal of the NPN transistor 22A, and the base terminal is used as a detection terminal connected to the non-inverting input terminal (+) of the operational amplifier 10 and also connected to the output terminal T2 of the buffer circuit 101. Furthermore, the emitter terminal is used as a second connection terminal directly or indirectly connected to the output terminal of the operational amplifier 10.

[0191] Then, based on the potential difference between the output terminal of the operational amplifier 10 and the output terminal T2 of the buffer circuit 101, the control transistor 23A switches the state between the base terminal of the NPN transistor 21A and the output terminal of the operational amplifier 10 from a non-conductive state to a conductive state when the output voltage Vout of the buffer circuit 101 falls within the high voltage range from the power supply voltage Vs1A to the power supply voltage Vs2A.

[0192] With this configuration, the control transistor 23A detects whether the output voltage Vout of the buffer circuit 101 falls within the high-voltage range from power supply voltage Vs1A to power supply voltage Vs2A. If the output voltage Vout of the buffer circuit 101 falls within the high-voltage range, the control transistor 23A turns on, establishing conduction between the output terminal of the operational amplifier 10 and the base terminal of the NPN transistor 22A. Accordingly, the NPN transistor 22A turns on, and a voltage within the high-voltage range corresponding to the output level of the operational amplifier 10 is applied to the output terminal T2 of the buffer circuit 101.

[0193] On the other hand, when the output voltage Vout of the buffer circuit 101 is within a low-voltage range, for example, from the reference potential to the power supply voltage Vs1A, the control transistor 23A causes a non-conductive state between the output terminal of the operational amplifier 10 and the NPN transistor 22A. Accordingly, the NPN transistor 21A, whose base terminal is connected to the output terminal of the operational amplifier 10, turns on, and a voltage within the low-voltage range corresponding to the output level of the operational amplifier 10 is applied to the output terminal T2 of the buffer circuit 101.

[0194] In this way, the range of the output voltage Vout of the buffer circuit 101 is divided into a high voltage range covered by the ON operation of the NPN transistor 22A powered by the power supply voltage Vs2A, and a low voltage range covered by the ON operation of the NPN transistor 21A powered by the power supply voltage Vs1A. The buffer circuit 101 is configured so that, based on the output voltage Vout of the buffer circuit 101, the transistor of the power supply voltage responsible for the voltage range to which the output voltage Vout belongs is turned ON.

[0195] Therefore, the difference between the power supply voltage (Vs1A or Vs2A) applied to the transistor in an on-state and the output voltage Vout is smaller than in a circuit configuration in which a single transistor covers the entire range of the output voltage Vout of the buffer circuit 101. This makes it possible to suppress power loss occurring in the transistor in an on-state, thereby reducing power loss in the buffer circuit 101.

[0196] In addition, by using the control transistor 23A, it is possible to create an intermediate state for maintaining the continuity of the output voltage Vout when switching between the NPN transistor 21A and the NPN transistor 22A. This makes the switching more continuous than when a discontinuous switching means is used, and allows the output voltage Vout of the buffer circuit 100 to change more smoothly.

[0197] Furthermore, when the output voltage Vout of the buffer circuit 101 falls within the high voltage range from the power supply voltage Vs1A to the power supply voltage Vs2A, the control transistor 23A of the second embodiment causes a current to flow between the base terminal of the PNP transistor 22 and the output terminal of the operational amplifier 10 based on the potential difference between the output terminal of the operational amplifier 10 and the output terminal T2 of the buffer circuit 101.

[0198] This configuration allows a load current to be supplied through the PNP transistor 22 in accordance with changes in the input voltage Vin to the operational amplifier 10 in the high voltage range.

[0199] In the second embodiment, the NPN transistor 21A supplies a current (Ic1) from the low power supply 11A to a load connected to the output terminal T2 of the buffer circuit 101 when the output voltage Vout of the buffer circuit 101 is in a low voltage range from the reference potential to the power supply voltage Vs1A. The NPN transistor 22A supplies a current (Ic2) from the high power supply 12A to a load connected to the output terminal T2 of the buffer circuit 101 when the output voltage Vout of the buffer circuit 101 is in a high voltage range from the power supply voltage Vs1A to the power supply voltage Vs2A.

[0200] According to this configuration, the voltage range of the output voltage Vout of the buffer circuit 101 is covered separately by the two NPN transistors 21A and 22A, so that the power loss of the buffer circuit 101 can be reduced while the adoption of the control transistor 23A can improve the continuity in the switching region of the power supply voltages Vs1A and Vs2A.

[0201] In the second embodiment, the power supply voltages Vs1A and Vs2A are lower than the reference potential that the buffer circuit 101 uses as a reference, and the power supply voltage Vs2A is lower than the power supply voltage Vs1A.

[0202] According to this configuration, by alternately switching between the two negative power supply voltages Vs1A and Vs2A, it is possible to reduce power loss while reproducing the negative output voltage Vout of the buffer circuit 101 in accordance with changes in the input voltage Vin to the operational amplifier 10.

[0203] The buffer circuit 101 of the second embodiment further includes a resistor element 31 having one end connected to the output terminal of the operational amplifier 10 and the other end connected to the base terminal of the NPN transistor 21A.

[0204] With this configuration, when the output voltage Vout of the buffer circuit 101 indicates a voltage value within the high voltage range, the amount of current flowing from the output terminal of the operational amplifier 10 to the base terminal of the NPN transistor 22A into the base terminal of the NPN transistor 21A can be reduced, thereby preventing malfunctions of the operational amplifier 10 and the NPN transistor 21A.

[0205] The buffer circuit 101 of the second embodiment further includes a rectifying element 32. The rectifying element 32 is connected between the collector terminal of the NPN transistor 21A and the output terminal T2 of the buffer circuit 101 such that the forward direction of the rectifying element 32 is the same as the forward direction of the NPN transistor 21A. Specifically, the cathode of the rectifying element 32 is connected to the collector terminal of the NPN transistor 21A, and the anode of the rectifying element 32 is connected to the output terminal T2 of the buffer circuit 101.

[0206] This configuration can prevent current from flowing from the low power supply 11A to the NPN transistor 22A when the output voltage Vout of the buffer circuit 100 is within the high voltage range, thereby preventing malfunctions of the operational amplifier 10 and the NPN transistor 21A.

[0207] Third Embodiment In the above embodiment, an example using two power supply voltages has been described, but this is not limiting and three or more power supply voltages may be used. Therefore, as a third embodiment, an example using three power supply voltages will be described.

[0208] 9 is a circuit diagram showing the configuration of a buffer circuit 102 according to the third embodiment. In addition to the configuration of the buffer circuit 100 shown in FIG. 1, the buffer circuit 102 includes a PNP transistor 24 as a third transistor and a control transistor 25 as a second control transistor.

[0209] 1, the buffer circuit 102 includes an output circuit 30, which includes a PNP transistor 24 and a control transistor 25 in addition to the components of the output circuit 20. Here, only the PNP transistor 24 and the control transistor 25 added to the output circuit 30 will be described, and the other components are the same as those of the output circuit 20, so description thereof will be omitted.

[0210] The output circuit 30 is connected to power supplies 11 to 13 as first to third power supplies for supplying power to a load connected to the output terminal T2 of the buffer circuit 102. The third power supply 13 applies a power supply voltage Vs3 to the PNP transistor 24 as a third voltage.

[0211] Like the power supply voltages Vs1 and Vs2, the power supply voltage Vs3 is a positive voltage value higher than the reference potential of the buffer circuit 102, and the voltage value of the power supply voltage Vs3 is higher than the voltage value of the power supply voltage Vs2. For example, the reference potential is set to 0 [V], the power supply voltage Vs1 is set to +5 [V], the power supply voltage Vs2 is set to +10 [V], and the power supply voltage Vs3 is set to +15 [V].

[0212] Hereinafter, the first power source 11 will be referred to as the low power source 11 , the second power source 12 as the medium power source 12 , and the third power source 13 as the high power source 13 .

[0213] The PNP transistor 24 is a PNP-type transistor. The PNP transistor 24 has an emitter terminal used as a power supply terminal, a base terminal used as a control terminal, and a collector terminal used as an output terminal. The PNP transistor 24 adjusts the current flowing between the emitter terminal and the collector terminal in accordance with the current flowing between the emitter terminal and the base terminal.

[0214] The emitter terminal of the PNP transistor 24 is connected to the high power supply 13. Therefore, a power supply voltage Vs3 higher than the power supply voltage Vs2 is applied to the emitter terminal of the PNP transistor 24 from the high power supply 13 as a third voltage.

[0215] The base terminal of the PNP transistor 24 is indirectly connected to the output terminal of the operational amplifier 10. The collector terminal of the PNP transistor 24 is connected to the non-inverting input terminal (+) of the operational amplifier 10.

[0216] The control transistor 25 detects the output voltage Vout of the buffer circuit 102, and when the detected output voltage Vout exceeds the power supply voltage Vs2, controls the transistor 25 to a conductive state that allows current to flow between the output terminal of the operational amplifier 10 and the base terminal of the PNP transistor 24.

[0217] In the third embodiment, the control transistor 25 is an NPN transistor, and has a collector terminal used as a first connecting terminal, a base terminal used as a detection terminal, and an emitter terminal used as a second connecting terminal.

[0218] The collector terminal of the control transistor 25 is connected to the base terminal of the PNP transistor 24, and the base terminal of the control transistor 25 is connected to the output terminal T2 of the buffer circuit 102. The emitter terminal of the control transistor 25 is connected to the collector terminal of the control transistor 23 serving as the first control transistor.

[0219] With this connection configuration, the control transistor 23 switches the state between the base terminal of the PNP transistor 22 and the output terminal of the operational amplifier 10 from a non-conductive state to a conductive state when the output voltage Vout of the buffer circuit 102 falls within the medium voltage range from the power supply voltage Vs1 to the power supply voltage Vs2, as in the first embodiment.

[0220] In addition, based on the potential difference between the output terminal of the operational amplifier 10 and the output terminal T2 of the buffer circuit 102, when the output voltage Vout of the buffer circuit 102 falls within a high voltage range from the power supply voltage Vs2 to the power supply voltage Vs3, the control transistor 25 switches the state between the base terminal of the PNP transistor 24 and the output terminal of the operational amplifier 10 from a non-conductive state to a conductive state via the control transistor 23.

[0221] In this way, by using three power supplies 11 to 13 in the third embodiment, even if the upper limit value of the output voltage Vout of the buffer circuit 102 is set higher than in the first embodiment, it is possible to output a voltage up to the power supply voltage Vs3 while reducing the power loss of the buffer circuit 102.

[0222] Next, the effects of the third embodiment will be described.

[0223] In the buffer circuit 102 according to the third embodiment, the output circuit 30 includes a PNP transistor 24 as a third transistor and a control transistor 25 as a second control transistor. Each of the PNP transistor 24 and the control transistor 25 has an emitter terminal, a base terminal, and a collector terminal.

[0224] In the PNP transistor 24, the emitter terminal is used as a power supply terminal to which a power supply voltage Vs3 as a third voltage is applied, and the base terminal is used as a control terminal indirectly connected to the output terminal of the operational amplifier 10. Furthermore, the collector terminal is connected to the non-inverting input terminal (+) which is the second input terminal of the operational amplifier 10 and is also used as an output terminal connected to the output terminal T2 of the buffer circuit 102.

[0225] The control transistor 25 has a collector terminal used as a first connection terminal connected to the base terminal of the PNP transistor 24, a base terminal connected to the non-inverting input terminal (+) of the operational amplifier 10 and used as a detection terminal connected to the output terminal T2 of the buffer circuit 101, and an emitter terminal used as a second connection terminal connected to the collector terminal of the control transistor 23.

[0226] When the output voltage Vout of the buffer circuit 102 is within the range from the power supply voltage Vs1 to the power supply voltage Vs2, the control transistor 23 switches the state between the base terminal of the PNP transistor 22 and the output terminal of the operational amplifier 10 from a non-conductive state to a conductive state.

[0227] Furthermore, based on the potential difference between the output terminal of the operational amplifier 10 and the output terminal of the buffer circuit 102, when the output voltage of the buffer circuit 102 falls within the range from power supply voltage Vs2 to power supply voltage Vs3, the control transistor 25 switches the state between the base terminal of the PNP transistor 24 and the output terminal of the operational amplifier 10 from a non-conductive state to a conductive state via the control transistor 23.

[0228] With this configuration, the output range of the output voltage Vout in the buffer circuit 102 is shared by three power supply voltages Vs1 to Vs3. Therefore, compared to a circuit configuration in which the entire output range is covered by one or two power supply voltages, the difference between the power supply voltage of the transistor in ON operation and the output voltage Vout is smaller, making it possible to reduce power loss in the transistor in ON operation. As a result, power loss in the buffer circuit 102 can be reduced.

[0229] (Fourth Embodiment) In the third embodiment, an example in which a third power supply 13 is added to the configuration of the source output buffer circuit 100 in order to use three power supplies has been described, but the same applies to the configuration of the sink output buffer circuit 101. Therefore, an example in which the number of power supplies in the sink output buffer circuit 101 is changed to three will be described below as a fourth embodiment.

[0230] 10 is a circuit diagram showing the configuration of a buffer circuit 103 according to a fourth embodiment. In addition to the configuration of the buffer circuit 101 shown in FIG. 6, the buffer circuit 103 includes an NPN transistor 24A as a third transistor and a control transistor 25A as a second control transistor.

[0231] 6, the buffer circuit 103 includes an output circuit 30A, which includes an NPN transistor 24A and a control transistor 25A in addition to the components of the output circuit 20A. Here, only the NPN transistor 24A and the control transistor 25 added to the output circuit 30A will be described, and the other components are the same as those of the output circuit 20A, so description thereof will be omitted.

[0232] The output circuit 30A is connected to power supplies 11A to 13A as first to third power supplies for supplying power to a load connected to the output terminal T2 of the buffer circuit 103. The third power supply 13A applies a power supply voltage Vs3A as a third voltage to the NPN transistor 24A.

[0233] Like the power supply voltages Vs1A and Vs2A, the power supply voltage Vs3A has a negative voltage value lower than the reference potential of the buffer circuit 103, and the voltage value of the power supply voltage Vs3A is lower than the voltage value of the power supply voltage Vs2. For example, the reference potential is set to 0 [V], the power supply voltage Vs1A is set to −5 [V], the power supply voltage Vs2A is set to −10 [V], and the power supply voltage Vs3A is set to −15 [V].

[0234] Therefore, in the following, the first power supply 11A will be referred to as the negative-side low power supply 11A, the second power supply 12A as the negative-side medium power supply 12A, and the third power supply 13A as the negative-side high power supply 13A.

[0235] The NPN transistor 24A is an NPN transistor. The NPN transistor 24A has an emitter terminal used as a power supply terminal, a base terminal used as a control terminal, and a collector terminal used as an output terminal. The NPN transistor 24A adjusts the current flowing between the emitter terminal and the collector terminal in accordance with the current flowing between the emitter terminal and the base terminal.

[0236] The emitter terminal of the NPN transistor 24A is connected to the high power supply 13A. Therefore, the power supply voltage Vs3A lower than the power supply voltage Vs2A is applied as a third voltage from the high power supply 13A to the emitter terminal of the NPN transistor 24A.

[0237] The base terminal of the NPN transistor 24A is indirectly connected to the output terminal of the operational amplifier 10. The collector terminal of the NPN transistor 24A is connected to the non-inverting input terminal (+) of the operational amplifier 10.

[0238] The control transistor 25A detects the output voltage Vout of the buffer circuit 103, and when the detected output voltage Vout falls below the power supply voltage Vs2A, controls it to a conductive state that allows current to flow between the output terminal of the operational amplifier 10 and the base terminal of the NPN transistor 24A.

[0239] In the fourth embodiment, the control transistor 25A is a PNP transistor and has a collector terminal used as a first connecting terminal, a base terminal used as a detection terminal, and an emitter terminal used as a second connecting terminal.

[0240] The collector terminal of the control transistor 25A is connected to the base terminal of the NPN transistor 24A, and the base terminal of the control transistor 25A is connected to the output terminal T2 of the buffer circuit 103. The emitter terminal of the control transistor 25A is connected to the collector terminal of the control transistor 23 serving as the first control transistor.

[0241] With this connection configuration, as in the second embodiment, the control transistor 23A switches the state between the base terminal of the NPN transistor 22A and the output terminal of the operational amplifier 10 from a non-conductive state to a conductive state when the output voltage Vout of the buffer circuit 103 falls within the medium voltage range from the power supply voltage Vs1A to the power supply voltage Vs2A.

[0242] In addition, based on the potential difference between the output terminal of the operational amplifier 10 and the output terminal T2 of the buffer circuit 103, when the output voltage Vout of the buffer circuit 103 falls within a high voltage range from the power supply voltage Vs2A to the power supply voltage Vs3A, the control transistor 25A switches the state between the base terminal of the NPN transistor 24A and the output terminal of the operational amplifier 10 from a non-conductive state to a conductive state via the control transistor 23A.

[0243] As described above, according to the fourth embodiment, the output range of the output voltage Vout in the buffer circuit 103 is shared by three power supply voltages Vs1A to Vs3A. Therefore, compared to a circuit configuration in which the entire output range is covered by one or two power supply voltages, the difference between the power supply voltage of the transistor in an ON state and the output voltage Vout is smaller, thereby reducing the power loss of the transistor in an ON state. Therefore, the power loss of the buffer circuit 103 can be reduced.

[0244] In the above embodiment, the voltage follower type buffer circuits 100 to 103 are used as an example, but the buffer circuits 100 to 103 are not limited to the voltage follower type. Therefore, other configuration examples will be described with reference to FIGS. 11 to 13.

[0245] 11 is a circuit diagram showing a non-inverting amplification type buffer circuit 100A according to a first modification. The buffer circuit 100A includes resistor elements 91 and 92 in addition to an operational amplifier 10 and output circuits 20, 20A, 30, and 30A.

[0246] One end of the resistor element 91 is connected to the non-inverting input terminal (+) of the operational amplifier 10, and the other end of the resistor element 91 is connected to the ground potential G as a reference potential. One end of the resistor element 92 is connected to the non-inverting input terminal (+) of the operational amplifier 10, and the other end of the resistor element 92 is connected to the output terminal T2 of the buffer circuit 100A.

[0247] The relationship between the input voltage Vin and the output voltage Vout of the buffer circuit 100A can be expressed by the following equation (8) using the resistance value R1 of the resistor element 91 and the resistance value R2 of the resistor element 92: Vout=Vin×(R2 / R1+1) (8)

[0248] In this way, the above embodiment can also be applied to the non-inverting amplification type buffer circuit 100 A. The power supply 10 A connected to the output circuits 20, 20 A, 30, and 30 A is made up of power supplies 11 to 13 and 11 A to 13 A.

[0249] 12 is a circuit diagram showing an inverting amplification type buffer circuit 100B according to a second modification. The buffer circuit 100B includes resistor elements 93 and 94 in addition to the operational amplifier 10 and output circuits 20, 20A, 30, and 30A.

[0250] One end of the resistor element 93 is connected to the input terminal T1, and the other end of the resistor element 93 is connected to the non-inverting input terminal (+) of the operational amplifier 10. Furthermore, one end of the resistor element 94 is connected to the non-inverting input terminal (+) of the operational amplifier 10, and the other end of the resistor element 94 is connected to the output terminal T2 of the buffer circuit 100B. Furthermore, the inverting input terminal (-) of the operational amplifier 10 is connected to the ground potential G as a reference potential.

[0251] In the buffer circuit 100B, unlike the non-inverting amplification type buffer circuit 100A, the non-inverting input terminal (+) of the operational amplifier is used as a first input terminal to which the input voltage Vin is supplied.

[0252] The relationship between the input voltage Vin and the output voltage Vout of the buffer circuit 100B can be expressed by the following equation (9) using the resistance value R1 of the resistor element 93 and the resistance value R2 of the resistor element 94: Vout=-Vin×(R2 / R1) (9)

[0253] In this way, the above embodiment can also be applied to the inverting amplification type buffer circuit 100B.

[0254] 13 is a circuit diagram showing a voltage shift type buffer circuit 100C according to a third modification. The buffer circuit 100C includes resistive elements 95 to 98 and a power supply 99 in addition to the operational amplifier 10 and output circuits 20, 20A, 30, and 30A.

[0255] One end of the resistor element 95 is connected to the input terminal T1, and the other end of the resistor element 95 is connected to the inverting input terminal (−) of the operational amplifier 10. One end of the resistor element 96 is connected to the positive electrode of the power supply 99, and the other end of the resistor element 96 is connected to the inverting input terminal (−) of the operational amplifier 10.

[0256] Furthermore, one end of the resistor element 97 is connected to the ground potential G as a reference potential, and the other end of the resistor element 97 is connected to the non-inverting input terminal (+) of the operational amplifier 10. Furthermore, one end of the resistor element 98 is connected to the non-inverting input terminal (+) of the operational amplifier 10, and the other end of the resistor element 98 is connected to the output terminal T2 of the buffer circuit 100C.

[0257] The relationship between the input voltage Vin and the output voltage Vout of the buffer circuit 100C can be expressed by the following equation (10) using the voltage Vb of the power supply 99, when the resistance values ​​R1 to R4 of the resistor elements 95 to 98 are the same: Vout=Vin+Vb (10)

[0258] In this way, the above embodiment can also be applied to the voltage shift type buffer circuit 100 C. Regarding the connection of the power supply 99, the positive and negative poles of the power supply 99 may be reversed so that the direction of the voltage Vb of the power supply 99 is reversed.

[0259] Fifth Embodiment In the buffer circuit 102 of the third embodiment, the operational amplifier 10 needs to draw base currents of the PNP transistors 21, 22, and 24, and these base currents increase in proportion to the load current. Therefore, if the required load current becomes too large, it may become difficult for the operational amplifier 10 to draw the base current. A solution to this problem will be described below.

[0260] 14 is a circuit diagram showing the configuration of a buffer circuit 104 according to the fifth embodiment. The buffer circuit 104 includes an output circuit 40 instead of the output circuit 30. In addition to the configuration of the output circuit 30, the output circuit 40 includes an NPN transistor 41 as a buffer transistor.

[0261] The NPN transistor 41 is an NPN-type transistor and has a collector terminal used as a first connection terminal, a base terminal used as a control terminal, and an emitter terminal used as a second connection terminal.

[0262] The collector terminal of the NPN transistor 41 is connected to the base terminal of the PNP transistor 21 and the emitter terminal of the control transistor 23. The emitter terminal of the NPN transistor 41 is connected to the ground potential G used as a reference potential.

[0263] The base terminal of the NPN transistor 41 is connected to the output terminal of the operational amplifier 10 .

[0264] In this way, when the NPN transistor 41 is inserted as a buffer for the operational amplifier 10, the phases of the output voltage Vop of the operational amplifier 10 and the output voltage Vout of the buffer circuit 102 are inverted. For this reason, in the fifth embodiment, the connection destination of the inverting input terminal (−) and the connection destination of the non-inverting input terminal (+) of the operational amplifier 10 are swapped, thereby establishing negative feedback for the output voltage Vout of the buffer circuit 100.

[0265] Specifically, the non-inverting input terminal (+) of the operational amplifier 10 is connected to the input terminal T1 of the buffer circuit 104, and the inverting input terminal (-) of the operational amplifier 10 is connected to the output terminal T2 of the buffer circuit 104, the collector terminals of the PNP transistors 21, 22, and 24, and the base terminals of the control transistors 23 and 25.

[0266] The buffer transistor realized by the NPN transistor 41 draws the base current instead of the operational amplifier 10, and can also be applied to other embodiments when it becomes difficult for the operational amplifier 10 to draw the base current as the load current increases. For example, the sink output buffer circuits 101 and 103 are provided with PNP transistors as buffer transistors, with the emitter terminals connected to the reference potential.

[0267] Next, the effects of the fifth embodiment will be described.

[0268] In the buffer circuit 104 according to the fifth embodiment, the first input terminal of the operational amplifier 10 is the non-inverting input terminal (+) and the second input terminal is the inverting input terminal (-). The output terminal of the PNP transistor 24 is the collector terminal connected to the inverting input terminal (-) of the operational amplifier 10, and the detection terminal of the control transistor 25 is the base terminal connected to the inverting input terminal (-) of the operational amplifier 10.

[0269] An input voltage Vin is supplied as an input signal to a non-inverting input terminal (+) of the operational amplifier 10. The inverting input terminal (−) of the operational amplifier 10 is connected to an output terminal T2 of the buffer circuit 102, the collector terminals of PNP transistors 21, 22, and 24, and the base terminals of control transistors 23 and 25.

[0270] The output circuit 40 further includes an NPN transistor 41 as a buffer transistor in addition to the configuration of the output circuit 30. In the NPN transistor 41, the collector terminal as a first connection terminal is connected to the base terminal of the PNP transistor 21 and the emitter terminal of the control transistor 23, and the base terminal as a control terminal is connected to the output terminal of the operational amplifier 10. Furthermore, the emitter terminal as a second connection terminal is connected to the reference potential (G).

[0271] With this configuration, the NPN transistor 41 can draw a larger amount of base current from the PNP transistors 21, 22, and 24 instead of the operational amplifier 10. This allows the load current output from the output terminal T2 of the buffer circuit 104 to be increased.

[0272] Therefore, in the buffer circuit 104 of the fifth embodiment, it is possible to reduce power loss while ensuring the magnitude of the required load current.

[0273] In the fifth embodiment, an example has been described in which the NPN transistor 41 is added as a buffer transistor to the configuration of the buffer circuit 102 of the third embodiment in order to increase the load current, but a buffer transistor may be added to the configuration of the buffer circuit 103 of the fourth embodiment. Even in this case, the load current output from the output terminal T2 of the buffer circuit 103 can be increased by adding a buffer transistor.

[0274] FIG. 15 is a circuit diagram showing an example of the configuration of a buffer circuit 104A obtained by changing the voltage follower type buffer circuit 104 shown in FIG. 14 to a voltage offset type.

[0275] 14, the buffer circuit 104A according to this modification includes voltage shift resistor elements 95 to 98 and a power supply 99 that constitute a feedback section for realizing the input / output characteristics of the voltage shift shown in Fig. 13. The buffer circuit 104A further includes a resistor element 42 for improving the stability of the negative feedback of the entire circuit, and resistor elements 43 and 44 for suppressing the base current of the PNP transistor 24 from flowing into the PNP transistor 22 and the control transistor 23 while the PNP transistor 24 is in an on-state.

[0276] In addition, the buffer circuit 104A includes resistive elements 51 to 54 and capacitive elements 55 to 58 for phase compensation, and rectifying elements 59 to 62 for protecting the PNP transistors 21 and 22 and the control transistors 23 and 25.

[0277] For example, the resistance values ​​of the resistor elements 42 to 44 are set to 33 Ω, 100 Ω, and 1 kΩ, respectively, the resistance values ​​of the resistor elements 51 to 54 are set to 100 Ω, 100 Ω, 1 kΩ, and 2.2 Ω, respectively, the capacitance values ​​of the capacitor elements 55 to 58 are set to 1 nF, 1 nF, 100 pF, and 220 nF, respectively, and the resistance value of the resistor elements 95 to 98 is set to 10 kΩ.

[0278] In this way, the buffer circuit 104A can perform voltage shift and phase compensation while reducing power loss and suppressing malfunctions and operational defects of the operational amplifier 10 and each transistor.

[0279] Next, an application example of the buffer circuits 100 to 104A will be described with reference to FIG.

[0280] FIG. 16 is a block diagram showing the functions of a measuring device 1 including a buffer circuit 104A.

[0281] The measurement device 1 is a device for measuring the AC impedance of a DUT under test. The measurement device 1 applies a constant AC current to the DUT under test, detects the voltage generated in the DUT under test, and calculates the impedance of the DUT under test using the detected voltage value and the current value of the constant current.

[0282] FIG. 16 shows an example of the configuration of a constant current circuit 1A in the measurement device 1 that supplies a constant AC current to the DUT under test.

[0283] The constant current circuit 1A includes a generator 2 that outputs an AC reference signal, a reference resistor 3, an output buffer circuit 4, a source output buffer circuit 104A, and a sink output buffer circuit 105A corresponding to the buffer circuit 104A. The buffer circuit 105A has a circuit configuration similar to that of the buffer circuit 104A, in which a buffer transistor is added to the NPN transistor 41, and a voltage shift function, a phase compensation function, etc. are added.

[0284] The buffer circuit 104A is configured so that the output voltage V+s of the output terminal T2 is shifted by +1.5 [V], and the buffer circuit 105A is configured so that the output voltage V-s of the output terminal T2 is shifted by -1.5 [V].

[0285] The output buffer circuit 4 is a push-pull type buffer circuit that outputs an output voltage Vout equal to the input voltage Vin and is capable of sourcing (discharging) and sinking (sinking) current. Here, the source current is supplied from the output terminal T2 of the buffer circuit 104A, and the sink current is supplied from the output terminal T2 of the buffer circuit 105A.

[0286] In place of the pair of buffer circuits 104A and 105A, for example, a pair of buffer circuits obtained by changing the voltage follower type buffer circuits 100 and 101 into a voltage shift type may be provided.

[0287] In this way, the buffer circuits 100 to 105A can be applied to the measurement device 1 that measures impedance. In the measurement device 1, by employing at least one of the buffer circuits 100 to 105A in the constant current circuit 1A, it is possible to reduce power loss in the constant current circuit 1A.

[0288] Although the above describes various embodiments of the present invention, the above embodiments merely illustrate some of the application examples of the present invention, and it is not intended that the technical scope of the present invention be limited to the specific configurations of the above embodiments.

[0289] In the above embodiment, bipolar transistors are used as the first to third transistors, but field-effect transistors and insulated-gate transistors may also be used. In addition, in the first embodiment, an example is described in which an AC input voltage Vin is input to the first input terminal of the operational amplifier 10, but this is not limiting, and the input voltage Vin may be a signal that changes irregularly.

[0290] 100 to 104 Buffer circuit 10 Operational amplifier 20, 20A, 30, 30A, 40 Output circuit 21, 22, 24 PNP transistors (first to third transistors) 23, 25 NPN transistors (first and second control transistors) 21A, 22A, 24A NPN transistors (first to third transistors) 23A, 25A PNN transistors (first and second control transistors) 31 Resistor element 32 Rectifier element

Claims

1. A buffer circuit that operates an operational amplifier with a first input terminal to which an input signal is supplied in a negative feedback manner, comprising: a first transistor having a power supply terminal to which a first voltage is applied, a control terminal connected directly or indirectly to the output terminal of the operational amplifier, and an output terminal connected to the second input terminal of the operational amplifier; a second transistor having a power supply terminal to which a second voltage is applied, a control terminal connected indirectly to the output terminal of the operational amplifier, and an output terminal connected to the second input terminal of the operational amplifier; and a control transistor having a first connection terminal connected to the control terminal of the second transistor, a detection terminal connected to the second input terminal of the operational amplifier, and a second connection terminal connected directly or indirectly to the output terminal of the operational amplifier, the second input terminal of the operational amplifier being connected to the output terminal of the buffer circuit, and the control transistor switching the state between the control terminal of the second transistor and the output terminal of the operational amplifier from a non-conductive state to a conductive state when the output voltage of the buffer circuit is within a range from the first voltage to the second voltage, based on a potential difference between the output terminal of the operational amplifier and the output terminal of the buffer circuit.

2. A buffer circuit according to claim 1, wherein the control transistor allows a current to flow between the control terminal of the second transistor and the output terminal of the operational amplifier based on a potential difference between the output terminal of the operational amplifier and the output terminal of the buffer circuit when the output voltage of the buffer circuit is within a range from the first voltage to the second voltage.

3. A buffer circuit according to claim 1, wherein the first transistor supplies a current to a load connected to the output terminal of the buffer circuit when the output voltage of the buffer circuit is in a range from a reference potential to the first voltage, and the second transistor supplies a current to a load connected to the output terminal of the buffer circuit when the output voltage of the buffer circuit is in a range from the first voltage to the second voltage.

4. A buffer circuit according to claim 1, wherein the first transistor and the second transistor are PNP transistors; the power supply terminal, the control terminal and the output terminal of each of the first transistor and the second transistor are the emitter terminal, the base terminal and the collector terminal of the PNP transistor, respectively; the control transistor is an NPN transistor; the first connection terminal, the detection terminal and the second connection terminal are the collector terminal, the base terminal and the emitter terminal of the NPN transistor, respectively; the first voltage and the second voltage are higher than a reference voltage of the buffer circuit, and the second voltage is higher than the first voltage.

5. A buffer circuit according to claim 1, wherein the first transistor and the second transistor are NPN transistors, the power supply terminal, the control terminal and the output terminal are the emitter terminal, the base terminal and the collector terminal of the NPN transistor, respectively, the control transistor is a PNP transistor, the first connection terminal, the detection terminal and the second connection terminal are the collector terminal, the base terminal and the emitter terminal of the PNP transistor, respectively, the first voltage and the second voltage are lower than a reference voltage of the buffer circuit, and the second voltage is lower than the first voltage.

6. A buffer circuit according to claim 1, wherein the first input terminal of said operational amplifier is an inverting input terminal, the second input terminal of said operational amplifier is a non-inverting input terminal, and the output terminal of said operational amplifier is directly connected to the control terminal of said first transistor.

7. A buffer circuit according to claim 1, further comprising a resistive element having one end connected to the output terminal of said operational amplifier and the other end connected to the control terminal of said first transistor.

8. A buffer circuit according to claim 1, further comprising a rectifying element connected between the output terminal of said first transistor and the output terminal of said buffer circuit so that its forward direction is in the same direction as the forward direction of said first transistor.

9. A buffer circuit according to claim 1, comprising: a third transistor having a power supply terminal to which a third voltage is applied, a control terminal indirectly connected to the output terminal of the operational amplifier, and an output terminal connected to the second input terminal of the operational amplifier; and a second control transistor having a first connection terminal connected to the control terminal of the third transistor, a detection terminal connected to the second input terminal of the operational amplifier, and a second connection terminal connected to the first connection terminal of a first control transistor which is the control transistor, wherein the first control transistor switches the state between the control terminal of the second transistor and the output terminal of the operational amplifier from a non-conductive state to a conductive state when the output voltage of the buffer circuit is within a range from the first voltage to the second voltage, and the second control transistor switches the state between the control terminal of the third transistor and the output terminal of the operational amplifier from a non-conductive state to a conductive state via the first control transistor when the output voltage of the buffer circuit is within a range from the second voltage to the third voltage, based on a potential difference between the output terminal of the operational amplifier and the output terminal of the buffer circuit.

10. A buffer circuit according to claim 1, further comprising a buffer transistor having a first connection terminal connected to the control terminal of said first transistor and the second connection terminal of said control transistor, a control terminal connected to the output terminal of said operational amplifier, and a second connection terminal connected to a reference potential.

11. A measuring device comprising a buffer circuit according to any one of claims 1 to 10.

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