Semiconductor device and manufacturing method

Abstract

To provide a semiconductor device and a manufacturing method enabling the productivity of the semiconductor device to be improved.SOLUTION: A semiconductor device includes a first electrode, a plurality of unit element regions, and a partitioning region. Each unit element region includes a first semiconductor portion, a second electrode, and a first conductive portion. The first semiconductor portion includes: a first semiconductor region of a first conductivity type provided on the first electrode; a second semiconductor region of a second conductivity type provided on the first semiconductor region; and a third semiconductor region of the first conductivity type provided on the second semiconductor region. The second electrode is provided on the second and third semiconductor regions, is electrically connected with the second and third semiconductor regions. The first conductive portion includes a portion opposed to the second semiconductor region via a first insulating film. A plurality of unit element regions include a pattern at least partially common to each other. The partitioning region includes a second semiconductor portion continuous to the first semiconductor portion and partitions the plurality of unit element regions.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] FIELD Embodiments of the present invention relate to a semiconductor device and a manufacturing method. [Background technology]

[0002] For example, in semiconductor devices including transistors, products of various chip sizes may be produced depending on characteristics such as desired current values, etc. In the field of semiconductor devices, there is a demand for improving productivity. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2003-023138 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a semiconductor device and a manufacturing method thereof that enable improvement in productivity. [Means for solving the problem]

[0005] The semiconductor device according to the embodiment includes a first electrode, a plurality of unit element regions, and a partition region. Each of the unit element regions includes a first semiconductor portion, a second electrode, and a first conductive portion. The first semiconductor portion includes a first semiconductor region of a first conductivity type provided on the first electrode, a second semiconductor region of a second conductivity type provided on the first semiconductor region, and a third semiconductor region of the first conductivity type provided on the second semiconductor region. The second electrode is provided on the second semiconductor region and the third semiconductor region and is electrically connected to the second semiconductor region and the third semiconductor region. The first conductive portion includes a portion facing the second semiconductor region via a first insulating film. The plurality of unit element regions include at least a partial common pattern. The partition region includes a second semiconductor portion continuous with the first semiconductor portion and partitions the plurality of unit element regions. [Brief explanation of the drawings]

[0006] [Figure 1] 1 is a schematic plan view illustrating a semiconductor device according to a first embodiment. [Figure 2] 1 is a schematic plan view illustrating a semiconductor device according to a first embodiment. [Figure 3] 1 is a schematic cross-sectional view illustrating a semiconductor device according to a first embodiment. [Figure 4] 1 is a schematic plan view illustrating a semiconductor device according to a first embodiment. [Figure 5] 1 is a schematic cross-sectional view illustrating a semiconductor device according to a first embodiment. [Figure 6] 6(a) and 6(b) are schematic plan views illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 7] 7(a) to 7(h) are schematic cross-sectional views illustrating the steps of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 8] 8(a) to 8(e) are schematic cross-sectional views illustrating the steps of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 9] FIG. 4 is a schematic plan view illustrating a modified example of the semiconductor device according to the first embodiment. [Figure 10] FIG. 4 is a schematic plan view illustrating a modified example of the semiconductor device according to the first embodiment. [Figure 11] FIG. 4 is a schematic plan view illustrating a modified example of the semiconductor device according to the first embodiment. [Figure 12] FIG. 4 is a schematic plan view illustrating a modified example of the semiconductor device according to the first embodiment. [Figure 13] FIG. 10 is a schematic plan view illustrating a semiconductor device according to a second embodiment. [Figure 14] FIG. 10 is a schematic cross-sectional view illustrating a semiconductor device according to a second embodiment. [Figure 15] FIG. 10 is a schematic plan view illustrating a semiconductor device according to a third embodiment. [Figure 16] FIG. 10 is a schematic cross-sectional view illustrating a semiconductor device according to a third embodiment. [Figure 17] FIG. 10 is a schematic plan view illustrating a semiconductor device according to a fourth embodiment. [Figure 18] FIG. 10 is a schematic cross-sectional view illustrating a semiconductor device according to a fourth embodiment. [Figure 19] FIG. 10 is a schematic plan view illustrating a semiconductor device according to a fourth embodiment. [Figure 20] FIG. 10 is a schematic cross-sectional view illustrating a semiconductor device according to a fourth embodiment. [Figure 21] FIG. 10 is a schematic plan view illustrating a semiconductor device according to a fifth embodiment. [Figure 22] FIG. 10 is a schematic cross-sectional view illustrating a semiconductor device according to a fifth embodiment. [Figure 23] FIG. 11 is a schematic plan view illustrating a modified example of the semiconductor device according to the fifth embodiment. [Figure 24] FIG. 10 is a schematic plan view illustrating a semiconductor device according to a sixth embodiment. [Figure 25] FIG. 10 is a schematic cross-sectional view illustrating a semiconductor device according to a sixth embodiment. [Figure 26] FIG. 13 is a schematic plan view illustrating a modification of the semiconductor device according to the sixth embodiment. [Figure 27] FIG. 13 is a schematic cross-sectional view illustrating a modified example of the semiconductor device according to the sixth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, embodiments of the present invention will be described with reference to the drawings. The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between parts, etc. are not necessarily the same as those in reality. Even when the same part is shown, the dimensions and ratios may be different depending on the drawing. In the present specification and the drawings, elements similar to those already explained are given the same reference numerals and detailed explanations will be omitted as appropriate. In each of the embodiments described below, the p-type (an example of the second conductivity type) and n-type (an example of the first conductivity type) of each semiconductor region may be reversed to implement each embodiment.

[0008] (First embodiment) FIG. 1 is a schematic plan view showing a semiconductor device according to the first embodiment. The semiconductor device 100 according to the first embodiment includes a plurality of unit element regions AA and a partition region DA. Semiconductor elements such as MOSFETs (metal-oxide-semiconductor field-effect transistors) and IGBTs (insulated gate bipolar transistors) are formed in the unit element regions AA. In this example, four unit element regions (first to fourth unit element regions A1 to A4) are provided as the plurality of unit element regions AA. The semiconductor device 100 has a 2×2 layout in which two unit element regions AA are arranged vertically (the third direction D3 in the figure) and two are arranged horizontally (the second direction D2 in the figure). However, in the embodiment, the number of unit element regions AA is an integer of one or more and is not particularly limited. Three or more unit element regions AA may be arranged in at least one of the second direction D2 and the third direction D3. For example, the plurality of unit element regions AA are arranged periodically in at least one of the second direction D2 and the third direction D3. The unit element area AA is, for example, a rectangular area having two sides extending in the second direction D2 and two sides extending in the third direction D3. When viewed from above, the unit element areas AA have the same outer periphery shape and area (size).

[0009] The partitioned areas DA are provided between adjacent unit element areas AA and are areas that partition the multiple unit element areas AA. For example, the partitioned areas DA are continuous with the multiple unit element areas AA and are in a lattice (cross) shape in this example. In this example, no elements such as transistors are provided in the partitioned areas DA.

[0010] A plurality of electrodes (a conductive film 40 including a first wiring portion 41 and a second electrode 12) are provided on the upper surface of the semiconductor device 100. Fig. 1 (and Figs. 9 to 12, 15, 17, 21, 23, 24, and 26 described below) shows the plurality of electrodes with dashed lines and is a perspective view that schematically shows the layout of the layers below the plurality of electrodes.

[0011] The semiconductor device 100 includes a semiconductor substrate. Each unit element area AA includes a first semiconductor portion 61 that is a part of the semiconductor substrate. Each partitioned area DA includes a second semiconductor portion 62 that is another part of the semiconductor substrate. The second semiconductor portion 62 is continuous with the first semiconductor portion 61.

[0012] FIG. 2 is a schematic plan view illustrating the semiconductor device according to the first embodiment. FIG. 3 is a schematic cross-sectional view illustrating the semiconductor device according to the first embodiment. Fig. 2 shows an enlarged view of the vicinity of region R1 shown in Fig. 1. Fig. 3 shows a cross section taken along line AA shown in Fig. 2.

[0013] 3, the semiconductor device 100 includes a first electrode 11 (drain electrode). The first semiconductor portion 61 of the unit element area AA is provided on the first electrode 11.

[0014] In the description of the embodiments, a first direction D1, a second direction D2, and a third direction D3 are used. The direction from the first electrode 11 toward the first semiconductor portion 61 is defined as the first direction D1. A direction perpendicular to the first direction D1 is defined as the second direction D2. A direction perpendicular to the first direction D1 and perpendicular to the second direction D2 is defined as the third direction D3. For ease of explanation, the direction from the first electrode 11 toward the first semiconductor portion 61 is referred to as "up," and the opposite direction is referred to as "down." These directions are based on the relative positional relationship between the first electrode 11 and the first semiconductor portion 61 and are unrelated to the direction of gravity.

[0015] 3, the first semiconductor portion 61 includes a semiconductor region 28 (drain region), a first semiconductor region 21 (drift region), a second semiconductor region 22 (base region), a plurality of third semiconductor regions 23 (source regions), and a plurality of contact portions (cell contacts) 71. Note that in FIG. 2 (and FIGS. 4, 13, and 19 described below), the ranges where the second semiconductor region 22 and the third semiconductor region 23 are provided are represented by dots.

[0016] The first semiconductor region 21 is provided on the first electrode 11 via the semiconductor region 28. The first semiconductor region 21 is electrically connected to the first electrode 11 via the semiconductor region 28. The first semiconductor region 21 and the semiconductor region 28 are of a first conductivity type (n-type). The impurity concentration of the first conductivity type in the first semiconductor region 21 is lower than the impurity concentration of the first conductivity type in the semiconductor region 28.

[0017] The second semiconductor region 22 is provided on a part of the first semiconductor region 21. The second semiconductor region 22 is of the second conductivity type (p-type).

[0018] The third semiconductor region 23 is provided on a portion of the second semiconductor region 22. The third semiconductor region 23 is of the first conductivity type. The impurity concentration of the first conductivity type in the third semiconductor region 23 is higher than the impurity concentration of the first conductivity type in the first semiconductor region 21. The multiple third semiconductor regions 23 are aligned in a third direction D3, and each third semiconductor region 23 extends in the second direction D2.

[0019] The plurality of contact portions 71 are provided on a portion of the second semiconductor region 22. The contact portions 71 are of the second conductivity type. The impurity concentration of the second conductivity type in the contact portions 71 is higher than the impurity concentration of the second conductivity type in the second semiconductor region 22. The plurality of contact portions 71 are aligned in the third direction D3, and each contact portion 71 extends in the second direction D2. When viewed from above, one contact portion 71 is arranged between two adjacent third semiconductor regions 23.

[0020] As shown in FIG. 3, each of the unit element regions AA further includes a plurality of first trenches T1, a plurality of first conductive portions 31 (gate electrodes), a plurality of first insulating films 51 (gate insulating films), and a second electrode 12 (source electrode).

[0021] The first conductive portion 31 is provided on a part of the first semiconductor region 21. The first conductive portion 31 has a portion facing a side surface of the second semiconductor region 22 with a first insulating film 51 interposed therebetween. The first conductive portion 31 also has a portion facing a side surface of the first semiconductor region 21 with the first insulating film 51 interposed therebetween, and a portion facing a side surface of the third semiconductor region 23 with the first insulating film 51 interposed therebetween. The first conductive portion 31 is aligned with the first to third semiconductor regions 21 to 23 in the third direction D3. The multiple first conductive portions 31 are aligned in the third direction D3, and each first conductive portion 31 extends in the second direction D2.

[0022] The first trench T1 is provided in the first semiconductor portion 61 and is a recess extending downward from the upper portion of the first semiconductor portion 61. The first trench T1 extends in an extension direction (in this example, the second direction D2) along the surface of the first semiconductor portion 61. The multiple first trenches T1 are aligned in a third direction D3. A first insulating film 51 is provided on the inner wall of the first trench T1. Each of the multiple first conductive portions 31 is disposed inside each of the multiple first trenches T1. Two third semiconductor regions 23 are provided between two adjacent first trenches T1.

[0023] The second electrode 12 is provided on the first conductive portion 31, the second semiconductor region 22, and the third semiconductor region 23. The second electrode 12 is electrically connected to the second semiconductor region 22 and the third semiconductor region 23. An insulating film 55 is provided between the first conductive portion 31 and the second electrode 12, and the first conductive portion 31 and the second electrode 12 are insulated from each other.

[0024] The second electrode 12 extends downward to a contact portion 71. The contact portion 71 electrically connects the second electrode 12 to the second semiconductor region 22.

[0025] 1 and 2, each of the plurality of unit element areas AA includes a first wiring portion 41 (gate wiring) and a plurality of contact portions 72 (gate contacts). The first wiring portion 41 is provided on the first semiconductor portion 61 and is aligned with the second electrode 12 in a direction perpendicular to the first direction D1. The first wiring portion 41 is disposed on both ends of the plurality of trenches T1 and the first conductive portion 31 in the extension direction (second direction D2). Each first conductive portion 31 is electrically connected to the first wiring portion 41 via each contact portion 72.

[0026] 1, the multiple first wiring portions 41 provided in the multiple unit element areas AA are continuous and electrically connected to each other. For example, the first wiring portion 41 in the first unit element area A1 is continuous with the first wiring portion 41 in the second unit element area A2. Each of the multiple first wiring portions 41 may be part of one continuous conductive film 40. The conductive film 40 is provided in the multiple unit element areas AAs and the partitioned areas DA.

[0027] In each unit element region AA, each contact portion 72 electrically connects each first conductive portion 31 to the first wiring portion 41. For example, the multiple contact portions 72 in the second unit element region A2 electrically connect the multiple first conductive portions 31 in the second unit element region A2 to the first wiring portion 41 in the second unit element region A2.

[0028] Contact portions 72 are provided on both ends in the extension direction of each first conductive portion 31. For example, the contact portions 72 are continuous with the conductive film 40 including the first wiring portion 41, and extend downward from the conductive film 40 to contact the first conductive portion 31. The contact portions 72 may be part of the conductive film 40. The contact portions 72 penetrate, for example, the insulating film 55 on the first conductive portion 31 to contact the first conductive portion 31.

[0029] The second electrodes 12 provided in the unit element areas AA may be electrically connected to each other by bonding or the like and set to the same potential.

[0030] 2, the third semiconductor region 23 is disposed below the second electrode 12, and is not disposed below the conductive film 40. The second semiconductor region 22 is disposed below the second electrode 12, and extends to below the conductive film 40. The second semiconductor region 22 does not have to be provided in the partitioned region DA.

[0031] In the embodiment, the plurality of unit element areas AA include a common pattern. The plurality of unit element areas AA include at least a part of the common pattern. For example, at least a part of the pattern of one unit element area AA is common to at least a part of the pattern of another unit element area AA.

[0032] The pattern of at least a portion of a unit element area AA refers to the number, position, and shape of at least a portion of the elements contained in the unit element area AA when viewed from above. "Common" (or "same") is not limited to being completely identical, but also includes being approximately the same. For example, even if there are some differences due to variations in process conditions, they are included in "common" (or "same").

[0033] Specifically, in this example, the common patterns are the pattern of the first conductive portion 31, the pattern of the first trench T1, the pattern of the contact portion 71, the pattern of the contact portion 72, and the pattern of the second semiconductor region 22. The common patterns are repeated periodically with the same period as the period of the plurality of unit element regions AA.

[0034] For example, the number, positions and shapes of the multiple first conductive parts 31 in the first unit element region A1 are the same as the number, positions and shapes of the multiple first conductive parts 31 in the second unit element region A2. For example, the number, positions and shape of the plurality of first trenches T1 in the first unit element region A1 are the same as the number, positions and shape of the plurality of first trenches T1 in the second unit element region A2. For example, the number, positions and shapes of the plurality of contact portions 71 in the first unit element region A1 are the same as the number, positions and shapes of the plurality of contact portions 71 in the second unit element region A2. For example, the number, positions and shapes of the plurality of contact portions 72 in the first unit element region A1 are the same as the number, positions and shapes of the plurality of contact portions 72 in the second unit element region A2. For example, the number, positions and shapes of the second semiconductor regions 22 in the first unit element region A1 are the same as the number, positions and shapes of the second semiconductor regions 22 in the second unit element region A2.

[0035] These patterns (the pattern of the plurality of first conductive portions 31, the pattern of the plurality of first trenches T1, the pattern of the plurality of contact portions 71, the pattern of the plurality of contact portions 72, and the pattern of the second semiconductor region 22) may be common to all the unit element areas AA. Note that the partitioned area DA does not need to include the common patterns of the unit element areas AA.

[0036] FIG. 4 is a schematic plan view illustrating the semiconductor device according to the first embodiment. FIG. 4 shows an enlarged view of the vicinity of R2 shown in FIG. 1. In addition, FIG. 4 indicates by dots the area where a fourth semiconductor region 24, which will be described later, is provided. A conductive region 44 (gate pad) is provided in at least one of the multiple unit element regions AA. In this example, the first unit element region A1 includes the conductive region 44, and the second to fourth unit element regions A2 to A4 do not include the conductive region 44. In the first unit element region A1, the conductive region 44 is provided on the first semiconductor portion 61 and is electrically connected to the first wiring portion 41. The conductive region 44 is continuous with the first wiring portion 41. The conductive region 44 may be a part of the conductive film 40 that includes the first wiring portion 41.

[0037] The conductive region 44 has a width greater than that of the first wiring portion 41. That is, as shown in Fig. 4, the width W44 in the second direction D2 of the conductive region 44 is greater than the width W41 in the second direction D2 of the first wiring portion 41. The width W41 is the width of a region of the conductive film 40 that is located at an end of the first unit element region A1 in the second direction D2 and extends in the third direction D3.

[0038] In the first unit element region A1, some of the multiple first trenches T1 extend below the conductive region 44. More specifically, as shown in FIG. 4, some of the multiple first trenches T1 include a first trench portion TR1 and a second trench portion TR2. The first trench portion TR1 is disposed below the second electrode 12 and contacts the third semiconductor region 23 (source region). The second trench portion TR2 extends from the first trench portion TR1 in the second direction D2 and is disposed below the conductive region 44. The length of the first trench T1 extending below the conductive region 44 is the same as the length of the first trench T1 not disposed below the conductive region 44. The second trench portion TR2 extends to the outer periphery of the first unit element region A1. That is, the second trench portion TR2 extends below the end of the conductive region 44 opposite to the first trench portion TR1.

[0039] In this example, some of the multiple first conductive portions 31 include a first portion 31a and a second portion 31b. The first portion 31a is a portion disposed inside the first trench portion TR1. The second portion 31b extends from the first portion 31a in the second direction D2 and is a portion disposed inside the second trench portion TR2.

[0040] The multiple contact portions 72 in the first unit element region A1 electrically connect the multiple first conductive portions 31 in the first unit element region A1 to the first wiring portion 41 and the conductive region 44 in the first unit element region A1. Specifically, in the first unit element region A1, the multiple contact portions 72 include a contact portion 72a and a contact portion 72b. The contact portion 72a is located between the first wiring portion 41 and the first conductive portion 31 in the up-down direction. The contact portion 72b is located between the conductive region 44 and the second portion 31b of the first conductive portion 31 in the up-down direction. The contact portion 72b extends downward from the conductive region 44 and is electrically connected to the second portion 31b.

[0041] FIG. 5 is a schematic cross-sectional view illustrating the semiconductor device according to the first embodiment. 5 shows a cross section taken along line BB shown in FIG. 4. In the first unit element region A1, the first semiconductor portion 61 further includes a fourth semiconductor region 24. The fourth semiconductor region 24 is located below the conductive region 44. The fourth semiconductor region 24 is disposed between the second semiconductor region 22 and the insulating film 55. The fourth semiconductor region 24 is of the second conductivity type. The impurity concentration of the second conductivity type in the fourth semiconductor region 24 is higher than the impurity concentration of the second conductivity type in the second semiconductor region 22. The second portion 31b of the first conductive portion 31 faces a side surface of the fourth semiconductor region 24 via the first insulating film 51.

[0042] 4, a part of the fourth semiconductor region 24 extends below the end of the second electrode 12. For example, the end of the fourth semiconductor region 24 contacts the end in the second direction D2 of some of the contact portions 71. The fourth semiconductor region 24 is aligned with the third semiconductor region 23 in the second direction D2.

[0043] An example of the material of each component of the semiconductor device 100 will be described. The first semiconductor portion 61 (first to fourth semiconductor regions 21 to 24, semiconductor region 28, cell contact) and the second semiconductor portion 62 contain silicon, silicon carbide, gallium nitride, or gallium arsenide as a semiconductor material. When silicon is used as the semiconductor material, arsenic, phosphorus, or antimony can be used as an n-type impurity. Boron can be used as a p-type impurity. The first conductive portion 31 includes a conductive material such as polysilicon, etc. Impurities may be added to the conductive material. The first insulating film 51 and the insulating film 55 contain an insulating material such as silicon oxide or silicon nitride. The first electrode 11, the second electrode 12 (conductive films 12a to 12c), the conductive film 40, and the contact portion 72 are conductive portions containing a metal such as aluminum or copper.

[0044] The operation of the semiconductor device 100 will now be described. With a positive voltage applied to the first electrode 11 relative to the second electrode 12, a voltage equal to or greater than the threshold is applied to the first conductive portion 31. This forms a channel (inversion layer) in the second semiconductor region 22, turning the semiconductor device 100 into an ON state. Electrons flow through the channel from the second electrode 12 to the first electrode 11. Thereafter, when the voltage applied to the first conductive portion 31 becomes lower than the threshold, the channel in the second semiconductor region 22 disappears, turning the semiconductor device 100 into an OFF state.

[0045] For example, in the off state, a positive voltage applied to the first electrode 11 relative to the second electrode 12 causes a depletion layer to expand from the interface between the first semiconductor region 21 and the first insulating film 51 toward the first semiconductor region 21. When the depletion layer expands into the first semiconductor region 21, carriers (electrons and holes) generated by impact ionization or the like are accelerated in the depletion layer, which may cause avalanche breakdown. When avalanche breakdown occurs, electrons are discharged from the first electrode 11 through the semiconductor region 28. Holes are discharged to the second electrode 12 through the contact portion 71.

[0046] A method for manufacturing the semiconductor device 100 will now be described. 6(a) and 6(b) are schematic plan views illustrating the method for manufacturing the semiconductor device according to the first embodiment. 6(a), the manufacturing method of the semiconductor device 100 includes a step of preparing a wafer Wf. A plurality of unit element areas AA and partition areas DA are defined on the wafer Wf. The partition areas DA are areas that can be used as dicing lines, for example.

[0047] The manufacturing method of the semiconductor device 100 further includes a step (dicing step) of cutting a portion of the partitioned area DA to separate the wafer Wf. A dicing blade or the like is used for the cutting. For example, the wafer Wf is cut at the cutting positions P1 shown in FIG. 6(a). That is, every other vertical and horizontal line of the grid-shaped partitioned area DA is set as the cutting position P1. This results in the manufacturing of the semiconductor device 100 with a 2×2 layout shown in FIG. 6(b).

[0048] The cutting position P1 can be changed according to the size information of the semiconductor device to be manufactured. The size information of the semiconductor device includes the number and arrangement of unit element areas AA included in one semiconductor device. That is, in this example, the size information of the semiconductor device indicates a 2×2 layout. More specifically, as shown in FIG. 6(a), the lattice-shaped partitioned area DA includes a plurality of vertical lines L3 (areas extending in the third direction D3) and a plurality of horizontal lines L2 (areas extending in the second direction D2). Depending on the size information of the semiconductor device, at least some of the vertical lines L3 and at least some of the horizontal lines L2 are selected as the cutting positions P1. In the dicing process, the wafer Wf is cut at the selected cutting positions P1.

[0049] For example, the size information of the semiconductor device may be a layout with one unit element area AA. In this case, the cutting positions P1 are all vertical and horizontal lines of the lattice-shaped partitioned area DA. For example, the size information of the semiconductor device may be a 3×3 layout in which three unit element areas AA are arranged vertically and three horizontally. In this case, the cutting positions P1 are every third vertical and horizontal line of the lattice-shaped partitioned area DA. In this way, the cutting positions P1 can be changed as appropriate depending on the number and arrangement of unit element areas AA included in the semiconductor device to be manufactured. Without being limited to the above, the size information of the semiconductor device may be any layout, such as a 2×1 layout (two unit element areas AA vertically and one horizontally).

[0050] 7(a) to 7(h) and 8(a) to 8(e) are schematic cross-sectional views illustrating the steps of a method for manufacturing a semiconductor device according to the first embodiment. These figures show the steps of preparing a wafer Wf. As shown in Fig. 7(a), a substrate is prepared in which a first semiconductor region 21 is formed on a semiconductor region 28.

[0051] As shown in FIG. 7(b), a first trench T1 is formed in the surface of the substrate using photolithography, RIE (Reactive Ion Etching), or the like.

[0052] 7(c), an insulating film is formed on the surface of the substrate by using, for example, thermal oxidation, etc. As a result, a first insulating film 51 is formed on the inner wall of the first trench T1. As shown in FIG. 7(d), a conductive film 31f that will become the first conductive portion 31 is formed inside the first trench T1 and on the surface of the substrate. 7(e), the conductive film 31f is removed from the inside of the first trench T1 using, for example, CDE (Chemical Dry Etching) or RIE, thereby forming the first conductive portion 31.

[0053] As shown in FIG. 7(f), the second semiconductor region 22 is formed by, for example, boron ion implantation. As shown in Figure 7(g), for example, boron ( 11 The fourth semiconductor region 24 is formed by ion implantation of B) or BF2. As shown in FIG. 7(h), the third semiconductor region 23 is formed by ion implantation of, for example, phosphorus or arsenic.

[0054] As shown in FIG. 8(a), a film 55f that will become the insulating film 55 is formed on the substrate by, for example, CVD (chemical vapor deposition). As shown in FIG. 8B, a part of the film 55f is removed by, for example, RIE, to form an insulating film 55. As shown in FIG. 8C, trenches T71 are formed in the third semiconductor region 23 and the second semiconductor region 22 by, for example, RIE, using the insulating film 55 as a mask. As shown in FIG. 8(d), a contact portion 71 is formed at the bottom of the trench T71 formed in FIG. 8(c) by, for example, ion implantation. 8(e), a second electrode 12 is formed on the front surface of the substrate. A conductive film 40 (first wiring portion 41 and conductive region 44) is also formed. Thereafter, a first electrode 11 is formed on the rear surface of the substrate.

[0055] The effects of the first embodiment will be described. In the embodiment, the plurality of unit element regions AA include at least a portion of a common pattern. For example, at least a portion of one of the plurality of unit element regions AA includes a pattern common to at least a portion of another of the plurality of unit element regions AA. In this case, the process of forming the common pattern can be performed regardless of the size information of the semiconductor device. This improves the productivity of the semiconductor device. For example, even when manufacturing semiconductor devices of different sizes, the process of forming the common pattern can be standardized. For example, in the semiconductor device 100 shown in FIG. 1 and other figures, as described above, the pattern of the plurality of first trenches T1, the pattern of the plurality of first conductive portions 31, and the pattern of the second semiconductor region 22 are common to the plurality of unit element regions AA. Therefore, the process of forming the first trenches T1 ( FIG. 7(b) ), the process of forming the first conductive portions 31 ( FIG. 7(e) ), and the process of forming the second semiconductor region 22 ( FIG. 7(f) ) are performed regardless of the size information of the semiconductor device 100. In other words, the processes shown in FIGS. 7(a) to 7(f) can be performed regardless of the size information of the semiconductor device 100.

[0056] For example, in semiconductor devices such as power devices, devices with various chip sizes may be required depending on the desired current value and on-resistance. However, manufacturing devices with various chip sizes can take time. To shorten lead times, many different chip sizes may be kept in stock. In contrast, in this embodiment, minimum unit size chips (unit element areas AA) of a basic size are arranged vertically and horizontally in an integer multiple and treated as a single chip. For example, a single chip has a configuration in which multiple unit element areas are periodically arranged and joined. This allows for commonality up to the intermediate process (in this example, the diffusion process of FIG. 7(f)) and allows wafers that have been manufactured up to that intermediate process to be kept in stock, thereby effectively shortening the manufacturing period. After the intermediate process, each wafer can be treated as a wafer for manufacturing chips of different sizes, for example, by dividing the wafers into lots.

[0057] On the other hand, the positions of the conductive region 44 (gate pad) and the fourth semiconductor region 24 are determined according to information about the size of the semiconductor device (chip size). That is, the unit element region AA (first unit element region A1) in which the conductive region 44 and the fourth semiconductor region 24 are formed is determined according to the information about the size of the semiconductor device. The pattern of the third semiconductor region 23, the pattern of the second electrode 12, the pattern of the multiple contact portions 71, etc. are determined accordingly. Therefore, the process of forming the fourth semiconductor region 24 ( FIG. 7( g) ), the process of forming the third semiconductor region 23 ( FIG. 7( h) ), the process of forming the multiple contact portions 71 ( FIGS. 8( c) and 8( d) ), and the process of forming the second electrode 12 ( FIG. 8( e) ) are performed according to information about the size of the semiconductor device 100. Then, in the process of singulating the wafer, the cutting position can be changed according to the information about the size of the semiconductor device, so that devices of the desired chip size can be manufactured.

[0058] Furthermore, for example, a conductive region 44 is formed in one of the plurality of unit element regions AA (first unit element region A1), and no conductive region 44 is formed in the other unit element regions AA (second to fourth unit element regions A2 to A4). In the other unit element regions AA, the second semiconductor region 22, the third semiconductor region 23, the contact portion 71, etc. are extended to form in the region corresponding to the position of the conductive region 44. This allows the region corresponding to the position of the conductive region 44 to be used as an effective element. The effective area can be expanded, and for example, the on-resistance can be reduced for the same chip area.

[0059] As described above, in the example shown in FIG. 4 and other figures, some of the multiple first trenches T1 in the first unit element region A1 extend below the conductive region 44. That is, some of the first trenches T1 include a first trench portion TR1 arranged below the second electrode 12 and a second trench portion TR2 extending from the first trench T1 in the second direction and arranged below the conductive region 44. This allows the pattern of the multiple first trenches T1 in the first unit element region A1 to be common to the pattern of the multiple first trenches T1 in the other unit element regions AA. This also improves the uniformity of the layout of the multiple first trenches T1.

[0060] Furthermore, since the first trench T1 extends to below the conductive region 44, the pattern of the multiple contact portions 72 in the first unit element region A1 is common to the pattern of the multiple contact portions 72 in the second unit element region A2. This makes it possible to improve, for example, the uniformity of the layout of the multiple contact portions 72.

[0061] Furthermore, in the first unit element region A1, the multiple contact portions 71 are disposed below the second electrode 12, but not below the conductive region 44. In this case, for example, during the avalanche breakdown described above, the potential of the second semiconductor region 22 below the conductive region 44 may rise, potentially causing a malfunction. For example, as described with reference to FIGS. 4 and 5 , if the second portion 31b of the first conductive portion 31 and the first insulating film 51 are disposed inside the second trench portion TR2 below the conductive region 44, the first insulating film 51 may be destroyed. In response to this, the semiconductor device 100 includes a fourth semiconductor region 24. The fourth semiconductor region 24 has a higher concentration of second-conductivity-type impurities than the second semiconductor region 22, and therefore has a lower resistance. This suppresses the rise in potential and prevents the first insulating film 51 from being destroyed.

[0062] (Variation 1) FIG. 9 is a schematic plan view showing a modification of the semiconductor device according to the first embodiment. 9 shows a layout with one unit element area AA. Each semiconductor device 101 includes one unit element area AA. In the manufacturing process of the semiconductor device 101, a conductive region 44 is formed in each of the multiple unit element areas AA. In each unit element area AA, a part of the first trench T1 extends to below the conductive region 44, and a fourth semiconductor region 24 is formed below the conductive region 44.

[0063] Even in this case, the process of forming the plurality of first trenches T1, the process of forming the plurality of first conductive portions 31, and the process of forming the second semiconductor region 22 do not depend on information about the size of the semiconductor device. Therefore, these processes can be the same as the processes in manufacturing the semiconductor device 100.

[0064] (Variation 2) FIG. 10 is a schematic plan view showing a modification of the semiconductor device according to the first embodiment. The semiconductor device 102 differs from the semiconductor device 100 shown in FIG. 1 in the planar shape of the conductive film 40. Specifically, in the semiconductor device 102, the conductive film 40 further includes a portion shown in the vicinity of region R3 in FIG. 10. That is, in each of the plurality of unit element regions AA, the conductive film 40 including the first wiring portion 41 surrounds the second electrode 12. For example, the entire periphery of each second electrode 12 is surrounded by the conductive film 40. This can increase the area of ​​the conductive film 40 and reduce the resistance of the conductive film 40 (e.g., gate wiring resistance).

[0065] (Variation 3) FIG. 11 is a schematic plan view showing a modification of the semiconductor device according to the first embodiment. The semiconductor device 103 differs from the semiconductor device 100 shown in FIG. 1 in the planar shapes of the second electrode 12 and the conductive film 40. Specifically, in the semiconductor device 103, the second electrode 12 in the first unit element region A1 and the second electrode 12 in the second unit element region A2 are formed as a single conductive film 12a and are continuously electrically connected. Compared to the semiconductor device 100, the conductive film 40 is not formed in the partitioned region DA between the first unit element region A1 and the second unit element region A2, and instead a conductive film 12a is formed. Similarly, in the semiconductor device 103, the second electrode 12 in the third unit element region A3 and the second electrode 12 in the fourth unit element region A4 are formed as a single conductive film 12b and are continuously electrically connected. Compared to the semiconductor device 100, the conductive film 40 is not formed in the partitioned region DA between the third unit element region A3 and the fourth unit element region A4, and instead a conductive film 12b is formed. This increases the area of ​​the conductive film that forms the second electrode 12, thereby reducing the resistance of the second electrode 12 (for example, source wiring resistance).

[0066] (Variation 4) FIG. 12 is a schematic plan view illustrating a modification of the semiconductor device according to the first embodiment. The semiconductor device 104 differs from the semiconductor device 100 shown in FIG. 1 in the planar shapes of the second electrodes 12, conductive films 40, and contact portions 72. Specifically, the second electrodes 12 of four unit element areas AA are formed as a single conductive film 12c and are continuously and electrically connected to each other. Compared to the semiconductor device 100, the conductive film 40 is not formed in the partitioned area DA between two adjacent unit element areas AA, and instead a conductive film 12c is formed. This further increases the area of ​​the conductive film forming the second electrodes 12, thereby further reducing the resistance of the second electrodes 12 (e.g., source wiring resistance). Note that no gate contact is arranged below the conductive film 12c. In one unit element area AA, a gate contact is arranged on one side in the second direction D2.

[0067] (Second embodiment) FIG. 13 is a schematic plan view illustrating a semiconductor device according to the second embodiment. The semiconductor device 120 according to the second embodiment differs from the semiconductor device 100 in the configuration near the conductive region 44 of the first unit element region A1 shown in Fig. 14. Other than this, the same explanation as for the semiconductor device 100 can be applied to the configuration of the semiconductor device 120.

[0068] FIG. 14 is a schematic cross-sectional view illustrating a semiconductor device according to the second embodiment. FIG. 14 shows a cross section taken along line CC shown in FIG. 13. As shown in FIGS. 13 and 14, the semiconductor device 120 does not include a fourth semiconductor region 24. In the semiconductor device 120, the second semiconductor region 22 is not disposed below the conductive film 40 including the conductive region 44. The side and bottom surfaces of the second trench portion TR2 disposed below the conductive film 40 are in contact with the first semiconductor region 21. A second insulating film 52 is disposed on the inner wall of the second trench portion TR2, instead of the first insulating film 51 shown in FIG. 5. That is, the second insulating film 52 is disposed between the second portion 31b of the first conductive portion 31 and the first semiconductor region 21. The second portion 31b faces the side surface of the first semiconductor region 21 via the second insulating film 52. The material of the second insulating film 52 may be the same as that of the first insulating film 51.

[0069] 14 is thicker than the thickness T51 (see FIG. 3) of the first insulating film 51. This makes it possible to suppress breakdown of the second insulating film 52, for example, even if the potential of the first semiconductor region 21 rises during an avalanche. By making the second insulating film 52 thicker, it is not necessary to arrange the second semiconductor region 22 and the fourth semiconductor region 24 below the conductive region 44.

[0070] (Third embodiment) FIG. 15 is a schematic plan view illustrating a semiconductor device according to the third embodiment. FIG. 16 is a schematic cross-sectional view illustrating a semiconductor device according to the third embodiment. 16 shows a cross section taken along line DD in FIG. 15. The semiconductor device 130 according to the third embodiment also has first to fourth unit element regions A1 to A4. In the semiconductor device 130, the second to fourth unit element regions A2 to A4 each have the same configuration as the first unit element region A1. The first unit element region A1 of the semiconductor device 130 differs from the first unit element region A1 of the semiconductor device 100 in the configurations of the first trench T1, the first conductive portion 31, and the contact portion 72 below the conductive region 44. Apart from this, the same explanation as for the semiconductor device 100 can be applied to the configuration of the semiconductor device 130.

[0071] 15, in the semiconductor device 130, the multiple first trenches T1 include a trench T11 and a trench T12. The trench T11 is a trench whose end is located below the conductive region 44. The trench T12 is a trench other than the trench T11.

[0072] The trench T11 does not extend to the center of the conductive region 44. The trench T11 is shorter than the trench T12 in the second direction D2. The end of the trench T11 is located below the end of the conductive region 44 on the second electrode 12 side. Therefore, the first conductive portion 31 disposed in the trench T11 does not extend to the center of the conductive region 44. The first conductive portion 31 disposed inside the trench T11 is shorter than the first conductive portion 31 disposed inside the trench T12 in the second direction D2. In addition, the contact portion 72 connecting the first conductive portion 31 in the trench T11 and the conductive region 44 is located below the end of the conductive region 44 on the second electrode 12 side.

[0073] In the semiconductor device 130, the common patterns included in the plurality of unit element areas AA may be the pattern of the third semiconductor region 23, the pattern of the second electrode 12, the pattern of the first wiring portion 41, and the pattern of the conductive region 44.

[0074] For example, the number, positions and shape of the third semiconductor regions 23 in the first unit element region A1 are common to the number, positions and shape of the third semiconductor regions 23 in the second unit element region A2. For example, the number, positions and shape of the second electrodes 12 in the first unit element region A1 are common to the number, positions and shape of the second electrodes 12 in the second unit element region A2. For example, the number, positions and shapes of the first wiring portions 41 in the first unit element region A1 are the same as the number, positions and shapes of the first wiring portions 41 in the second unit element region A2. For example, the number, positions, and shapes of the conductive regions 44 in the first unit element region A1 are the same as the number, positions, and shapes of the conductive regions 44 in the second unit element region A2.

[0075] As described above, in the semiconductor device 130, each unit element area AA includes a first wiring portion 41 and a conductive region 44. In each unit element area AA, the conductive film 40 including the first wiring portion 41 and the conductive region 44 surrounds the second electrode 12. The patterns of the second electrode 12, the first wiring portion 41, and the conductive region 44 are common to multiple unit element areas AA. This allows for commonality of processes up to, for example, the metal process (e.g., the process shown in FIG. 8(e)) even when manufacturing semiconductor devices of different sizes. This further improves productivity. In addition, because unit element areas AA of the same pattern are repeatedly arranged, singular points in the layout are less likely to occur. This makes it less likely that, for example, poor withstand voltage or breakdown will occur at the singular points.

[0076] (Fourth embodiment) FIG. 17 is a schematic plan view illustrating the semiconductor device according to the fourth embodiment. The semiconductor device 140 according to the fourth embodiment is provided with a second conductive portion 32 (field plate (FP)), a contact portion 75 (FP contact), and an insulating film 53 (FP insulating film, see FIG. 18 ) in addition to the semiconductor device 100. Accordingly, in the semiconductor device 140, the contact portion 71 and the first conductive portion 31 are divided in the second direction D2 compared to the semiconductor device 100. Also, as will be described later, the internal configuration of the trench T1 and the arrangement of the contact portion 72 below the conductive region 44 are different from those of the semiconductor device 100. The semiconductor device 140 does not necessarily have to include the fourth semiconductor region 24. Furthermore, in accordance with the above, the arrangements of the second semiconductor region 22 and the third semiconductor region 23 may be changed as appropriate. Otherwise, the same explanation as for the semiconductor device 100 can be applied to the configuration of the semiconductor device 140.

[0077] 17, each unit element area AA includes a plurality of second conductive portions 32 and a plurality of contact portions 75. The plurality of second conductive portions 32 are disposed inside the plurality of first trenches T1. The plurality of second conductive portions 32 are aligned in the third direction D3. The second conductive portions 32 extend in the second direction D2.

[0078] Each of the multiple contact portions 75 is disposed on a corresponding one of the multiple first trenches T1. The contact portion 75 is located in the center of the first trench T1 in the second direction D2. The contact portion 75 is located, for example, between the second electrode 12 and the second conductive portion 32 in the up-down direction, and electrically connects the second electrode 12 and the second conductive portion 32. For example, the contact portion 75 is continuous with the second electrode 12 and extends downward from the second electrode 12 to contact the second conductive portion 32. The contact portion 75 may be part of a conductive film that forms the second electrode 12.

[0079] In each unit element area AA, the multiple contact portions 75 are aligned in the third direction D3. In the center of the unit element area AA where the contact portions 75 are aligned, the first conductive portion 31 and the contact portion 71 are not provided.

[0080] FIG. 18 is a schematic cross-sectional view illustrating the semiconductor device according to the fourth embodiment. Fig. 18 shows a cross section taken along line E-E shown in Fig. 17. As shown in Fig. 18, an insulating film 53 is provided on the inner walls (bottom and inner side surfaces) of the first trench T1. The second conductive portion 32 has a portion that faces the side surface of the first semiconductor region 21 via the insulating film 53. In the first trench T1, the first conductive portion 31 and the first insulating film 51 are provided on the second conductive portion 32 and the insulating film 53. For example, the thickness T53 of the insulating film 53 is thicker than the thickness T51 of the first insulating film 51.

[0081] FIG. 19 is a schematic plan view illustrating a semiconductor device according to the fourth embodiment. 19 shows an enlarged view of the conductive region 44 and its vicinity shown in FIG. 17. The second conductive portion 32 includes a first FP portion 32a and a second FP portion 32b. The first FP portion 32a is a portion disposed inside the first trench portion TR1 disposed below the second electrode 12. The second FP portion 32b extends from the first FP portion 32a in the second direction D2 and is a portion disposed inside the second trench portion TR2 disposed below the conductive region 44. As in FIG. 18, the first conductive portion 31, the second conductive portion 32 (first FP portion 32a), the first insulating film 51, and the insulating film 53 are disposed inside the first trench portion TR1.

[0082] The contact portion 72b is disposed below the end region 44a of the conductive region 44. The end region 44a is the end of the conductive region 44 in the second direction D2 that is closer to the second electrode 12. That is, in this example, the contact portion 72b is not aligned with the contact portion 72a in the third direction D3. The first conductive portion 31 connected to the contact portion 72b is shorter than the first conductive portion 31 connected to the contact portion 72a. The second semiconductor region 22 extends from below the second electrode 12 to below the end region 44a. In order to increase the breakdown voltage in the FP structure, for example, the second semiconductor region 22 (base layer) is positioned inside the trench tip and outside the contact 72a.

[0083] FIG. 20 is a schematic cross-sectional view illustrating a semiconductor device according to the fourth embodiment. 20 shows a cross section taken along line FF shown in FIG. 19. The first conductive portion 31 and the first insulating film 51 are not provided in the second trench portion TR2 below the conductive region 44. The second trench portion TR2 is provided with the second FP portion 32b of the second conductive portion 32 and an insulating film 53. In this example, unlike the example of FIG. 5, the second semiconductor region 22 and the fourth semiconductor region 24 are not provided below the conductive region 44. However, similar to the example of FIG. 5, the second semiconductor region 22 and the fourth semiconductor region 24 may also be disposed below the conductive region 44.

[0084] The material of the second conductive portion 32 may be the same as that of the first conductive portion 31. The material of the insulating film 53 may be the same as that of the first insulating film 51.

[0085] By providing the second conductive portion 32, for example, the depletion layer can easily spread to the first semiconductor region 21, the electric field can be alleviated, and the breakdown voltage of the semiconductor device 140 can be increased. Furthermore, as described above, the first conductive portion 31 is not arranged in the second trench portion TR2 below the conductive region 44, and the second FP portion 32b is arranged therein. Therefore, the first insulating film 51 is not arranged in the second trench portion TR2, and the insulating film 53 is arranged therein. This makes it possible to prevent the first insulating film 51 from breaking down below the conductive region 44 during avalanche breakdown.

[0086] (Fifth embodiment) FIG. 21 is a schematic plan view illustrating a semiconductor device according to the fifth embodiment. The semiconductor device 150 shown in FIG. 21 differs from the semiconductor device 104 shown in FIG. 12 in the configuration of the conductive film 40 and the partitioned region DA. In this example, a transistor is provided in the partitioned region DA. The multiple second electrodes 12 are formed as a single conductive film 12c and are continuously and electrically connected to each other. The conductive film 40 including the first wiring portion 41 and the conductive region 44 is provided so as to surround the outer periphery (e.g., the entire periphery) of the conductive film 12c. Otherwise, the same explanation as for the semiconductor device 104 can be applied to the configuration of the semiconductor device 150.

[0087] FIG. 22 is a schematic cross-sectional view illustrating a semiconductor device according to the fifth embodiment. Fig. 22 shows a cross section taken along line GG in Fig. 21. As shown in Fig. 22, the second semiconductor portion 62 in the partitioned region DA is provided on the first electrode 11. Furthermore, the partitioned region DA is provided with a transistor similar to that in the unit element region AA. That is, the second semiconductor portion 62 includes a fifth semiconductor region 25 (drift region), a sixth semiconductor region 26 (base region), a plurality of seventh semiconductor regions 27 (source regions), a plurality of second trenches T2, and a plurality of contact portions 73. The partitioned region DA includes a plurality of third conductive portions 33 (gate electrodes), a plurality of insulating films 54 (gate insulating films), and a third electrode 13 (source electrode).

[0088] The fifth semiconductor region 25 is provided on the first electrode 11 via a semiconductor region 29. The fifth semiconductor region 25 and the semiconductor region 29 are of the first conductivity type. The impurity concentration of the first conductivity type in the fifth semiconductor region 25 is lower than the impurity concentration of the first conductivity type in the semiconductor region 29. The sixth semiconductor region 26 is provided on a part of the fifth semiconductor region 25. The sixth semiconductor region 26 is of the second conductivity type. The seventh semiconductor region 27 is provided on a part of the sixth semiconductor region 26. The seventh semiconductor region 27 is of the first conductivity type. The impurity concentration of the first conductivity type in the seventh semiconductor region 27 is higher than the impurity concentration of the first conductivity type in the fifth semiconductor region 25.

[0089] The semiconductor region 29 and the fifth semiconductor region 25 in the partitioned region DA may be part of the same semiconductor layer that is continuous with the semiconductor region 28 and the first semiconductor region 21 in the unit element region AA, respectively. On the other hand, the sixth semiconductor region 26 does not have to be continuous with the second semiconductor region 22. In other words, a semiconductor region of the first conductivity type (for example, part of the first semiconductor region 21 or the fifth semiconductor region 25) may be disposed between the sixth semiconductor region 26 and the second semiconductor region 22. However, the sixth semiconductor region 26 and the second semiconductor region 22 may be continuous.

[0090] The plurality of contact portions 73 are provided on a portion of the sixth semiconductor region 26. More specifically, the contact portions 73 are provided on the bottoms of trenches T73 provided in the sixth semiconductor region 26 and the seventh semiconductor region 27. The contact portions 73 are of the second conductivity type. The impurity concentration of the second conductivity type in the contact portions 73 is higher than the impurity concentration of the second conductivity type in the sixth semiconductor region 26. The third conductive portion 33 is provided on a portion of the fifth semiconductor region 25. The third conductive portion 33 has a portion facing a side surface of the sixth semiconductor region 26 via an insulating film 54. The second trench T2 is provided in the second semiconductor portion 62 and extends along the surface of the second semiconductor portion 62. The insulating film 54 is provided on the inner wall of the second trench T2. Each of the plurality of third conductive portions 33 is disposed inside each of the plurality of second trenches T2. The material of the insulating film 54 may be the same as that of the first insulating film 51.

[0091] The third electrode 13 is provided on the third conductive portion 33, the sixth semiconductor region 26, and the seventh semiconductor region 27. The third electrode 13 is electrically connected to the sixth semiconductor region 26 and the seventh semiconductor region 27. The contact portion 73 is provided between the third electrode 13 and the sixth semiconductor region 26 and is in contact with the third electrode 13 and the sixth semiconductor region 26. The contact portion 73 electrically connects the third electrode 13 to the sixth semiconductor region 26. An insulating film 55 is provided between the third conductive portion 33 and the third electrode 13. The third electrode 13 is continuous with the second electrode 12 in the unit element area AA and is electrically connected to the second electrode 12. The third electrode 13 may be a part of the conductive film 12c including the second electrode 12.

[0092] The areas between adjacent unit element areas AA (each of areas d1 to d4) may have the same configuration as that shown in Fig. 22. However, the second trenches T2, the third conductive portions 33, the contact portions 73 (trench T73), and the seventh semiconductor regions 27 extend along the peripheries (sides) of adjacent unit element areas AA. Specifically, as shown in Fig. 21, for example, in the partitioned area DA, between the first unit element area A1 and the second unit element area A2 (area d1) and between the third unit element area A3 and the fourth unit element area A4 (area d2), the second trenches T2, the third conductive portions 33, and the contact portions 73 extend in the second direction D2. For example, in the partitioned region DA, between the first unit element region A1 and the third unit element region A3 (region d3) and between the second unit element region A2 and the fourth unit element region A4 (region d4), the second trench T2, the third conductive portion 33, and the contact portion 73 extend in the third direction D3. The second trench T2, the third conductive portion 33, and the contact portion 73 do not need to be provided at the lattice intersections C1 of the partitioned region DA (adjacent to the corners of the four unit element regions AA, between the region d1 and the region d2, and between the region d3 and the region d4).

[0093] 21 , the partitioned region DA further includes a plurality of contact portions 74 (gate contacts) and a second wiring portion 42 (gate wiring). The second wiring portion 42 is provided on the second semiconductor portion 62. The second wiring portion 42 is part of the conductive film 40 that includes the first wiring portion 41, and is continuous with the first wiring portion 41. Each of the plurality of third conductive portions 33 is electrically connected to the second wiring portion 42 via each of the plurality of contact portions 74.

[0094] The first wiring portion 41 and the second wiring portion 42 (and the conductive region 44) are located on the outer periphery of the plurality of unit element areas AA and the partitioned areas DA. The conductive film 40 (the first wiring portion 41, the second wiring portion 42, and the conductive region 44) surrounds the conductive film 12c (the second electrode 12 and the third electrode 13).

[0095] A contact portion 74 is provided on one end of each third conductive portion 33 in the extension direction. For example, the contact portion 74 extends downward continuously from the conductive film 40 including the second wiring portion 42. The contact portion 74 may be a part of the conductive film 40. For example, the contact portion 74 penetrates the insulating film 55 on the third conductive portion 33 and contacts the third conductive portion 33. In this way, the contact portion 74 electrically connects the third conductive portion 33 to the second wiring portion 42. The contact portions 74 provided in the first region d1 and the second region d2 are aligned with the multiple contact portions 72 in the third direction D3.

[0096] In this way, elements (transistors) are also provided in the divided regions DA in the semiconductor device 150. This allows the divided regions DA to be used effectively, and the ineffective area can be reduced. The first wiring portion 41 and the second wiring portion 42 are located on the periphery of the plurality of unit element areas AA and the partitioned areas DA, which makes it easy to form contacts to the elements in the partitioned areas DA. Furthermore, the second trenches T2, the third conductive portions 33, and the contact portions 73 extend along the peripheries of the adjacent unit element areas AA. The second trenches T2, the third conductive portions 33, and the contact portions 73 are not provided at the intersections of the lattice-shaped partitioned areas DA. As a result, even if the size of the semiconductor device to be manufactured is changed and the partitioned areas DA shown in FIG. 21 are selected as the cutting positions, the cutting direction and the second trenches T2 are not perpendicular to each other. This improves the stability of cutting.

[0097] (Variation 5) FIG. 23 is a schematic plan view illustrating a modification of the semiconductor device according to the fifth embodiment. 23 illustrates a wafer Wf before a dicing process. The wafer Wf is provided with a plurality of unit element regions AA and partition regions DA that will become semiconductor devices 151. One semiconductor device 151 includes one unit element region AA. The semiconductor device 151 is manufactured by cutting the partition regions DA at cutting positions P1 shown in FIG.

[0098] Each unit element region AA is similar to the unit element region AA of the semiconductor device 101 shown in FIG. 9, for example. That is, a conductive region 44 is provided in each unit element region AA. Furthermore, a second trench T2 is provided in the partitioned region DA, similar to the semiconductor device 150. The second trench T2 extends along the cutting position P1. In the semiconductor device 151 having one unit element region AA, the contact portion 73 and the contact portion 74 do not need to be provided in the partitioned region DA.

[0099] (Sixth embodiment) FIG. 24 is a schematic plan view illustrating a semiconductor device according to the sixth embodiment. The semiconductor device 160 shown in FIG. 24 differs from the semiconductor device 104 shown in FIG. 12 in the configuration of the partitioned region DA. In this example, a pn junction diode is provided in the partitioned region DA. The multiple second electrodes 12 are formed as a single conductive film 12c and are continuously and electrically connected to each other. Other than this, the same explanation as for the semiconductor device 104 can be applied to the configuration of the semiconductor device 160.

[0100] FIG. 25 is a schematic cross-sectional view illustrating a semiconductor device according to the sixth embodiment. Figure 25 shows a cross section taken along line HH in Figure 24. As shown in Figure 25, the second semiconductor portion 62 in the partitioned region DA is provided on the first electrode 11. The second semiconductor portion 62 includes a semiconductor region 29 (cathode region), a fifth semiconductor region 25 (drift region), a sixth semiconductor region 26 (anode region), and a plurality of contact portions 76. The partitioned region DA includes a third electrode 13 (anode electrode).

[0101] The fifth semiconductor region 25 is provided on the first electrode 11 via a semiconductor region 29. The fifth semiconductor region 25 and the semiconductor region 29 are of the first conductivity type. The impurity concentration of the first conductivity type in the fifth semiconductor region 25 is lower than the impurity concentration of the first conductivity type in the semiconductor region 29. The sixth semiconductor region 26 is provided on a part of the fifth semiconductor region 25. The sixth semiconductor region 26 is of the second conductivity type.

[0102] The semiconductor region 29 and the fifth semiconductor region 25 in the partitioned region DA may be part of the same semiconductor layer that is continuous with the semiconductor region 28 and the first semiconductor region 21 in the unit element region AA, respectively. On the other hand, the sixth semiconductor region 26 does not have to be continuous with the second semiconductor region 22. In other words, a semiconductor region of the first conductivity type (for example, part of the first semiconductor region 21 or the fifth semiconductor region 25) may be disposed between the sixth semiconductor region 26 and the second semiconductor region 22.

[0103] The plurality of contact portions 76 are provided on a portion of the sixth semiconductor region 26. More specifically, the contact portions 76 are provided at the bottom of trenches T76 provided in the sixth semiconductor region 26. The contact portions 76 are of the second conductivity type. The impurity concentration of the second conductivity type in the contact portions 76 is higher than the impurity concentration of the second conductivity type in the sixth semiconductor region 26.

[0104] The third electrode 13 is provided on the sixth semiconductor region 26 and is electrically connected to the sixth semiconductor region 26. The contact portion 76 is provided between the third electrode 13 and the sixth semiconductor region 26 and is in contact with the third electrode 13 and the sixth semiconductor region 26. The contact portion 76 electrically connects the third electrode 13 to the sixth semiconductor region 26. For example, the contact portion 76 is in ohmic contact with the third electrode 13. An insulating film 55 is provided between the sixth semiconductor region 26 and the third electrode 13. The third electrode 13 is continuous with the second electrode 12 in the unit element region AA and is electrically connected to the second electrode 12. The third electrode 13 may be a part of the conductive film 12c including the second electrode 12.

[0105] The sections between adjacent unit element regions AA (each of the regions d1 to d4) may have the same configuration as that shown in FIG. 25. However, the multiple contact portions 76 (trench T76) extend along the peripheries (sides) of adjacent unit element regions AA. Specifically, as shown in FIG. 24, for example, in the partitioned region DA, the contact portions 76 extend in the second direction D2 between the first unit element region A1 and the second unit element region A2 (region d1) and between the third unit element region A3 and the fourth unit element region A4 (region d2). For example, in the partitioned region DA, the contact portions 76 extend in the third direction D3 between the first unit element region A1 and the third unit element region A3 (region d3) and between the second unit element region A2 and the fourth unit element region A4 (region d4). The contact portions 76 do not need to be provided at the lattice intersections C1 of the partitioned region DA.

[0106] When the potential of the third electrode 13 is higher than that of the first electrode 11, the pn junction between the fifth semiconductor region 25 and the sixth semiconductor region 26 is forward biased, allowing current to flow from the third electrode 13 to the first electrode 11. Conversely, when the potential of the first electrode 11 is higher than that of the third electrode 13, the pn junction between the fifth semiconductor region 25 and the sixth semiconductor region 26 is reverse biased, suppressing the flow of current. The diode formed in the partitioned region DA functions as a body diode connected in parallel to the transistor formed in the unit element region AA.

[0107] In this way, in the semiconductor device 160, an element (pn junction diode) is also provided in the partitioned region DA. This allows the partitioned region DA to be used effectively, and the ineffective area can be reduced. Also, for example, the area of ​​the pn junction can be increased to increase the area of ​​the diode. This allows, for example, to reduce the forward voltage Vf of the diode.

[0108] (Variation 6) FIG. 26 is a schematic plan view illustrating a modification of the semiconductor device according to the sixth embodiment. 26 differs from the semiconductor device 160 shown in FIG. 24 in the configuration of the partitioned region DA. In this example, a Schottky barrier diode is provided in the partitioned region DA instead of a pn junction diode. Other than this, the same explanation as for the semiconductor device 160 can be applied to the configuration of the semiconductor device 161.

[0109] FIG. 27 is a schematic cross-sectional view showing a modification of the semiconductor device according to the sixth embodiment. Fig. 27 shows a cross section taken along line II in Fig. 26. As shown in Fig. 27, the second semiconductor portion 62 in the partitioned region DA is provided on the first electrode 11. The second semiconductor portion 62 includes a semiconductor region 29 (cathode region) and a fifth semiconductor region 25. The partitioned region DA includes a plurality of contact portions 77 and a third electrode 13.

[0110] The fifth semiconductor region 25 is provided on the first electrode 11 via a semiconductor region 29. The fifth semiconductor region 25 and the semiconductor region 29 are of the first conductivity type. The third electrode 13 is provided on the fifth semiconductor region 25 and is electrically connected to the fifth semiconductor region 25 via a contact portion 77. The third electrode 13 is continuous with the second electrode 12 in the unit element area AA and is electrically connected to the second electrode 12. The third electrode 13 may be a part of the conductive film 12c including the second electrode 12. An insulating film 55 is arranged between the fifth semiconductor region 25 and the third electrode 13.

[0111] The contact portion 77 is provided on the fifth semiconductor region 25 and is in Schottky contact with the fifth semiconductor region 25. For example, the contact portion 77 is a conductor that is continuous with the third electrode 13, extends downward from the third electrode 13, and contacts the fifth semiconductor region 25. The contact portion 77 may be a part of the conductive film 12c that includes the third electrode 13. The contact portion 77 penetrates the insulating film 55 and is in contact with the fifth semiconductor region 25. In this way, the contact portion 77 forms a Schottky junction with the fifth semiconductor region 25 and electrically connects the fifth semiconductor region 25 to the third electrode 13.

[0112] The spaces between adjacent unit element areas AA (each of areas d1 to d4) may have the same configuration as in Fig. 27. However, the multiple contact portions 77 extend along the peripheries (sides) of the adjacent unit element areas AA. The contact portions 77 do not need to be provided at the intersections C1 of the grid pattern of the divided areas DA.

[0113] When the potential of the third electrode 13 is higher than that of the first electrode 11, the Schottky junction between the conductive film 12c and the fifth semiconductor region 25 is forward biased, allowing current to flow from the third electrode 13 to the first electrode 11. Conversely, when the potential of the first electrode 11 is higher than that of the third electrode 13, the Schottky junction is reverse biased, and the flow of current is suppressed by the Schottky barrier. It functions as a body diode connected in parallel with the transistor formed in region AA.

[0114] In this way, in the semiconductor device 160, an element (Schottky diode) is also provided in the partitioned region DA. This allows the partitioned region DA to be used effectively, and the ineffective area can be reduced. When a Schottky barrier diode is formed, the forward voltage Vf of the diode is easier to reduce than in the case of a pn junction diode. Furthermore, for example, since a Schottky diode is a unipolar device, it is easier to shorten the reverse recovery time during switching than in the case of a bipolar device.

[0115] According to the embodiment, it is possible to provide a semiconductor device that allows for improved productivity.

[0116] In each of the embodiments described above, the relative level of the impurity concentration between each semiconductor region can be confirmed using, for example, a scanning capacitance microscope (SCM). Note that the carrier concentration in each semiconductor region can be considered to be equal to the concentration of activated impurities in each semiconductor region. Therefore, the relative level of the carrier concentration between each semiconductor region can also be confirmed using an SCM. Furthermore, the impurity concentration in each semiconductor region can be measured using, for example, SIMS (secondary ion mass spectrometry).

[0117] In this specification, "electrically connected" includes not only connection through direct contact but also connection via other conductive members. In this specification, "perpendicular" does not only mean strictly perpendicular, but also includes, for example, variations in the manufacturing process, and it is sufficient if the perpendicular is substantially perpendicular.

[0118] Although several embodiments of the present invention have been described above, these embodiments are presented by way of example only and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, modifications, etc. can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, as well as within the scope of the invention and its equivalents as set forth in the claims. Furthermore, the above-described embodiments can be implemented in combination with each other. [Explanation of symbols]

[0119] 11 first electrode, 12 second electrode, 12a to 12c conductive film, 13 third electrode, 21 to 27 first to seventh semiconductor regions, 28, 29 semiconductor region, 31 first conductive portion, 31a first portion, 31b second portion, 31f conductive film, 32 second conductive portion, 32a first FP portion, 32b second FP portion, 33 third conductive portion, 40 conductive film, 41 first wiring portion, 42 second wiring portion, 44 conductive region, 44a end region, 51 first insulating film, 52 second insulating film, 53 to 55 insulating films, 61 first semiconductor portion, 62 second semiconductor portion, 71 to 77 contact portions, 100 to 104, 120, 130, 140, 150, 151, 160, 161 Semiconductor device, A1 to A4 first to fourth unit element regions, AA unit element region, d1 to d4 regions, DA partition region, L2 horizontal line, L3 vertical line, P1 cutting position, T1 first trench, T11, T12 trenches, T2 second trench, T71, T73, T76 trenches, TR1 first trench portion, TR2 second trench portion, Wf wafer

Claims

1. A first electrode; A plurality of unit element regions, each of which comprises: a first semiconductor portion including a first semiconductor region of a first conductivity type provided on the first electrode, a second semiconductor region of a second conductivity type provided on the first semiconductor region, and a third semiconductor region of the first conductivity type provided on the second semiconductor region; a second electrode provided on the second semiconductor region and the third semiconductor region and electrically connected to the second semiconductor region and the third semiconductor region; a first conductive portion facing the second semiconductor region via a first insulating film; a plurality of unit element regions each including at least a portion of a common pattern; a partition region including a second semiconductor portion continuous with the first semiconductor portion and partitioning the plurality of unit element regions; Equipped with each of the plurality of unit element regions includes a plurality of first trenches provided in the first semiconductor portion and extending in an extension direction along a surface of the first semiconductor portion, and a first wiring portion provided on the first semiconductor portion; In each of the plurality of unit element regions, a plurality of the first conductive portions are provided, the first conductive portions are disposed inside the plurality of first trenches, and are electrically connected to the first wiring portion; a first unit element region among the plurality of unit element regions includes a conductive region that is provided on the first semiconductor portion, is electrically connected to the first wiring portion, and has a width wider than that of the first wiring portion; some of the plurality of first trenches include a first trench portion disposed below the second electrode and a second trench portion extending from the first trench portion in an extension direction and disposed below the conductive region; each of the plurality of unit element regions includes a plurality of second conductive portions disposed inside the plurality of first trenches; the plurality of first conductive portions of the first unit element region are not disposed in the second trench portion, a portion of the plurality of second conductive portions of the first unit element region including a portion disposed in the first trench portion and a portion disposed in the second trench portion;

2. 2. The semiconductor device according to claim 1, wherein the common pattern is at least one of a pattern of the first conductive portion, a pattern of the second semiconductor region, and a pattern of the second electrode.

3. the first unit element region includes a plurality of contact portions that electrically connect the plurality of first conductive portions of the first unit element region to the first wiring portion and the conductive regions of the first unit element region, a second unit element region among the plurality of unit element regions includes a plurality of contact portions that electrically connect the plurality of first conductive portions of the second unit element region to the first wiring portion of the second unit element region; 3. The semiconductor device according to claim 1, wherein a pattern of the plurality of contact parts in the first unit element region is common to a pattern of the plurality of contact parts in the second unit element region.

4. each of the plurality of unit element regions includes the conductive region; In each of the plurality of unit element regions, a conductive film including the first wiring portion and the conductive region surrounds the second electrode, 4. The semiconductor device according to claim 1, wherein the common pattern is a pattern of the conductive region.

5. A first electrode; A plurality of unit element regions, each of which comprises: a first semiconductor portion including a first semiconductor region of a first conductivity type provided on the first electrode, a second semiconductor region of a second conductivity type provided on the first semiconductor region, and a third semiconductor region of the first conductivity type provided on the second semiconductor region; a second electrode provided on the second semiconductor region and the third semiconductor region and electrically connected to the second semiconductor region and the third semiconductor region; a first conductive portion facing the second semiconductor region via a first insulating film; a plurality of unit element regions each including at least a portion of a common pattern; a partition region including a second semiconductor portion continuous with the first semiconductor portion and partitioning the plurality of unit element regions; Equipped with a first unit element region among the plurality of unit element regions includes: a first wiring portion provided on the first semiconductor portion and electrically connected to the first conductive portion; and a conductive region provided on the first semiconductor portion and electrically connected to the first wiring portion, the conductive region having a width wider than that of the first wiring portion; a conductive film including the first wiring portion and the conductive region surrounds the second electrode; a second unit element region of the plurality of unit element regions includes the first wiring portion and does not include the conductive region;

6. A first electrode; A plurality of unit element regions, each of which comprises: a first semiconductor portion including a first semiconductor region of a first conductivity type provided on the first electrode, a second semiconductor region of a second conductivity type provided on the first semiconductor region, and a third semiconductor region of the first conductivity type provided on the second semiconductor region; a second electrode provided on the second semiconductor region and the third semiconductor region and electrically connected to the second semiconductor region and the third semiconductor region; a first conductive portion facing the second semiconductor region via a first insulating film; a plurality of unit element regions each including at least a portion of a common pattern; a partition region including a second semiconductor portion continuous with the first semiconductor portion and partitioning the plurality of unit element regions; Equipped with each of the plurality of unit element regions includes: a first wiring portion provided on the first semiconductor portion and electrically connected to the first conductive portion; and a conductive region provided on the first semiconductor portion and electrically connected to the first wiring portion, the conductive region having a width wider than that of the first wiring portion; In each of the plurality of unit element regions, a conductive film including the first wiring portion and the conductive region surrounds the second electrode, In each of the plurality of unit element regions, the conductive regions are located in a common direction with respect to the second electrode in a plane parallel to the second electrode, The common pattern is a pattern of the conductive region.

7. each of the plurality of unit element regions includes a plurality of first trenches provided in the first semiconductor portion and extending in an extension direction along a surface of the first semiconductor portion; In each of the plurality of unit element regions, a plurality of the first conductive portions are provided, the first conductive portions are disposed inside the plurality of first trenches, and are electrically connected to the first wiring portion; some of the plurality of first trenches in a first unit element region among the plurality of unit element regions include a first trench portion arranged below the second electrode and a second trench portion extending from the first trench portion in an extension direction and arranged below the conductive region; 7. The semiconductor device according to claim 5, wherein the second trench portion and the conductive region are connected at an end of the second trench portion opposite to the first trench portion.

8. In the first unit element region, the first semiconductor portion includes a fourth semiconductor region disposed below the conductive region, the fourth semiconductor region having a higher impurity concentration of the second conductivity type than a higher impurity concentration of the second conductivity type in the second semiconductor region; 8. The semiconductor device according to claim 7, wherein a portion of the plurality of first conductive portions of the first unit element region includes a first portion arranged in the first trench portion, and a second portion extending from the first portion in the extension direction and arranged in the second trench portion.

9. some of the plurality of first conductive portions of the first unit element region include a first portion disposed in the first trench portion and a second portion extending from the first portion in the extension direction and disposed in the second trench portion; the first unit element region includes a second insulating film provided between the second portion and the first semiconductor region; 8. The semiconductor device according to claim 7, wherein the second insulating film has a thickness greater than that of the first insulating film.

10. A first electrode; A plurality of unit element regions, each of which comprises: a first semiconductor portion including a first semiconductor region of a first conductivity type provided on the first electrode, a second semiconductor region of a second conductivity type provided on the first semiconductor region, and a third semiconductor region of the first conductivity type provided on the second semiconductor region; a second electrode provided on the second semiconductor region and the third semiconductor region and electrically connected to the second semiconductor region and the third semiconductor region; a first conductive portion facing the second semiconductor region via a first insulating film; a plurality of unit element regions each including at least a portion of a common pattern; a partition region including a second semiconductor portion continuous with the first semiconductor portion and partitioning the plurality of unit element regions; Equipped with the partitioned region has a third electrode continuous with the second electrode, the plurality of unit element regions include a first unit element region and a second unit element region, the first unit element region and the second unit element region are spaced apart from each other in a first direction in a plane parallel to the second electrode; the third electrode extends in a second direction intersecting the first direction between the first unit element region and the second unit element region in the plane.

11. the second semiconductor portion of the partition region includes a fifth semiconductor region of a first conductivity type provided on the first electrode, a sixth semiconductor region of a second conductivity type provided on the fifth semiconductor region, and a seventh semiconductor region of the first conductivity type provided on the sixth semiconductor region, The partitioned area is a second trench provided in the second semiconductor portion; a third conductive portion that is disposed inside the second trench and has a portion that faces a side surface of the sixth semiconductor region via an insulating film; The semiconductor device according to claim 10 , wherein the third electrode is provided on the sixth semiconductor region and the seventh semiconductor region and is electrically connected to the sixth semiconductor region and the seventh semiconductor region.

12. each of the plurality of unit element regions includes a first wiring portion provided on the first semiconductor portion and electrically connected to the first conductive portion; the partitioned region includes a second wiring portion provided on the second semiconductor portion, electrically connected to the third conductive portion, and continuous with the first wiring portion; The semiconductor device according to claim 11 , wherein the first wiring portion and the second wiring portion are located on the outer periphery of the plurality of unit element regions and the partitioned region.

13. the second semiconductor portion of the partition region includes a fifth semiconductor region of a first conductivity type provided on the first electrode, and a sixth semiconductor region of a second conductivity type provided on the fifth semiconductor region; The semiconductor device according to claim 10 , wherein the third electrode is provided on the sixth semiconductor region and is electrically connected to the sixth semiconductor region.

14. the second semiconductor portion of the partition region includes a fifth semiconductor region of the first conductivity type provided on the first electrode; the third electrode is provided on the fifth semiconductor region and is electrically connected to the fifth semiconductor region; The semiconductor device according to claim 10 , wherein the partitioned region includes a contact portion that forms a Schottky junction with the fifth semiconductor region and electrically connects the fifth semiconductor region to the third electrode.

15. Each of the plurality of unit element regions includes a plurality of first trenches provided in the first semiconductor portion and extending in an extension direction along a surface of the first semiconductor portion, and a first wiring portion provided on the first semiconductor portion; In each of the plurality of unit element regions, a plurality of the first conductive portions are provided, the first conductive portions are disposed inside the plurality of first trenches, and are electrically connected to the first wiring portion; the first unit element region includes a conductive region that is provided on the first semiconductor portion, is electrically connected to the first wiring portion, and has a width wider than that of the first wiring portion; some of the plurality of first trenches include a first trench portion disposed below the second electrode and a second trench portion extending from the first trench portion in an extension direction and disposed below the conductive region; 15. The semiconductor device according to claim 10, wherein the second trench portion and the conductive region are connected at an end of the second trench portion opposite to the first trench portion.

16. a semiconductor device including a first electrode and at least one unit element region, the unit element region including: a first semiconductor portion including a first semiconductor region of a first conductivity type provided on the first electrode, a second semiconductor region of a second conductivity type provided on the first semiconductor region, and a third semiconductor region of the first conductivity type provided on the second semiconductor region; a second electrode provided on the second semiconductor region and the third semiconductor region and electrically connected to the second semiconductor region and the third semiconductor region; and a first conductive portion including a portion facing the second semiconductor region via an insulating film, a wafer in which a plurality of unit element regions and partition regions that partition the plurality of unit element regions are set, a first unit element region among the plurality of unit element regions includes: a first wiring portion provided on the first semiconductor portion and electrically connected to the first conductive portion; and a conductive region provided on the first semiconductor portion and electrically connected to the first wiring portion, the conductive region having a width wider than that of the first wiring portion; a conductive film including the first wiring portion and the conductive region surrounds the second electrode; a second unit element region among the plurality of unit element regions includes the first wiring portion but does not include the conductive region; providing a wafer; cutting a part of the partitioned regions at cutting positions that can be changed depending on the number and arrangement of the unit element regions included in the semiconductor device to separate the wafer; A manufacturing method comprising:

17. A method for manufacturing a semiconductor device comprising: a first electrode; and at least one unit element region, wherein the unit element region comprises: a first semiconductor portion including a first semiconductor region of a first conductivity type provided on the first electrode, a second semiconductor region of a second conductivity type provided on the first semiconductor region, and a third semiconductor region of the first conductivity type provided on the second semiconductor region; a second electrode provided on the second semiconductor region and the third semiconductor region and electrically connected to the second semiconductor region and the third semiconductor region; and a first conductive portion including a portion facing the second semiconductor region via an insulating film, a wafer in which a plurality of unit element regions and partition regions that partition the plurality of unit element regions are set, each of the plurality of unit element regions includes: a first wiring portion provided on the first semiconductor portion and electrically connected to the first conductive portion; and a conductive region provided on the first semiconductor portion and electrically connected to the first wiring portion, the conductive region having a width wider than that of the first wiring portion; In each of the plurality of unit element regions, a conductive film including the first wiring portion and the conductive region surrounds the second electrode, In each of the plurality of unit element regions, the conductive regions are located in a common direction with respect to the second electrode in a plane parallel to the second electrode, the conductive region has a common pattern among the plurality of unit element regions; providing a wafer; cutting a part of the partitioned regions at cutting positions that can be changed depending on the number and arrangement of the unit element regions included in the semiconductor device to separate the wafer; A manufacturing method comprising:

Images