Exposure apparatus and semiconductor device manufacturing method

Abstract

To improve a yield of a semiconductor device.SOLUTION: An exposure device in an embodiment includes a stage 140, a measurement device 144, and a control device 10. The control device 10 calculates each of a first correction coefficient corresponding to positional deviation of a magnification component in a first direction and a second correction coefficient corresponding to positional deviation of a magnification component in a second direction, on the basis of a measurement result of at least three parts of alignment marks, in substrate exposure processing. The control device 10 uses the first correction coefficient for correction of the positional deviation of the magnification component in the first direction, and uses a third correction coefficient on the basis of the first correction coefficient for correction of the positional deviation of the magnification component in the second direction when first setting is applied. The control device 10 uses a fourth correction coefficient on the basis of the second correction coefficient for correction of the positional deviation of the magnification component in the first direction, and uses the second correction coefficient for correction of the positional deviation of the magnification component in the second direction when second setting is applied.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The embodiment is an exposure apparatus , and The present invention relates to a method for manufacturing a semiconductor device. [Background technology]

[0002] Three-dimensional stacking technology is known for stacking semiconductor circuit boards in three dimensions. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2021-150533 Summary of the Invention [Problem to be solved by the invention]

[0004] To improve the yield of semiconductor devices. [Means for solving the problem]

[0005] An exposure apparatus according to an embodiment exposes a substrate with illumination light via a projection optical system. The exposure apparatus includes a stage, a measurement device, and a control device. The stage holds the substrate. The measurement device measures alignment marks on the substrate in at least three locations. The control device moves the stage based on measurement results from the measurement device to control the exposure position relative to the substrate. During exposure processing of the substrate, the control device calculates a first correction coefficient corresponding to a positional deviation of a magnification component in a first direction and a second correction coefficient corresponding to a positional deviation of a magnification component in a second direction intersecting with the first direction, based on measurement results of the alignment marks in at least three locations. When a first setting is applied, the control device uses the first correction coefficient to correct the positional deviation of the magnification component in the first direction, and a third correction coefficient based on the first correction coefficient to correct the positional deviation of the magnification component in the second direction. When a second setting is applied, the control device uses a fourth correction coefficient based on the second correction coefficient to correct the positional deviation of the magnification component in the first direction, and the second correction coefficient to correct the positional deviation of the magnification component in the second direction. [Brief explanation of the drawings]

[0006] [Figure 1] 1A to 1C are schematic diagrams illustrating an outline of a method for manufacturing a semiconductor device. [Figure 2] 1A and 1B are schematic diagrams showing an example of an overlay misalignment component that may occur in the manufacturing process of a semiconductor device. [Figure 3] FIG. 1 is a schematic diagram showing an example of the arrangement of alignment marks used in the manufacturing process of a semiconductor device. [Figure 4] 10 is a table showing an example of the correction performance of an overlay misalignment component within a wafer surface in an exposure apparatus and a bonding apparatus used in the manufacturing process of a semiconductor device. [Figure 5] FIG. 1 is a block diagram showing an example of the configuration of an exposure apparatus according to the first embodiment. [Figure 6] 5 is a flowchart showing an example of exposure processing of the exposure apparatus according to the first embodiment. [Figure 7] 6 is a table showing an example of an exposure recipe used in the exposure apparatus according to the first embodiment. [Figure 8]5A and 5B are schematic diagrams showing an example of a change in overlay misalignment due to wafer magnification when alignment correction in normal mode is used in the manufacturing process of the semiconductor device according to the first embodiment. [Figure 9] 5A and 5B are schematic diagrams showing an example of a change in overlay misalignment due to wafer magnification when alignment correction in normal mode is used in the manufacturing process of the semiconductor device according to the first embodiment. [Figure 10] 5A and 5B are schematic diagrams showing an example of a change in overlay misalignment due to wafer magnification when X-weighted mode alignment correction is used in the manufacturing process of the semiconductor device according to the first embodiment. [Figure 11] 5A and 5B are schematic diagrams showing an example of a change in overlay misalignment due to wafer magnification when Y-weighted mode alignment correction is used in the manufacturing process of the semiconductor device according to the first embodiment. [Figure 12] 5A and 5B are schematic diagrams showing an example of a change in overlay misalignment in wafer orthogonality when normal mode alignment correction is used in the manufacturing process of the semiconductor device according to the first embodiment. [Figure 13] 5A and 5B are schematic diagrams showing an example of a change in overlay misalignment in wafer orthogonality when normal mode alignment correction is used in the manufacturing process of the semiconductor device according to the first embodiment. [Figure 14] 5A and 5B are schematic diagrams showing an example of a change in overlay misalignment in wafer orthogonality when X-weighted mode alignment correction is used in the manufacturing process of the semiconductor device according to the first embodiment. [Figure 15] 5A and 5B are schematic diagrams showing an example of a change in overlay misalignment in wafer orthogonality when Y-emphasis mode alignment correction is used in the manufacturing process of the semiconductor device according to the first embodiment. [Figure 16] FIG. 10 is a block diagram showing an example of the configuration of a semiconductor manufacturing system according to a second embodiment. [Figure 17] FIG. 10 is a block diagram showing an example of the configuration of a joining device according to a second embodiment. [Figure 18] FIG. 10 is a block diagram showing an example of the configuration of a server according to the second embodiment. [Figure 19] FIG. 10 is a schematic view showing an outline of a bonding process of a bonding apparatus according to a second embodiment. [Figure 20] 10 is a flowchart showing an example of a process related to correction of wafer magnification in a bonding process of a bonding apparatus according to a second embodiment. [Figure 21] 10 is a flowchart showing an example of a process related to correction of wafer magnification in a bonding process of a bonding apparatus according to a modified example of the second embodiment. [Figure 22] 11 is a flowchart showing an example of a method for creating a correction formula for overlay misalignment used in the joining device according to the third embodiment. [Figure 23] 11 is a flowchart showing an example of a joining process of the joining device according to the third embodiment. [Figure 24] FIG. 11 is a schematic diagram showing an example of a plurality of wafers used to create a correction formula for overlay misalignment used in the bonding apparatus according to the third embodiment. [Figure 25] 11 is a graph showing an example of a change in shift measurement error amount before and after creation of a correction formula for overlay misalignment in a joining process of the joining apparatus according to the third embodiment. [Figure 26] FIG. 10 is a block diagram showing an example of the configuration of a memory device according to a fourth embodiment. [Figure 27] FIG. 10 is a circuit diagram showing an example of the circuit configuration of a memory cell array included in a memory device according to a fourth embodiment. [Figure 28] FIG. 10 is a perspective view showing an example of the structure of a memory device according to a fourth embodiment. [Figure 29] FIG. 10 is a plan view showing an example of a planar layout of a memory cell array included in a memory device according to a fourth embodiment. [Figure 30] FIG. 10 is a cross-sectional view showing an example of the cross-sectional structure of a memory cell array included in a memory device according to a fourth embodiment. [Figure 31] 31 is a cross-sectional view taken along line XXXI-XXXI in FIG. 30, showing an example of the cross-sectional structure of a memory pillar included in a memory device according to a fourth embodiment. [Figure 32] FIG. 10 is a cross-sectional view showing an example of the cross-sectional structure of a memory device according to a fourth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, embodiments will be described with reference to the drawings. Each embodiment illustrates an apparatus or method for embodying the technical idea of ​​the invention. The drawings are schematic or conceptual. The dimensions and ratios of each drawing are not necessarily the same as those in reality. Illustrations of components have been omitted as appropriate. Hatching added to the drawings does not necessarily relate to the material or characteristics of the components. In this specification, components having substantially the same function and configuration are assigned the same reference numerals. Numbers added to reference numerals are used to refer to the same reference numerals and to distinguish between similar elements.

[0008] In this specification, a semiconductor device is formed by bonding two semiconductor circuit substrates, each having a semiconductor circuit formed thereon, and then separating the bonded semiconductor circuit substrates into individual chips. Hereinafter, the semiconductor circuit substrates are referred to as "wafers." The process of bonding two wafers is referred to as the "bonding process." The device that performs the bonding process is referred to as the "bonding device." The upper wafer during the bonding process is referred to as the "upper wafer UW." The lower wafer during the bonding process is referred to as the "lower wafer LW." The two bonded wafers, i.e., the set of the upper wafer UW and the lower wafer LW, are referred to as the "bonded wafer BW." In this specification, the X and Y directions are directions that intersect each other and are parallel to the wafer surfaces. The Z direction is a direction that intersects the X and Y directions and is perpendicular to the wafer surfaces. The "wafer surface" refers to the surface on which semiconductor circuits are formed in a pre-processing step described below. The "wafer back surface" refers to the surface opposite the wafer surface. In this specification, "upper and lower" are defined based on the direction along the Z direction.

[0009] <Overview of semiconductor device manufacturing method> 1 is a schematic diagram showing an outline of a method for manufacturing a semiconductor device. Below, a rough processing flow in the method for manufacturing a semiconductor device of this specification will be described with reference to FIG.

[0010] First, wafers are assigned to lots ("lot assignment"). The lots are classified, for example, into lots including upper wafers UW and lots including lower wafers LW. Then, front-end processes are carried out on the lots including upper wafers UW and the lots including lower wafers LW, respectively, and semiconductor circuits are formed on the upper wafers UW and the lower wafers LW, respectively. The front-end processes include a combination of "exposure processing," "exposure OL (Overlay) measurement," and "processing."

[0011] The exposure process is a process of transferring a mask pattern onto a wafer, for example, by irradiating a wafer coated with resist with light transmitted through a mask. The area to which the mask pattern is transferred by one exposure corresponds to one shot. In the exposure process, one shot of exposure is repeatedly performed by shifting the exposure position. In other words, the exposure process is performed using a step-and-repeat method. In the exposure process, the arrangement and shape of each shot are corrected based on the measurement results of the alignment mark (described below), and the overlay position with the underlying pattern formed on the wafer is adjusted (aligned). The arrangement (layout) of multiple shots on the upper wafer UW and the arrangement (layout) of multiple shots on the lower wafer LW are set to be the same. Hereinafter, the device that performs the exposure process will be referred to as the "exposure device."

[0012] Exposure OL measurement is a process for measuring the amount of overlay misalignment between a pattern formed by exposure processing and a pattern underlying the exposure processing. The measurement results of the amount of overlay misalignment obtained by exposure OL measurement are used for determining rework for the exposure processing and for calculating an overlay misalignment correction value to be applied to subsequent lots. Processing is a process for processing (e.g., etching) a wafer using a mask formed by exposure processing. When processing is completed, the used mask is removed and the next process is performed.

[0013] After the pre-processing is completed, the bonding process is performed. In the bonding process, a bonding device positions the surface of the upper wafer UW and the surface of the lower wafer LW so that they face each other. Then, the bonding device adjusts (aligns) the overlapping positions of the patterns formed on the surfaces of the upper wafer UW and the lower wafer LW. Then, the bonding device bonds the surfaces of the upper wafer UW and the lower wafer LW together to form a bonded wafer BW.

[0014] Bonded wafer BW formed by bonding processing is subjected to bonding OL (Overlay) measurement. Bonded OL measurement is a process for measuring the amount of overlay misalignment between the pattern formed on the surface of the upper wafer UW and the pattern formed on the surface of the lower wafer LW. The measurement result of the overlay misalignment obtained by bonding OL measurement is used to calculate the overlay misalignment correction value to be applied to the exposure processing of the subsequent lot.

[0015] The amount of overlay misalignment that occurs during exposure and bonding processes can be expressed by a combination of various components. FIG. 2 is a schematic diagram showing an example of overlay misalignment components that can occur during the manufacturing process of a semiconductor device. FIG. 2 illustrates mathematical expressions corresponding to each overlay misalignment component and the change in shape of one shot based on the mathematical expressions. As shown in FIG. 2, the overlay misalignment components include, for example, (A) offset component, (B) magnification component, (C) rhombic (orthogonality) component, (D) eccentric magnification component, (E) trapezoidal component, (F) fan-shaped component, (G) C-shaped magnification component, (H) accordion-shaped component, (I) biased C-shaped distortion component, and (J) river flow component. Each of the overlay misalignment components (A) to (J) in FIG. 2 further includes components in the X and Y directions.

[0016] Below are listed the formulas corresponding to each component of (A) to (J) in Figure 2. In the formulas below, "x" and "y" correspond to the coordinate in the X direction (X coordinate) and the coordinate in the Y direction (Y coordinate), respectively. "dx" and "dy" are the amounts of overlay misalignment in the X direction and the Y direction, respectively. "K1" to "K20" are the coefficients of each overlay misalignment component. (A) The offset (shift) component in the X direction is "dx=K1." The offset (shift) component in the Y direction is "dy=K2." (B) The magnification component in the X direction is “dx=K3·x”. The magnification component in the Y direction is “dy=K4·y”. (C) The rhombus (orthogonality) component in the X direction is “dx=K5·y”. The rhombus (orthogonality) component in the Y direction is “dy=K6·x”. (D) The eccentricity magnification component in the X direction is "dx=K7 x 2 The eccentricity magnification component in the Y direction is "dy=K8·y 2 " (E) The trapezoidal component in the X direction is “dx=K9·x·y”. The trapezoidal component in the Y direction is “dy=K10·x·y”. (F) The fan component in the X direction is “dx=K11·y 2 " The fan component in the Y direction is "dy=K12·x 2 " (G) The C-shaped magnification component in the X direction is “dx=K13·x 3 " The C-shaped magnification component in the Y direction is "dy=K14·y 3 " (H) The accordion component in the X direction is “dx=K15·x 2 ·y". The accordion component in the Y direction is "dy=K16·x·y 2 " (I) The C-shaped distortion component in the X direction is “dx=K17·x·y 2 The C-shaped distortion component in the Y direction is "dy=K18·x 2 ·y”. (J) The flow component of the river in the X direction is “dx=K19·y 3 " The river flow component in the Y direction is "dy=K20·x 3 "

[0017] Although FIG. 2 illustrates an example of an overlay misalignment component on a shot-by-shot basis, an overlay misalignment component occurring within the wafer surface can also be expressed by the same overlay misalignment component on a shot-by-shot basis. Hereinafter, the overlay misalignment due to the magnification component occurring within the wafer surface will also be referred to as "wafer magnification." The overlay misalignment due to the orthogonality component occurring within the wafer surface will also be referred to as "wafer orthogonality." The exposure tool and the bonding tool each use the measurement results of the alignment marks formed on the wafer to align the overlay position.

[0018] 3A and 3B are schematic diagrams showing an example of the arrangement of alignment marks used in the manufacturing process of a semiconductor device. (A) of Fig. 3 illustrates the positions of alignment marks AM measured during exposure processing. (B) of Fig. 3 illustrates the positions of alignment marks AM on the upper wafer UW measured during bonding processing. (C) of Fig. 3 illustrates the positions of alignment marks AM on the lower wafer LW measured during bonding processing.

[0019] As shown in Figure 3(A), the exposure apparatus can measure alignment marks AM at multiple points (at least three or more points) arranged on a wafer during exposure processing.The exposure apparatus can then calculate correction values ​​for overlay misalignment components, such as shift components in the X and Y directions, magnification components, and orthogonality components, by functionally approximating the measurement results of the alignment marks AM in a Cartesian coordinate system.The exposure apparatus can also correct overlay misalignment components on a shot-by-shot basis and within the wafer surface.In this way, the exposure apparatus can correct complex overlay misalignment components.

[0020] As shown in Figures 3(B) and (C), the bonding apparatus measures at least three alignment marks AM_C, AM_L, and AM_R arranged on each of the upper wafer WU and the lower wafer LW during the bonding process. Alignment mark AM_C is arranged near the center of the wafer. The bonding apparatus uses the measurement results of alignment mark AM_C to align the shift component of the wafer. Alignment marks AM_L and AM_R are arranged on one side and the other side of the outer periphery of the wafer, respectively. The bonding apparatus uses the measurement results of alignment marks AM_L and AM_R to align the rotation component of the wafer.

[0021] In this way, the bonding apparatus can calculate correction values ​​for simple overlay misalignment components (shift components and rotation components) within the wafer surface using at least three alignment marks AM_C, AM_L, and AM_R. The bonding apparatus can also measure the alignment marks AM of the upper wafer UW and the lower wafer LW in parallel. For example, the alignment marks AM_C of the upper wafer UW and the lower wafer LW are positioned offset from the wafer center in opposite directions to each other because they are measured simultaneously due to limitations on the placement of the alignment marks AM.

[0022] FIG. 4 is a table showing an example of the correction performance of an overlay misalignment component within a wafer plane in an exposure tool and a bonding tool used in a semiconductor device manufacturing process. As shown in FIG. 4, the shift component can be corrected by both the exposure tool and the bonding tool. The wafer magnification common to both the X and Y directions (XY common magnification component) can be corrected by both the exposure tool and the bonding tool. A method for correcting the XY common magnification component in a bonding tool will be described later. The wafer magnification that differs between the X and Y directions (XY differential magnification component) can be corrected by the exposure tool. On the other hand, the XY differential magnification component is difficult to correct in a bonding tool. The rotation component can be corrected by both the exposure tool and the bonding tool. The rotation component that differs between the X and Y directions (orthogonality component) can be corrected by the exposure tool. On the other hand, the orthogonality component is difficult to correct in a bonding tool. The overlay misalignment component (random component) that occurs randomly within the wafer plane can be corrected on a shot-by-shot basis by the exposure tool. On the other hand, the random component is difficult to correct in a bonding tool.

[0023] [1] First embodiment The first embodiment relates to an exposure apparatus that can change alignment correction settings in a specific pre-processing step for the lower wafer LW in accordance with the design of the semiconductor device. Below, details of the exposure apparatus 1 according to the first embodiment will be described.

[0024] [1-1] Configuration of exposure tool 1 5 is a block diagram showing an example of the configuration of exposure apparatus 1 according to the first embodiment. As shown in Fig. 5, exposure apparatus 1 includes, for example, a control device 10, a storage device 11, a transport device 12, a communication device 13, and an exposure unit 14.

[0025] The control device 10 is a computer or the like that controls the overall operation of the exposure apparatus 1. The control device 10 controls each of the storage device 11, the transport device 12, the communication device 13, and the exposure unit 14. Although not shown, the control device 10 is equipped with a CPU (Central Processing Unit), ROM (Read Only Memory), RAM (Random Access Memory), and the like. The CPU is a processor that executes various programs related to the control of the apparatus. The ROM is a non-volatile storage medium that stores the control program for the apparatus. The RAM is a volatile storage medium used as a working area for the CPU.

[0026] The storage device 11 is a storage medium used to store data, programs, and the like. The storage device 11 stores, for example, an exposure recipe 110 and correction value information 111. The exposure recipe 110 is a table in which exposure processing settings are recorded. The exposure recipe 110 includes information such as the shape and layout of the shot, the exposure dose, focus settings, and alignment settings. The exposure recipe 110 can be prepared for each processing step or processing lot. The correction value information 111 is a log that records the overlay misalignment correction values ​​(i.e., alignment results) used when the exposure processing was performed.

[0027] The transfer device 12 is an apparatus equipped with a transfer arm capable of transferring wafers and a transition for temporarily placing multiple wafers. For example, the transfer device 12 transfers the wafer WF received from an external coating and developing apparatus to the exposure unit 14. After the exposure process, the transfer device 12 transfers the wafer WF received from the exposure unit 14 to the outside of the exposure apparatus 1. Note that the "coating and developing apparatus" is an apparatus that performs pre-processing and post-processing of the exposure process. The pre-processing of the exposure process includes the process of coating the wafer with a resist material (photosensitive material). The post-processing of the exposure process includes the process of developing the pattern exposed on the wafer. Note that multiple semiconductor manufacturing apparatuses may be used as the apparatuses used in the pre-processing and post-processing of the exposure process.

[0028] The communication device 13 is a communication interface that can be connected to a network. The exposure apparatus 1 may operate based on operations from a terminal on the network, or the exposure recipe 110 and the correction value information 111 may be stored in a server on the network.

[0029] The exposure unit 14 is a collection of components used in the exposure process. The exposure unit 14 includes, for example, a wafer stage 140, a reticle stage 141, a light source 142, a projection optical system 143, and a camera 144. The wafer stage 140 has a function of holding a wafer WF. The reticle stage 141 has a function of holding a reticle RT (mask). The respective stage positions of the wafer stage 140 and the reticle stage 141 can be controlled under the control of the control device 10. The light source 142 irradiates the generated light onto the reticle RT. The projection optical system 143 collects the light transmitted through the reticle RT onto the surface of the wafer WF. The camera 144 is an imaging mechanism used to measure the alignment marks AM.

[0030] [1-2] Manufacturing method of semiconductor device Below, as a method for manufacturing a semiconductor device according to the first embodiment, an example of a specific process using the exposure apparatus 1 will be described. That is, a semiconductor device is manufactured using the exposure method (exposure process) according to the first embodiment described below.

[0031] [1-2-1] Exposure processing 6 is a flowchart showing an example of exposure processing in the exposure apparatus 1 according to the first embodiment. The flow of exposure processing in the exposure apparatus 1 will be explained below with reference to FIG.

[0032] When the exposure apparatus 1 is notified by the coating and developing apparatus that the pre-processing of the wafer is complete, the exposure apparatus 1 starts the exposure process (START).

[0033] First, a wafer is loaded into the exposure apparatus 1 (S100). The wafer loaded from the coating and developing apparatus is held by the wafer stage 140.

[0034] Next, the exposure apparatus 1 checks the exposure recipe 110 (S101), which causes the control apparatus 10 to determine the processing conditions to be applied to the loaded wafer.

[0035] Next, the exposure apparatus 1 measures the alignment marks AM (S102). Specifically, the camera 144 photographs a plurality of alignment marks AM arranged at predetermined positions on the wafer.

[0036] Next, the exposure apparatus 1 executes alignment correction processing (S103). Specifically, the control apparatus 10 calculates correction values ​​for the shot arrangement, shot shape, etc. to be exposed on the wafer, based on the results of capturing the multiple alignment marks AM.

[0037] Next, the exposure apparatus 1 executes the exposure sequence (S104). Specifically, the control apparatus 10 controls the light source 142, the wafer stage 140, and the reticle stage 141 based on the correction value calculated in S103, and irradiates the wafer with light that has passed through the mask in a step-and-repeat manner.

[0038] Next, the exposure apparatus 1 updates (S105) the correction value information 111. That is, in S105, the correction value calculated in S103 is recorded in the correction value information 111 in association with the processed wafer.

[0039] Next, the exposure apparatus 1 unloads the wafer (S106). The unloaded wafer is handed over to the coating and developing apparatus. The coating and developing apparatus performs processes such as heat treatment, development, and cleaning on the wafer after the exposure process. As a result, a pattern is formed on the wafer.

[0040] When the wafer is unloaded, the exposure apparatus 1 ends the exposure process (end).

[0041] [1-2-2] Specific examples of exposure recipes 7 is a table showing an example of an exposure recipe 110 used in the exposure apparatus 1 according to the first embodiment. As shown in Fig. 7, the exposure recipe 110 stores setting items, options, and process types in association with each other. The setting items of the exposure recipe 110 include, for example, "alignment correction," "wafer magnification correction," "wafer magnification correction ratio (MagX / MagY)," "wafer rotation correction," and "wafer rotation correction ratio (RotX / RotY)."

[0042] Alignment correction setting options include "normal (mode)," "X-weighted (mode)," and "Y-weighted (mode)." The normal mode is a setting that applies approximately 100% correction to the overlay misalignment components in both the X and Y directions when executing the exposure process. The X-weighted mode is a setting that applies emphasis to the correction of the overlay misalignment component in the X direction when executing the exposure process. Specifically, the X-weighted mode applies approximately 100% correction to the overlay misalignment component in the X direction to the alignment results. On the other hand, the X-weighted mode applies correction to the overlay misalignment component in the Y direction based on a correction ratio with respect to the X-direction correction value. The Y-weighted mode is a setting that applies priority to the correction of the overlay misalignment component in the Y direction when executing the exposure process. Specifically, the Y-weighted mode applies approximately 100% correction to the overlay misalignment component in the Y direction to the alignment results. On the other hand, the Y-weighted mode applies correction to the overlay misalignment component in the X direction based on a correction ratio with respect to the Y-direction correction value.

[0043] Options for the wafer magnification correction setting include "off" and "on." When the wafer magnification correction setting is "off," the exposure apparatus 1 applies normal mode conditions to calculate the correction value of the wafer magnification in the exposure process. When the wafer magnification correction setting is "on," the exposure apparatus 1 applies X-weighted mode or Y-weighted mode conditions to calculate the correction value of the wafer magnification in the exposure process. Furthermore, when the wafer magnification correction setting is "on," the setting of the wafer magnification correction ratio is referenced. The setting of the wafer magnification correction ratio indicates the ratio (MagX / MagY) between the correction value of the wafer magnification in the X direction (MagX) and the correction value of the wafer magnification in the Y direction (MagY) in alignment correction. The wafer magnification correction ratio is set, for example, within the range of 0.5 to 2.0. When MagX / MagY=1, the exposure apparatus 1 sets the exposure apparatus reference MagX:MagY to 1:1.

[0044] Options for the wafer rotation correction setting include "off" and "on." When the wafer rotation correction setting is "off," the exposure apparatus 1 applies normal mode conditions to calculate the correction value of the wafer rotation component in the exposure process. When the wafer rotation correction setting is "on," the exposure apparatus 1 applies X-weighted mode or Y-weighted mode conditions to calculate the correction value of the wafer rotation component in the exposure process. Furthermore, when the wafer rotation correction setting is "on," the wafer rotation correction ratio setting is referenced. The wafer rotation correction ratio setting indicates the ratio (RotX / RotY) between the correction value (RotX) of the wafer orthogonality in the X direction and the correction value (RotY) of the wafer orthogonality in the Y direction in alignment correction. The wafer rotation correction ratio is set, for example, within the range of 0.5 to 2.0. When RotX / RotY=1, the exposure apparatus 1 sets the exposure apparatus reference RotX:RotY to 1:1.

[0045] The process type is, for example, a parameter assigned to each processing step of the exposure tool. The process type includes, for example, a first group and a second group. The processing steps of the first group are, for example, assigned to the exposure processing of the first half of the pre-processing. The processing steps of the second group are, for example, assigned to the exposure processing for forming a wiring layer near the wafer surface in the pre-processing. For example, the normal mode is used as the alignment correction setting for the first group. For example, the Y-weighted mode is used as the alignment correction setting for the second group. Furthermore, for example, the wafer magnification correction setting is "on," the wafer magnification correction ratio is set to "1," and the wafer rotation correction setting is set to "off" for the second group. In this way, whether the X-weighted mode or the Y-weighted mode is used, at least one of the wafer magnification correction and the wafer rotation correction may be used. By editing the exposure recipe 110, the user can change alignment correction parameters such as the X-weighted mode or the Y-weighted mode for each processing step or processing lot.

[0046] [1-2-3] Specific examples of alignment correction processing Specific examples of alignment correction processing will be described below with reference to FIGS. 8 to 15. Each of FIGS. 8 to 15 shows, in simplified form, the shot shapes of the upper wafer UW in the pre-processing, the shot shapes of the lower wafer LW before and after the exposure processing in the pre-processing, the alignment correction in the bonding processing, and the overlay state of the bonded wafer BW after bonding. The illustrated shot shapes exemplify the shapes of a set of multiple shots arranged within the wafer plane, and schematically illustrate the state in which the effects of variations in wafer magnification and wafer orthogonality occur within the wafer plane. The alignment correction processing will be described below with a focus on wafer magnification and wafer orthogonality. However, in actual exposure processing, the alignment results can be reflected in both the shot-by-shot overlay misalignment component (shot component) and the wafer-plane overlay misalignment component (wafer component).

[0047] FIG. 8 is a schematic diagram showing an example of a change in wafer magnification overlay misalignment when normal mode alignment correction is used in the manufacturing process of the semiconductor device according to the first embodiment. As shown in FIG. 8, the XY ratio of the wafer magnification of the lower wafer LW in this example is equivalent to the XY ratio of the wafer magnification of the lower topography of the upper wafer UW. In this example, since the alignment correction setting is normal mode, the shot shape to which wafer component correction is applied by the exposure process is corrected to be substantially identical to the base shape. Therefore, the occurrence of wafer magnification overlay misalignment is suppressed in the exposure process of the lower wafer LW. Furthermore, the XY ratio of the wafer magnification of the lower wafer LW after the exposure process is equivalent to the XY ratio of the wafer magnification of the upper wafer UW. Thereafter, the bonding device performs the bonding process by applying common wafer magnification correction to the lower wafer LW. In this example, since the XY ratios of the wafer magnification of the upper wafer UW and the lower wafer LW during the bonding process are equivalent, the wafer magnification overlay misalignment between the upper wafer UW and the lower wafer LW in the bonded wafer BW is suppressed.

[0048] FIG. 9 is a schematic diagram showing an example of a change in wafer magnification overlay misalignment when normal mode alignment correction is used in the semiconductor device manufacturing process according to the first embodiment. As shown in FIG. 9 , the XY ratio of the wafer magnification of the lower wafer LW in this example is different from the XY ratio of the wafer magnification of the lower topography of the upper wafer UW. In this example, because the alignment correction setting is normal mode, the shot shape to which wafer component correction is applied by the exposure process is corrected to be substantially identical to the base shape. Therefore, the occurrence of wafer magnification overlay misalignment is suppressed in the exposure process of the lower wafer LW. Furthermore, the XY ratio of the wafer magnification of the lower wafer LW after the exposure process is different from the XY ratio of the wafer magnification of the upper wafer UW. The bonding device then performs a bonding process on the lower wafer LW by applying common XY wafer magnification correction. In this example, the XY ratios of the wafer magnifications of the upper wafer UW and the lower wafer LW are different during the bonding process, and the bonding device cannot correct the XY difference in wafer magnification, so there remains a misalignment in the wafer magnifications between the upper wafer UW and the lower wafer LW on the bonded wafer BW.

[0049] FIG. 10 is a schematic diagram showing an example of a change in wafer magnification overlay misalignment when X-weighted mode alignment correction is used in the semiconductor device manufacturing process according to the first embodiment. As shown in FIG. 10 , the XY ratio of the wafer magnification of the lower wafer LW in this example is different from the XY ratio of the wafer magnification of the upper wafer UW. In this example, because the alignment correction setting is X-weighted mode, the wafer magnification applied to the correction of wafer components in the exposure process is equal to the XY ratio of the wafer magnification of the upper wafer UW, and is set to suppress overlay misalignment with the base shape only in the X direction. Therefore, during the exposure process of the lower wafer LW, overlay misalignment in the X direction is suppressed, while overlay misalignment in the Y direction remains. The bonding device then performs a bonding process on the lower wafer LW by applying a common wafer magnification correction for both X and Y. In this example, because the XY ratios of the wafer magnifications of the upper wafer UW and the lower wafer LW are equal during the bonding process, overlay misalignment between the upper wafer UW and the lower wafer LW in the bonded wafer BW is suppressed.

[0050] FIG. 11 is a schematic diagram showing an example of a change in wafer magnification overlay misalignment when Y-priority mode alignment correction is used in the semiconductor device manufacturing process according to the first embodiment. As shown in FIG. 11 , the XY ratio of the wafer magnification of the lower wafer LW in this example is different from the XY ratio of the wafer magnification of the upper wafer UW. In this example, since the alignment correction setting is Y-priority mode, the wafer magnification applied to the correction of wafer components in the exposure process is equal to the XY ratio of the wafer magnification of the upper wafer UW, and is set to suppress overlay misalignment with the base shape only in the Y direction. Therefore, during the exposure process of the lower wafer LW, overlay misalignment in the Y direction is suppressed, while overlay misalignment in the X direction remains. The bonding device then performs a bonding process on the lower wafer LW by applying a common wafer magnification correction for both X and Y. In this example, since the XY ratios of the wafer magnifications of the upper wafer UW and the lower wafer LW are equal during the bonding process, overlay misalignment between the upper wafer UW and the lower wafer LW in the bonded wafer BW is suppressed.

[0051] FIG. 12 is a schematic diagram showing an example of a change in overlay misalignment in wafer orthogonality when normal-mode alignment correction is used in the manufacturing process of the semiconductor device according to the first embodiment. As shown in FIG. 12, the XY ratio of the wafer orthogonality of the lower wafer LW in this example is equivalent to the XY ratio of the wafer orthogonality of the lower topography of the upper wafer UW. In this example, since the alignment correction setting is normal mode, the shot shape to which wafer component correction is applied in the exposure process is corrected to be substantially identical to the base shape. Therefore, the occurrence of overlay misalignment in wafer orthogonality is suppressed in the exposure process of the lower wafer LW. Furthermore, the XY ratio of the wafer orthogonality of the lower wafer LW after the exposure process is equivalent to the XY ratio of the wafer orthogonality of the upper wafer UW. Thereafter, the bonding apparatus performs a bonding process by applying common wafer orthogonality correction (i.e., rotation correction) to the lower wafer LW. In this example, since the XY ratios of the wafer orthogonality of the upper wafer UW and the lower wafer LW during the bonding process are equivalent, overlay misalignment in wafer orthogonality between the upper wafer UW and the lower wafer LW in the bonded wafer BW is suppressed.

[0052] FIG. 13 is a schematic diagram showing an example of a change in overlay misalignment in wafer orthogonality when normal-mode alignment correction is used in the manufacturing process of the semiconductor device according to the first embodiment. As shown in FIG. 13, the XY ratio of the wafer orthogonality of the lower wafer LW in this example is different from the XY ratio of the wafer orthogonality of the lower topography of the upper wafer UW. In this example, since the alignment correction setting is normal mode, the shot shape to which wafer-component correction is applied by the exposure process is corrected to be substantially identical to the base shape. Therefore, the occurrence of overlay misalignment in wafer orthogonality is suppressed in the exposure process of the lower wafer LW. Furthermore, the XY ratio of the wafer orthogonality of the lower wafer LW after the exposure process is different from the XY ratio of the wafer orthogonality of the upper wafer UW. The bonding device then performs a bonding process on the lower wafer LW by applying common XY wafer orthogonality correction (i.e., rotation correction) to the lower wafer LW. In this example, the XY ratios of the wafer orthogonality of the upper wafer UW and the lower wafer LW are different during the bonding process, and the bonding device cannot correct the XY difference in the wafer orthogonality, so there remains a misalignment in the wafer orthogonality between the upper wafer UW and the lower wafer LW in the bonded wafer BW.

[0053] FIG. 14 is a schematic diagram showing an example of a change in overlay misalignment in wafer orthogonality when X-weighted alignment correction is used in the manufacturing process of the semiconductor device according to the first embodiment. As shown in FIG. 14, the XY ratio of the wafer orthogonality of the lower wafer LW in this example is different from the XY ratio of the wafer orthogonality of the upper wafer UW. In this example, because the alignment correction setting is X-weighted alignment, the wafer orthogonality applied to the correction of wafer components in the exposure process is equal to the XY ratio of the wafer orthogonality of the upper wafer UW, and is set to suppress overlay misalignment with the base shape only in the X direction. Therefore, during the exposure process of the lower wafer LW, overlay misalignment in the wafer orthogonality in the X direction is suppressed, while overlay misalignment in the wafer orthogonality in the Y direction remains. The bonding device then performs a bonding process on the lower wafer LW by applying common XY wafer orthogonality correction (i.e., rotation correction) to the wafer orthogonality in both X and Y directions. In this example, the XY ratios of the wafer orthogonality of the upper wafer UW and the lower wafer LW are equal during bonding, so that misalignment of the wafer orthogonality between the upper wafer UW and the lower wafer LW in the bonded wafer BW is suppressed.

[0054] FIG. 15 is a schematic diagram showing an example of a change in overlay misalignment in wafer orthogonality when Y-weighted alignment correction is used in the manufacturing process of a semiconductor device according to the first embodiment. As shown in FIG. 15, the XY ratio of the wafer orthogonality of the lower wafer LW in this example is different from the XY ratio of the wafer orthogonality of the upper wafer UW. In this example, since the alignment correction setting is Y-weighted, the wafer orthogonality applied to the correction of wafer components in the exposure process is equal to the XY ratio of the wafer orthogonality of the upper wafer UW, and is set to suppress overlay misalignment with the base shape only in the Y direction. Therefore, during the exposure process of the lower wafer LW, overlay misalignment in the wafer orthogonality in the Y direction is suppressed, while overlay misalignment in the wafer orthogonality in the X direction remains. The bonding device then performs a bonding process on the lower wafer LW by applying common XY wafer orthogonality correction (i.e., rotation correction) to the wafer orthogonality in both X and Y directions. In this example, the XY ratios of the wafer orthogonality of the upper wafer UW and the lower wafer LW are equal during bonding, so that misalignment of the wafer orthogonality between the upper wafer UW and the lower wafer LW in the bonded wafer BW is suppressed.

[0055] [1-3] Effects of the first embodiment The exposure apparatus 1 according to the first embodiment described above can improve the yield of semiconductor devices. The effects of the exposure apparatus 1 according to the first embodiment will be described in detail below.

[0056] Bonding devices are known that can only correct the overlay misalignment of the wafer magnification and rotational components between the upper wafer UW and the lower wafer LW by the same values ​​for both the X and Y components. In a bonded wafer BW formed using such a bonding device, if the X and Y differences in the wafer magnification between the upper wafer UW and the lower wafer LW vary between the wafers, overlay misalignment between the upper wafer UW and the lower wafer LW may remain, as described with reference to FIG. 9. Similarly, if the X and Y differences in the wafer orthogonality between the upper wafer UW and the lower wafer LW vary between the wafers, overlay misalignment between the upper wafer UW and the lower wafer LW may remain, as described with reference to FIG. 13.

[0057] One possible method for improving the overlay misalignment during the bonding process is to adjust the wafer magnification and the XY difference in wafer orthogonality of the pattern on the bonding surface of the lower wafer LW to match that of the upper wafer UW. This can reduce the overlay misalignment between the lower wafer LW and the upper wafer UW during the bonding process. However, when the pattern on the bonding surface of the lower wafer LW is adjusted to match that of the upper wafer UW, overlay misalignment between the pattern on the bonding surface and the underlying pattern may remain, as described with reference to FIGS. 10, 11, 13, and 14.

[0058] On the other hand, the allowable range for misalignment of the pattern on the bonding surface with the underlying pattern may be narrow in one of the X and Y directions and wide in the other direction. In other words, even if priority is given to correcting the misalignment between the upper wafer UW and the lower wafer LW, and the misalignment between the pattern on the bonding surface of the lower wafer LW and the underlying pattern worsens, the impact of the misalignment in either the X or Y direction on the yield may be small.

[0059] Therefore, the exposure apparatus 1 according to the first embodiment has a function of determining the correction value of the wafer magnification in one of the X and Y directions obtained by measuring the alignment mark AM during the exposure process, based on the correction value of the wafer magnification in the other direction.

[0060] Specifically, when the X-weighted mode is used, the exposure apparatus 1 can match the correction value of the X-direction wafer magnification of the lower wafer LW to the substrate, and determine the correction value of the Y-direction wafer magnification based on the wafer magnification correction ratio. When the X-weighted mode is used, the exposure apparatus 1 can match the correction value of the X-direction wafer orthogonality of the lower wafer LW to the substrate, and determine the correction value of the Y-direction wafer orthogonality based on the wafer rotation correction ratio. Furthermore, when the Y-weighted mode is used, the exposure apparatus 1 can match the correction value of the Y-direction wafer magnification of the lower wafer LW to the substrate, and determine the correction value of the X-direction wafer magnification based on the wafer magnification correction ratio. When the Y-weighted mode is used, the exposure apparatus 1 can match the correction value of the X-direction wafer orthogonality of the lower wafer LW to the substrate, and determine the correction value of the Y-direction wafer orthogonality based on the wafer rotation correction ratio.

[0061] In the exposure apparatus 1 according to the first embodiment, different alignment correction settings can be used depending on the tendency of the ranges in which overlay misalignment can be tolerated in the X and Y directions in each processing step. Specifically, if the range in which overlay misalignment can be tolerated is wide only in the Y direction, it is preferable to use the X-weighted mode as the alignment correction setting. If the range in which overlay misalignment can be tolerated is wide only in the X direction, it is preferable to use the Y-weighted mode as the alignment correction setting. If the range in which overlay misalignment can be tolerated is strict in both the X and Y directions, it is preferable to use the normal mode as the alignment correction setting, which aligns the overlay misalignment components in the X and Y directions with the substrate.

[0062] As described above, by using the X-weighted mode or the Y-weighted mode, the exposure apparatus 1 according to the first embodiment increases the overlay misalignment in the direction where the range of tolerance for overlay misalignment is wide, but can suppress the overlay misalignment in the direction that has the greatest impact on yield. In other words, by appropriately allowing overlay misalignment in processes and directions where the range of tolerance for overlay misalignment is wide, the exposure apparatus 1 according to the first embodiment can suppress overlay misalignment in processes and directions where the range of tolerance for overlay misalignment is narrow, thereby improving the yield of semiconductor devices.

[0063] [2] Second embodiment The second embodiment relates to a semiconductor manufacturing system that changes the correction value of the wafer magnification of the lower wafer LW in a bonding process based on the exposure results of the lower wafer LW and the upper wafer UW. Details of the semiconductor manufacturing system PS according to the second embodiment will be described below.

[0064] [2-1] Configuration [2-1-1] Configuration of semiconductor manufacturing system PS Fig. 16 is a block diagram showing an example of the configuration of a semiconductor manufacturing system PS according to the second embodiment. As shown in Fig. 16, the semiconductor manufacturing system PS includes, for example, an exposure apparatus 1, a bonding apparatus 2, and a server 3. The exposure apparatus 1, the bonding apparatus 2, and the server 3 are configured to be able to communicate with each other via a network NW. The network NW may use wired communication or wireless communication.

[0065] [2-1-2] Configuration of joining device 2 17 is a block diagram showing an example of the configuration of the joining device 2 according to the second embodiment. As shown in FIG. 17, the joining device 2 includes, for example, a control device 20, a transport device 21, a communication device 22, and a joining unit 23.

[0066] The control device 20 is a computer or the like that controls the overall operation of the bonding apparatus 2. The control device 20 controls each of the transport device 21, the communication device, and the bonding unit 23. Although not shown in the figure, the control device 20 includes a CPU, a ROM, a RAM, etc., similar to the exposure apparatus 1.

[0067] The transfer device 21 is an apparatus equipped with a transfer arm capable of transferring wafers, a transition for temporarily placing multiple wafers, etc. For example, the transfer device 21 transfers the upper wafer UW and the lower wafer LW received from a pre-treatment device for the bonding process to the bonding unit 23. After the bonding process, the transfer device 21 transfers the bonded wafer BW received from the bonding unit 23 to the outside of the bonding apparatus 2. The transfer device 21 may also be equipped with a mechanism for turning the wafers upside down.

[0068] The communication device 22 is a communication interface connectable to the network NW. The joining device 2 may operate under the control of a terminal on the network NW, may store an operation log in a server 3 on the network NW, or may calculate a correction value for overlay misalignment based on information stored in the server 3.

[0069] The bonding unit 23 is a collection of components used in the bonding process. The bonding unit 23 includes, for example, a lower stage 230, a stress device 231, a camera 232, an upper stage 233, a pressure pin 234, and a camera 235. The lower stage 230 has a function of holding the lower wafer LW. The lower stage 230 includes, for example, a wafer chuck that holds the wafer by vacuum suction. The stress device 231 has a function of applying stress to the lower stage 230 and deforming the lower wafer LW via the lower stage 230. The amount of expansion (scaling) of the lower wafer LW held on the lower stage 230 changes depending on the amount of deformation of the lower stage 230 caused by the stress device 231. The camera 232 is an imaging mechanism disposed on the lower stage 230 side and used to measure the alignment mark AM on the upper wafer UW. The upper stage 233 has a function of holding the upper wafer UW. The upper stage 233 includes, for example, a wafer chuck that holds the wafer by vacuum suction. The pressing pin 234 is a pin that can be driven vertically under the control of the control device 20 and press the upper surface of the center of the upper wafer UW held on the upper stage 233. The camera 235 is an imaging mechanism that is arranged on the upper stage 233 side and is used to measure the alignment marks AM of the lower wafer LW. The bonding device 2 may also have a vacuum pump that is used to vacuum-suck the lower stage 230 and the upper stage 233.

[0070] The lower stage 230 and the upper stage 233 are configured so that the lower wafer LW held on the lower stage 230 and the upper wafer UW held on the upper stage 233 can be disposed opposite each other. That is, the upper stage 233 can be disposed above the lower stage 230. In other words, the lower stage 230 and the upper stage 233 can face each other. In the bonding process, the upper surface of the upper wafer UW is the back surface of the upper wafer UW and is held by the upper stage 233 of the bonding apparatus 2. In the bonding process, the lower surface of the upper wafer UW is the front surface of the upper wafer UW and corresponds to the bonding surface. The upper surface of the lower wafer LW is the front surface of the lower wafer LW and corresponds to the bonding surface. The lower surface of the lower wafer LW is the back surface of the lower wafer LW and is held by the lower stage 230 of the bonding apparatus 2. The bonding apparatus 2 can adjust the shift component and rotation component of the overlay misalignment by adjusting the relative positions of the lower stage 230 and the upper stage 233. Furthermore, the bonding apparatus 2 can deform the lower stage 230 using the stress device 231, thereby adjusting the wafer magnification common to the X and Y directions of the lower wafer LW held on the deformed lower stage 230.

[0071] The "pretreatment device for bonding" described above is a device that modifies and hydrophilizes the bonding surfaces of the upper wafer UW and the lower wafer LW to enable bonding before the bonding process by the bonding device 2. Briefly, the pretreatment device first performs plasma processing on the surfaces of the upper wafer UW and the lower wafer LW to modify the surfaces of the upper wafer UW and the lower wafer LW. In the plasma processing, oxygen ions or nitrogen ions are generated from oxygen gas or nitrogen gas, which serves as a process gas, under a predetermined reduced pressure. The generated oxygen ions or nitrogen ions are then irradiated onto the bonding surfaces of the wafers. The pretreatment device then supplies pure water to the surfaces of the upper wafer UW and the lower wafer LW. Hydroxyl groups are then attached to the surfaces of the upper wafer UW and the lower wafer LW, making the surfaces hydrophilic. The upper wafer UW and the lower wafer LW, whose bonding surfaces have been modified and hydrophilized in this manner, are used in the bonding process. The bonding device 2 may be combined with a pretreatment device or the like to form a bonding system.

[0072] [2-1-3] Server 3 configuration Fig. 18 is a block diagram showing an example of the configuration of the server 3 according to the second embodiment. As shown in Fig. 18, the server 3 includes, for example, a CPU 30, a ROM 31, a RAM 32, a storage device 33, and a communication device 34. The CPU 30 is a processor that executes various programs related to the control of the server 3. The ROM 31 is a non-volatile storage device that stores the control program for the server 3. The RAM 32 is a volatile storage device used as a work area for the CPU 30. The storage device 33 is a non-volatile storage medium that can store information received from the exposure apparatus 1, the bonding apparatus 2, etc. The communication device 34 is a communication interface that can be connected to the network NW.

[0073] [2-2] Manufacturing method of semiconductor device Below, an example of a specific process using the bonding apparatus 2 will be described as a method for manufacturing a semiconductor device according to the second embodiment. That is, a semiconductor device is manufactured using the bonding method (bonding process) of the second embodiment described below. In the following description, alignment of the shift component will be referred to as "shift alignment," and alignment of the rotation component will be referred to as "rotational alignment." In other words, alignment correction (or simply "alignment") includes shift alignment and rotational alignment. In this specification, "shift alignment" and "rotational alignment" each include measuring at least one associated alignment mark AM and calculating an alignment correction value based on the measurement result of the alignment mark AM.

[0074] [2-2-1] Overview of the joining process Fig. 19 is a schematic diagram showing an overview of the joining process of the joining device 2 according to the second embodiment. In the joining process, (1) to (8) in Fig. 19 each show the state of the joining unit 23 in the joining process. Below, a rough processing flow in the joining process will be described with reference to Fig. 19.

[0075] FIG. 19(1) shows the state of the joining unit 23 before the joining process.

[0076] When the bonding process is started, the control device 20 controls the stress device 10 based on the correction value of the wafer magnification common to the X direction and the Y direction. 231 As shown in Figure 19 (2), 230 Transform the.

[0077] Next, the control device 20 causes the transfer device 21 to transfer the lower wafer LW to the lower stage 230, and transfer the upper wafer UW to the upper stage 233. Then, as shown in (3) of Fig. 19, the control device 20 causes the lower stage 230 to hold the lower wafer LW, and the upper stage 233 to hold the upper wafer UW. Note that the surfaces of the upper wafer UW and the lower wafer LW transferred to the bonding device 2 have been modified and made hydrophilic by a pretreatment device for the bonding process.

[0078] Next, the control device 20 performs rotational alignment. Specifically, first, as shown in (4) of Fig. 19, the control device 20 controls the positions of the lower stage 230 and the upper stage 233 to align the optical axis of the camera 232 of the lower stage 230 with the position of the alignment mark AM_L of the upper wafer UW, and align the optical axis of the camera 235 of the upper stage 233 with the position of the alignment mark AM_L of the lower wafer LW. Then, the control device 20 measures the alignment mark AM_L of the upper wafer UW using the camera 232, and measures the alignment mark AM_L of the lower wafer LW using the camera 235.

[0079] 19(5), the control device 20 controls the positions of the lower stage 230 and the upper stage 233 to align the optical axis of the camera 232 of the lower stage 230 with the position of the alignment mark AM_R of the upper wafer UW, and align the optical axis of the camera 235 of the upper stage 233 with the position of the alignment mark AM_R of the lower wafer LW. The control device 20 then measures the alignment mark AM_R of the upper wafer UW using the camera 232, and measures the alignment mark AM_R of the lower wafer LW using the camera 235. The control device 20 then calculates the amount of correction for the rotational component of overlay misalignment based on the measurement results of the alignment marks AM_L and AM_R by the cameras 232 and 235 acquired by the processes of FIG. 19(4) and (5).

[0080] Next, the control device 20 performs origin alignment for the cameras. Specifically, as shown in (6) of Fig. 19, the control device 20 controls the positions of the lower stage 230 and the upper stage 233 to insert a common target 236 between the optical axis of the camera 232 on the lower stage 230 and the optical axis of the camera 235 on the upper stage 233. Then, the control device 20 aligns the origins of the cameras 232 and 235 based on the measurement results of the common target 236 by each of the cameras 232 and 235.

[0081] Next, the control device 20 performs shift alignment. Specifically, first, as shown in (7) of FIG. 19 , the control device 20 controls the positions of the lower stage 230 and the upper stage 233 to align the optical axis of the camera 232 of the lower stage 230 with the position of the alignment mark AM_C of the upper wafer UW, and align the optical axis of the camera 235 of the upper stage 233 with the position of the alignment mark AM_C of the lower wafer LW. Then, the control device 20 measures the alignment mark AM_C of the upper wafer UW using the camera 232, and measures the alignment mark AM_C of the lower wafer LW using the camera 235. Then, the control device 20 calculates a correction value for the overlay misalignment of the shift component based on the measurement results of the alignment marks AM_C of the lower wafer LW and the upper wafer UW.

[0082] Next, the control device 20 executes the bonding process as shown in (8) of Fig. 19. Specifically, first, the control device 20 performs horizontal alignment based on the correction values ​​calculated by the rotational alignment and the shift alignment and the calibration result of the camera origin, and adjusts the relative position between the lower stage 230 and the upper stage 233. Then, the control device 20 moves the position of the upper stage 233 closer to the lower stage 230 to adjust the distance between the upper wafer UW and the lower wafer LW. Then, the control device 20 lowers the pressing pin 244 to press down the center of the upper wafer UW, bringing the surfaces of the upper wafer UW into contact with the surfaces of the lower wafer LW.

[0083] The control device 20 then releases the upper wafer UW from the upper stage 243, sequentially from the inside to the outside. The upper wafer UW then drops onto the lower wafer LW, and the surfaces of the upper wafer UW and the lower wafer LW are bonded together. Specifically, van der Waals forces (intermolecular forces) are generated between the modified bonding surfaces of the upper wafer UW and the modified bonding surfaces of the lower wafer LW, bonding the contacting portions of the upper wafer UW and the lower wafer LW together. Furthermore, because the bonding surfaces of the upper wafer UW and the lower wafer LW are hydrophilized, hydrophilic groups in the contacting portions of the upper wafer UW and the lower wafer LW hydrogen bond together (intermolecular forces), further firmly bonding the contacting portions of the upper wafer UW and the lower wafer LW together.

[0084] [2-2-2] Wafer magnification correction method 20 is a flowchart showing an example of steps related to correction of wafer magnification in the bonding process of the bonding apparatus 2 according to the second embodiment. Hereinafter, a method of correcting wafer magnification in the second embodiment will be described with reference to FIG.

[0085] First, the pre-processing of each of the upper wafer UW and the lower wafer LW is performed. Specifically, the exposure processing of the upper wafer UW is performed (S210). Correction value information 111a including the correction value of the wafer magnification used in the exposure processing of S210 is stored in the server 3 (S211). Similarly, the exposure processing of the lower wafer LW is performed (S220). Correction value information 111b including the correction value of the wafer magnification used in the exposure processing of S220 is stored in the server 3 (S221).

[0086] When the pre-processing of the upper wafer UW and the lower wafer LW is completed (S230), the server 3 calculates a correction value for the wafer magnification in the bonding process based on the correction value information 111a and 111b stored in S211 and S221, respectively (S231). Specifically, in S231, the server 3 calculates the difference between the processing value of the wafer magnification for the upper wafer UW (alignment correction value + overlay correction value) and the processing value of the wafer magnification for the lower wafer LW (alignment correction value + overlay correction value). The server 3 then feeds forward the calculation result of S231 to the bonding apparatus 2. Note that in this specification, an "alignment correction value" refers to a correction value for overlay misalignment calculated based on the measurement results of the alignment mark AM. An "overlay correction value" refers to a correction value calculated based on the result of exposure OL measurement, for example, in advanced process control performed during large-scale lot processing.

[0087] Thereafter, the bonding apparatus 2 executes the bonding process using the correction value of the wafer magnification calculated in S231. That is, the bonding apparatus 2 determines the correction value of the wafer magnification in the bonding process based on the alignment results of the exposure processes of the upper wafer UW and the lower wafer LW in the previous process. In other words, in the bonding process, the bonding apparatus 2 controls the stress device 231 based on the difference between the alignment results of the exposure processes of the upper wafer UW and the lower wafer LW in the previous process to deform the lower stage 230 ((2) in FIG. 19). Other operations in the bonding process are the same as those described using FIG. 19.

[0088] In the above description, the case where the correction value of the wafer magnification in the bonding process is determined using the server 3 has been exemplified, but the present invention is not limited to this. The exposure apparatus 1 or the bonding apparatus 2 may calculate the correction value of the wafer magnification in the bonding process. In this case, information regarding the correction value of the wafer magnification is exchanged between the exposure apparatus 1 and the bonding apparatus 2.

[0089] [2-3] Effects of the second embodiment 3, the bonding apparatus 2 may have fewer measurement points for the alignment marks AM than the exposure apparatus 1. Furthermore, the bonding apparatus 2 may not have a means for measuring the wafer magnification (i.e., the size of the wafer) in alignment measurement.

[0090] Therefore, in the semiconductor manufacturing system PS according to the second embodiment, the exposure apparatus 1 feeds forward information about the wafer size obtained by alignment measurement (correction value information 111) to the bonding apparatus 2. Then, the bonding apparatus 2 uses, in the bonding process, a correction value for the wafer magnification based on the feedforward correction value information 111. As a result, the bonding apparatus 2 according to the second embodiment can suppress the occurrence of overlay misalignment of the wafer magnification during the bonding process, and can improve the yield of semiconductor devices.

[0091] [2-4] Modification of the second embodiment Changes in the size of a wafer held on a stage (e.g., by vacuum suction), i.e., changes in wafer magnification, tend to be affected by the film (film stress) on the wafer surface. In other words, there is a correlation between the amount of wafer warpage and wafer magnification. Therefore, in a modified example of the second embodiment, the warpage of each of the upper wafer UW and the lower wafer LW is measured in a pre-process, and a correction value for the wafer magnification in the bonding process is determined based on the amount of warpage.

[0092] 21 is a flowchart showing an example of steps related to correction of wafer magnification in the bonding process of the bonding apparatus 2 according to the modified example of the second embodiment. Hereinafter, a method of correcting wafer magnification in the modified example of the second embodiment will be described with reference to FIG.

[0093] First, the upper wafer UW and the lower wafer LW are subjected to respective pre-processing steps. Specifically, an exposure process is performed on the upper wafer UW (S210). Thereafter, the warpage of the upper wafer UW is measured (S240), and the measurement results of S240 are stored in the server 3 as wafer warpage information (S241). Similarly, an exposure process is performed on the lower wafer LW (S220). Thereafter, the warpage of the lower wafer LW is measured (S250), and the measurement results of S250 are stored in the server 3 as wafer warpage information (S251). Note that the timings at which the processes of S240 and S250 are performed are preferably such that the film stresses on the surfaces of the upper wafer UW and the lower wafer LW (i.e., the amount of wafer warpage) are equivalent to those before the bonding process is performed.

[0094] Then, when the pre-processing of each of the upper wafer UW and the lower wafer LW is completed (S230), the server 3 calculates a correction value for the wafer magnification in the bonding process based on the wafer warpage information stored in S241 and S251 (S260). In S260, the server 3 uses a relational expression between the wafer warpage and the wafer magnification to calculate the correction value for the wafer magnification. This relational expression may be calculated based on measurement results of the warpage and wafer magnification of multiple wafers, or may be calculated based on simulation results. Then, the server 3 feeds forward the calculation result of S260 to the bonding apparatus 2.

[0095] Thereafter, the bonding apparatus 2 performs the bonding process using the correction value of the wafer magnification calculated in S261. That is, the bonding apparatus 2 determines the correction value of the wafer magnification in the bonding process based on the amount of warpage of each of the upper wafer UW and the lower wafer LW in the previous process. More specifically, in the bonding process, the bonding apparatus 2 controls the stress device 231 based on the difference in the amount of warpage of each of the upper wafer UW and the lower wafer LW in the previous process to deform the lower stage 230 ((2) in FIG. 19). Other operations in the bonding process are the same as those described using FIG. 19.

[0096] The semiconductor device manufacturing method according to the modified example of the second embodiment described above can suppress the occurrence of misalignment during the bonding process, as in the second embodiment, and can improve the yield of semiconductor devices.

[0097] [3] Third embodiment The third embodiment relates to a semiconductor manufacturing system PS that corrects alignment errors of shift components during bonding processing in accordance with the wafer magnifications of the lower wafer LW and the upper wafer UW. Details of the semiconductor manufacturing system PS according to the third embodiment will be described below.

[0098] [3-1] Manufacturing method of semiconductor device An example of a specific process using the semiconductor manufacturing system PS will be described below as a method for manufacturing a semiconductor device according to the third embodiment. That is, a semiconductor device is manufactured using the bonding method (bonding process) according to the third embodiment described below.

[0099] [3-1-1] How to create a correction formula 22 is a flowchart showing an example of a method for creating a correction formula for overlay misalignment used in the joining device 2 according to the third embodiment. Hereinafter, the method for creating a correction formula for overlay misalignment in the third embodiment will be described with reference to FIG.

[0100] First, an upper wafer UW and a lower wafer LW are prepared with different wafer magnifications in a predetermined process (S300). Two or more wafer magnification conditions are preferably prepared, and as many conditions as possible are prepared. The predetermined process corresponds, for example, to an exposure process of the wiring layers near the surfaces of the upper wafer UW and the lower wafer LW.

[0101] Next, the bonding apparatus 2 measures the alignment marks AM of each of the upper wafer UW and the lower wafer LW at multiple measurement points (S301). When measuring the alignment marks AM, the bonding apparatus 2 uses wafer magnification correction using the stress apparatus 231. That is, when measuring the alignment marks AM, the lower wafer LW is in a state in which the wafer magnification has been corrected. Then, the alignment measurement results are stored in, for example, the server 3.

[0102] Next, the server 3 calculates the amount of change in the measurement coordinates for each measurement point based on the multiple wafer magnification setting values ​​prepared in S300 and the alignment measurement results in S301 (S302).

[0103] Next, the server 3 creates a relational expression between the measurement coordinates and the amount of change in the measurement coordinates for each of the upper wafer UW and the lower wafer LW, in association with the wafer magnification (S303). This relational expression (correction expression) is calculated, for example, by functionally approximating the calculation result of S302 in a Cartesian coordinate system. The correction expression for the lower wafer LW is associated with the correction value of the magnification component used in the exposure process of the lower wafer LW and indicates the relationship between the measurement coordinates of the alignment marks AM on the lower wafer LW and the measurement error between the measurement coordinates and the center position of the lower wafer LW. The correction expression for the upper wafer UW is associated with the correction value of the magnification component used in the exposure process of the upper wafer UW and indicates the relationship between the measurement coordinates of the alignment marks AM on the upper wafer UW and the measurement error between the measurement coordinates and the center position of the upper wafer UW. The relational expressions between the measurement coordinates and the amount of change in the measurement coordinates at each wafer magnification for the upper wafer UW and the lower wafer LW may be stored in the server 3 or transferred to the bonding apparatus 2.

[0104] [3-1-2] Joining process 23 is a flowchart showing an example of the joining process of the joining device 2 according to the third embodiment. Hereinafter, the flow of the joining process of the joining device 2 according to the third embodiment will be described with reference to FIG.

[0105] When the bonding apparatus 2 is notified by the pre-processing apparatus for the bonding process that the pre-processing of the wafers has been completed, the bonding apparatus 2 starts the bonding process (START).

[0106] First, the bonding apparatus 2 acquires the correction value information 111 for each of the upper wafer UW and the lower wafer LW (S310). The bonding apparatus 2 may acquire the correction value information 111 from the server 3 or from the exposure apparatus 1.

[0107] Next, the bonding apparatus 2 deforms the lower stage 230 based on the correction value information 111 (S311). The process of S317 is similar to the process of (2) in Fig. 19 described in the second embodiment.

[0108] Next, the bonding apparatus 2 loads the upper wafer UW and the lower wafer LW (S312). The process of S312 is the same as the process of (3) in FIG.

[0109] Next, the bonding apparatus 2 performs rotational alignment (S313). The process of S313 is similar to the processes (4) and (5) of Fig. 19 described in the second embodiment.

[0110] Next, the joining device 2 executes the origin alignment process for the cameras 242 and 245 (S314). The process of S314 is the same as the process of (6) in Fig. 19 described in the second embodiment.

[0111] Next, the joining device 2 performs shift alignment (S315). The process of S315 is similar to the process of (7) in Fig. 19 described in the second embodiment.

[0112] Next, the bonding apparatus 2 corrects the shift alignment correction amount using the relational expression created in S303 (S316). Specifically, the control apparatus 20 acquires each correction value for the wafer magnification of the upper wafer UW and the wafer magnification of the lower wafer LW from the correction value information 111. Then, the control apparatus 20 calculates the amount of error in the shift alignment measurement result for the upper wafer UW by substituting the measurement coordinates of the alignment mark AM_C of the upper wafer UW into the relational expression corresponding to the wafer magnification of the upper wafer UW created in S303. Similarly, the control apparatus 20 calculates the amount of error in the shift alignment measurement result for the lower wafer LW by substituting the measurement coordinates of the alignment mark AM_C of the lower wafer LW into the relational expression corresponding to the wafer magnification of the lower wafer LW created in S303. Then, the control apparatus 20 calculates the amount of error in the shift alignment measurement result for the upper wafer UW and the lower wafer LW, taking into account the amount of error in the shift alignment measurement results for each of the upper wafer UW and the lower wafer LW. The "amount of error in the shift alignment measurement results" refers to the amount of deviation between the coordinates of the wafer center obtained from the shift alignment measurement results and the actual position of the wafer center. When the position of the wafer center is estimated from the measurement results of alignment mark AM_C, the "error in the shift alignment measurement results" can occur depending on the distance between the measurement coordinates of alignment mark AM_C and the position of the wafer center, and the magnitude of the wafer magnification.

[0113] In other words, the control device 20 adjusts the relative positions of the first stage and the second stage based on the measurement results of the alignment mark AM_C of the lower wafer LW, the measurement results of the alignment mark AM_C of the upper wafer UW, the correction equation associated with the lower wafer LW, and the correction equation associated with the upper wafer UW. Specifically, the control device 10 adjusts the relative positions of the first stage and the second stage based on a numerical value obtained by adding the measurement error calculated using the correction equation associated with the lower wafer LW to the measurement result of the alignment mark AM_C of the lower wafer LW, and a numerical value obtained by adding the measurement error calculated using the correction equation associated with the upper wafer UW to the measurement result of the alignment mark AM_C of the upper wafer UW. Note that the processes of S315 and S316 may be integrated.

[0114] Next, the bonding apparatus 2 bonds the upper wafer UW and the lower wafer LW together (S317). The process of S317 is the same as the process of (8) in FIG. 19 described in the second embodiment.

[0115] Next, the bonding apparatus 2 unloads the bonded wafer BW (S318).

[0116] When the bonded wafer BW is unloaded, the bonding apparatus 2 ends the bonding process (end).

[0117] In addition, in S316, if the value of the wafer magnification acquired from the correction value information 111 does not match the wafer magnification associated with the relational expression created in S303, the control device 20 may use a relational expression created with a closer wafer magnification. Furthermore, when creating the correction value, the control device 20 may create a relational expression that predicts the relationship between the wafer magnification and the amount of error in the shift alignment measurement result based on multiple relational expressions, and use the relational expression in S316.

[0118] [3-1-3] Specific examples FIG. 24 is a schematic diagram showing an example of multiple wafers used to create a correction equation for overlay misalignment used in the bonding apparatus 2 according to the third embodiment. FIG. 24 illustrates wafers W1 to W5 on which exposure processing has been performed with different wafer magnifications. The wafer magnifications of wafers W1, W2, W3, W4, and W5 are set to −2 ppm, −1 ppm, 0 ppm, +1 ppm, and +2 ppm, respectively. As shown in the figure, when the wafer magnification is changed, the size of multiple shots within the wafer surface changes. Because patterns are formed on wafers W1 to W5 using the same mask, alignment marks AM are positioned at the same coordinates. However, because wafer magnifications differ for wafers W1 to W5, the positions of alignment marks AM on the actual wafers shift depending on the wafer magnification. Specifically, the smaller the wafer magnification, the closer the alignment marks AM are positioned to the center, and the larger the wafer magnification, the closer the alignment marks AM are positioned to the outer periphery.

[0119] FIG. 25 is a graph showing an example of changes in the amount of shift alignment measurement error before and after creating a correction equation for overlay misalignment in the bonding process of the bonding apparatus 2 according to the third embodiment. FIG. 25 shows the relationship between the wafer X coordinate and the amount of shift measurement error corresponding to the measurement results of wafers W1 to W5. The server 3 obtains measurement results such as those shown in FIG. 25A based on the method for creating the correction equation described in [3-1-1]. The slope of the shift measurement error before correction increases as the wafer magnification increases. In this example, the server 3 calculates a correction equation for the amount of shift alignment measurement error for each of the wafer magnifications of −2 ppm, −1 ppm, 0 ppm, +1 ppm, and +2 ppm. As a result, as shown in FIG. 25B, the slope of the shift measurement error after correction is smaller than that before correction. In other words, shift measurement error can be suppressed regardless of the wafer X coordinate position.

[0120] [3-2] Effects of the third embodiment During shift alignment, the bonding apparatus 2 calculates the shift amount from the measurement result of the alignment mark AM_C at one point on the wafer surface. However, if the wafer magnification fluctuates, the measurement result of the alignment mark AM_C by the bonding apparatus 2 may deviate from the coordinates of the alignment mark AM_C based on the exposure apparatus 1 (measurement error). In other words, variations in wafer magnification may cause fluctuations in the alignment measurement result, which may result in misalignment between the upper wafer UW and the lower wafer LW during the bonding process.

[0121] Therefore, in the third embodiment, the exposure apparatus 1 sends the processing results of the exposure apparatus 1 in the previous process (correction value information 111 including the wafer magnification) to the bonding apparatus 2. Then, the bonding apparatus 2 corrects the measurement error of the shift alignment caused by the wafer magnification based on the processing results of the wafer magnification received from the exposure apparatus 1. In other words, the bonding apparatus 2 according to the third embodiment predicts and corrects the positional deviation amount of the measurement coordinates according to the wafer magnifications of the upper wafer UW and the lower wafer LW.

[0122] As a result, the bonding apparatus 2 according to the third embodiment can reduce the amount of misalignment from the apparatus reference due to the wafer magnification. Therefore, the semiconductor device manufacturing method according to the third embodiment can suppress the occurrence of misalignment during the bonding process, thereby improving the yield of semiconductor devices.

[0123] [3-3] Modification of the third embodiment In the third embodiment, the case where the measurement error is corrected based on the wafer magnification has been exemplified, but the present invention is not limited to this. The bonding apparatus 2 may correct the amount of wafer measurement error based on wafer warpage information. As explained in the second embodiment, the amount of wafer warpage has a correlation with the wafer magnification. Therefore, the bonding apparatus 2 can estimate the amount of correction for the wafer magnification based on the amount of wafer warpage. Therefore, by utilizing the wafer magnification based on the information on the warpage of each of the upper wafer UW and the lower wafer LW, the bonding apparatus 2 can use the relational expression created in S303 and correct the measurement error. Note that a relational expression between the amount of wafer warpage and the amount of measurement error may be created for each of the upper wafer UW and the lower wafer LW. In addition, the bonding apparatus 2 In the third embodiment, when selecting the relational equation to be used, both the amount of warpage of the wafer and the correction value information 111 including the wafer magnification may be used. In the third embodiment, generation of the relational equation for the upper wafer UW, which is relatively less likely to cause measurement error, may be omitted. In this case, both the process related to the formation of the relational equation corresponding to the upper wafer UW and the process related to the correction of measurement error are omitted.

[0124] [4] Fourth embodiment The fourth embodiment relates to a specific example of a semiconductor device to which the semiconductor device manufacturing methods described in the first to third embodiments can be applied. Below, a memory device 4, which is a NAND flash memory, will be described as a specific example of a semiconductor device.

[0125] [4-1] Configuration [4-1-1] Memory device 4 configuration 26 is a block diagram showing an example of the configuration of a memory device 4 according to the fourth embodiment. As shown in FIG. 26, the memory device 4 includes, for example, a memory interface (memory I / F) 40, a sequencer 41, a memory cell array 42, a driver module 43, a row decoder module 44, and a sense amplifier module 45.

[0126] The memory I / F 40 is a hardware interface connected to an external memory controller. The memory I / F 40 performs communication between the memory device 4 and the memory controller in accordance with an interface standard. The memory I / F 40 supports, for example, the NAND interface standard.

[0127] The sequencer 41 is a control circuit that controls the overall operation of the memory device 4. Based on commands received via the memory I / F 40, the sequencer 41 controls the driver module 43, the row decoder module 44, the sense amplifier module 45, etc., to execute read operations, write operations, erase operations, etc.

[0128] The memory cell array 42 is a storage circuit including a set of multiple memory cells. The memory cell array 42 includes multiple blocks BLK0 to BLKn (n is an integer equal to or greater than 1). The block BLK is used, for example, as a unit for erasing data. The memory cell array 42 is also provided with multiple bit lines and multiple word lines. Each memory cell is associated with, for example, one bit line and one word line. Each memory cell is identified based on an address that identifies the word line WL and an address that identifies the bit line BL.

[0129] The driver module 43 is a driver circuit that generates voltages used in read operations, write operations, erase operations, etc. The driver module 43 is connected to the row decoder module 44 via multiple signal lines. The driver module 43 can change the voltages applied to each of the multiple signal lines based on a page address received via the memory I / F 40.

[0130] The row decoder module 44 is a decoder that decodes a row address received via the memory I / F 40. The row decoder module 44 selects one block BLK based on the decoding result. Then, the row decoder module 44 transfers voltages applied to the multiple signal lines to multiple wirings (such as word lines WL) provided in the selected block BLK.

[0131] The sense amplifier module 45 is a sense circuit that senses data read from a selected block BLK based on the voltage of the bit line BL during a read operation. The sense amplifier module 45 transmits the read data to the memory controller via the memory I / F 40. During a write operation, the sense amplifier module 45 can apply a voltage to each bit line BL according to the data to be written to the memory cell.

[0132] [4-1-2] Circuit configuration of memory cell array 42 Fig. 27 is a circuit diagram showing an example of the circuit configuration of a memory cell array 42 included in a memory device 4 according to the fourth embodiment. Fig. 27 shows one block BLK among a plurality of blocks BLK included in the memory cell array 42. As shown in Fig. 27, the block BLK includes, for example, string units SU0 to SU3.

[0133] Each string unit SU includes multiple NAND strings NS. The NAND strings NS are associated with bit lines BL0 to BLm (m is an integer equal to or greater than 1), respectively. Different column addresses are assigned to the bit lines BL0 to BLm. Each bit line BL is shared by NAND strings NS assigned the same column address across multiple blocks BLK. Each NAND string NS includes, for example, memory cell transistors MT0 to MT7 and select transistors STD and STS.

[0134] Each memory cell transistor MT includes a control gate and a charge storage layer and stores data nonvolatilely. The memory cell transistors MT0 to MT7 of each NAND string NS are connected in series. The control gates of the memory cell transistors MT0 to MT7 are connected to word lines WL0 to WL7, respectively. Each of the word lines WL0 to WL7 is provided for each block BLK. A group of multiple memory cell transistors MT connected to a common word line WL in the same string unit SU is called, for example, a "cell unit CU." When each memory cell transistor MT stores one bit of data, the cell unit CU stores "one page of data." The cell unit CU can have a storage capacity of two or more pages of data depending on the number of bits of data stored in the memory cell transistors MT.

[0135] Each of the select transistors STD and STS is used to select a string unit SU. The drain of the select transistor STD is connected to the associated bit line BL. The source of the select transistor STD is connected to one end of the memory cell transistors MT0 to MT7 connected in series. The gates of the select transistors STD included in the string units SU0 to SU3 are connected to select gate lines SGD0 to SGD3, respectively. The drain of the select transistor STS is connected to the other end of the memory cell transistors MT0 to MT7 connected in series. The source of the select transistor STS is connected to a source line SL. The gate of the select transistor STS is connected to a select gate line SGS. The source line SL is shared by, for example, multiple blocks BLK.

[0136] [4-1-3] Structure of memory device 4 An example of the structure of the memory device 4 according to the fourth embodiment will be described below. In the fourth embodiment, the X direction corresponds to the extension direction of the word lines WL, the Y direction corresponds to the extension direction of the bit lines BL, and the Z direction corresponds to the vertical direction with respect to the surface of the semiconductor substrate used to form the memory device 4.

[0137] FIG. 28 is a perspective view showing an example of the structure of a memory device 4 according to the fourth embodiment. As shown in FIG. 28, the memory device 4 includes a memory chip MC and a CMOS chip CC. The lower surface of the memory chip MC corresponds to the surface of the lower wafer LW. The upper surface of the CMOS chip CC corresponds to the surface of the upper wafer UW. The memory chip MC includes, for example, a memory region MR, lead-out regions HR1 and HR2, and a pad region PR1. The CMOS chip CC includes, for example, a sense amplifier region SR, a peripheral circuit region PERI, transfer regions XR1 and XR2, and a pad region PR2.

[0138] The memory region MR includes a memory cell array 42. The lead-out regions HR1 and HR2 include wiring used for connecting between stacked wiring provided in the memory chip MC and a row decoder module 44 provided in the CMOS chip CC. The pad region PR1 includes pads used for connecting between the memory device 4 and a memory controller. The lead-out regions HR1 and HR2 sandwich the memory region MR in the X direction. The pad region PR1 is adjacent to the memory region MR and each of the lead-out regions HR1 and HR2 in the Y direction.

[0139] The sense amplifier region SR includes a sense amplifier module 45. The peripheral circuit region PERI includes a sequencer 41, a driver module 43, etc. The transfer regions XR1 and XR2 include a row decoder module 44. The pad region PR2 includes a memory I / F 40. The sense amplifier region SR and the peripheral circuit region PERI are arranged adjacent to each other in the Y direction and overlap with the memory region MR. The transfer regions XR1 and XR2 sandwich the set of the sense amplifier region SR and the peripheral circuit region PERI in the X direction and overlap with the lead-out regions HR1 and HR2, respectively. The pad region PR2 overlaps with the pad region PR1 of the memory chip MC.

[0140] The memory chip MC has a plurality of bonding pads BP at the bottom of each of the memory region MR, the lead-out regions HR1 and HR2, and the pad region PR1. The bonding pads BP of the memory region MR are connected to the associated bit lines BL. The bonding pads BP of the lead-out region HR are connected to the associated wiring (e.g., word lines WL) of the stacked wiring provided in the memory region MR. The bonding pads BP of the pad region PR1 are connected to pads (not shown) provided on the upper surface of the memory chip MC. The pads provided on the upper surface of the memory chip MC are used, for example, for connection between the memory device 4 and a memory controller.

[0141] The CMOS chip CC has multiple bonding pads BP on the top of each of the sense amplifier region SR, peripheral circuit region PERI, transfer regions XR1 and XR2, and pad region PR2. The bonding pads BP of the sense amplifier region SR overlap with the bonding pads BP of the memory region MR. The bonding pads BP of the transfer regions XR1 and XR2 overlap with the bonding pads BP of the lead-out regions HR1 and HR2, respectively. The bonding pads BP of the pad region PR1 overlap with the bonding pads BP of the pad region PR2.

[0142] The memory device 4 has a structure in which the bottom surface of the memory chip MC and the top surface of the CMOS chip CC are bonded together. Of the multiple bonding pads BP provided on the memory device 4, two bonding pads BP facing each other between the memory chip MC and the CMOS chip CC are bonded together and thereby electrically connected. This electrically connects the circuits in the memory chip MC and the CMOS chip CC via the bonding pads BP. The pair of two bonding pads BP facing each other between the memory chip MC and the CMOS chip CC may have a boundary or may be integrated.

[0143] (Plane layout of memory cell array 42) FIG. 29 is a plan view showing an example of a planar layout of a memory cell array 42 included in a memory device 4 according to the fourth embodiment. FIG. 29 shows a region including one block BLK in a memory region MR. As shown in FIG. 29, the memory device 4 includes, for example, a plurality of slits SLT, a plurality of slits SHE, a plurality of memory pillars MP, a plurality of bit lines BL, and a plurality of contacts CV. In the memory region MR, the planar layout described below is repeatedly arranged in the Y direction.

[0144] Each slit SLT has a structure in which, for example, an insulating material is embedded. Each slit SLT insulates adjacent wirings (for example, word lines WL0 to WL7 and select gate lines SGD and SGS) via the slit SLT. Each slit SLT has a portion extending along the X direction, and crosses the memory region MR and the lead-out regions HR1 and HR2 along the X direction. A plurality of slits SLT are aligned in the Y direction. The regions partitioned by the slits SLT correspond to blocks BLK.

[0145] Each slit SHE has a structure in which an insulating material is embedded, for example. Each slit SHE insulates adjacent wirings (at least the select gate lines SGD) via the slit SLT. Each slit SHE has a portion extending along the X direction and crosses the memory region MR. A plurality of slits SHE are aligned in the Y direction. In this example, three slits SHE are arranged between adjacent slits SLT. A plurality of regions separated by the slits SLT and SHE correspond to the string units SU0 to SU3, respectively.

[0146] Each memory pillar MP functions as, for example, one NAND string NS. The memory pillars MP are arranged in a staggered pattern of, for example, 19 rows in the region between two adjacent slits SLT. Counting from the top of the page, one slit SHE overlaps the fifth row of memory pillar MP, the tenth row of memory pillar MP, and the fifteenth row of memory pillar MP.

[0147] Each bit line BL has a portion extending in the Y direction and crosses an area where multiple blocks BLK are provided along the Y direction. The multiple bit lines BL are aligned in the X direction. Each bit line BL is arranged so as to overlap at least one memory pillar MP for each string unit SU. In this example, two bit lines BL overlap each memory pillar MP.

[0148] Each contact CV is provided between one of the bit lines BL overlapping the memory pillar MP and the memory pillar MP. The contact CV electrically connects the memory pillar MP and the bit line BL. Note that the contact CV between the memory pillar MP overlapping the slit SHE and the bit line BL is omitted.

[0149] (Cross-sectional structure of memory cell array 42) FIG. 30 is a cross-sectional view showing an example of the cross-sectional structure of a memory cell array 42 included in a memory device 4 according to the fourth embodiment. FIG. 30 shows a cross section along the Y direction, including memory pillars MP and slits SLT in a memory region MR. Note that the Z direction in FIG. 30 points downward on the paper, but in the description of FIG. 30, the upper side of the paper will be referred to as "upper" and the lower side of the paper will be referred to as "lower." As shown in FIG. 30, the memory device 4 includes, for example, insulator layers 50-57, conductor layers 60-66, and contacts V1 and V2.

[0150] The insulator layer 50 is provided, for example, on the bottom layer of the memory chip MC. A conductor layer 60 is provided on the insulator layer 50. An insulator layer 51 is provided on the conductor layer 60. A conductor layer 61 and an insulator layer 52 are alternately provided on the insulator layer 51. An insulator layer 53 is provided on the topmost conductor layer 61. A conductor layer 62 and an insulator layer 54 are alternately provided on the insulator layer 53. An insulator layer 55 is provided on the topmost conductor layer 62. A conductor layer 63 and an insulator layer 56 are alternately provided on the insulator layer 55. An insulator layer 57 is provided on the topmost conductor layer 63. A conductor layer 64 is provided on the insulator layer 57. A contact V1 is provided on the conductor layer 64. A conductor layer 65 is provided on the contact V1. A contact V2 is provided on the conductive layer 65. A conductive layer 66 is provided on the contact V2. Hereinafter, the wiring layers on which the conductive layers 64, 65, and 66 are provided will be referred to as "M0," "M1," and "M2," respectively.

[0151] Each of the conductive layers 60, 61, 62, and 63 is formed, for example, in a plate shape extending along the XY plane. The conductive layer 64 is formed, for example, in a line shape extending in the Y direction. The conductive layers 60, 61, and 63 are used as a source line SL, a select gate line SGS, and a select gate line SGD, respectively. The multiple conductive layers 62 are used, in order from the conductive layer 60 side, as word lines WL0 to WL7, respectively. The conductive layer 64 is used as a bit line BL. The contacts V1 and V2 are formed in a columnar shape. The conductive layers 64 and 65 are connected via a contact V1. The conductive layers 65 and 66 are connected via a contact V2. The conductive layer 65 is, for example, a wiring formed in a line shape extending in the X direction. The conductive layer 66 contacts the interface of the memory chip MC and is used as a bonding pad BP. The conductive layer 66 includes, for example, copper.

[0152] The slit SLT has a plate-like portion extending along the XZ plane, and separates the insulator layers 51-56 and the conductor layers 61-63. Each memory pillar MP extends along the Z direction and penetrates the insulator layers 51-56 and the conductor layers 61-63. Each memory pillar MP includes, for example, a core member 70, a semiconductor layer 71, and a stacked film 72. The core member 70 is an insulator extending along the Z direction. The semiconductor layer 71 covers the core member 70. The lower part of the semiconductor layer 71 is in contact with the conductor layer 60. The stacked film 72 covers the side surface of the semiconductor layer 71. A contact CV is provided on the semiconductor layer 71. The conductor layer 64 is in contact with the contact CV.

[0153] In the illustrated region, a contact CV corresponding to one of the two memory pillars MP is shown. A contact CV is connected to the memory pillar MP to which the contact CV is not connected in the region in question in a region not illustrated. The portion where the memory pillar MP intersects with the multiple conductor layers 61 functions as a select transistor STS. The portion where the memory pillar MP intersects with the multiple conductor layers 62 functions as a memory cell transistor MT. The portion where the memory pillar MP intersects with the multiple conductor layers 63 functions as a select transistor STD.

[0154] (Cross-sectional structure of memory pillar MP) 31 is a cross-sectional view taken along line XXXI-XXXI in FIG. 30, showing an example of the cross-sectional structure of a memory pillar MP included in the memory device 4 according to the fourth embodiment. FIG. 31 shows a cross section including the memory pillar MP and the conductive layer 62 and parallel to the conductive layer 60. As shown in FIG. 31, the stacked film 72 includes, for example, a tunnel insulating film 73, an insulating film 74, and a block insulating film 75.

[0155] The core member 70 is provided, for example, in the center of the memory pillar MP. The semiconductor layer 71 surrounds the side surface of the core member 70. The tunnel insulating film 73 surrounds the side surface of the semiconductor layer 71. The insulating film 74 surrounds the side surface of the tunnel insulating film 73. The block insulating film 75 surrounds the side surface of the insulating film 74. The conductor layer 62 surrounds the side surface of the block insulating film 75. The semiconductor layer 71 is used as channels (current paths) of the memory cell transistors MT0 to MT7 and the select transistors STD and STS. Each of the tunnel insulating film 73 and the block insulating film 75 contains, for example, silicon oxide. The insulating film 74 is used as a charge storage layer of the memory cell transistor MT and contains, for example, silicon nitride. As a result, each of the memory pillars MP functions as one NAND string NS.

[0156] (Cross-sectional structure of memory device 4) Fig. 32 is a cross-sectional view showing an example of the cross-sectional structure of a memory device 4 according to the fourth embodiment. Fig. 32 shows a cross section including a memory region MR and a sense amplifier region SR, i.e., a cross section including a memory chip MC and a CMOS chip CC. As shown in Fig. 32, the memory device 4 includes a semiconductor substrate 80, conductor layers GC and 81 to 84, and contacts CS and C0 to C3 in the sense amplifier region SR.

[0157] The semiconductor substrate 80 is a substrate used to form the CMOS chip CC. The semiconductor substrate 80 includes a plurality of well regions (not shown). For example, a transistor TR is formed in each of the plurality of well regions. The plurality of well regions are isolated from each other by, for example, STI (Shallow Trench Isolation). A conductor layer GC is provided on the semiconductor substrate 80 via a gate insulating film. The conductor layer GC in the sense amplifier region SR is used as the gate electrode of the transistor TR included in the sense amplifier module 45. A contact C0 is provided on the conductor layer GC. Two contacts CS are provided on the semiconductor substrate 80 corresponding to the source and drain of the transistor TR.

[0158] A conductor layer 81 is provided on each of the contacts CS and C0. A contact C1 is provided on the conductor layer 81. A conductor layer 82 is provided on the contact C1. The conductor layers 81 and 82 are electrically connected via the contact C1. A contact C2 is provided on the conductor layer 82. A conductor layer 83 is provided on the contact C2. The conductor layers 82 and 83 are electrically connected via the contact C2. A contact C3 is provided on the conductor layer 83. A conductor layer 84 is provided on the contact C3. The conductor layers 83 and 84 are electrically connected via the contact C3. Hereinafter, the wiring layers on which the conductor layers 81 to 84 are provided will be referred to as "D0", "D1", "D2", and "D3", respectively.

[0159] The conductive layer 84 contacts the interface of the CMOS chip CC and is used as a bonding pad BP. The conductive layer 84 in the sense amplifier region SR is bonded to the conductive layer 66 (i.e., the bonding pad BP of the memory chip MC) in the memory region MR arranged opposite to it. Each conductive layer 84 in the sense amplifier region SR is electrically connected to one bit line BL. The conductive layer 84 includes, for example, copper.

[0160] In the memory device 4, the wiring layer D3 of the CMOS chip CC and the wiring layer M2 of the memory chip MC are adjacent to each other by bonding the memory chip MC and the CMOS chip CC. The semiconductor substrate 80 corresponds to the back side of the upper wafer UW, and the wiring layer D3 corresponds to the front side of the upper wafer UW. The insulator layer 50 corresponds to the back side of the lower wafer LW, and the wiring layer M2 corresponds to the front side of the lower wafer LW. The semiconductor substrate used to form the memory chip MC is removed during processes such as pad formation after the bonding process.

[0161] [4-2] Effects of the fourth embodiment As described above, the memory device 4 includes, for example, a memory chip MC including a structure in which memory cells are stacked three-dimensionally, and a CMOS chip CC including other control circuits. Between the memory chip MC and the CMOS chip CC, the memory chip MC tends to have greater wafer-to-wafer variation in wafer magnification. Specifically, the memory chip MC includes a highly stacked memory cell array 42, which can lead to greater variation in wafer warpage and thus wafer magnification. On the other hand, the shot arrangement of the CMOS chip CC is closer to an ideal lattice based on the exposure tool. Therefore, when a bonding process is performed, it is preferable that the wafer on which the memory chip MC is formed be assigned to the lower wafer LW, which allows for wafer magnification correction, and the wafer on which the CMOS chip CC is formed be assigned to the upper wafer UW. This allows each of the first to third embodiments to improve the yield of the memory device 4.

[0162] In the wiring layer near the bonding surface in the pre-processing of the memory chip MC, for example, the tolerance for misalignment in the process of the wiring layer M1 is narrow. For example, a conductor layer 65 extending in the X direction is formed on the wiring layer M1. The contact V2 connected to the wiring layer M1 is formed so as to overlap the conductor layer 65. That is, there is a margin of error in the X direction for the overlap in the process of forming the contact V2, but not in the Y direction. Therefore, it is preferable to use the Y-priority mode in the exposure process for forming the contact V2 in this example. In this way, by using the exposure apparatus 1 according to the first embodiment during the manufacturing of the memory device 4, the influence of the XY difference in wafer magnification can be suppressed, and the yield of semiconductor devices can be improved.

[0163] [5] Other In the embodiments, the flowcharts used to explain the operations are merely examples. The order of the operations described using the flowcharts may be rearranged as possible, other processes may be added, or some processes may be omitted. In the above-described embodiments, the case where alignment correction is applied to the lower wafer LW placed (held) on the lower stage 230 and then bonded is described as an example. However, this is not limiting. The alignment correction in the bonding process may be applied to the upper wafer UW placed (held) on the upper stage 233, or may be applied to both the upper wafer UW held on the upper stage 233 and the lower wafer LW held on the lower stage 230. In this specification, a microprocessing unit (MPU), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or the like may be used instead of a CPU. Furthermore, each of the processes described in the embodiments may be realized by dedicated hardware. The processes described in the embodiments may be a mixture of processes executed by software and processes executed by hardware, or only one of them may be used.

[0164] In this specification, "connection" refers to electrical connection and does not exclude the presence of another element between them. "Electrically connected" may refer to an insulator as long as it functions similarly to an electrically connected structure. "Columnar" refers to a structure provided in a hole formed during a manufacturing process. "Planar view" corresponds to viewing an object in a direction perpendicular to the surface of the semiconductor substrate 80, for example. "Region" may be considered to be a configuration contained by the semiconductor substrate 80 of the CMOS chip CC. For example, if the semiconductor substrate 80 is defined as including a memory region MR, the memory region MR is associated with the region above the semiconductor substrate 80. The bonding pad BP may also be referred to as "bonding metal." The camera 144 of the exposure apparatus 1 may be configured with a separate optical system (microscope) and a light-receiving sensor. Each of the cameras 144, 232, and 235 may be referred to as a "measuring device" as long as it is capable of measuring the alignment mark AM. In this specification, "overlay misalignment" may be rephrased as "positional misalignment."

[0165] The configuration described in the fourth embodiment is merely an example, and the configuration of the memory device 4 is not limited thereto. The circuit configuration, planar layout, and cross-sectional structure of the memory device 4 may be modified as appropriate depending on the design of the memory device 4. For example, although the fourth embodiment illustrates a case in which the memory chip MC is provided on the CMOS chip CC, the CMOS chip CC may be provided on the memory chip MC. Although the example illustrates a case in which the memory chip MC is assigned to the lower wafer LW and the CMOS chip CC is assigned to the upper wafer UW, the memory chip MC may be assigned to the upper wafer UW and the CMOS chip CC may be assigned to the lower wafer LW. When applying the manufacturing methods described in the first to third embodiments, it is preferable to assign a wafer with large variations in wafer magnification to the lower wafer LW. This can suppress misalignment during the bonding process, thereby suppressing defects caused by misalignment.

[0166] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the inventions and their equivalents as defined in the claims. [Explanation of symbols]

[0167] 1... exposure apparatus, 2... bonding apparatus, 3... server, 4... memory device, 10... control apparatus, 11... storage device, 110... exposure recipe, 111... correction value information, 12... transport apparatus, 13... communication device, 14... exposure unit, 140... wafer stage, 141... reticle stage, 142... light source, 143... projection optical system, 144... camera, 20... control apparatus, 21... transport apparatus, 22... communication device, 23... bonding unit, 230... lower stage, 231... stress device, 232... camera, 233... upper stage, 234... pressure pin, 235... camera, 236... common target, 30... CPU, 31... ROM, 32... RAM, 33... storage device, 34... communication device, 40... memory interface 1. Interface, 41...sequencer, 42...memory cell array, 43...driver module, 44...row decoder module, 45...sense amplifier module, 50-57...insulating layer, 50...insulating layer, 51-57...insulating layer, 60-66...conductor layer, 70...core member, 71...semiconductor layer, 72...laminated film, 73...tunnel insulating film, 74...insulating film, 75...block insulating film, 80...semiconductor substrate, 81-84...conductor layer, C0-C3, V1, V2...contacts, M0-M2, D0-D3...wiring layer, BLK...block, SU...string unit, MT...memory cell transistor, TR...transistor, BL...bit line, WL...word line, SGD, SGS...select gate line

Claims

1. An exposure apparatus that exposes a substrate with illumination light via a projection optical system, a stage for holding the substrate; a measurement device that measures at least three alignment marks on the substrate; a control device that moves the stage based on the measurement result of the measurement device and controls an exposure position relative to the substrate, The control device, in the exposure processing of the substrate, calculating a first correction coefficient corresponding to a positional deviation of a magnification component in a first direction and a second correction coefficient corresponding to a positional deviation of a magnification component in a second direction intersecting with the first direction based on the measurement results of the at least three alignment marks; when a first setting is applied, the first correction coefficient is used to correct a positional deviation of a magnification component in the first direction, and a third correction coefficient based on the first correction coefficient is used to correct a positional deviation of a magnification component in the second direction; when the second setting is applied, a fourth correction coefficient based on the second correction coefficient is used to correct the positional deviation of the magnification component in the first direction, and the second correction coefficient is used to correct the positional deviation of the magnification component in the second direction. Exposure device.

2. the first setting includes setting a ratio between the first correction coefficient and the third correction coefficient, the second setting includes setting a ratio between the second correction coefficient and the fourth correction coefficient.

2. The exposure apparatus according to claim 1.

3. The control device, in the exposure process, calculating a fifth correction coefficient corresponding to a positional deviation of the orthogonality component in the first direction and a sixth correction coefficient corresponding to a positional deviation of the orthogonality component in the second direction based on the measurement results of the at least three alignment marks; when the first setting is applied, the fifth correction coefficient is used to correct a positional deviation of the orthogonality component in the first direction, and a seventh correction coefficient based on the fifth correction coefficient is used to correct a positional deviation of the orthogonality component in the second direction; when the second setting is applied, an eighth correction coefficient based on the sixth correction coefficient is used to correct the positional deviation of the orthogonality component in the first direction, and the sixth correction coefficient is used to correct the positional deviation of the orthogonality component in the second direction.

3. The exposure apparatus according to claim 1.

4. the first setting includes setting a ratio between the fifth correction coefficient and the seventh correction coefficient, the second setting includes setting a ratio between the sixth correction coefficient and the eighth correction coefficient.

4. The exposure apparatus according to claim 3.

5. measuring at least three alignment marks on the substrate; calculating a first correction coefficient corresponding to a positional deviation of a magnification component in a first direction and a second correction coefficient corresponding to a positional deviation of a magnification component in a second direction intersecting with the first direction based on measurement results of the at least three alignment marks; exposing the substrate when a first setting is applied to an exposure process on the substrate, using the first correction coefficient for correcting a positional deviation of a magnification component in the first direction, and using a third correction coefficient based on the first correction coefficient for correcting a positional deviation of a magnification component in the second direction; exposing the substrate when a second setting is applied to the exposure process, using a fourth correction coefficient based on the second correction coefficient for correcting a positional deviation of a magnification component in the first direction, and using the second correction coefficient for correcting a positional deviation of a magnification component in the second direction; A method for manufacturing a semiconductor device, comprising:

6. calculating a fifth correction coefficient corresponding to a positional deviation of the orthogonality component in the first direction and a sixth correction coefficient corresponding to a positional deviation of the orthogonality component in the second direction based on measurement results of the at least three alignment marks; when the first setting is applied to the exposure process, using the fifth correction coefficient to correct a positional deviation of an orthogonality component in the first direction, and using a seventh correction coefficient based on the fifth correction coefficient to correct a positional deviation of an orthogonality component in the second direction; when the second setting is applied to the exposure process, using an eighth correction coefficient based on the sixth correction coefficient to correct a positional deviation of an orthogonality component in the first direction, and using the sixth correction coefficient to correct a positional deviation of an orthogonality component in the second direction; The method for manufacturing a semiconductor device according to claim 5 , further comprising:

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