Semiconductor device and manufacturing method thereof

Abstract

To provide a semiconductor device capable of suppressing the characteristic deterioration thereof, and a method for manufacturing the same.SOLUTION: According to an embodiment, a semiconductor device includes a semiconductor layer, a first insulating film provided on the semiconductor layer, gate wiring provided on the first insulating film, and a source electrode provided on the first insulating film. The device further includes a second insulating film provided on the gate wiring and the source electrode and including a portion sandwiched between the gate wiring and the source electrode, and a drain electrode provided below the semiconductor layer. Further, an upper surface of the first insulating film includes a first region where the concentration of phosphorus is a first value and a second region where the concentration of phosphorus is a second value that is higher than the first value. The first region is present between the semiconductor layer and the gate wiring or the source electrode, and the second region is present between the semiconductor layer and the portion of the second insulating film.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] FIELD Embodiments of the present invention relate to a semiconductor device and a manufacturing method thereof. [Background technology]

[0002] A power transistor is provided with a source electrode and a gate wiring electrically connected to the gate electrode. At least a part of the source electrode and the gate wiring is formed on an insulating film. If this insulating film contains phosphorus (P), the phosphorus may adversely affect the performance of the power transistor. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 11-008234 [Patent Document 2] Patent No. 6822089 [Patent Document 3] Japanese Patent Application Publication No. 8-083846 [Patent Document 4] Japanese Patent Application Publication No. 2018-182032 Summary of the Invention [Problem to be solved by the invention]

[0004] A semiconductor device capable of suppressing deterioration of characteristics and a method for manufacturing the same are provided. [Means for solving the problem]

[0005] According to one embodiment, a semiconductor device includes a semiconductor layer, a first insulating film provided on the semiconductor layer, a gate wiring provided on the first insulating film, and a source electrode provided on the first insulating film. The device further includes a second insulating film provided on the gate wiring and the source electrode, including a portion sandwiched between the gate wiring and the source electrode, and a drain electrode provided below the semiconductor layer. Furthermore, an upper surface of the first insulating film includes a first region having a first phosphorus concentration and a second region having a phosphorus concentration of a second value higher than the first value. The first region is located between the semiconductor layer and the gate wiring or the source electrode, and the second region is located between the semiconductor layer and the portion of the second insulating film. [Brief explanation of the drawings]

[0006] [Figure 1] 1 is a cross-sectional view showing the structure of a semiconductor device according to a first embodiment. [Figure 2] 1 is a plan view showing the structure of a semiconductor device according to a first embodiment. [Figure 3] 4 is another cross-sectional view showing the structure of the semiconductor device of the first embodiment. FIG. [Figure 4] 4 is another cross-sectional view showing the structure of the semiconductor device of the first embodiment. FIG. [Figure 5] 4 is another cross-sectional view showing the structure of the semiconductor device of the first embodiment. FIG. [Figure 6] FIG. 3 is another plan view showing the structure of the semiconductor device according to the first embodiment. [Figure 7] FIG. 4 is a cross-sectional view showing the structure of a semiconductor device according to a modified example of the first embodiment. [Figure 8] FIG. 10 is a plan view showing the structure of a semiconductor device according to a modified example of the first embodiment. [Figure 9] FIG. 3 is a cross-sectional view showing the structure of a semiconductor device of a first comparative example of the first embodiment. [Figure 10] FIG. 10 is a cross-sectional view showing the structure of a semiconductor device of a second comparative example of the first embodiment. [Figure 11] 3A to 3C are cross-sectional views showing a first example of a method for manufacturing the semiconductor device according to the first embodiment. [Figure 12] 5A to 5C are cross-sectional views showing a second example of the method for manufacturing the semiconductor device according to the first embodiment. [Figure 13] 5A to 5C are cross-sectional views showing a third example of the method for manufacturing the semiconductor device according to the first embodiment. [Figure 14] 1 is a cross-sectional view (1 / 9) showing details of the method for manufacturing the semiconductor device according to the first embodiment. [Figure 15] 10 is a cross-sectional view (2 / 9) illustrating details of the method for manufacturing the semiconductor device according to the first embodiment. FIG. [Figure 16] 10 is a cross-sectional view (3 / 9) illustrating details of the method for manufacturing the semiconductor device according to the first embodiment. FIG. [Figure 17] 4 is a cross-sectional view (4 / 9) illustrating details of the method for manufacturing the semiconductor device according to the first embodiment. FIG. [Figure 18] 5 is a cross-sectional view (5 / 9) illustrating details of the method for manufacturing the semiconductor device according to the first embodiment. FIG. [Figure 19] 6 is a cross-sectional view (6 / 9) showing details of the method for manufacturing the semiconductor device according to the first embodiment. FIG. [Figure 20] 7 is a cross-sectional view (7 / 9) showing details of the method for manufacturing the semiconductor device according to the first embodiment. FIG. [Figure 21] 8 is a cross-sectional view (8 / 9) showing details of the method for manufacturing the semiconductor device according to the first embodiment. FIG. [Figure 22] 9 is a cross-sectional view (9 / 9) showing details of the method for manufacturing the semiconductor device according to the first embodiment. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0007] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to the drawings. In Figures 1 to 22, the same components are denoted by the same reference numerals, and duplicated descriptions will be omitted.

[0008] (First embodiment) (1) Structure of the semiconductor device Fig. 1 is a cross-sectional view showing the structure of a semiconductor device according to a first embodiment. Fig. 1 shows a cross section of a transistor in the semiconductor device according to the present embodiment. This transistor is, for example, a power MOSFET having a trench gate structure.

[0009] The semiconductor device of this embodiment includes a semiconductor layer 1, a drain electrode 2, a source electrode 3, a plurality of gate trenches GT, and a plurality of contact portions CP. The semiconductor device of this embodiment further includes a gate electrode 4, a field plate electrode 5, an insulating film 11, and an insulating film 12 in each gate trench GT. The semiconductor device of this embodiment further includes an insulating film 13.

[0010] The semiconductor layer 1 includes a drift layer 1a and a drain layer 1b, and further includes a base layer 1c, a contact layer 1d, and a source layer 1e for each contact portion CP shown in FIG.

[0011] The structure of the semiconductor device of this embodiment will be described below with reference to FIG.

[0012] The semiconductor layer 1 is composed of, for example, a plurality of impurity semiconductor layers, which will be described later. The semiconductor layer 1 includes, for example, a semiconductor substrate such as a Si (silicon) substrate. FIG. 1 shows the X and Y directions, which are parallel to and perpendicular to the upper and lower surfaces of the semiconductor layer 1, and the Z direction, which is perpendicular to the upper and lower surfaces of the semiconductor layer 1. In this specification, the +Z direction is treated as the upward direction, and the −Z direction is treated as the downward direction. The −Z direction may or may not coincide with the direction of gravity. The upper and lower surfaces of the semiconductor layer 1 are examples of a first surface and a second surface, respectively.

[0013] The drift layer 1a is an n-type layer provided in the semiconductor layer 1. The drain layer 1b is an n-type layer provided in the semiconductor layer 1 and is arranged below the drift layer 1a. Each base layer 1c is a p-type layer provided in the semiconductor layer 1 and is arranged on the drift layer 1a between the gate trenches GT. Each contact layer 1d is a p+-type layer provided in the semiconductor layer 1 and is arranged on the corresponding base layer 1c between the gate trenches GT. Each source layer 1e is an n-type layer provided in the semiconductor layer 1 and is arranged on the corresponding base layer 1c between the gate trenches GT. The multiple gate trenches GT are formed in the semiconductor layer 1 on the upper surface side of the semiconductor layer 1, extend in the Y direction, and are adjacent to each other in the X direction.

[0014] The p+ and n+ layers contain p- and n-type impurities at concentrations higher than those in the p- and n-type layers, respectively. The p- and n-type layers contain p- and n-type impurities at concentrations higher than those in the p- and n-type layers, respectively.

[0015] The drain electrode 2 is formed on the lower surface of the semiconductor layer 1. The drain electrode 2 is in contact with the drain layer 1b. The drain electrode 2 is a metal layer such as an Al (aluminum) layer or an Au (gold) layer.

[0016] The source electrode 3 is formed on the upper surface of the semiconductor layer 1. The source electrode 3 includes a plurality of contact portions CP, and each contact portion CP is in contact with a corresponding contact layer 1d and source layer 1e. The source electrode 3 is formed of a metal such as aluminum (Al).

[0017] Each gate electrode 4 and each field plate electrode 5 is formed in the corresponding gate trench GT via an insulating film 11. In FIG. 1, each gate electrode 4 is formed on the insulating film 11 and below the insulating film 12, and each field plate electrode 5 is formed in the insulating film 11. Each gate electrode 4 is, for example, a polysilicon layer or a metal layer. Each field plate electrode 5 is, for example, a polysilicon layer or a metal layer. The insulating film 11 is, for example, a SiO2 film (silicon oxide film). The insulating film 12 is, for example, a SiO2 film. In each gate trench GT, the gate electrode 4 and the field plate electrode 5 extend in the Y direction, and the gate electrode 4 is disposed above the field plate electrode 5.

[0018] The insulating film 13 is formed on the upper surface of the semiconductor layer 1 and is sandwiched between the semiconductor layer 1 and the source electrode 3. Each contact portion CP of the source electrode 3 is formed in the insulating film 13. The insulating film 13 is further formed on the insulating films 11 and 12 in each gate trench GT. The insulating film 11 electrically insulates the gate electrode 4 from the field plate electrode 5, and the insulating films 12 and 13 electrically insulate the gate electrode 4 from the source electrode 3. The insulating film 13 is, for example, a SiO2 film. The insulating film 13 may be other than a SiO2 film (for example, a SiON film (silicon oxynitride film)). Further details of the insulating film 13 will be described later.

[0019] 2 is a plan view showing the structure of the semiconductor device of the first embodiment, and shows a cross section taken along line AA' in FIG.

[0020] 2 shows a source electrode 3 and a gate wiring 6 formed on a semiconductor layer 1. The source electrode 3 includes a planar portion 21 having a planar shape and a plurality of linear portions 22 having linear shapes extending from the planar portion 21. The source electrode 3 shown in FIG. 1 shows the planar portion 21 of the source electrode 3.

[0021] The gate wiring 6 includes a pad portion 23 having a planar shape and a plurality of linear wiring portions 24 extending from the pad portion 23. The pad portion 23 of the gate wiring 6 is used, for example, as a bonding pad for electrically connecting a bonding wire. In FIG. 2, each wiring portion 24 of the gate wiring 6 is sandwiched between the planar portion 21 and one linear portion 22 of the source electrode 3 in the Y direction.

[0022] 2 further shows a plurality of gate trenches GT formed in the semiconductor layer 1, similar to FIG. 1. These gate trenches GT extend in the Y direction and are adjacent to one another in the X direction. Similarly to FIG. 1, FIG. 2 further shows a plurality of contact portions CP that are part of the source electrode 3 (planar portion 21). These contact portions CP also extend in the Y direction and are adjacent to one another in the X direction. Each contact portion CP is disposed between two gate trenches GT.

[0023] 2 further shows a plurality of field plate contacts FPC that are part of the source electrode 3 (linear portion 22), and a gate contact GC that is part of the gate wiring 6 (wiring portion 24). Each field plate contact FPC is disposed on one gate trench GT and electrically connects one field plate electrode 5 (FIG. 1) in this gate trench GT to the source electrode 3. Each gate contact GC is disposed on one gate trench GT and electrically connects one gate electrode 4 (FIG. 1) in this gate trench GT to the gate wiring 6. Further details of the field plate contacts FPC and the gate contacts GC will be described later with reference to FIGS. 3 and 4.

[0024] Fig. 3 is another cross-sectional view showing the structure of the semiconductor device of the first embodiment. Fig. 3 shows a cross section taken along line BB' in Fig. 2. While Fig. 1 shows a cross section of the source electrode 3 (planar portion 21), Fig. 3 shows a cross section of the gate wiring 6 (wiring portion 24).

[0025] The gate wiring 6 is formed on the upper surface of the semiconductor layer 1. The gate wiring 6 includes a plurality of gate contacts GC, and FIG. 3 shows one of these gate contacts GC. Each gate contact GC is in contact with the gate electrode 4 in the corresponding gate trench GT. The gate wiring 6 is formed of a metal such as aluminum (Al). An insulating film 13 is sandwiched between the semiconductor layer 1 and the gate wiring 6, and each gate contact GC of the gate wiring 6 is formed in the insulating film 13.

[0026] Fig. 4 is another cross-sectional view showing the structure of the semiconductor device of the first embodiment. Fig. 4 shows a cross section taken along line CC' in Fig. 2. Fig. 4 shows cross sections of the source electrode 3 (linear portion 22) and the gate wiring 6 (wiring portion 24).

[0027] The source electrode 3 includes multiple field plate contacts FPCs, and FIG. 4 shows one of these field plate contacts FPCs. Each field plate contact FPC is in contact with a field plate electrode 5 in a corresponding gate trench GT. An insulating film 13 is sandwiched between the semiconductor layer 1 and the source electrode 3, and each field plate contact FPC of the source electrode 3 is formed within the insulating film 13.

[0028] The semiconductor device of this embodiment further includes an insulating film 14 and an insulating film 15. The insulating film 14 is formed on the insulating film 13. The insulating film 14 is, for example, a SiO2 film. The insulating film 14 may be formed of a material other than a SiO2 film (for example, a SiON film). Further details of the insulating film 14 will be described later. The insulating film 15 is formed on the source electrode 3, the gate wiring 6, and the insulating film 14 in a manner that partially exposes the upper surfaces of the source electrode 3 and the gate wiring 6. The insulating film 15 is, for example, a stacked film including, in order, a SiO2 film, a SiN film (silicon nitride film), and a polyimide film. The insulating film 15 corresponds to a passivation insulating film.

[0029] Next, the structure of the semiconductor device of this embodiment will be described in more detail with reference to FIGS.

[0030] Fig. 5 is another cross-sectional view showing the structure of the semiconductor device of the first embodiment.Fig. 6 is another plan view showing the structure of the semiconductor device of the first embodiment.

[0031] 6, like FIG. 2, shows a source electrode 3 and gate wiring 6 formed on a semiconductor layer 1. However, FIG. 6 shows a plan view obtained by rotating the plan view shown in FIG. 2 by 90 degrees clockwise. The source electrode 3 includes one planar portion 21 having a planar shape and three linear portions 22 extending linearly from the planar portion 21. The gate wiring 6 includes one pad portion 23 having a planar shape and three linear wiring portions 24 extending linearly from the pad portion 23.

[0032] FIG. 5 shows a cross section taken along line D-D' in FIG. 6. Thus, FIG. 5 shows one planar portion 21, one linear portion 22 (source electrode 3), one pad portion 23, and two wiring portions 24 (gate wirings 6). However, for ease of viewing, the cross section shown in FIG. 5 is illustrated with the X-direction width of the planar portion 21 and the X-direction width of the pad portion 23 shorter than those in FIG. 6. In the following description, the insulating films 13 and 14 of this embodiment will be described in detail. Therefore, FIG. 5 omits illustration of other components of the semiconductor device of this embodiment (such as the drain electrode 2, gate electrode 4, field plate electrode 5, insulating film 11, insulating film 12, and gate trench GT). The structures of these omitted components are similar to those described with reference to FIGS. 1 to 4.

[0033] The insulating films 13 and 14 of this embodiment will be described in detail below with reference to Fig. 5. In this description, Fig. 6 will also be referred to as appropriate. The following description is applicable not only to the structures shown in Figs. 5 and 6, but also to the structures shown in Figs. 1 to 4.

[0034] FIG. 5 shows the upper surface S of the underlying insulating film including the insulating films 13 and 14. This underlying insulating film is formed on the semiconductor layer 1 as a base for the source electrode 3 and the gate wiring 6. As described above, the insulating film 14 of this embodiment is formed on the insulating film 13 so as to be provided within the insulating film 13 (see FIG. 4). Therefore, the upper surface S of the underlying insulating film includes the upper surface of the insulating film 13 and the upper surface of the insulating film 14. The underlying insulating film including the insulating films 13 and 14 is an example of a first insulating film. Moreover, the insulating film 13 is an example of a third insulating film, and the insulating film 14 is an example of a fourth insulating film.

[0035] The insulating films 13 and 14 are, for example, SiO2 films. More specifically, the insulating film 13 is, for example, an NSG (Non-doped Silicate Glass) film. This insulating film 13 contains Si (silicon) and O (oxygen), but does not contain any intentionally doped elements. On the other hand, the insulating film 14 is, for example, a PSG (Phospho Silicate Glass) film. This insulating film 14 contains Si (silicon), O (oxygen), and P (phosphorus).

[0036] Therefore, the P concentration in the insulating film 14 is higher than the P concentration in the insulating film 13. In this embodiment, the insulating film 14 contains a high concentration of P atoms, and the insulating film 13 contains no P atoms or only a low concentration of P atoms. For example, if P atoms in the insulating film 14 are diffused into the insulating film 13 for some reason, the insulating film 13 also contains P atoms. The value of the P concentration in the insulating film 13 is, for example, 1.0×10 18 cm -3 The value of the P concentration in the insulating film 14 is, for example, 1.0×10 18 ~1.0×10 22 cm -3 The former value is an example of the first value, and the latter value is an example of the second value. When the insulating film 13 does not contain P atoms, the value of the P concentration in the insulating film 13 is zero.

[0037] The upper surface S of the underlying insulating film in this embodiment includes a region R1 which is the upper surface of the insulating film 13 and a region R2 which is the upper surface of the insulating film 14. In this embodiment, the region R2 contains a high concentration of P atoms, and the region R1 contains no P atoms or a low concentration of P atoms. As described above, the P concentration in the region R1 is, for example, 1.0×10 18 cm -3 On the other hand, the P concentration in the region R2 is, for example, 1.0 × 10 18 ~1.0×10 22 cm -3 Region R1 is an example of the first region, and region R2 is an example of the second region.

[0038] In this embodiment, region R1 is located below the source electrode 3 and below the gate line 6, and region R2 is located between the source electrode 3 and the gate line 6. Therefore, region R1 contacts the lower surface of the source electrode 3 and the lower surface of the gate line 6. On the other hand, region R2 is sandwiched between the source electrode 3 and the gate line 6 in plan view, and contacts the lower surface of the insulating film 15. This also applies to the insulating films 14 and 15 shown in FIG. 4 above.

[0039] In FIG. 5, region R1 exists between semiconductor layer 1 and source electrode 3 or gate wiring 6. Furthermore, insulating film 15 includes a portion sandwiched between source electrode 3 and gate wiring 6, and region R2 exists between semiconductor layer 1 and this portion of insulating film 15. Insulating film 15 is an example of a second insulating film.

[0040] Here, the relationship between the portions of the source electrode 3 and the gate line 6 above the upper surface S and the regions R1 and R2 will be described. In this embodiment, the region R1 exists below the source electrode 3 and the gate line 6, but does not exist between the source electrode 3 and the gate line 6. Similarly, the region R2 exists between the source electrode 3 and the gate line 6, but does not exist below the source electrode 3 or the gate line 6. In this way, the region R1 in this embodiment does not extend to the region between the source electrode 3 and the gate line 6, and the region R2 in this embodiment does not extend to the region below the source electrode 3 or the gate line 6.

[0041] 6, the areas occupied by the source electrode 3 and the gate line 6 are indicated by dot hatching, and other areas are indicated by white. The area R1 in this embodiment coincides with the area indicated by dot hatching. On the other hand, the area R2 in this embodiment coincides with the area indicated by white.

[0042] The region R1 may extend to the region between the source electrode 3 and the gate line 6, and the region R2 may extend to the region below the source electrode 3 or below the gate line 6. An example of such regions R1 and R2 will be described later with reference to FIGS. 7 and 8.

[0043] The insulating film 14 may be a BPSG (Boro Phospho Silicate Glass) film instead of a PSG film. The insulating film 14 contains Si (silicon), O (oxygen), P (phosphorus), and B (boron).

[0044] In this case, the B concentration in the insulating film 14 is higher than the B concentration in the insulating film 13. The insulating film 14 contains a high concentration of B atoms, while the insulating film 13 contains no B atoms or a low concentration of B atoms. The B concentration in the insulating film 13 is, for example, 1.0×10 18 cm -3 The B concentration in the insulating film 14 is, for example, 1.0×10 18 ~1.0×10 22 cm -3 The former value is an example of a third value, and the latter value is an example of a fourth value. Note that the P concentration in the insulating films 13, 14 when the insulating film 14 is a BPSG film can be set in the same way as the P concentration in the insulating films 13, 14 when the insulating film 14 is a PSG film.

[0045] When the insulating film 14 is a BPSG film, the region R2 contains a high concentration of B atoms, and the region R1 contains no B atoms or a low concentration of B atoms. As described above, the B concentration in the region R1 is, for example, 1.0×10 18 cm -3 On the other hand, the B concentration in the region R2 is, for example, 1.0×1018 ~1.0×10 22 cm -3 The P concentration in the regions R1 and R2 when the insulating film 14 is a BPSG film can be set in the same manner as the P concentration in the regions R1 and R2 when the insulating film 14 is a PSG film.

[0046] As will be described later, the insulating film 14 is formed, for example, by forming the source electrode 3 and the gate wiring 6 on the insulating film 13, and then implanting P ions or B ions into the insulating film 13 using the source electrode 3 and the gate wiring 6 as a mask. In this case, the P ions or B ions arrive at the upper surface of the insulating film 13 exposed between the source electrode 3 and the gate wiring 6, and a part of the insulating film 13 changes into the insulating film 14. This insulating film 14 is formed between the source electrode 3 and the gate wiring 6. In this case, P atoms or B atoms may enter the source electrode 3 or the gate wiring 6, or may adhere to the surface of the source electrode 3 or the gate wiring 6. In this case, the finished semiconductor device may contain P atoms or B atoms inside or on the surface of the source electrode 3 or the gate wiring 6.

[0047] Fig. 7 is a cross-sectional view showing the structure of a semiconductor device according to a modified example of the first embodiment. Fig. 8 is a plan view showing the structure of a semiconductor device according to a modified example of the first embodiment. Fig. 7 shows a cross section taken along line D-D' in Fig. 8. However, in order to make the drawing easier to see, the cross section shown in Fig. 7 is shown with the width of the planar portion 21 in the X direction and the width of the pad portion 23 in the X direction shorter than the widths in Fig. 8.

[0048] 7 shows regions R1 and R2 of this modified example. In this modified example, region R1 exists under the source electrode 3 and under the gate wiring 6, and region R2 exists between the source electrode 3 and the gate wiring 6. However, region R2 of this modified example extends to the regions under the source electrode 3 and under the gate wiring 6.

[0049] 7 shows the width W1 between the source electrode 3 and the gate line 6, and the width W2 of the region R2. In this modification, the region R2 protrudes to the region below the source electrode 3 and the gate line 6, so the width W2 is longer than the width W1 (W2>W1).

[0050] 7 further shows the protrusion width ΔW of region R2. In this modification, region R2 protrudes by the protrusion width ΔW to the region below the source electrode 3 and the gate wiring 6. When region R2 protrudes isotropically, the protrusion width ΔW is given by the formula ΔW=(W2-W1) / 2. The protrusion width ΔW is, for example, about 1 μm.

[0051] In Figure 8, the areas occupied by the source electrode 3 and the gate wiring 6 are indicated by dot hatching, and other areas are indicated by white. In this embodiment, area R1 is narrower than the area indicated by dot hatching. On the other hand, area R2 in this embodiment is wider than the area indicated by white. In Figure 8, the line shown within the source electrode 3 and the gate wiring 6 indicates the boundary between area R1 and area R2.

[0052] As will be described later, the insulating film 14 is formed, for example, by forming the source electrode 3 and the gate wiring 6 on the insulating film 13, and then implanting P ions or B ions into the insulating film 13 using the source electrode 3 and the gate wiring 6 as a mask. In this case, the insulating film 14 shown in FIG. 5 can be formed, for example, by causing the P ions or B ions to proceed parallel to the Z direction. On the other hand, the insulating film 14 shown in FIG. 7 can be formed, for example, by causing the P ions or B ions to proceed at an angle with respect to the Z direction. In other words, the insulating film 14 shown in FIG. 7 can be formed by obliquely irradiating the P ions or B ions.

[0053] FIG. 9 is a cross-sectional view showing the structure of a semiconductor device of a first comparative example of the first embodiment.

[0054] 9, the semiconductor device of this comparative example includes only the insulating film 13 instead of the insulating films 13 and 14. Therefore, the upper surface S of this comparative example is the upper surface of the insulating film 13. As described above, the insulating film 13 is, for example, an NSG film.

[0055] In this comparative example, a problem occurs in that mobile ions enter the cell of the power MOSFET through the gap between the source electrode 3 and the gate wiring 6. As a result, there is a risk that the threshold voltage of the neighboring cell will decrease.

[0056] FIG. 10 is a cross-sectional view showing the structure of a semiconductor device of a second comparative example of the first embodiment.

[0057] 10, the semiconductor device of this comparative example includes insulating films 13 and 14. However, the insulating film 14 of this comparative example is formed on the entire upper surface of the insulating film 13. Therefore, the upper surface S of this comparative example is the upper surface of the insulating film 14. As described above, the insulating film 14 is, for example, a PSG film (or a BPSG film).

[0058] According to this comparative example, the insulating film 14 is exposed in the gap between the source electrode 3 and the gate wiring 6, so that mobile ions can be gettered by the insulating film 14. This makes it possible to suppress a decrease in the threshold voltage.

[0059] However, if the insulating film 14 absorbs moisture, phosphorus oxide (and even boron oxide) is formed, which may cause defects in the power MOSFET. Furthermore, phosphorus atoms (and even boron atoms) in the insulating film 14 may scatter onto the side surfaces of the source electrode 3 and the gate wiring 6, which may reduce the avalanche resistance and trr resistance of the power MOSFET.

[0060] 5, the semiconductor device of this embodiment includes insulating films 13 and 14 such that the upper surface S is the upper surface of the insulating films 13 and 14. Specifically, region R1 is located below the source electrode 3 and the gate wiring 6, and region R2 is located between the source electrode 3 and the gate wiring 6.

[0061] Therefore, according to this embodiment, the insulating film 14 is exposed in the gap between the source electrode 3 and the gate wiring 6, and thus it is possible to getter mobile ions by the insulating film 14. Furthermore, according to this embodiment, it is possible to reduce the amount of moisture absorption by the insulating film 14 and the amount of scattered phosphorus atoms (and boron atoms) by reducing the proportion of the insulating film 14 that occupies the upper surface S. This makes it possible to suppress the disadvantages of the insulating film 14 while enjoying the advantages of the insulating film 14.

[0062] (2) Manufacturing method of semiconductor device Next, three examples of methods for forming the insulating films 13 and 14 of this embodiment will be described with reference to FIGS.

[0063] FIG. 11 is a cross-sectional view showing a first example of the method for manufacturing the semiconductor device according to the first embodiment.

[0064] First, an insulating film 13 is formed on the semiconductor layer 1, and then a source electrode 3 and a gate wiring 6 are formed on the insulating film 13 (FIG. 11(a)). The source electrode 3 and the gate wiring 6 are formed, for example, by forming a common material for the source electrode 3 and the gate wiring 6 on the insulating film 13 and processing this material by lithography and RIE (Reactive Ion Etching). FIG. 11(a) shows the width W1 between the source electrode 3 and the gate wiring 6.

[0065] Next, ions are implanted into the insulating film 13 using the source electrode 3 and the gate wiring 6 as a mask (FIG. 11(b)). At this time, P (phosphorus) ions and O (oxygen) ions are used for the ion implantation. As a result, an insulating film 14 is formed in the insulating film 13. The insulating film 13 is, for example, an SiO2 film (NSG film). Therefore, the insulating film 14 becomes an SiO2 film (PSG film) into which P atoms and O atoms are introduced due to the ion implantation.

[0066] In this ion implantation, P ions and O ions are selectively implanted into the insulating film 13 between the source electrode 3 and the gate line 6. This makes it possible to form an upper surface S including regions R1 and R2. Region R1 is formed below the source electrode 3 and below the gate line 6, and region R2 is formed between the source electrode 3 and the gate line 6. The P concentration in region R2 is higher than the P concentration in region R1. The P ions and O ions may be implanted into the insulating film 13 simultaneously or sequentially.

[0067] In this ion implantation, ions may be irradiated perpendicularly or obliquely. Perpendicular irradiation makes it possible to form regions R1 and R2 having the shapes shown in FIG. 5 , while oblique irradiation makes it possible to form regions R1 and R2 having the shapes shown in FIG. 7 . FIG. 11(b) shows region R2, which protrudes to the region below source electrode 3 or gate wiring 6 as a result of oblique irradiation. FIG. 11(b) also shows the width W2 of region R2. Note that region R2 protruding to the region below source electrode 3 or gate wiring 6 may be formed for a reason other than oblique irradiation, such as by diffusion of P atoms introduced into insulating film 14.

[0068] O ions are used for ion implantation, for example, to form P—O bonds in the insulating film 14. The ratio of the number of P atoms to O atoms introduced into the insulating film 14 is preferably, for example, about 2:5.

[0069] Next, an insulating film 15 is formed on the source electrode 3, the gate wiring 6, and the insulating film 14 (FIG. 11(c)). In this manner, the semiconductor device of this embodiment is manufactured. The drain electrode 2, the gate electrode 4, and the field plate electrode 5 are formed, for example, before the step of FIG. 11(a) is performed. In this case, the drain electrode 2 is formed on one surface of the semiconductor layer 1, and the source electrode 3 and the gate wiring 6 are formed on the other surface of the semiconductor layer 1.

[0070] The ion implantation may be performed using P ions, O ions, and B (boron) ions. In this case, the insulating film 14 becomes a SiO2 film (BPSG film) into which P atoms, O atoms, and B atoms are introduced due to the ion implantation. The P concentration and B concentration in region R2 are higher than those in region R1, respectively. The P ions, O ions, and B ions may be implanted into the insulating film 13 simultaneously or sequentially.

[0071] Furthermore, in the above ion implantation, P atoms or B atoms may enter the source electrode 3 or the gate wiring 6, or may adhere to the surface of the source electrode 3 or the gate wiring 6. In this case, the finished semiconductor device may contain P atoms or B atoms inside or on the surface of the source electrode 3 or the gate wiring 6.

[0072] After the ion implantation, the insulating films 13 and 14 may or may not be annealed. For example, if annealing improves the performance of the insulating film 14, annealing may be performed. On the other hand, if annealing does not improve the performance of the insulating film 14 or improves it only slightly, annealing may not be performed.

[0073] 12 is a cross-sectional view showing a second example of the method for manufacturing the semiconductor device according to the first embodiment. In the description of FIG. 12, the description of the same points as in FIG. 11 will be omitted as appropriate.

[0074] First, an insulating film 13 is formed on the semiconductor layer 1, a resist film 31 is formed on the insulating film 13, and the resist film 31 is patterned into resist patterns 31a and 31b (FIG. 12(a)). In plan view, the resist patterns 31a and 31b have the same shape as the region R1 to be formed later. FIG. 12(a) shows the width W2 of the region R2 to be formed later, which is the width between the resist patterns 31a and 31b. The resist film 31 is an example of a first film.

[0075] Next, using the resist patterns 31a and 31b as a mask, ions are implanted into the insulating film 13 (FIG. 12(b)). As a result, an insulating film 14 is formed in the insulating film 13. When P ions and O ions are implanted, the insulating film 14 becomes a PSG film. When P ions, O ions, and B ions are implanted, the insulating film 14 becomes a BPSG film.

[0076] In this ion implantation, P ions or the like are selectively implanted into the insulating film 13 between the resist patterns 31a and 31b. This makes it possible to form an upper surface S including regions R1 and R2. Region R1 is formed below the resist patterns 31a and 31b, and region R2 is formed between the resist patterns 31a and 31b. FIG. 12(b) shows region R2, which does not protrude into the region below the resist patterns 31a and 31b as a result of vertical ion irradiation. In this case, oblique irradiation may be performed instead of vertical irradiation.

[0077] Next, the resist patterns 31a and 31b are removed, and the source electrode 3 and gate wiring 6 are formed on the insulating films 13 and 14, and an insulating film 15 is formed on the source electrode 3, gate wiring 6, and insulating film 14 (FIG. 12(c)). Most of the source electrode 3 and gate wiring 6 are disposed in region R1. In this manner, the semiconductor device of this embodiment is manufactured. FIG. 12(c) shows the width W1 between the source electrode 3 and the gate wiring 6.

[0078] According to the second example, by using vertical irradiation instead of oblique irradiation, it is possible to form the region R2 that protrudes to the region below the source electrode 3 or the gate wiring 6. On the other hand, according to the first example, it is possible to form the regions R1 and R2 without using the resist film 31.

[0079] Note that region R2 in the second example may be formed in a shape different from region R2 in the first example. For example, region R2 in the second example may be formed in only a part of the region between the source electrode 3 and the gate line 6. This can be achieved, for example, by setting the shapes of resist patterns 31a and 31b so that region R2 is formed in only a part of the region between the source electrode 3 and the gate line 6.

[0080] 13 is a cross-sectional view showing a third example of the method for manufacturing the semiconductor device according to Embodiment 1. In the description of FIG. 13, the description of the same points as in FIG. 11 will be omitted as appropriate.

[0081] First, an insulating film 13 is formed on the semiconductor layer 1, a hard mask film 32 is formed on the insulating film 13, and the hard mask film 32 is processed into mask patterns 32a and 32b by lithography and RIE (FIG. 13(a)). In plan view, the mask patterns 32a and 32b have roughly the same shape as the region R1 to be formed later. FIG. 13(a) shows the width W3 between the mask patterns 32a and 32b. The hard mask film 32 is, for example, a SiN film. The hard mask film 32 is also an example of a first film.

[0082] Next, a gas containing P atoms and O atoms is supplied to the insulating film 13, and the insulating film 13 is exposed to this gas (FIG. 13(a)). At this time, the mask patterns 32a and 32b are used as masks for gas supply. As a result, P atoms and O atoms are introduced into the insulating film 13, and an insulating film 14 is formed in the insulating film 13 (FIG. 13(b)). This gas is, for example, POCl2 gas. This gas may further contain B atoms. When P atoms and O atoms are introduced, the insulating film 14 becomes a PSG film. When P atoms, O atoms, and B atoms are introduced, the insulating film 14 becomes a BPSG film.

[0083] This gas supply selectively introduces P atoms and the like into the insulating film 13 between the mask patterns 32a and 32b. This allows the formation of an upper surface S including regions R1 and R2. Region R1 is formed below the mask patterns 32a and 32b, and region R2 is formed between the mask patterns 32a and 32b. This gas supply also introduces P atoms and the like isotropically into the insulating film 13. Therefore, region R2 shown in FIG. 13(b) protrudes to the region below the mask patterns 32a and 32b. FIG. 13(b) shows the width W2 of region R2, which is wider than width W3.

[0084] Next, the mask patterns 32a and 32b are removed, and the source electrode 3 and gate wiring 6 are formed on the insulating films 13 and 14, and an insulating film 15 is formed on the source electrode 3, gate wiring 6, and insulating film 14 (FIG. 13(c)). Most of the source electrode 3 and gate wiring 6 are disposed in region R1. In this manner, the semiconductor device of this embodiment is manufactured. FIG. 13(c) shows the width W1 between the source electrode 3 and the gate wiring 6.

[0085] According to the third example, it is possible to easily form the region R2 that protrudes to the region below the source electrode 3 or the gate wiring 6 by supplying gas. For example, this gas supply can be performed by batch processing in which multiple semiconductor layers 1 (e.g., multiple semiconductor substrates) are processed simultaneously. This gas supply is also called phosphorus diffusion or vapor phase diffusion. On the other hand, according to the first example, it is possible to form the regions R1 and R2 without using a hard mask film 32.

[0086] Note that region R2 in the third example may be formed in a shape different from region R2 in the first example. For example, region R2 in the third example may be formed in only a part of the region between the source electrode 3 and the gate line 6. This can be achieved, for example, by setting the shapes of mask patterns 32a and 32b so that region R2 is formed in only a part of the region between the source electrode 3 and the gate line 6.

[0087] 13(a) may be performed at a high temperature (e.g., about 800°C). In this case, it is desirable to form the hard mask film 32 from a material that can withstand high temperatures. This hard mask film 32 may be a film other than a SiN film as long as it can withstand high temperatures.

[0088] The insulating film 14 may be formed by a method other than the first to third examples. For example, an opening may be formed in the insulating film 13 by lithography and RIE, and the insulating film 14 may be embedded in the opening. In this case, the opening is formed in the region where the region R2 is to be formed.

[0089] Next, the method for manufacturing the semiconductor device of this embodiment will be described in more detail with reference to FIGS.

[0090] 14 to 22 are cross-sectional views showing details of the method for manufacturing the semiconductor device of the first embodiment.

[0091] First, a plurality of gate trenches GT are formed in the semiconductor layer 1 by lithography and RIE (FIG. 14(a)). These gate trenches GT are formed to extend in the Y direction and to be adjacent to each other in the X direction.

[0092] Next, an insulating film 11a for the insulating film 11 is formed on the entire surface of the semiconductor layer 1 (FIG. 14(b)). As a result, the insulating film 11a is formed on the side surface and bottom surface of each gate trench GT. The insulating film 11a is, for example, a SiO2 film.

[0093] Next, a material for the field plate electrode 5 is formed over the entire surface of the semiconductor layer 1 (FIG. 15(a)). As a result, the material is formed in each gate trench GT via the insulating film 11a. The material is, for example, a polysilicon layer.

[0094] Next, the material of the field plate electrode 5 is processed by wet etching (FIG. 15(b)). As a result, the material is removed outside the gate trench GT, remains in the gate trench GT, and is formed into the field plate electrode 5 in each gate trench GT.

[0095] Next, the insulating film 11a is processed by wet etching (FIG. 16(a)). As a result, the insulating film 11a is removed outside the gate trench GT and remains inside the gate trench GT.

[0096] Next, the surfaces of the semiconductor layer 1 and the field plate electrode 5 are thermally oxidized (FIG. 16(b)). As a result, a thermally oxidized film is formed on the surfaces of the semiconductor layer 1 and the field plate electrode 5 as an insulating film 11b for the insulating film 11. The insulating film 11b is, for example, a SiO2 film.

[0097] Next, the material of the gate electrode 4 is formed on the entire surface of the semiconductor layer 1 (FIG. 17(a)). As a result, the material is formed in each gate trench GT via the insulating film 11. The material is, for example, a polysilicon layer.

[0098] Next, the material of the gate electrode 4 is processed by wet etching (FIG. 17(b)). As a result, the material is removed outside the gate trench GT and remains in the gate trench GT, forming the gate electrode 4 in each gate trench GT.

[0099] Next, an insulating film 12 is formed on the entire surface of the semiconductor layer 1 by CVD (Chemical Vapor Deposition) (FIG. 18(a)). As a result, the insulating film 12 is formed in each gate trench GT via the gate electrode 4. The insulating film 12 is, for example, a SiO2 film.

[0100] Next, the insulating film 12 is subjected to a heat treatment (FIG. 18(b)). As a result, the insulating film 12 is softened and the surface of the insulating film 12 is flattened.

[0101] Next, the insulating film 12 is processed by dry etching (FIG. 19(a)). As a result, the insulating film 12 is removed outside the gate trench GT and remains inside the gate trench GT.

[0102] Next, p-type impurity ions are implanted from the upper surface side of the semiconductor layer 1 (FIG. 19(b)). As a result, p-type impurity atoms are introduced into the semiconductor layer 1. The p-type impurity is, for example, B (boron).

[0103] Next, the semiconductor layer 1 is subjected to a heat treatment (FIG. 20(a)). As a result, the above-mentioned p-type impurities are activated and diffused in the semiconductor layer 1, and a base layer 1c is formed in the semiconductor layer 1. The region below the base layer 1c in the semiconductor layer 1 is a drift layer 1a.

[0104] Next, n-type impurity ions are implanted from the upper surface side of the semiconductor layer 1, and the semiconductor layer 1 is subjected to a heat treatment (FIG. 20(b)). As a result, n-type impurity atoms are introduced into the semiconductor layer 1, etc., and the n-type impurities are activated and diffused within the semiconductor layer 1, forming a source layer 1e on the base layer 1c within the semiconductor layer 1. The n-type impurity is, for example, P (phosphorus).

[0105] Next, an insulating film 13 is formed on the entire surface of the semiconductor layer 1 by CVD (FIG. 21(a)). As a result, the insulating film 13 is formed on the insulating film 12, the gate electrode 4, and the insulating film 11. The insulating film 13 is, for example, an NSG film (SiO2 film).

[0106] Next, a plurality of contact trenches CT are formed in the insulating film 13, the insulating film 11, and the semiconductor layer 1 by lithography and RIE (FIG. 21(b)). As a result, the base layer 1c is exposed in each contact trench CT. These contact trenches CT are formed to extend in the Y direction and adjacent to each other in the X direction.

[0107] Next, p-type impurity ions are implanted into the semiconductor layer 1 through each contact trench CT, and the semiconductor layer 1 is subjected to a heat treatment (FIG. 22(a)). As a result, p-type impurity atoms are introduced into the semiconductor layer 1, and the p-type impurities are activated and diffused within the semiconductor layer 1, forming a contact layer 1d on the base layer 1c within the semiconductor layer 1. The p-type impurity is, for example, B (boron).

[0108] Next, a material for the source electrode 3 is formed on the entire surface of the semiconductor layer 1, and the material is processed by lithography and RIE (FIG. 22(b)). As a result, the source electrode 3 is formed on the insulating film 13. Note that a portion of the source electrode 3 extends into the contact trench CT. As a result, a contact portion CP is formed in each contact trench CT, and each contact portion CP is formed on the contact layer 1d. In this manner, the semiconductor device of this embodiment is manufactured.

[0109] The gate wiring 6 is formed, for example, from the material of the source electrode 3 at the same time as the source electrode 3. In this case, before forming the material, openings for embedding the field plate contact FPC and the gate contact GC are formed in the insulating films 13 and 12 (see FIG. 4).

[0110] 14(a), the drain electrode 2 and the drain layer 1b are formed. At this time, the drain electrode 2 is formed on one surface of the semiconductor layer 1, and the source electrode 3 and the gate wiring 6 are formed on the other surface of the semiconductor layer 1. The drain layer 1b is formed in the semiconductor layer 1 from the surface of the semiconductor layer 1 on which the drain electrode 2 is formed.

[0111] The insulating films 14 and 15 can be formed by the methods of the first to third examples described with reference to Figures 11 to 13. In this case, the insulating film 14 is formed, for example, before or after the source electrode 3 and the gate wiring 6 are formed. The insulating film 15 is formed, for example, after the source electrode 3 and the gate wiring 6 are formed. This makes it possible to form regions R1 and R2 on the upper surface S of the base insulating film including the insulating films 13 and 14.

[0112] As described above, the semiconductor device of this embodiment is manufactured so that the upper surface S of the underlying insulating film, which includes the insulating films 13 and 14, includes regions R1 and R2. Region R1 has a low P concentration and is provided below the source electrode 3 and the gate wiring 6. Region R2 has a high P concentration and is provided between the source electrode 3 and the gate wiring 6. Therefore, according to this embodiment, it is possible to suitably form the source electrode 3 and the gate wiring 6 on the underlying insulating film containing P (phosphorus). According to this embodiment, such a structure makes it possible to suppress deterioration of the characteristics of the semiconductor device.

[0113] Although several embodiments have been described above, these embodiments are presented only as examples and are not intended to limit the scope of the invention. The novel apparatus and method described herein may be embodied in various other forms. Furthermore, various omissions, substitutions, and modifications may be made to the forms of the apparatus and method described herein without departing from the spirit of the invention. The appended claims and their equivalents are intended to cover such forms and modifications that fall within the scope and spirit of the invention. [Explanation of symbols]

[0114] 1: semiconductor layer, 1a: drift layer, 1b: drain layer, 1c: base layer, 1d: contact layer, 1e: source layer, 2: drain electrode, 3: source electrode, 4: gate electrode, 5: field plate electrode, 6: gate wiring, 11: insulating film, 11a: insulating film, 11b: insulating film, 12: insulating film, 13: insulating film, 14: insulating film, 15: insulating film, 21: Planar portion, 22: Linear portion, 23: Pad portion, 24: Wiring portion, 31: resist film, 31a: resist pattern, 31b: resist pattern, 32: hard mask film, 32a: mask pattern, 32b: mask pattern

Claims

1. a semiconductor layer; a first insulating film provided on the semiconductor layer; a gate wiring provided on the first insulating film, the gate wiring including a first portion provided in the first insulating film; a source electrode provided on the first insulating film, the source electrode including a second portion provided within the first insulating film; a second insulating film provided on the gate wiring and the source electrode, the second insulating film including a third portion sandwiched between the gate wiring and the source electrode; a drain electrode provided under the semiconductor layer, an upper surface of the first insulating film includes a first region having a first phosphorus concentration and a second region having a second phosphorus concentration higher than the first concentration; the first region is present between the semiconductor layer and the gate wiring or the source electrode, the second region is present between the semiconductor layer and the third portion of the second insulating film, the first region includes a region sandwiched between the second region and the first portion of the gate wiring or the second portion of the source electrode; Semiconductor device.

2. The first value is 1.0×10 １８ cm －３ The semiconductor device according to claim 1 , wherein the thickness is less than 100 μm.

3. The second value is 1.0×10 １８ ~1.0 x 10 ２２ cm －３ 3. The semiconductor device according to claim 1, wherein:

4. 4. The semiconductor device according to claim 1, wherein phosphorus is present inside or on the surface of at least one of said gate wiring and said source electrode.

5. the concentration of boron in the first region is a third value; the concentration of boron in the second region is a fourth value higher than the third value; The semiconductor device according to claim 1 .

6. The third value is 1.0×10 １８ cm －３ The semiconductor device according to claim 5 , wherein the thickness is less than 100 μm.

7. The fourth value is 1.0×10 １８ ~1.0 x 10 ２２ cm －３ 7. The semiconductor device according to claim 5, wherein:

8. The first insulating film is a third insulating film provided on the semiconductor layer, the third insulating film having a phosphorus concentration of the first value; a fourth insulating film provided on the third insulating film, the fourth insulating film having a phosphorus concentration of the second value; the first region is an upper surface of the third insulating film, the second region is an upper surface of the fourth insulating film, the third insulating film includes a portion sandwiched between the fourth insulating film and the first portion of the gate wiring or the second portion of the source electrode; The semiconductor device according to claim 1 .

9. forming a first insulating film on a first surface of the semiconductor layer; forming a gate wiring on the first insulating film, the gate wiring including a first portion provided in the first insulating film; forming a source electrode on the first insulating film, the source electrode including a second portion provided in the first insulating film; forming a second insulating film on the gate wiring and the source electrode, the second insulating film including a third portion sandwiched between the gate wiring and the source electrode; forming a drain electrode on a second surface of the semiconductor layer; This includes: a first region having a first phosphorus concentration and a second region having a second phosphorus concentration higher than the first concentration, formed on an upper surface of the first insulating film; the first region is formed between the semiconductor layer and the gate wiring or the source electrode, the second region is formed between the semiconductor layer and the third portion of the second insulating film, the first region is formed to include a region sandwiched between the second region and the first portion of the gate wiring or the second portion of the source electrode; A method for manufacturing a semiconductor device.

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