Semiconductor Devices

Abstract

To provide a semiconductor device capable of suppressing a malfunction.SOLUTION: A semiconductor device 1 according to one embodiment includes: a first transistor N1 having one end connected to a power supply voltage terminal P1, the other end connected to a first node ND1, and a gate connected to a first output terminal P4; a first circuit 10 configured to control a voltage Vnd1 of the first node ND1 on the basis of a voltage of a ground voltage terminal P2; a second circuit 20 configured to control a voltage VOUT1 of the first output terminal P4 on the basis of the voltage of the ground voltage terminal P2 and a voltage VIN of an input terminal P3; and a third circuit 30 configured to control switching between connection and disconnection between the ground voltage terminal P2 and the first circuit 10.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] FIELD An embodiment of the present invention relates to a semiconductor device. [Background technology]

[0002] 2. Description of the Related Art Semiconductor devices for supplying a power supply voltage to an external load are known. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 3814958 [Patent Document 2] Patent No. 5438468 [Patent Document 3] Japanese Patent Application Laid-Open No. 2014-165575 Summary of the Invention [Problem to be solved by the invention]

[0004] A semiconductor device capable of suppressing malfunction is provided. [Means for solving the problem]

[0005] The semiconductor device according to the embodiment includes a first transistor having one end connected to a power supply voltage terminal, the other end connected to a first node, and a gate connected to a first output terminal; a diode connected between a ground voltage terminal and the first node; The voltage of the first node is set based on the voltage of the ground voltage terminal. clamp a first circuit for controlling the a control circuit connected to a power supply voltage terminal, a ground voltage terminal, and an input terminal, determining whether the ground voltage terminal is in an open state with the outside from a voltage difference between the power supply voltage terminal and the ground voltage terminal, and outputting a first voltage based on the voltage of the input terminal if the ground voltage terminal is not in an open state, and outputting a second voltage if the ground voltage terminal is in an open state; and a second transistor having one end connected to the first output terminal and the other end connected to the first node, and having a gate to which a third voltage based on the voltage output by the control circuit is applied, and controlling the second transistor based on the voltage output by the control circuit a second circuit that controls the voltage of the first output terminal; a third transistor having one end connected to a ground voltage terminal, the other end connected to the first circuit, and a gate connected to a power supply voltage terminal; and a timer circuit that measures time and outputs a voltage, and controls the third transistor based on the voltage output by the timer circuit; and a third circuit that controls switching between connection and disconnection between the ground voltage terminal and the first circuit. When the ground voltage terminal is not disconnected from the outside and the first transistor transitions from the on state to the off state, the third circuit turns the third transistor on, the first circuit clamps the voltage of the first node based on the voltage of the ground voltage terminal, and the third circuit turns the third transistor off based on the voltage of the timer circuit output after a predetermined time has elapsed. When the ground voltage terminal is disconnected from the outside, the third circuit turns the third transistor off, and the second circuit turns the second transistor on. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a circuit diagram showing an example of a semiconductor device according to the first embodiment. [Figure 2] FIG. 2 is a timing chart showing voltages at various terminals during operation of the semiconductor device according to the first embodiment. [Figure 3] FIG. 3 is a timing chart showing voltages at various terminals etc. during operation of the semiconductor device according to the first embodiment. [Figure 4] FIG. 4 is a circuit diagram illustrating an example of a semiconductor device according to the second embodiment. [Figure 5] FIG. 5 is a timing chart showing voltages at various terminals during operation of the semiconductor device according to the second embodiment. [Figure 6] FIG. 6 is a timing chart showing voltages at various terminals during operation of the semiconductor device according to the second embodiment. [Figure 7] FIG. 7 is a timing chart showing voltages at various terminals during operation of the semiconductor device according to the second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, embodiments will be described with reference to the drawings. In the following description, components having substantially the same functions and configurations are designated by the same reference numerals, and repeated explanations may be omitted. Furthermore, all descriptions of one embodiment also apply to descriptions of other embodiments, unless explicitly or obviously excluded.

[0008] 1. First embodiment A semiconductor device according to a first embodiment will be described below, taking as an example a semiconductor device that supplies a power supply voltage to an external load by driving a switch element.

[0009] 1.1 Configuration 1.1.1 Circuit configuration of semiconductor device The circuit configuration of a semiconductor device according to this embodiment will be described with reference to Fig. 1. Fig. 1 is a circuit diagram showing an example of a semiconductor device. In the following description, when the source and drain of a transistor are not specified, either the source or the drain of the transistor will be referred to as "one end of the transistor," and the other of the source or the drain of the transistor will be referred to as "the other end of the transistor."

[0010] The semiconductor device 1 is, for example, an IC (Integrated Circuit) chip. The semiconductor device 1 supplies a power supply voltage to an external load LD. The semiconductor device 1 and the load LD may correspond to, for example, a part of an in-vehicle system. The load LD may correspond to, for example, a headlight, a power window, or the like.

[0011] The semiconductor device 1 includes a power supply voltage terminal P1, a ground voltage terminal P2, an input terminal P3, a first output terminal P4, a second output terminal P5, a switch element SW, a first control circuit CTL1, a drive circuit DRV, a clamp circuit 10, a breakage protection circuit 20, a switching control circuit 30, and resistor elements R6 and R10.

[0012] A power supply voltage VDD is supplied to the power supply voltage terminal P1 from the outside.

[0013] A ground voltage GND is supplied to the ground voltage terminal P2 from an external source. For example, the ground voltage terminal P2 is electrically connected to a power supply (hereinafter also referred to as a "GND power supply") that supplies the voltage GND via wiring. In the case of an in-vehicle system, for example, a connector for the voltage GND of a car battery is electrically connected to the ground voltage terminal P2. Note that the ground voltage terminal P2 may be grounded.

[0014] An external voltage VIN is supplied to the input terminal P3. The voltage VIN is a high (“H”) level voltage or a low (“L”) level voltage. The “L” level voltage is, for example, the voltage GND. The semiconductor device 1 operates based on the voltage VIN.

[0015] A voltage VOUT1 is applied from the first output terminal P4 to the switch element SW.

[0016] A voltage VOUT2 is applied to the node ND1 from the second output terminal P5.

[0017] The switch element SW is, for example, an n-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The switch element SW switches between connection and disconnection between the power supply voltage terminal P1 and the external load LD. In the following, a case where the switch element SW is an n-channel MOSFET (hereinafter also referred to as "NMOS transistor") N1 will be described.

[0018] One end of the transistor N1 is connected to the power supply voltage terminal P1, the other end is connected to a node ND1, and the gate is connected to the first output terminal P4. The voltage VOUT1 is applied to the gate of the transistor N1 from the first output terminal P4. The node ND1 is connected to the second output terminal P5.

[0019] The first control circuit CTL1 is a circuit that controls the drive circuit DRV. The first control circuit CTL1 is connected to a power supply voltage terminal P1, an input terminal P3, and a node ND2. The first control circuit CTL1 receives a voltage VDD from the power supply voltage terminal P1 and a voltage VIN from the input terminal P3. The first control circuit CTL1 outputs a voltage based on the voltage VIN to the node ND2. When the voltage VIN is at a high level, the first control circuit CTL1 outputs a high-level voltage. On the other hand, when the voltage VIN is at a low level, the first control circuit CTL1 outputs a low-level voltage. The low-level voltage output from the first control circuit CTL1 is, for example, the voltage GND.

[0020] The driver circuit DRV is a circuit that drives the transistor N1. The driver circuit DRV is connected to a node ND2 and a first output terminal P4. The voltage of the node ND2 (hereinafter referred to as "voltage Vnd2") is applied to the driver circuit DRV. The driver circuit DRV outputs a voltage based on the voltage Vnd2 to the first output terminal P4. When the voltage VIN (voltage Vnd2) is at a "H" level, the driver circuit DRV outputs a "H" level voltage. On the other hand, when the voltage VIN (voltage Vnd2) is at a "L" level, the driver circuit DRV outputs a "L" level voltage. The voltage output from the driver circuit DRV is applied to the gate of the transistor N1 as a voltage VOUT1 via the first output terminal P4. The "L" level voltage output from the driver circuit DRV is, for example, a voltage GND.

[0021] The clamp circuit 10 is a circuit that clamps the voltage Vnd1 at the node ND1 (hereinafter referred to as "voltage Vnd1") so that the voltage Vnd1 does not drop from the voltage VDD beyond the withstand voltage (e.g., 40 V) between the drain and source of the transistor N1 when the voltage VIN transitions from the "H" level to the "L" level. The clamp circuit 10 is connected to the node ND3, the first output terminal P4, and the second output terminal P5. The details of the clamp circuit 10 will be described later.

[0022] The open circuit protection circuit 20 is a circuit that protects the transistor N1 from overheating and breakdown due to an unintended ON state caused by an unstable voltage at the ground voltage terminal P2 when the wiring connecting the ground voltage terminal P2 and the GND power supply is disconnected. When the wiring connecting the ground voltage terminal P2 and the GND power supply is disconnected, this refers to a state in which the ground voltage terminal P2 and the GND power supply are not electrically connected. In the case of an in-vehicle system, this refers to, for example, a case in which the connector for the car battery voltage GND is disconnected from the ground voltage terminal P2. Hereinafter, the state in which the wiring connecting the ground voltage terminal P2 and the GND power supply is disconnected will be referred to as a "GND open circuit state," and the state in which it is not disconnected will be referred to as a "GND non-open circuit state." The open circuit protection circuit 20 is connected to the power supply voltage terminal P1, the ground voltage terminal P2, the input terminal P3, the first output terminal P4, and the second output terminal P5. Details of the open circuit protection circuit 20 will be described later.

[0023] The switching control circuit 30 is a circuit that controls switching between connection and disconnection between the ground voltage terminal P2 and the clamp circuit 10. The switching control circuit 30 is connected to the power supply voltage terminal P1, the ground voltage terminal P2, and nodes ND2 and ND3. Details of the switching control circuit 30 will be described later.

[0024] One end of the resistor R6 is connected to the first output terminal P4, and the other end is connected to the second output terminal P5. The resistor R6 is provided to prevent the transistor N1 from turning on when the voltage VIN is at the “L” level.

[0025] One end of the resistor R10 is connected to the power supply voltage terminal P1, and the other end is connected to the ground voltage terminal P2. The resistor R10 represents the resistance of a circuit (not shown) provided between the power supply voltage terminal P1 and the ground voltage terminal P2.

[0026] The load LD includes, for example, a resistor R1 and an inductor L1. One end of the resistor R1 is connected to a node ND1, and the other end is grounded. One end of the inductor L1 is connected to the node ND1, and the other end is grounded.

[0027] 1.1.2 Clamp circuit configuration The circuit configuration of the clamp circuit 10 will be described.

[0028] As shown in FIG. 1, the clamp circuit 10 includes a diode D1 and Zener diodes ZD1 to ZD3.

[0029] The anode of the diode D1 is connected to the node ND3, and the cathode is connected to the node ND4. The forward voltage Vf of the diode D1 is, for example, 0.7V.

[0030] The anode of the diode ZD1 is connected to the first output terminal P4, and the cathode is connected to the node ND4. The reverse voltage (breakdown voltage) Vz1 of the diode ZD1 is, for example, 6 V.

[0031] The anode of the diode ZD2 is connected to the node ND5, and the cathode is connected to the first output terminal P4. The reverse voltage Vz2 of the diode ZD2 is, for example, 6V.

[0032] The anode of the diode ZD3 is connected to the second output terminal P5, and the cathode is connected to the node ND5. The reverse voltage Vz3 of the diode ZD3 is, for example, 6 V.

[0033] The diode D1 and the Zener diodes ZD1 to ZD3 are provided to clamp the voltage Vnd1 of the node ND1. Note that the number of Zener diodes is not limited to three.

[0034] 1.1.3 Configuration of disconnection protection circuit The circuit configuration of the disconnection protection circuit 20 will be described.

[0035] As shown in FIG. 1, the disconnection protection circuit 20 includes a second control circuit CTL2, NMOS transistors N2 and N3, and resistance elements R2 to R5.

[0036] The second control circuit CTL2 controls the transistors N2 and N3. The second control circuit CTL2 is connected to the power supply voltage terminal P1, the ground voltage terminal P2, the input terminal P3, and a node ND6. The second control circuit CTL2 receives a voltage VDD from the power supply voltage terminal P1, a voltage GND from the ground voltage terminal P2, and a voltage VIN from the input terminal P3. The second control circuit CTL2 outputs a voltage based on the voltage VIN to the node ND6. When the voltage VIN is at a high level, the second control circuit CTL2 outputs a high-level voltage. On the other hand, when the voltage VIN is at a low level, the second control circuit CTL2 outputs a low-level voltage. The low-level voltage output from the second control circuit CTL2 is, for example, the voltage GND. When the voltage difference between the power supply voltage terminal P1 and the ground voltage terminal P2 is smaller than the voltage value capable of driving the second control circuit CTL2 (for example, when the ground voltage terminal P2 is in a GND disconnection state), the second control circuit CTL2 outputs a low-level voltage.

[0037] One end of the transistor N2 is connected to the node ND7, the other end is connected to the second output terminal P5, and the gate is connected to the node ND6.

[0038] One end of the transistor N3 is connected to the node ND8, the other end is connected to the second output terminal P5, and the gate is connected to the node ND7.

[0039] One end of the resistor R2 is connected to the node ND6, and the other end is connected to the second output terminal P5. The resistor R2 is provided to turn on the transistor N2 when the voltage of the node ND6 (hereinafter referred to as "voltage Vnd6") is at the "H" level.

[0040] One end of the resistor element R3 is connected to the power supply voltage terminal P1, and the other end is connected to a node ND7.

[0041] One end of the resistor element R4 is connected to the node ND7, and the other end is connected to the second output terminal P5.

[0042] Resistor elements R3 and R4 are provided to apply a voltage obtained by dividing the voltage between the power supply voltage terminal P1 and the second output terminal P5 to the gate of transistor N3, and resistor elements R3 and R4 are also provided to turn on transistor N3 when transistor N2 is turned off.

[0043] One end of the resistor R5 is connected to the first output terminal P4, and the other end is connected to the node ND8. The resistor R5 is provided to rapidly draw charge from the gate of the transistor N1 to the second output terminal P5 when the transistor N3 is turned on, thereby quickly turning off the transistor N1. The resistance value of the resistor R5 is lower than the resistance value of the resistor R6.

[0044] 1.1.4 Configuration of the switching control circuit The circuit configuration of the switching control circuit 30 will be described.

[0045] As shown in FIG. 1, the switching control circuit 30 includes an inverter circuit INV1, flip-flop (FF) circuits FF1 and FF2, a timer circuit TMR, NMOS transistors N4 to N6, and resistance elements R7 to R9.

[0046] The input terminal of the inverter circuit INV1 is connected to the node ND2, and the output terminal is connected to a node ND9.

[0047] The FF circuit FF1 is, for example, a D flip-flop. The FF circuit FF1 has three input terminals (CLK, D, and R) and two output terminals (Q and QN). The terminal CLK of the FF circuit FF1 is connected to a node ND2, a voltage VREG is applied to the terminal D, and the terminal R is connected to a node ND10. The voltage VREG is an "H" level voltage. The terminal R is a terminal for resetting the values ​​of the terminals Q and QN. The terminal QN of the FF circuit FF1 is connected to a node ND11.

[0048] When the voltage Vnd2 of the node ND2 applied to the terminal CLK rises from the "L" level to the "H" level, the FF circuit FF1 takes in the voltage VREG at the terminal D. The FF circuit FF1 outputs the value taken in at the terminal D from the terminal Q, and outputs the inverted value of the terminal Q from the terminal QN.

[0049] When a high-level voltage is applied to the terminal R, the FF circuit FF1 resets the values ​​of the terminals Q and QN to low and high levels, respectively.

[0050] The FF circuit FF2 is, for example, a D flip-flop. The FF circuit FF2 has the same configuration as the FF circuit FF1. The terminal CLK of the FF circuit FF2 is connected to the node ND9, the voltage VREG is applied to the terminal D, the terminal R is connected to the node ND11, and the terminal Q is connected to the node ND12.

[0051] When the voltage of node ND9 applied to terminal CLK rises from "L" level to "H" level, FF circuit FF2 takes in voltage VREG at terminal D. FF circuit FF2 outputs the value taken in at terminal D from terminal Q, and outputs the inverted value of terminal Q from terminal QN.

[0052] When a high-level voltage is applied to the terminal R, the FF circuit FF2 resets the values ​​of the terminals Q and QN to low and high levels, respectively.

[0053] The timer circuit TMR is a circuit that measures time and controls the timing for resetting the values ​​of the terminals Q and QN of the FF circuit FF1. The timer circuit TMR is connected to nodes ND10 and ND12. The timer circuit TMR outputs a voltage based on the voltage of the node ND12 (hereinafter referred to as "voltage Vnd12") to the node ND10. When the values ​​of the terminals Q and QN of the FF circuit FF1 are reset, the timer circuit TMR outputs a "H" level voltage. On the other hand, when the values ​​of the terminals Q and QN of the FF circuit FF1 are not reset, the timer circuit TMR outputs a "L" level voltage.

[0054] The timer circuit TMR outputs a high-level voltage, for example, after a certain time has elapsed since the voltage Vnd12 of the node ND12 went high. The certain time is set in advance in consideration of the time it takes for the voltage Vnd1 of the node ND1 to return from the voltage VDD to the voltage GND when the voltage VIN transitions from high to low. The certain time is, for example, longer than the time it takes for the voltage Vnd1 of the node ND1 to return from the voltage VDD to the voltage GND when the voltage VIN transitions from high to low.

[0055] One end of the transistor N4 is connected to the node ND13, the other end is connected to the node ND3, and the gate is connected to the node ND12.

[0056] One end of the transistor N5 is connected to the node ND14, the other end is connected to the node ND3, and the gate is connected to the node ND13.

[0057] The transistor N6 has one end connected to the ground voltage terminal P2, the other end connected to a node ND3, and a gate connected to a node ND14. The transistor N6 is provided to switch between connection and disconnection between the ground voltage terminal P2 and the clamp circuit 10.

[0058] One end of the resistor R7 is connected to the node ND12, and the other end is connected to the node ND3. The resistor R7 is provided to turn on the transistor N4 when the voltage Vnd12 of the node ND12 is at the “H” level.

[0059] One end of the resistor R8 is connected to the power supply voltage terminal P1, and the other end is connected to a node ND13. The resistor R8 is provided to turn on the transistor N5 when the transistor N4 is turned off.

[0060] One end of the resistor R9 is connected to the power supply voltage terminal P1, and the other end is connected to a node ND14. The resistor R9 is provided to turn on the transistor N6 when the transistor N5 is turned off.

[0061] 1.2 Operation The operation of the semiconductor device 1 according to this embodiment will be described. The operations performed by the semiconductor device 1 include a first operation and a second operation. The first operation is an operation to control the source voltage of the transistor N1 (the voltage Vnd1 at the node ND1) when the voltage VIN transitions from the "H" level to the "L" level. The second operation is an operation to control the gate voltage of the transistor N1 (the voltage VOUT1 at the first output terminal P4) when the ground voltage terminal P2 is in a GND disconnection state.

[0062] The voltages at various terminals, etc. during operation of the semiconductor device 1 will be described with reference to Figures 2 and 3. Figures 2 and 3 are timing charts showing the voltages at various terminals, etc. during operation of the semiconductor device 1. Below, we will explain the case where the ground voltage terminal P2 is in an undisconnected state with the outside GND from time T0 to time T7, and then becomes disconnected from the outside GND at time T7.

[0063] 2, from time T0 to time T1, a voltage VIN (for example, voltage GND) at an "L" level is supplied to the input terminal P3, and a voltage GND is supplied to the ground voltage terminal P2.

[0064] The first control circuit CTL1 outputs a low-level voltage to the node ND2 based on the voltage VIN (low level). The voltage Vnd2 of the node ND2 becomes a low-level voltage (for example, the voltage GND).

[0065] The voltage Vnd2 ("L" level) at the node ND2 is applied to the terminal CLK of the FF circuit FF1, the voltage VREG is applied to the terminal D, and a "L" level voltage is applied from the timer circuit TMR to the terminal R. As a result, a "H" level voltage is output from the terminal QN of the FF circuit FF1 to the node ND11. The voltage at the node ND11 becomes a "H" level voltage.

[0066] The voltage Vnd2 ("L" level) of the node ND2 is applied to the input terminal of the inverter circuit INV1. The inverter circuit INV1 outputs a "H" level voltage to the node ND9. The voltage of the node ND9 becomes a "H" level voltage.

[0067] The voltage ("H" level) of the node ND9 is applied to the terminal CLK of the FF circuit FF2, the voltage VREG is applied to the terminal D, and the voltage ("H" level) of the node ND11 is applied to the terminal R. As a result, the values ​​of the terminals Q and QN of the FF circuit FF2 are reset to the "L" level and the "H" level, respectively. A "L" level voltage (e.g., voltage GND) is output from the terminal Q of the FF circuit FF2 to the node ND12. The voltage Vnd12 of the node ND12 becomes a "L" level voltage (e.g., voltage GND). As a result, the transistor N4 is turned off. The voltage of the node ND13 becomes a "H" level voltage. As a result, the transistor N5 is turned on. The voltage of the node ND14 becomes a "L" level voltage (e.g., voltage GND). As a result, the transistor N6 is turned off.

[0068] The timer circuit TMR outputs a low-level voltage (for example, the voltage GND) to the node ND10, causing the voltage of the node ND10 to become a low-level voltage.

[0069] The second control circuit CTL2 outputs a low-level voltage to the node ND6 based on the voltage VIN (low level). The voltage Vnd6 at the node ND6 becomes a low-level voltage (for example, voltage GND). This turns the transistor N2 off. The voltage at the node ND7 becomes a high-level voltage (for example, a voltage that turns on the transistor N3). This turns the transistor N3 on.

[0070] The drive circuit DRV outputs a low-level voltage to the first output terminal P4 based on the voltage Vnd2 (low level) of the node ND2. The voltage VOUT1 of the first output terminal P4 becomes a low-level voltage (e.g., GND). The voltage VOUT1 (low level) is applied from the first output terminal P4 to the gate of the transistor N1. This turns the transistor N1 off. The voltage VDD is not supplied to the load LD from the power supply voltage terminal P1. This causes the voltage Vnd1 of the node ND1 to become the voltage GND. The voltage VOUT2 of the second output terminal P5 becomes the voltage GND.

[0071] No current flows through the diodes D1 and ZD1 to ZD3.

[0072] At time T1, the input terminal P3 is supplied with a voltage VIN at "H" level.

[0073] The first control circuit CTL1 outputs a voltage of "H" level to the node ND2 based on the voltage VIN ("H" level), so that the voltage Vnd2 of the node ND2 becomes a voltage of "H" level.

[0074] The voltage Vnd2 ("H" level) of the node ND2 is applied to the terminal CLK of the FF circuit FF1, the voltage VREG is applied to the terminal D, and a "L" level voltage is applied from the timer circuit TMR to the terminal R. As a result, a "L" level voltage (for example, voltage GND) is output from the terminal QN of the FF circuit FF1 to the node ND11. The voltage of the node ND11 becomes a "L" level voltage.

[0075] The voltage Vnd2 ("H" level) of the node ND2 is applied to the input terminal of the inverter circuit INV1. The inverter circuit INV1 outputs a "L" level voltage to the node ND9. The voltage of the node ND9 becomes a "L" level voltage.

[0076] The voltage ("L" level) of node ND9 is applied to the terminal CLK of the FF circuit FF2, the voltage VREG is applied to the terminal D, and the voltage ("L" level) of node ND11 is applied to the terminal R. As a result, an "L" level voltage is output from the terminal Q of the FF circuit FF2 to the node ND12. The voltage Vnd12 of the node ND12 becomes an "L" level voltage. As a result, the transistor N4 is turned off. The voltage of the node ND13 becomes an "H" level voltage. As a result, the transistor N5 is turned on. The voltage of the node ND14 becomes an "L" level voltage. As a result, the transistor N6 is turned off.

[0077] The timer circuit TMR outputs a low-level voltage to the node ND10, causing the voltage at the node ND10 to become low.

[0078] The second control circuit CTL2 outputs a high-level voltage to the node ND6 based on the voltage VIN (high level). The voltage Vnd6 at the node ND6 becomes a high-level voltage (for example, a voltage that turns on the transistor N2). This turns on the transistor N2. The voltage at the node ND7 becomes a low-level voltage (for example, the voltage GND). This turns off the transistor N3.

[0079] The drive circuit DRV outputs a high-level voltage to the first output terminal P4 based on the voltage Vnd2 (high level) of the node ND2. The voltage VOUT1 of the first output terminal P4 becomes a high-level voltage (for example, a voltage higher than the voltage VDD). The voltage VOUT1 (high level) is applied from the first output terminal P4 to the gate of the transistor N1. This turns the transistor N1 on. The voltage VDD is supplied to the load LD from the power supply voltage terminal P1. This causes the voltage Vnd1 of the node ND1 to become the voltage VDD. Magnetic energy is stored in the inductor L1. The voltage VOUT2 of the second output terminal P5 becomes the voltage VDD.

[0080] No current flows through the diodes D1 and ZD1 to ZD3.

[0081] At time T2, the input terminal P3 is supplied with the voltage VIN at the "L" level.

[0082] The first control circuit CTL1 outputs a voltage of "L" level to the node ND2 based on the voltage VIN ("L" level). The voltage Vnd2 of the node ND2 becomes a voltage of "L" level.

[0083] The voltage Vnd2 ("L" level) at the node ND2 is applied to the terminal CLK of the FF circuit FF1, the voltage VREG is applied to the terminal D, and a "L" level voltage is applied from the timer circuit TMR to the terminal R. As a result, a "L" level voltage is output from the terminal QN of the FF circuit FF1 to the node ND11. The voltage at the node ND11 becomes a "L" level voltage.

[0084] The voltage Vnd2 ("L" level) of the node ND2 is applied to the input terminal of the inverter circuit INV1. The inverter circuit INV1 outputs a "H" level voltage to the node ND9. The voltage of the node ND9 becomes a "H" level voltage.

[0085] The voltage ("H" level) of node ND9 is applied to the terminal CLK of the FF circuit FF2, the voltage VREG is applied to the terminal D, and the voltage ("L" level) of node ND11 is applied to the terminal R. As a result, a "H" level voltage is output from the terminal Q of the FF circuit FF2 to the node ND12. The voltage Vnd12 of the node ND12 becomes a "H" level voltage. As a result, the transistor N4 is turned on. The voltage of the node ND13 becomes a "L" level voltage (for example, voltage GND). As a result, the transistor N5 is turned off. The voltage of the node ND14 becomes a "H" level voltage. As a result, the transistor N6 is turned on.

[0086] The timer circuit TMR outputs a low-level voltage to the node ND10, causing the voltage at the node ND10 to become low.

[0087] As described above, when the voltage VIN transitions from the “H” level to the “L” level (when the transistor N1 transitions from the on state to the off state), the switching control circuit 30 electrically connects the ground voltage terminal P2 and the clamp circuit 10.

[0088] The second control circuit CTL2 outputs a low-level voltage to the node ND6 based on the voltage VIN (low level). The voltage Vnd6 at the node ND6 becomes a low-level voltage. This turns the transistor N2 off. The voltage at the node ND7 becomes a high-level voltage. This turns the transistor N3 on.

[0089] The drive circuit DRV outputs a low-level voltage to the first output terminal P4 based on the voltage Vnd2 (low level) of the node ND2. The voltage VOUT1 of the first output terminal P4 becomes a low-level voltage. The voltage VOUT1 (low level) is applied from the first output terminal P4 to the gate of the transistor N1. This turns the transistor N1 off. The voltage VDD is not supplied to the load LD from the power supply voltage terminal P1. As a result, the voltage Vnd1 of the node ND1 drops to a negative voltage as the inductor L1 releases magnetic energy.

[0090] When the voltage Vnd1 at node ND1 becomes negative, transistor N6 is turned on, and current begins to flow from the ground voltage terminal P2 to node ND1 via diodes D1, ZD1, ZD2, and ZD3 and the second output terminal P5. The voltage Vnd1 at node ND1 then stops decreasing. This voltage is called the "clamp voltage VCL." The clamp voltage is determined by voltages Vf, Vz1, Vz2, and Vz3. The clamp voltage VCL is lower than voltage GND by the sum of voltages Vf, Vz1, Vz2, and Vz3 (voltage Vf + voltage Vz1 + voltage Vz2 + voltage Vz3). The clamp voltage VCL is set so that the voltage difference Vd between voltage VDD and voltage VCL is smaller than the drain-source breakdown voltage of transistor N1.

[0091] When the inductor L1 finishes discharging magnetic energy, current stops flowing from the ground voltage terminal P2 to the node ND1 via the diodes D1, ZD1, ZD2, and ZD3 and the second output terminal P5, causing the voltage Vnd1 at the node ND1 to rise.

[0092] At time T3, the voltage Vnd1 at the node ND1 becomes the voltage GND, and the voltage VOUT2 at the second output terminal P5 becomes the voltage GND.

[0093] As described above, the clamp circuit 10 controls the voltage Vnd1 of the node ND1 based on the voltage of the ground voltage terminal P2. The operation from time T2 to time T3 corresponds to the first operation.

[0094] At time T4, the timer circuit TMR outputs a high-level voltage to the node ND10. The voltage of the node ND10 becomes a high-level voltage. Time T4 is, for example, when a certain time has elapsed since time T2, that is, when a certain time has elapsed since the voltage Vnd12 of the node ND12 became high.

[0095] The first control circuit CTL1 outputs a voltage of "L" level to the node ND2 based on the voltage VIN ("L" level). The voltage Vnd2 of the node ND2 becomes a voltage of "L" level.

[0096] The voltage Vnd2 ("L" level) at node ND2 is applied to the terminal CLK of the FF circuit FF1, the voltage VREG is applied to the terminal D, and a "H" level voltage is applied from the timer circuit TMR to the terminal R. As a result, the values ​​of the terminals Q and QN of the FF circuit FF1 are reset to the "L" level and the "H" level, respectively. A "H" level voltage is output from the terminal QN of the FF circuit FF1 to the node ND11. The voltage of the node ND11 becomes a "H" level voltage.

[0097] The voltage Vnd2 ("L" level) of the node ND2 is applied to the input terminal of the inverter circuit INV1. The inverter circuit INV1 outputs a "H" level voltage to the node ND9. The voltage of the node ND9 becomes a "H" level voltage.

[0098] The voltage ("H" level) of node ND9 is applied to the terminal CLK of the FF circuit FF2, the voltage VREG is applied to the terminal D, and the voltage ("H" level) of node ND11 is applied to the terminal R. As a result, the values ​​of the terminals Q and QN of the FF circuit FF2 are reset to the "L" level and the "H" level, respectively. A "L" level voltage is output from the terminal Q of the FF circuit FF2 to the node ND12. The voltage Vnd12 of the node ND12 becomes a "L" level voltage. As a result, the transistor N4 is turned off. The voltage of the node ND13 becomes a "H" level voltage. As a result, the transistor N5 is turned on. The voltage of the node ND14 becomes a "L" level voltage. As a result, the transistor N6 is turned off.

[0099] The timer circuit TMR outputs a low-level voltage to the node ND10, causing the voltage at the node ND10 to become low.

[0100] As described above, the switching control circuit 30 electrically connects the ground voltage terminal P2 and the clamp circuit 10, and after a predetermined time has elapsed, electrically disconnects the ground voltage terminal P2 from the clamp circuit 10. In other words, the switching control circuit 30 electrically disconnects the ground voltage terminal P2 from the clamp circuit 10 based on the “H” level voltage (voltage indicating that the predetermined time has elapsed) output by the timer circuit TMR.

[0101] The second control circuit CTL2 outputs a low-level voltage to the node ND6 based on the voltage VIN (low level). The voltage Vnd6 at the node ND6 becomes a low-level voltage. This turns the transistor N2 off. The voltage at the node ND7 becomes a high-level voltage. This turns the transistor N3 on.

[0102] The drive circuit DRV outputs a low-level voltage to the first output terminal P4 based on the voltage Vnd2 (low level) of the node ND2. The voltage VOUT1 of the first output terminal P4 becomes a low-level voltage. The voltage VOUT1 (low level) is applied from the first output terminal P4 to the gate of the transistor N1. This turns the transistor N1 off. The voltage VDD is not supplied to the load LD from the power supply voltage terminal P1. This causes the voltage Vnd1 of the node ND1 to become the voltage GND. The voltage VOUT2 of the second output terminal P5 becomes the voltage GND.

[0103] No current flows through the diodes D1 and ZD1 to ZD3.

[0104] 3, at time T5, the timer circuit TMR outputs a voltage of "L" level to the node ND10, so that the voltage of the node ND10 becomes a voltage of "L" level.

[0105] The operation of the semiconductor device 1 from time T5 to time T6 is the same as that from time T0 to time T1.

[0106] At time T6, the input terminal P3 is supplied with the voltage VIN at "H" level.

[0107] The operation of the semiconductor device 1 from time T6 to time T7 is the same as that from time T1 to time T2.

[0108] At time T7, the ground voltage terminal P2 is disconnected from the GND. At this time, the transistor N6 is in the off state. That is, the switching control circuit 30 electrically disconnects the ground voltage terminal P2 from the clamp circuit 10.

[0109] When the ground voltage terminal P2 is disconnected from GND, the voltage at the ground voltage terminal P2 becomes unstable. Because the transistor N6 is off, the voltage at the ground voltage terminal P2 rises to the voltage VDD.

[0110] At time T8, the voltage difference between the power supply voltage terminal P1 and the ground voltage terminal P2 becomes smaller than the voltage value capable of driving the second control circuit CTL2. As a result, the second control circuit CTL2 outputs a low-level voltage to the node ND6. The voltage Vnd6 of the node ND6 becomes a low-level voltage. As a result, the transistor N2 is turned off.

[0111] At time T9, the voltage at node ND7 goes high. This turns on transistor N3. Charge is rapidly drawn from the gate of transistor N1 to the second output terminal P5. This causes the voltage at the gate of transistor N1 to drop quickly.

[0112] At time T10, the voltage at the gate of transistor N1 becomes voltage GND. This turns transistor N1 off. In other words, the voltage VOUT1 at the first output terminal P4 becomes a voltage that turns transistor N1 off. The voltage VDD is not supplied to the load LD from the power supply voltage terminal P1. This causes the voltage Vnd1 at node ND1 to become voltage GND. The voltage VOUT2 at the second output terminal P5 becomes voltage GND.

[0113] Other operations of the semiconductor device 1 from time T7 to time T10 are similar to those from time T1 to time T2.

[0114] As described above, the disconnection protection circuit 20 controls the voltage at the first output terminal P4 based on the voltage at the ground voltage terminal P2 and the voltage at the input terminal P3. The operation from time T7 to time T10 corresponds to the second operation.

[0115] 1.3 Effects The configuration according to this embodiment can suppress malfunction of the semiconductor device. This effect will be described below.

[0116] When the ground voltage terminal P2 is disconnected from the GND, the voltage at the ground voltage terminal P2 becomes unstable. If the ground voltage terminal P2 is electrically connected to the clamp circuit 10, the voltage at the ground voltage terminal P2 may be clamped due to the electrical connection between the ground voltage terminal P2 and node ND1 via diodes D1, ZD1, ZD2, and ZD3 and the second output terminal P5. When the voltage at the ground voltage terminal P2 is clamped, the voltage at the ground voltage terminal P2 may not rise to voltage VDD. In this case, the second control circuit CTL2 outputs a high-level voltage. This turns on transistor N2 and turns off transistor N3. Therefore, the gate voltage of transistor N1 cannot be lowered to a low-level voltage, and transistor N1 may be unintentionally turned on. In this case, transistor N1 may overheat and be damaged.

[0117] In contrast, in this embodiment, when the ground voltage terminal P2 is in a GND disconnection state, the transistor N6 is turned off. That is, the ground voltage terminal P2 is not electrically connected to the clamp circuit 10. In other words, the ground voltage terminal P2 is not electrically connected to the node ND1 via the diodes D1, ZD1, ZD2, and ZD3 and the second output terminal P5. Therefore, the voltage of the ground voltage terminal P2 is not clamped. Therefore, the voltage of the ground voltage terminal P2 rises to the voltage VDD. When the voltage of the ground voltage terminal P2 rises to the voltage VDD, the second control circuit CTL2 outputs a low-level voltage. This turns off the transistor N2 and turns on the transistor N3. This allows the gate voltage of the transistor N1 to be lowered to the low-level voltage, turning off the transistor N1. This prevents the transistor N1 from overheating and breaking down.

[0118] In this embodiment, when the voltage VIN transitions from the "H" level to the "L" level, the transistor N6 is turned on. That is, the ground voltage terminal P2 and the clamp circuit 10 are electrically connected. In other words, the ground voltage terminal P2 and the node ND1 are electrically connected via the diodes D1, ZD1, ZD2, and ZD3 and the second output terminal P5. Therefore, the voltage Vnd1 of the node ND1 is clamped to the clamp voltage VCL. The clamp voltage VCL is set so that the voltage difference Vd between the voltage VDD and the voltage VCL is smaller than the drain-source breakdown voltage of the transistor N1. This prevents the transistor N1 from exceeding the drain-source breakdown voltage and breaking down.

[0119] Therefore, according to this embodiment, malfunction of the semiconductor device can be suppressed.

[0120] 2. Second embodiment A semiconductor device according to a second embodiment will be described. The semiconductor device according to this embodiment differs from the first embodiment in the configuration of the semiconductor device. The following description will focus on the differences from the first embodiment.

[0121] 2.1 Circuit configuration of semiconductor device The circuit configuration of the semiconductor device according to this embodiment will be described with reference to Fig. 4. Fig. 4 is a circuit diagram showing an example of a semiconductor device.

[0122] The semiconductor device 1 includes a protection circuit PRT.

[0123] The protection circuit PRT is a circuit that protects the semiconductor device 1 when some kind of abnormality is detected. The protection circuit PRT is, for example, an overheat protection circuit or an overcurrent protection circuit. The overheat protection circuit determines that the semiconductor device 1 is abnormal (detects the abnormality) when, for example, the temperature of the semiconductor device 1 becomes higher than a reference value. The overcurrent protection circuit determines that the semiconductor device 1 is abnormal (detects the abnormality) when, for example, the current flowing through the semiconductor device 1 becomes higher than a reference value. The protection circuit PRT is connected to a node ND15.

[0124] The protection circuit PRT outputs a high ("H") level voltage or a low ("L") level voltage to the node ND15. When the protection circuit PRT does not detect an abnormality (when the semiconductor device 1 is normal), the protection circuit PRT outputs an "H" level voltage. On the other hand, when the protection circuit PRT detects an abnormality (when the semiconductor device 1 is abnormal), the protection circuit PRT outputs an "L" level voltage. The "L" level voltage is, for example, the voltage GND.

[0125] The driver circuit DRV is connected to the nodes ND2 and ND15 and the first output terminal P4. The voltage Vnd2 at the node ND2 and the voltage at the node ND15 (hereinafter referred to as "voltage Vnd15") are applied to the driver circuit DRV. The driver circuit DRV outputs a voltage based on the voltages Vnd2 and Vnd15 to the first output terminal P4. When the voltage Vnd15 at the node ND15 is at "H" level, the driver circuit DRV outputs a voltage based on the voltage VIN (voltage Vnd2). On the other hand, when the voltage Vnd15 at the node ND15 is at "L" level, the driver circuit DRV outputs a voltage at "L" level.

[0126] The switching control circuit 30 is connected to the power supply voltage terminal P1, the ground voltage terminal P2, and the nodes ND2, ND3, and ND15. The switching control circuit 30 will be described in detail later.

[0127] The configuration of the semiconductor device 1 other than the switching control circuit 30 is the same as that of the first embodiment.

[0128] 2.2 Configuration of the switching control circuit The circuit configuration of the switching control circuit 30 will be described.

[0129] As shown in FIG. 4, the switching control circuit 30 includes a NAND circuit NAND1 and an inverter circuit INV2.

[0130] One input terminal of the NAND circuit NAND1 is connected to the node ND2, the other input terminal is connected to the node ND15, and the output terminal is connected to the node ND16.

[0131] The input terminal of the inverter circuit INV2 is connected to the node ND16, and the output terminal is connected to the node ND17.

[0132] The input terminal of the inverter circuit INV1 is connected to the node ND17, and the output terminal is connected to the node ND9.

[0133] The terminal CLK of the FF circuit FF1 is connected to the node ND17, the voltage VREG is applied to the terminal D, and the terminal R is connected to the node ND10. The terminal QN of the FF circuit FF1 is connected to the node ND11.

[0134] Other configurations of the switching control circuit 30 are the same as those in the first embodiment.

[0135] 2.3 Operation The operation of the semiconductor device 1 according to this embodiment will be described. The operations performed by the semiconductor device 1 include a first operation, a second operation, and a third operation. The third operation is an operation for controlling the source voltage of the transistor N1 (the voltage Vnd1 of the node ND1) when the protection circuit PRT detects an abnormality.

[0136] The voltages at various terminals and the like during operation of the semiconductor device 1 will be described with reference to Figures 5 to 7. Figures 5 to 7 are timing charts showing the voltages at various terminals and the like during operation of the semiconductor device 1. Below, a case will be described in which the ground voltage terminal P2 is in an undisconnected state with the outside GND from time T0 to time T12, the protection circuit PRT detects an abnormality from time T7 to time T8, and the ground voltage terminal P2 is in a disconnected state with the outside GND at time T12.

[0137] 5, from time T0 to time T1, a voltage VIN (for example, voltage GND) at an "L" level is supplied to the input terminal P3, and a voltage GND is supplied to the ground voltage terminal P2.

[0138] The first control circuit CTL1 outputs a low-level voltage to the node ND2 based on the voltage VIN (low level). The voltage Vnd2 of the node ND2 becomes a low-level voltage (for example, the voltage GND).

[0139] The protection circuit PRT outputs a high-level voltage to the node ND15, causing the voltage Vnd15 of the node ND15 to become a high-level voltage.

[0140] The voltage Vnd2 ("L" level) of the node ND2 is applied to one input terminal of the NAND circuit NAND1, and the voltage Vnd15 ("H" level) of the node ND15 is applied to the other input terminal. The NAND circuit NAND1 outputs a "H" level voltage to the node ND16. The voltage of the node ND16 becomes a "H" level voltage.

[0141] The voltage ("H" level) of the node ND16 is applied to the input terminal of the inverter circuit INV2. The inverter circuit INV2 outputs a "L" level voltage to the node ND17. The voltage of the node ND17 becomes a "L" level voltage.

[0142] The voltage ("L" level) of node ND17 is applied to terminal CLK of FF circuit FF1, voltage VREG is applied to terminal D, and a "L" level voltage is applied from timer circuit TMR to terminal R. As a result, a "H" level voltage is output from terminal QN of FF circuit FF1 to node ND11. The voltage of node ND11 becomes a "H" level voltage.

[0143] The voltage ("L" level) of the node ND17 is applied to the input terminal of the inverter circuit INV1. The inverter circuit INV1 outputs a "H" level voltage to the node ND9. The voltage of the node ND9 becomes a "H" level voltage.

[0144] The voltage ("H" level) of the node ND9 is applied to the terminal CLK of the FF circuit FF2, the voltage VREG is applied to the terminal D, and the voltage ("H" level) of the node ND11 is applied to the terminal R. As a result, the values ​​of the terminals Q and QN of the FF circuit FF2 are reset to the "L" level and the "H" level, respectively. A "L" level voltage (e.g., voltage GND) is output from the terminal Q of the FF circuit FF2 to the node ND12. The voltage Vnd12 of the node ND12 becomes a "L" level voltage (e.g., voltage GND). As a result, the transistor N4 is turned off. The voltage of the node ND13 becomes a "H" level voltage. As a result, the transistor N5 is turned on. The voltage of the node ND14 becomes a "L" level voltage (e.g., voltage GND). As a result, the transistor N6 is turned off.

[0145] The timer circuit TMR outputs a low-level voltage (for example, the voltage GND) to the node ND10, causing the voltage of the node ND10 to become a low-level voltage.

[0146] The second control circuit CTL2 outputs a low-level voltage to the node ND6 based on the voltage VIN (low level). The voltage Vnd6 at the node ND6 becomes a low-level voltage (for example, voltage GND). This turns the transistor N2 off. The voltage at the node ND7 becomes a high-level voltage (for example, a voltage that turns on the transistor N3). This turns the transistor N3 on.

[0147] The drive circuit DRV outputs a low-level voltage to the first output terminal P4 based on the voltage Vnd2 (low level) of the node ND2 and the voltage Vnd15 (high level) of the node ND15. The voltage VOUT1 of the first output terminal P4 becomes a low-level voltage (e.g., GND). The voltage VOUT1 (low level) is applied from the first output terminal P4 to the gate of the transistor N1. This turns the transistor N1 off. The voltage VDD is not supplied to the load LD from the power supply voltage terminal P1. This causes the voltage Vnd1 of the node ND1 to become the voltage GND. The voltage VOUT2 of the second output terminal P5 becomes the voltage GND.

[0148] No current flows through the diodes D1 and ZD1 to ZD3.

[0149] At time T1, the input terminal P3 is supplied with a voltage VIN at "H" level.

[0150] The first control circuit CTL1 outputs a voltage of "H" level to the node ND2 based on the voltage VIN ("H" level), so that the voltage Vnd2 of the node ND2 becomes a voltage of "H" level.

[0151] The protection circuit PRT outputs a high-level voltage to the node ND15, causing the voltage Vnd15 of the node ND15 to become a high-level voltage.

[0152] The voltage Vnd2 ("H" level) of the node ND2 is applied to one input terminal of the NAND circuit NAND1, and the voltage Vnd15 ("H" level) of the node ND15 is applied to the other input terminal. The NAND circuit NAND1 outputs a "L" level voltage to the node ND16. The voltage of the node ND16 becomes a "L" level voltage.

[0153] The voltage ("L" level) of the node ND16 is applied to the input terminal of the inverter circuit INV2. The inverter circuit INV2 outputs a "H" level voltage to the node ND17. The voltage of the node ND17 becomes a "H" level voltage.

[0154] The voltage ("H" level) of the node ND17 is applied to the terminal CLK of the FF circuit FF1, the voltage VREG is applied to the terminal D, and the "L" level voltage from the timer circuit TMR is applied to the terminal R. As a result, a "L" level voltage (for example, voltage GND) is output from the terminal QN of the FF circuit FF1 to the node ND11. The voltage of the node ND11 becomes a "L" level voltage.

[0155] The voltage ("H" level) of the node ND17 is applied to the input terminal of the inverter circuit INV1. The inverter circuit INV1 outputs a "L" level voltage to the node ND9. The voltage of the node ND9 becomes a "L" level voltage.

[0156] The voltage ("L" level) of node ND9 is applied to the terminal CLK of the FF circuit FF2, the voltage VREG is applied to the terminal D, and the voltage ("L" level) of node ND11 is applied to the terminal R. As a result, an "L" level voltage is output from the terminal Q of the FF circuit FF2 to the node ND12. The voltage Vnd12 of the node ND12 becomes an "L" level voltage. As a result, the transistor N4 is turned off. The voltage of the node ND13 becomes an "H" level voltage. As a result, the transistor N5 is turned on. The voltage of the node ND14 becomes an "L" level voltage. As a result, the transistor N6 is turned off.

[0157] The timer circuit TMR outputs a low-level voltage to the node ND10, causing the voltage at the node ND10 to become low.

[0158] The second control circuit CTL2 outputs a high-level voltage to the node ND6 based on the voltage VIN (high level). The voltage Vnd6 at the node ND6 becomes a high-level voltage (for example, a voltage that turns on the transistor N2). This turns on the transistor N2. The voltage at the node ND7 becomes a low-level voltage (for example, the voltage GND). This turns off the transistor N3.

[0159] The drive circuit DRV outputs a high-level voltage to the first output terminal P4 based on the voltage Vnd2 (high level) of the node ND2 and the voltage Vnd15 (high level) of the node ND15. The voltage VOUT1 of the first output terminal P4 becomes a high-level voltage (for example, a voltage higher than the voltage VDD). The voltage VOUT1 (high level) is applied from the first output terminal P4 to the gate of the transistor N1. This turns the transistor N1 on. The voltage VDD is supplied to the load LD from the power supply voltage terminal P1. This causes the voltage Vnd1 of the node ND1 to become the voltage VDD. Magnetic energy is stored in the inductor L1. The voltage VOUT2 of the second output terminal P5 becomes the voltage VDD.

[0160] No current flows through the diodes D1 and ZD1 to ZD3.

[0161] At time T2, the input terminal P3 is supplied with the voltage VIN at the "L" level.

[0162] The first control circuit CTL1 outputs a voltage of "L" level to the node ND2 based on the voltage VIN ("L" level). The voltage Vnd2 of the node ND2 becomes a voltage of "L" level.

[0163] The protection circuit PRT outputs a high-level voltage to the node ND15, causing the voltage Vnd15 of the node ND15 to become a high-level voltage.

[0164] The voltage Vnd2 ("L" level) of the node ND2 is applied to one input terminal of the NAND circuit NAND1, and the voltage Vnd15 ("H" level) of the node ND15 is applied to the other input terminal. The NAND circuit NAND1 outputs a "H" level voltage to the node ND16. The voltage of the node ND16 becomes a "H" level voltage.

[0165] The voltage ("H" level) of the node ND16 is applied to the input terminal of the inverter circuit INV2. The inverter circuit INV2 outputs a "L" level voltage to the node ND17. The voltage of the node ND17 becomes a "L" level voltage.

[0166] The voltage ("L" level) of node ND17 is applied to terminal CLK of FF circuit FF1, voltage VREG is applied to terminal D, and a "L" level voltage from timer circuit TMR is applied to terminal R. As a result, a "L" level voltage is output from terminal QN of FF circuit FF1 to node ND11. The voltage of node ND11 becomes a "L" level voltage.

[0167] The voltage ("L" level) of the node ND17 is applied to the input terminal of the inverter circuit INV1. The inverter circuit INV1 outputs a "H" level voltage to the node ND9. The voltage of the node ND9 becomes a "H" level voltage.

[0168] The voltage ("H" level) of node ND9 is applied to the terminal CLK of the FF circuit FF2, the voltage VREG is applied to the terminal D, and the voltage ("L" level) of node ND11 is applied to the terminal R. As a result, a "H" level voltage is output from the terminal Q of the FF circuit FF2 to the node ND12. The voltage Vnd12 of the node ND12 becomes a "H" level voltage. As a result, the transistor N4 is turned on. The voltage of the node ND13 becomes a "L" level voltage (for example, voltage GND). As a result, the transistor N5 is turned off. The voltage of the node ND14 becomes a "H" level voltage. As a result, the transistor N6 is turned on.

[0169] The timer circuit TMR outputs a low-level voltage to the node ND10, causing the voltage at the node ND10 to become low.

[0170] As described above, when the voltage VIN transitions from the “H” level to the “L” level (when the transistor N1 transitions from the on state to the off state), the switching control circuit 30 electrically connects the ground voltage terminal P2 and the clamp circuit 10.

[0171] The second control circuit CTL2 outputs a low-level voltage to the node ND6 based on the voltage VIN (low level). The voltage Vnd6 at the node ND6 becomes a low-level voltage. This turns the transistor N2 off. The voltage at the node ND7 becomes a high-level voltage. This turns the transistor N3 on.

[0172] The drive circuit DRV outputs a low-level voltage to the first output terminal P4 based on the voltage Vnd2 (low level) of the node ND2 and the voltage Vnd15 (high level) of the node ND15. The voltage VOUT1 of the first output terminal P4 becomes a low-level voltage. The voltage VOUT1 (low level) is applied from the first output terminal P4 to the gate of the transistor N1. This turns the transistor N1 off. The voltage VDD is not supplied to the load LD from the power supply voltage terminal P1. As a result, the voltage Vnd1 of the node ND1 drops to a negative voltage as the inductor L1 releases magnetic energy. As in the first embodiment, the voltage Vnd1 of the node ND1 drops to the clamp voltage VCL and then rises.

[0173] At time T3, the voltage Vnd1 at the node ND1 becomes the voltage GND, and the voltage VOUT2 at the second output terminal P5 becomes the voltage GND.

[0174] As described above, the clamp circuit 10 controls the voltage Vnd1 of the node ND1 based on the voltage of the ground voltage terminal P2. The operation from time T2 to time T3 corresponds to the first operation.

[0175] At time T4, the timer circuit TMR outputs a high-level voltage to the node ND10. The voltage of the node ND10 becomes a high-level voltage. Time T4 is, for example, when a certain time has elapsed since time T2, that is, when a certain time has elapsed since the voltage Vnd12 of the node ND12 became high.

[0176] The first control circuit CTL1 outputs a voltage of "L" level to the node ND2 based on the voltage VIN ("L" level). The voltage Vnd2 of the node ND2 becomes a voltage of "L" level.

[0177] The protection circuit PRT outputs a high-level voltage to the node ND15, causing the voltage Vnd15 of the node ND15 to become a high-level voltage.

[0178] The voltage Vnd2 ("L" level) of the node ND2 is applied to one input terminal of the NAND circuit NAND1, and the voltage Vnd15 ("H" level) of the node ND15 is applied to the other input terminal. The NAND circuit NAND1 outputs a "H" level voltage to the node ND16. The voltage of the node ND16 becomes a "H" level voltage.

[0179] The voltage ("H" level) of the node ND16 is applied to the input terminal of the inverter circuit INV2. The inverter circuit INV2 outputs a "L" level voltage to the node ND17. The voltage of the node ND17 becomes a "L" level voltage.

[0180] The voltage ("L" level) of node ND17 is applied to the terminal CLK of FF circuit FF1, the voltage VREG is applied to terminal D, and a "H" level voltage is applied from the timer circuit TMR to terminal R. As a result, the values ​​of terminals Q and QN of FF circuit FF1 are reset to "L" level and "H" level, respectively. A "H" level voltage is output from terminal QN of FF circuit FF1 to node ND11. The voltage of node ND11 becomes a "H" level voltage.

[0181] The voltage ("L" level) of the node ND17 is applied to the input terminal of the inverter circuit INV1. The inverter circuit INV1 outputs a "H" level voltage to the node ND9. The voltage of the node ND9 becomes a "H" level voltage.

[0182] The voltage ("H" level) of node ND9 is applied to the terminal CLK of the FF circuit FF2, the voltage VREG is applied to the terminal D, and the voltage ("H" level) of node ND11 is applied to the terminal R. As a result, the values ​​of the terminals Q and QN of the FF circuit FF2 are reset to the "L" level and the "H" level, respectively. A "L" level voltage is output from the terminal Q of the FF circuit FF2 to the node ND12. The voltage Vnd12 of the node ND12 becomes a "L" level voltage. As a result, the transistor N4 is turned off. The voltage of the node ND13 becomes a "H" level voltage. As a result, the transistor N5 is turned on. The voltage of the node ND14 becomes a "L" level voltage. As a result, the transistor N6 is turned off.

[0183] The timer circuit TMR outputs a low-level voltage to the node ND10, causing the voltage at the node ND10 to become low.

[0184] As described above, the switching control circuit 30 electrically connects the ground voltage terminal P2 and the clamp circuit 10, and then electrically disconnects the ground voltage terminal P2 and the clamp circuit 10 after a predetermined time has elapsed.

[0185] The second control circuit CTL2 outputs a low-level voltage to the node ND6 based on the voltage VIN (low level). The voltage Vnd6 at the node ND6 becomes a low-level voltage. This turns the transistor N2 off. The voltage at the node ND7 becomes a high-level voltage. This turns the transistor N3 on.

[0186] The drive circuit DRV outputs a low-level voltage to the first output terminal P4 based on the voltage Vnd2 (low level) of the node ND2 and the voltage Vnd15 (high level) of the node ND15. The voltage VOUT1 of the first output terminal P4 becomes a low-level voltage. The voltage VOUT1 (low level) is applied from the first output terminal P4 to the gate of the transistor N1. This turns the transistor N1 off. The voltage VDD is not supplied to the load LD from the power supply voltage terminal P1. This causes the voltage Vnd1 of the node ND1 to become the voltage GND. The voltage VOUT2 of the second output terminal P5 becomes the voltage GND.

[0187] No current flows through the diodes D1 and ZD1 to ZD3.

[0188] 6, at time T5, the timer circuit TMR outputs a voltage of "L" level to the node ND10, so that the voltage of the node ND10 becomes a voltage of "L" level.

[0189] The operation of the semiconductor device 1 from time T5 to time T6 is the same as that from time T0 to time T1.

[0190] At time T6, the input terminal P3 is supplied with the voltage VIN at "H" level.

[0191] The operation of the semiconductor device 1 from time T6 to time T7 is the same as that from time T1 to time T2.

[0192] At time T7, the protection circuit PRT detects an abnormality.

[0193] When an abnormality is detected, the protection circuit PRT outputs a voltage of "L" level to the node ND15. The voltage Vnd15 of the node ND15 becomes a voltage of "L" level (for example, the voltage GND).

[0194] The voltage Vnd2 ("H" level) of the node ND2 is applied to one input terminal of the NAND circuit NAND1, and the voltage Vnd15 ("L" level) of the node ND15 is applied to the other input terminal. The NAND circuit NAND1 outputs a "H" level voltage to the node ND16. The voltage of the node ND16 becomes a "H" level voltage.

[0195] The voltage ("H" level) of the node ND16 is applied to the input terminal of the inverter circuit INV2. The inverter circuit INV2 outputs a "L" level voltage to the node ND17. The voltage of the node ND17 becomes a "L" level voltage.

[0196] The voltage ("L" level) of node ND17 is applied to terminal CLK of FF circuit FF1, voltage VREG is applied to terminal D, and a "L" level voltage from timer circuit TMR is applied to terminal R. As a result, a "L" level voltage is output from terminal QN of FF circuit FF1 to node ND11. The voltage of node ND11 becomes a "L" level voltage.

[0197] The voltage ("L" level) of the node ND17 is applied to the input terminal of the inverter circuit INV1. The inverter circuit INV1 outputs a "H" level voltage to the node ND9. The voltage of the node ND9 becomes a "H" level voltage.

[0198] The voltage ("H" level) of node ND9 is applied to the terminal CLK of the FF circuit FF2, the voltage VREG is applied to the terminal D, and the voltage ("L" level) of node ND11 is applied to the terminal R. As a result, a "H" level voltage is output from the terminal Q of the FF circuit FF2 to the node ND12. The voltage Vnd12 of the node ND12 becomes a "H" level voltage. As a result, the transistor N4 is turned on. The voltage of the node ND13 becomes a "L" level voltage (for example, voltage GND). As a result, the transistor N5 is turned off. The voltage of the node ND14 becomes a "H" level voltage. As a result, the transistor N6 is turned on.

[0199] The timer circuit TMR outputs a low-level voltage to the node ND10, causing the voltage at the node ND10 to become low.

[0200] As described above, when the protection circuit PRT detects an abnormality, the switching control circuit 30 electrically connects the ground voltage terminal P2 and the clamp circuit 10.

[0201] The second control circuit CTL2 outputs a low-level voltage to the node ND6. The voltage Vnd6 at the node ND6 becomes a low-level voltage. This turns the transistor N2 off. The voltage at the node ND7 becomes a high-level voltage. This turns the transistor N3 on.

[0202] The drive circuit DRV outputs a low-level voltage to the first output terminal P4 based on the voltage Vnd2 (low level) of the node ND2 and the voltage Vnd15 (high level) of the node ND15. The voltage VOUT1 of the first output terminal P4 becomes a low-level voltage. The voltage VOUT1 (low level) is applied from the first output terminal P4 to the gate of the transistor N1. This turns the transistor N1 off. The voltage VDD is not supplied to the load LD from the power supply voltage terminal P1. As a result, the voltage Vnd1 of the node ND1 drops to a negative voltage as the inductor L1 releases magnetic energy. As in the first operation, the voltage Vnd1 of the node ND1 drops to the clamp voltage VCL and then rises.

[0203] At time T8, the input terminal P3 is supplied with the "L" level voltage VIN. The voltage Vnd1 at the node ND1 becomes the voltage GND. The voltage VOUT2 at the second output terminal P5 becomes the voltage GND. As a result, the protection circuit PRT no longer detects an abnormality.

[0204] When the protection circuit PRT no longer detects an abnormality, it outputs a high-level voltage to the node ND15, causing the voltage Vnd15 of the node ND15 to become a high-level voltage.

[0205] As described above, the clamp circuit 10 controls the voltage Vnd1 of the node ND1 based on the voltage of the ground voltage terminal P2. The operation from time T7 to time T8 corresponds to the third operation.

[0206] The operation of the semiconductor device 1 from time T8 to time T10 is the same as that from time T3 to time T5.

[0207] 7, at time T10, the timer circuit TMR outputs a voltage of "L" level to the node ND10, so that the voltage of the node ND10 becomes a voltage of "L" level.

[0208] The operation of the semiconductor device 1 from time T10 to time T11 is the same as that from time T0 to time T1.

[0209] At time T11, the input terminal P3 is supplied with the voltage VIN at "H" level.

[0210] The operation of the semiconductor device 1 from time T11 to time T12 is the same as that from time T1 to time T2.

[0211] At time T12, the ground voltage terminal P2 is disconnected from the GND. At this time, the transistor N6 is in the off state. That is, the switching control circuit 30 electrically disconnects the ground voltage terminal P2 from the clamp circuit 10.

[0212] When the ground voltage terminal P2 is disconnected from GND, the voltage at the ground voltage terminal P2 becomes unstable. Because the transistor N6 is off, the voltage at the ground voltage terminal P2 rises to the voltage VDD.

[0213] At time T13, the voltage difference between the power supply voltage terminal P1 and the ground voltage terminal P2 becomes smaller than the voltage value capable of driving the second control circuit CTL2. As a result, the second control circuit CTL2 outputs a low-level voltage to the node ND6. The voltage Vnd6 of the node ND6 becomes a low-level voltage. As a result, the transistor N2 is turned off.

[0214] At time T14, the voltage at node ND7 goes high. This turns on transistor N3. Charge is rapidly drawn from the gate of transistor N1 to the second output terminal P5. This causes the voltage at the gate of transistor N1 to drop quickly.

[0215] At time T15, the voltage at the gate of transistor N1 becomes voltage GND. This turns transistor N1 off. In other words, the voltage VOUT1 at the first output terminal P4 becomes a voltage that turns transistor N1 off. The voltage VDD is not supplied to the load LD from the power supply voltage terminal P1. This causes the voltage Vnd1 at node ND1 to become voltage GND. The voltage VOUT2 at the second output terminal P5 becomes voltage GND.

[0216] Other operations of the semiconductor device 1 from time T12 to time T15 are similar to those from time T1 to time T2.

[0217] As described above, the disconnection protection circuit 20 controls the voltage at the first output terminal P4 based on the voltage at the ground voltage terminal P2 and the voltage at the input terminal P3. The operation from time T12 to time T15 corresponds to the second operation.

[0218] 2.4 Effects The configuration according to this embodiment provides the same effects as the first embodiment.

[0219] Furthermore, in this embodiment, when the protection circuit PRT detects an abnormality, the transistor N6 is turned on. That is, the ground voltage terminal P2 and the clamp circuit 10 are electrically connected. In other words, the ground voltage terminal P2 and the node ND1 are electrically connected via the diodes D1, ZD1, ZD2, and ZD3 and the second output terminal P5. Therefore, similar to the first operation, the voltage Vnd1 of the node ND1 is clamped to the clamp voltage VCL. Therefore, even when the protection circuit PRT detects an abnormality, the transistor N1 can be prevented from exceeding the drain-source breakdown voltage and being broken.

[0220] 3. Modifications, etc. As described above, the semiconductor device (1) according to the embodiment includes a first transistor (N1) having one end connected to a power supply voltage terminal (P1), the other end connected to a first node (ND1), and a gate connected to a first output terminal (P4), a first circuit (10) that controls a voltage (Vnd1) at the first node (ND1) based on a voltage at a ground voltage terminal (P2), a second circuit (20) that controls a voltage (VOUT1) at the first output terminal (P4) based on the voltage at the ground voltage terminal (P2) and the voltage (VIN) at the input terminal (P3), and a third circuit (30) that controls switching between connection and disconnection between the ground voltage terminal (P2) and the first circuit (10).

[0221] The embodiment is not limited to the above-described embodiment, and various modifications are possible.

[0222] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, as well as within the scope of the invention described in the claims and their equivalents. [Explanation of symbols]

[0223] 1...semiconductor device, 10...clamp circuit, 20...disconnection protection circuit, 30...switching control circuit, P1...power supply voltage terminal, P2...ground voltage terminal, P3...input terminal, P4...first output terminal, P5...second output terminal, SW...switching element, CTL1...first control circuit, DRV...drive circuit, CTL2...second control circuit, INV1, INV2...inverter circuit, FF1, FF2...FF circuit, TMR...timer circuit, NAND1...NAND circuit, PRT...protection circuit, LD...load, N1 to N6...NMOS transistors, R1 to R10...resistance element, L1...inductor, D1...diode, ZD1 to ZD3...Zener diode

Claims

1. a first transistor having one end connected to a power supply voltage terminal, the other end connected to a first node, and a gate connected to a first output terminal; a first circuit having a diode connected between a ground voltage terminal and the first node, and clamping and controlling the voltage of the first node based on the voltage of the ground voltage terminal; a control circuit connected to the power supply voltage terminal, the ground voltage terminal, and an input terminal, which determines whether the ground voltage terminal is in a disconnected state with the outside based on a voltage difference between the power supply voltage terminal and the ground voltage terminal, and outputs a first voltage based on the voltage of the input terminal if the ground voltage terminal is not in a disconnected state, and outputs a second voltage if the ground voltage terminal is in a disconnected state; a second transistor, one end of which is connected to the first output terminal and the other end of which is connected to the first node, and a third voltage based on the voltage output by the control circuit is applied to a gate of the second transistor; a second circuit that controls the second transistor based on the voltage output by the control circuit, thereby controlling the voltage of the first output terminal; a third transistor having one end connected to the ground voltage terminal, the other end connected to the first circuit, and a gate connected to the power supply voltage terminal; A timer circuit that measures time and outputs voltage. a third circuit that controls switching between connection and disconnection between the ground voltage terminal and the first circuit by controlling the third transistor based on the voltage output by the timer circuit; Equipped with when the ground voltage terminal is not disconnected from the outside and the first transistor transitions from an on state to an off state, the third circuit turns the third transistor on, the first circuit clamps the voltage of the first node based on the voltage of the ground voltage terminal, and the third circuit turns the third transistor off based on the voltage of the timer circuit output after a predetermined time has elapsed; When the ground voltage terminal is disconnected from the outside, the third circuit turns the third transistor off, and the second circuit turns the second transistor on. Semiconductor device.

2. When the ground voltage terminal is in a non-disconnected state with the outside and the first transistor transitions from an on state to an off state, if the third circuit turns the third transistor on, the voltage of the first node does not drop from the power supply voltage beyond the breakdown voltage between the one end and the other end of the first transistor, The semiconductor device according to claim 1.

3. When the ground voltage terminal is disconnected from the outside, if the third circuit turns off the third transistor, the voltage of the first output terminal becomes a voltage that turns off the first transistor. The semiconductor device according to claim 1.

4. a fourth circuit for detecting an abnormality in the semiconductor device; Further provided with When the ground voltage terminal is not disconnected from the outside and the fourth circuit detects an abnormality, the third circuit turns on the third transistor. The semiconductor device according to claim 1.

5. when the third circuit turns on the third transistor, the voltage of the first node does not drop from a power supply voltage to a level exceeding a breakdown voltage between the one end and the other end of the first transistor; 5. The semiconductor device according to claim 4.

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