Semiconductor Devices

Abstract

To provide a semiconductor device capable of reducing on-resistance.SOLUTION: A semiconductor device includes: a first electrode (drain electrode); a first conductivity-type first semiconductor region (drift region 1); a conductive portion 20; a second conductivity-type second semiconductor region (base region 2); a first conductivity-type third semiconductor region (source region 3); a gate electrode 31; and a second electrode (source electrode). The first semiconductor region is provided on the first electrode, and is electrically connected to the first electrode. A plurality of the conductive portions are provided via an insulating portion 10 in the first semiconductor region and are respectively provided in a second direction D2 and a third direction D3. The second semiconductor region is provided on a portion of the first semiconductor region. The third semiconductor region is provided on a portion of the second semiconductor region. The second electrode is provided on the second semiconductor region, the third semiconductor region, and the gate electrode, and is electrically connected to the second semiconductor region, the third semiconductor region, and the plurality of conductive portions.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] FIELD An embodiment of the present invention relates to a semiconductor device. [Background technology]

[0002] Semiconductor devices such as metal oxide semiconductor field effect transistors (MOSFETs) are used for power conversion, etc. It is desirable for semiconductor devices to have low on-resistance. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2002-83963 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a semiconductor device capable of reducing the on-resistance. [Means for solving the problem]

[0005] The semiconductor device according to the embodiment includes a first electrode, a first semiconductor region of a first conductivity type, a conductive portion, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type, a gate electrode, and a second electrode. The first semiconductor region is provided on the first electrode and electrically connected to the first electrode. The conductive portions are provided in the first semiconductor region with insulating portions interposed therebetween, and a plurality of conductive portions are provided in a second direction and a third direction. The second direction is perpendicular to a first direction extending from the first electrode toward the first semiconductor region. The third direction is perpendicular to the first direction and intersects with the second direction. The second semiconductor region is provided on a portion of the first semiconductor region. The third semiconductor region is provided on a portion of the second semiconductor region. The gate electrode is provided on the second semiconductor region via a gate insulating layer. The second electrode is provided on the second semiconductor region, the third semiconductor region, and the gate electrode, and is electrically connected to the second semiconductor region, the third semiconductor region, and the plurality of conductive portions. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a plan view showing a semiconductor device according to an embodiment. [Figure 2] FIG. 2 is an enlarged plan view of a portion A of FIG. [Figure 3] FIG. 3 is an enlarged plan view of a portion A in FIG. [Figure 4] FIG. 4 is a cross-sectional view taken along the line B1-B2 in FIGS. [Figure 5] 5(a) and 5(b) are plan and cross-sectional views showing a portion of the semiconductor device according to the embodiment. [Figure 6] 6(a) and 6(b) are cross-sectional views showing a method for manufacturing a semiconductor device according to the embodiment. [Figure 7] 7(a) and 7(b) are cross-sectional views showing a method for manufacturing a semiconductor device according to the embodiment. [Figure 8]8(a) and 8(b) are cross-sectional views showing a method for manufacturing a semiconductor device according to the embodiment. [Figure 9] FIG. 9 is a cross-sectional view showing a part of a semiconductor device according to a reference example. [Figure 10] FIG. 10 is a cross-sectional view showing a part of a semiconductor device according to a reference example. [Figure 11] FIG. 11 is a plan view showing a part of a semiconductor device according to a first modification of the embodiment. [Figure 12] FIG. 12 is a schematic diagram showing the operation of the semiconductor device according to the first modification of the embodiment. [Figure 13] FIG. 13 is a plan view showing a part of a semiconductor device according to a second modification of the embodiment. [Figure 14] FIG. 14 is a plan view showing a part of a semiconductor device according to a second modification of the embodiment. [Figure 15] FIG. 15 is an enlarged plan view of a part of FIG. [Figure 16] FIG. 16 is a schematic diagram showing the operation of the semiconductor device according to the second modification of the embodiment. [Figure 17] FIG. 17 is a plan view showing a part of a semiconductor device according to a third modification of the embodiment. [Figure 18] FIG. 18 is a plan view showing a part of a semiconductor device according to a fourth modification of the embodiment. [Figure 19] FIG. 19 is a plan view showing a part of a semiconductor device according to a fourth modification of the embodiment. [Figure 20] FIG. 20 is a cross-sectional view taken along the line A1-A2 in FIGS. [Figure 21] FIG. 21 is a plan view showing a part of another semiconductor device according to a fourth modification of the embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, embodiments of the present invention will be described with reference to the drawings. The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between parts, etc. are not necessarily the same as those in reality. Furthermore, even when the same part is shown, the dimensions and ratios may be different depending on the drawing. In addition, in the present specification and each drawing, elements similar to those already explained are given the same reference numerals, and detailed explanations will be omitted as appropriate. In the following description and drawings, n + , n, n - and p + The notation "p" indicates the relative level of each impurity concentration. That is, a notation with "+" indicates a relatively higher impurity concentration than a notation with neither "+" nor "-" attached, and a notation with "-" indicates a relatively lower impurity concentration than a notation with neither attached. When both p-type and n-type impurities are contained in each region, these notations indicate the relative level of the net impurity concentration after the impurities compensate for each other. In each of the embodiments described below, the p-type and n-type of each semiconductor region may be reversed to implement each embodiment.

[0008] Fig. 1 is a plan view showing a semiconductor device according to an embodiment. Figs. 2 and 3 are enlarged plan views of a portion A in Fig. 1. Fig. 4 is a cross-sectional view taken along B1-B2 in Figs. 2 and 3. Fig. 2 corresponds to the cross-sectional view taken along C1-C2 in Fig. 4. Fig. 3 corresponds to the cross-sectional view taken along D1-D2 in Fig. 4. The semiconductor device according to the embodiment is a MOSFET. As shown in FIGS. 1 to 4, the semiconductor device 100 according to the embodiment has n - p-type (first conductivity type) drift region 1 (first semiconductor region), p-type (second conductivity type) base region 2 (second semiconductor region), n + source region 3 (third semiconductor region), p + Shape contact area 4, n +The semiconductor device includes a drain region 5, an insulating portion 10, a conductive portion 20, a gate electrode 30, a gate insulating layer 35, an insulating layer 36, a drain electrode 40 (first electrode), a source electrode 50 (second electrode), a gate pad 60, and a gate wiring 61. Note that the insulating layer 36 and the source electrode 50 are omitted in Figures 2 and 3. The gate electrode 30 is also omitted in Figure 3.

[0009] In the description of the embodiment, the drain electrodes 40 to n - The direction toward the drift region 1 is referred to as "direction D1" (first direction). The direction perpendicular to direction D1 is referred to as "direction D2" (second direction). The direction perpendicular to direction D1 and intersecting with direction D2 is referred to as "direction D3" (third direction). - The direction toward the drift region 1 is called "up" and the opposite direction is called "down." These directions are the direction between the drain electrode 40 and the n - This is a direction based on the relative positional relationship with the shape drift region 1 and is unrelated to the direction of gravity.

[0010] 1, a source electrode 50, a gate pad 60, and a gate wiring 61 are provided on the upper surface of the semiconductor device 100. The gate pad 60 and the gate wiring 61 are spaced apart from the source electrode 50 and are electrically isolated from the source electrode 50. The gate wiring 61 is provided around the source electrode 50 in a plane (first plane) perpendicular to the direction D1. The gate wiring 61 is electrically connected to the gate pad 60.

[0011] As shown in FIG. 4, the drain electrode 40 is provided on the bottom surface of the semiconductor device 100. + The drain region 5 is provided on the drain electrode 40 and is electrically connected to the drain electrode 40. - The drift region 1 is n + The n-type drain region 5 is provided on the n-type drain region 5. - The n-type impurity concentration of the n-type drift region 1 is + The n-type impurity concentration of the n-type drain region 5 is lower than that of the n-type impurity concentration of the n-type drain region 5. - The drift region 1 is n +The semiconductor layer 1 is electrically connected to the drain electrode 40 via the drain region 5 .

[0012] The conductive portion 20 is - The p-type base region 2 is provided in the n-type drift region 1 via an insulating portion 10. As shown in FIGS. 2 to 4, a plurality of conductive portions 20 are provided in the directions D2 and D3. The insulating portions 10 are spaced apart from each other in the directions D2 and D3. - The n-type semiconductor layer is provided on a part of the drift region 1 and is located between the conductive portions 20. + Shape source region 3 and p + Each of the p-type contact regions 4 is provided on a part of the p-type base region 2. + The p-type impurity concentration of the p-type contact region 4 is higher than the p-type impurity concentration of the p-type base region 2.

[0013] The gate electrode 30 is provided on the p-type base region 2 via a gate insulating layer 35. The gate electrode 30 is electrically connected to a gate wiring 61.

[0014] n - 3 and 4, the n-type drift region 1 includes a first region 1R aligned with the p-type base region 2 in the direction D2, and a second region 2R located below the p-type base region 2. In the illustrated example, the gate electrode 30 is formed over a portion of the first region 1R, a portion of the p-type base region 2, and the n-type drift region 1R. + The first region 1R is located on a part of the n-type source region 3. For example, the n-type impurity concentration of the first region 1R is higher than the n-type impurity concentration of the second region 2R.

[0015] 2, the gate electrode 30 includes a first electrode portion 31. The multiple conductive portions 20 include a pair of conductive portions 20 adjacent to each other in direction D2. The position of the first electrode portion 31 in direction D2 is between the position of one of the pair of conductive portions 20 in direction D2 and the position of the other of the pair of conductive portions 20 in direction D2. The first electrode portion 31 extends in an extension direction that intersects with direction D2 connecting the pair of conductive portions 20. In other words, the length of the first electrode portion 31 in the extension direction is longer than the length of the first electrode portion 31 in direction D2.

[0016] As shown in FIG. 4, the source electrode 50 is + Shape source region 3, p + The n-type contact region 4 and the gate electrode 30 are provided on the n-type contact region 4 and the gate electrode 30. + Shape source region 3, p + The p-type base region 2 is electrically connected to the p-type contact region 4 and the conductive portion 20. + The gate electrode 30 is electrically connected to the source electrode 50 via the contact region 4. The gate electrode 30 is electrically isolated from the source electrode 50 by an insulating layer .

[0017] In the illustrated example, the source electrode 50 includes a first extension portion 51 and a second extension portion 52. The first extension portion 51 penetrates the insulating layer 36 and extends along the direction D1. The lower end of the first extension portion 51 is + Shape source region 3 and p + The first extension portion 51 and the second extension portion 52 are in contact with the gate electrode 30 in the direction D2. The second extension portion 52 penetrates the insulating layer 36 and extends along the direction D1. The lower end of the second extension portion 52 is in contact with the conductive portion 20. A portion of the first extension portion 51 and a portion of the second extension portion 52 are located between the gate electrodes 30 in the direction D2.

[0018] 5(a) and 5(b) are plan and cross-sectional views showing a portion of the semiconductor device according to the embodiment. 5(a) and 5(b), the operation of the semiconductor device 100 will be described. In addition, in Fig. 5(a), the gate electrode 30 is indicated by a dashed line.

[0019] With a positive voltage applied to the drain electrode 40 relative to the source electrode 50, a voltage equal to or greater than the threshold is applied to the gate electrode 30. This forms a channel (inversion layer) in the p-type base region 2, turning the semiconductor device 100 into an ON state. Electrons flow from the source electrode 50 to the drain electrode 40 through the channel in the p-type base region 2, as indicated by arrow a1 in FIGS. 5(a) and 5(b). When the voltage applied to the gate electrode 30 becomes lower than the threshold, the channel in the p-type base region 2 disappears, turning the semiconductor device 100 into an OFF state.

[0020] When the semiconductor device 100 is switched to the off state, the positive voltage applied to the drain electrode 40 relative to the source electrode 50 increases. The potential of the conductive portion 20 is substantially the same as the potential of the source electrode 50. - The potential difference between the drift region 1 and the conductive portion 20 causes n - The n-type semiconductor layer is formed on the interface between the drift region 1 and the insulating portion 10. - The depletion layer spreads toward the n-type drift region 1. This spread of the depletion layer can increase the breakdown voltage of the semiconductor device 100. Alternatively, the breakdown voltage of the semiconductor device 100 can be increased while maintaining the breakdown voltage. - The n-type impurity concentration in the n-type drift region 1 can be increased, and the on-resistance of the semiconductor device 100 can be reduced.

[0021] An example of the material of each component of the semiconductor device 100 will be described. n - p-type drift region 1, p-type base region 2, n + Shape source region 3, p + contact region 4, and n + The n-type drain region 5 includes a semiconductor material. The semiconductor material may be silicon, silicon carbide, gallium nitride, or gallium arsenide. The n-type impurity may be arsenic, phosphorus, or antimony. The p-type impurity may be boron.

[0022] The insulating portion 10, the gate insulating layer 35, and the insulating layer 36 include insulating materials. For example, the insulating portion 10, the gate insulating layer 35, and the insulating layer 36 include silicon oxide, silicon nitride, or silicon oxynitride. The conductive portion 20 and the gate electrode 30 include polysilicon. The conductive portion 20 and the gate electrode 30 may be doped with n-type or p-type impurities. The drain electrode 40, the source electrode 50, the gate pad 60, and the gate wiring 61 include metals such as titanium, tungsten, or aluminum.

[0023] 6(a) to 8(b) are cross-sectional views showing a method for manufacturing a semiconductor device according to the embodiment. First, n + A semiconductor substrate including a semiconductor layer 5a is prepared. + On the semiconductor layer 5a, a semiconductor material is epitaxially grown to form an n - As shown in FIG. 6(a), a n-type semiconductor layer 1a is formed by reactive ion etching (RIE). - An opening OP1 is formed in the semiconductor layer 1a. A plurality of openings OP1 are formed in the directions D2 and D3.

[0024] The inner surface of the opening OP1 and - An insulating layer 10a is formed along the upper surface of the semiconductor layer 1a by thermal oxidation or chemical vapor deposition (CVD). A conductive layer is formed on the insulating layer 10a by CVD. The upper surface of the conductive layer is recessed by chemical dry etching (CDE) or wet etching. As a result, a conductive layer 20a is formed inside the opening OP1. As shown in FIG. 6(b), the upper surface of the insulating layer 10a is recessed by CDE or wet etching, and the conductive layer 20a is formed inside the opening OP1. - The upper surface of the semiconductor layer 1a is exposed.

[0025] Thermal oxidation removes exposed n - An insulating layer 35a is formed on the upper surface of the semiconductor layer 1a. A conductive layer is formed on the insulating layer 35a by CVD. This conductive layer is patterned by RIE to form a conductive layer 30a as shown in FIG. 7(a).

[0026] n- P-type impurities and n-type impurities are ion-implanted in the upper surface of the n-type semiconductor layer 1a to form an n-type semiconductor region 1b, a p-type semiconductor region 2a, and an n-type semiconductor region 3b. + The insulating layer 36a is formed by CVD to cover the conductive layer 30a, as shown in FIG.

[0027] By RIE, a part of the insulating layer 36a, a part of the insulating layer 35a, and n + A part of the p-type semiconductor region 3a and a part of the p-type semiconductor region 2a are removed to form an opening OP2. + The p-type semiconductor region 3a is exposed. P-type impurities are ion-implanted into the p-type semiconductor region 2a through the opening OP2. + 8(a), another part of the insulating layer 36a is removed by RIE to form an opening OP3, through which the conductive layer 20a is exposed.

[0028] A barrier metal 50a filling the openings OP2 and OP3 is formed by CVD. The barrier metal 50a has a laminated structure of, for example, a titanium nitride layer, a titanium layer, and a tungsten layer. An aluminum layer 50b is formed on the barrier metal 50a by sputtering. The barrier metal 50a and the aluminum layer 50b are patterned. + The n-type semiconductor layer 5a is then grown to a predetermined thickness. + The lower surface of the semiconductor layer 5a is ground. As shown in FIG. 8(b), the n + An aluminum layer 40a is formed on the lower surface of the shaped semiconductor layer 5a. In this way, the semiconductor device 100 is manufactured.

[0029] n shown in Figure 8(b) - The semiconductor layer 1a is a n-type semiconductor layer shown in FIGS. - The n-type semiconductor region 1b corresponds to the second region 2R of the n-type drift region 1. - The p-type semiconductor region 2a corresponds to the first region 1R of the p-type drift region 1. The p-type semiconductor region 2a corresponds to the p-type base region 2. + The semiconductor region 3a is n +Corresponding to the source region 3. + The semiconductor region 4a is p + corresponding to the contact area 4. + The semiconductor layer 5a is an n-type + The insulating layer 10a corresponds to the insulating portion 10. The conductive layer 20a corresponds to the conductive portion 20. The conductive layer 30a corresponds to the gate electrode 30. The insulating layer 35a corresponds to the gate insulating layer 35. The insulating layer 36a corresponds to the insulating layer 36. The aluminum layer 40a corresponds to the drain electrode 40. The patterned barrier metal 50a and aluminum layer 50b correspond to the source electrode 50, the gate pad 60, and the gate wiring 61.

[0030] 9 and 10 are cross-sectional views showing a part of a semiconductor device according to a reference example. In a semiconductor device 100r1 shown in FIG. 9, a gate electrode 30r1 is provided in the semiconductor region via a gate insulating layer 35r. The gate insulating layer 35r is spaced apart from the insulating portion 10. In a semiconductor device 100r2 shown in FIG. 10, a gate electrode 30r2 is provided in the insulating portion 10r. The gate electrode 30r2 is electrically connected to a gate wiring layer 38 via a contact portion 37. The gate wiring layer 38 is provided along the first surface and is located between the semiconductor region and the source electrode 50.

[0031] In both the semiconductor devices 100r1 and 100r2, a plurality of conductive portions 20 are provided in the directions D2 and D3. This structure reduces the number of conductive portions 20 by n compared to when the conductive portions 20 extend in one direction. - This increases the volume of the drift region 1. This increases the number of current paths in the on-state, thereby reducing the on-resistance of the semiconductor devices 100r1 and 100r2.

[0032] On the other hand, in the semiconductor device 100r1, n -The area where the drift region 1 and the gate electrode 30r1 face each other is large, and the capacitance Cgd between the drain electrode 40 and the gate electrode 30r1 is increased. In the semiconductor device 100r2, the gate electrode 30r2 is provided in the insulating portion 10r. - This reduces the area where the drift region 1 faces the gate electrode 30r2. However, the semiconductor device 100r2 requires a gate wiring layer 38 for electrically connecting the gate electrode 30r2 to the gate wiring 61, a contact portion 37 for connecting the gate electrode 30r2 and the gate wiring layer 38, and other components. This requires a margin to accommodate positional variations in the contact portion 37, and increases the number of manufacturing processes. Furthermore, since the gate wiring layer 38 faces the source electrode 50 in the direction D1, the capacitance Cgs between the gate electrode 30r1 and the source electrode 50 also increases.

[0033] To address these issues, in the semiconductor device 100 according to the embodiment, a plurality of conductive portions 20 are provided, and a gate electrode 30 is provided on the p-type base region 2 via a gate insulating layer 35. By providing a plurality of conductive portions 20 in the directions D2 and D3, the on-resistance of the semiconductor device 100 can be reduced, similar to the semiconductor devices 100r1 and 100r2. Furthermore, by providing the gate electrode 30 on the p-type base region 2, the on-resistance of the semiconductor device 100 can be reduced by a factor of n compared to the semiconductor device 100r1. - The area where the drift region 1 and the gate electrode 30 face each other is reduced, thereby reducing the capacitance Cgd. A wiring layer or the like for connecting the gate electrode 30 and the gate wiring 61 is not required, and the number of manufacturing steps can be reduced compared to the semiconductor device 100r2. Furthermore, since the contact portion 37 is not required, the conductive portion 20, the gate electrode 30, and the like can be provided at a higher density by the margin of the contact portion 37. Furthermore, omitting the gate wiring layer 38 reduces the capacitance Cgs compared to the semiconductor device 100r2.

[0034] According to the embodiment, it is possible to reduce the on-resistance of the semiconductor device 100 while suppressing the occurrence of the above-mentioned problems.

[0035] (First Modification) 11 is a plan view showing a part of a semiconductor device according to a first modification of the embodiment, in which the insulating layer 36 and the source electrode 50 are omitted. In the semiconductor device 110 according to the first modification, as shown in FIG. 11, a plurality of p-type base regions 2 and a plurality of n-type base regions 3 are arranged around one conductive portion 20 along the first surface. + A p-type source region 3 is provided. A p-type base region 2 and a first region 1R are provided alternately around one conductive portion 20 along the first surface.

[0036] More specifically, the p-type base region 2, n-type base region 3, and n-type base region 4 are formed between the conductive portions 20 adjacent to each other in the direction D2. + The p-type source region 3 and the first region 1R are located between the other conductive portions 20 adjacent to each other in the direction D3. + A p-type source region 3 and another first region 1R are located between the further conductive portions 20 adjacent to each other in the direction D4. + A p-type source region 3 and a further first region 1R are located in the p-type base region 2. A direction D4 is perpendicular to the direction D1 and intersects with the directions D2 and D3. A first electrode portion 31 is provided on each p-type base region 2 with a gate insulating layer 35 interposed therebetween.

[0037] The structures in the A1-A2 cross section, the B1-B2 cross section, and the C1-C2 cross section in FIG. 11 are the same as the cross-sectional structures shown in FIG.

[0038] FIG. 12 is a schematic diagram showing the operation of the semiconductor device according to the first modification of the embodiment. 12 shows the semiconductor device 110 in an on-state. In the semiconductor device 110, a p-type base region 2 is provided between adjacent conductive portions 20 in each of the directions D2 to D4. Therefore, in the on-state, electrons flow from the p-type base region 2 to the first region 1R along each of the directions D2 to D4, as indicated by arrow a2. According to the first modification, the area of ​​the channel formed per unit area (channel density) is larger than in the semiconductor device 100, and the on-resistance of the semiconductor device 110 can be reduced.

[0039] (Second Modification) 13 and 14 are plan views showing a part of a semiconductor device according to a second modification of the embodiment. The insulating layer 36 and the source electrode 50 are omitted in Fig. 13 and 14. The gate electrode 30 is indicated by a dashed line in Fig. 14. 13, the semiconductor device 120 according to the second modification is different from the semiconductor device 110 in that the gate electrode 30 further includes a second electrode portion 32. The second electrode portion 32 is connected to one end of the first electrode portion 31 in the extension direction. When viewed from the direction D1, the second electrode portion 32 extends from one end of the first electrode portion 31 toward the conductive portion 20. The first electrode portion 31 is connected to a part of the p-type base region 2, the n-type base region 3, and the p-type base region 4 via the gate insulating layer 35. + The second electrode portion 32 is located on a part of the p-type source region 3 and a part of the first region 1R. The second electrode portion 32 is connected to another part of the p-type base region 2, the n-type source region 3, and the n-type source region 1R via the gate insulating layer 35. + The second region 1R is located on another part of the source region 3 and another part of the first region 1R.

[0040] FIG. 15 is an enlarged plan view of a part of FIG. 14, the plurality of conductive portions 20 include conductive portions 20-1 to 20-3. The plurality of first electrode portions 31 include first electrode portions 31-1 to 31-3. The plurality of second electrode portions 32 include second electrode portions 32-1 to 32-9. The plurality of first regions 1R include first regions 1Ra to 1Rc.

[0041] The conductive portion 20-1 and the conductive portion 20-2 are adjacent to each other in the direction D2. The position of the first electrode portion 31-1 in the direction D2 is between the position of the conductive portion 20-1 in the direction D2 and the position of the conductive portion 20-2 in the direction D2. The first electrode portion 31-1 extends in an extension direction that intersects with the direction connecting the conductive portions 20-1 and 20-2. The second electrode portions 32-1 to 32-4 are each connected to both ends of the first electrode portion 31-1 in the extension direction. The positions of the second electrode portions 32-1 and 32-2 in the direction D2 are between the position of the first electrode portion 31-1 in the direction D2 and the position of the conductive portion 20-1 in the direction D2. The positions of the second electrode portions 32-3 and 32-4 in the direction D2 are between the positions of the first electrode portion 31-1 in the direction D2 and the conductive portion 20-2 in the direction D2. The position of the first region 1Ra in the direction D2 is between the positions of the first electrode portion 31-1 in the direction D2 and the conductive portion 20-2 in the direction D2.

[0042] Similarly, the conductive portion 20-2 and the conductive portion 20-3 are adjacent to each other in the direction D3. The position of the first electrode portion 31-2 in the direction D3 is between the position of the conductive portion 20-2 in the direction D3 and the position of the conductive portion 20-3 in the direction D3. The first electrode portion 31-2 extends in an extension direction that intersects with the direction connecting the conductive portions 20-2 and 20-3. The second electrode portions 32-4 to 32-7 are each connected to both ends of the first electrode portion 31-2 in the extension direction. The position of the first region 1Rb in the direction D3 is between the position of the first electrode portion 31-2 in the direction D3 and the position of the conductive portion 20-3 in the direction D2. The conductive portion 20-1 and the conductive portion 20-3 are adjacent to each other in the direction D4. The position of the first electrode portion 31-3 in direction D4 is between the position of the conductive portion 20-1 in direction D4 and the position of the conductive portion 20-3 in direction D4. The first electrode portion 31-3 extends in an extension direction that intersects with the direction connecting the conductive portion 20-1 and the conductive portion 20-3. The second electrode portions 32-2, 32-6, 32-8, and 32-9 are connected to both ends of the first electrode portion 31-3 in the extension direction. The position of the first region 1Rc in direction D4 is between the position of the first electrode portion 31-3 in direction D4 and the position of the conductive portion 20-1 in direction D4.

[0043] FIG. 16 is a schematic diagram showing the operation of the semiconductor device according to the second modification of the embodiment. 16 shows the semiconductor device 120 in the on state. When the semiconductor device 120 is in the on state, a channel is formed in the p-type base region 2 by the first electrode portion 31 and the second electrode portion 32. In the on state, as shown by arrow a3, electrons flow from the p-type base region 2 to the first region 1R through the channel formed by the second electrode portion 32. According to the second modification, the channel density is even greater than that of the semiconductor device 110, and the on-resistance of the semiconductor device 120 can be further reduced.

[0044] According to the first modification, the second electrode portion 32 is not provided, so that the p +When avalanche breakdown occurs in a semiconductor device, a large number of carriers are generated. + The electrons are discharged through the contact region 4 to the source electrode 50. + If the area of ​​the p-type contact region 4 is large, the electrical resistance to holes can be reduced. For example, the potential fluctuation of the p-type base region 2 can be suppressed, and the n - a p-type drift region 1, a p-type base region 2, and an n + This can suppress the operation of a parasitic transistor formed by the source region 3. Therefore, according to the first modification, the avalanche resistance of the semiconductor device 110 can be improved compared to the semiconductor device 120.

[0045] (Third Modification) 17 is a plan view showing a part of a semiconductor device according to a third modification of the embodiment, in which the insulating layer 36 and the source electrode 50 are omitted and the gate electrode 30 is indicated by a dashed line. In the examples shown in FIGS. 11 to 16, a plurality of first electrode portions 31 are arranged in a regular hexagonal shape. Furthermore, one first electrode portion 31 and a pair of second electrode portions 32 are aligned in the direction in which the first electrode portion 31 extends. The positional relationships between the first electrode portions 31 and between the first electrode portions 31 and the second electrode portions 32 are not limited to those shown in these figures. For example, as in a semiconductor device 130 according to a third modification shown in FIG. 17, the ends of the first electrode portions 31 extending in the directions D2 to D4 may be offset from each other. One first electrode portion 31 and a pair of second electrode portions 32 may be aligned with a slight offset in the direction in which the first electrode portion 31 extends. As shown in FIG. 17, the specific shape of the gate electrode 30 can be modified as appropriate as long as current can flow in two or more of the directions D2 to D4.

[0046] (Fourth Modification) 18 and 19 are plan views showing a portion of a semiconductor device according to a fourth modified example of the embodiment. FIG. 20 is a cross-sectional view taken along A1-A2 in FIGS. 18 and 19. FIG. 18 corresponds to the cross-sectional view taken along B1-B2 in FIG. 20. FIG. 19 corresponds to the cross-sectional view taken along C1-C2 in FIG. 20. In FIGS. 18 and 19, the insulating layer 36 and the source electrode 50 are omitted. In FIG. 19, the gate electrode 30 is further omitted. 18 and 19, in the semiconductor device 140 according to the fourth modification, the directions D2 and D3, which are the arrangement directions of the conductive portions 20, are perpendicular to each other. Furthermore, in the semiconductor device 140, the p-type base region 2, the n + The shapes in the XY plane of the source region 3, the insulating portion 10, the gate electrode 30, etc. are different. The plurality of first electrode portions 31 of the gate electrode 30 are provided in a lattice pattern.

[0047] Except for the arrangement direction and shape, the positional relationship of the components in the semiconductor device 140 is substantially the same as that of the semiconductor devices 100 to 130. For example, as shown in FIGS. 18 to 20, p-type base regions 2, n-type + A p-type source region 3 and a first region 1R are provided, and a first electrode portion 31 is located thereon. The first electrode portion 31 extends along direction D2 or D3, and the second electrode portion 32 extends from one end of the first electrode portion 31 toward the conductive portion 20. In the XY plane, p-type base regions 2 and first regions 1R are provided alternately around one conductive portion 20.

[0048] 21 is a plan view showing a part of another semiconductor device according to the fourth modification of the embodiment, in which the insulating layer 36 and the source electrode 50 are omitted. In a semiconductor device having a rectangular insulating portion 10, a plurality of lattice-shaped first electrode portions 31, etc., the direction D3 does not have to be perpendicular to the direction D2, as shown in Fig. 21. In the semiconductor device 150 shown in Fig. 21, the positions of the conductive portions 20 in the direction D2 are different for the conductive portions 20 adjacent to each other in the direction D3. The positions of the first electrode portions 31 in the direction D2 are different for the first electrode portions 31 adjacent to each other in the direction D3.

[0049] 18 to 21, the specific shape and arrangement direction of each component of the semiconductor device can be changed as appropriate. In any of the configurations, by arranging a plurality of conductive portions 20 in two directions that intersect with each other and providing a gate electrode 30 on the p-type base region 2, it is possible to reduce the on-resistance of the semiconductor device while suppressing an increase in capacitance Cgd or an increase in the number of manufacturing steps.

[0050] Although several embodiments of the present invention have been described above, these embodiments are presented by way of example only and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, modifications, etc. can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, as well as within the scope of the invention and its equivalents as set forth in the claims. Furthermore, the above-described embodiments can be implemented in combination with each other. [Explanation of symbols]

[0051] 1:n - Shape drift region, 1a:n - n-type semiconductor layer, 1b: n-type semiconductor region, 1R, 1Ra to 1Rc: first region, 2: p-type base region, 2a: p-type semiconductor region, 2R: second region, 3: n + Shape source area, 3a:n + Shape semiconductor area, 4:p + Shape contact area, 4a:p + Shape semiconductor area, 5:n + Shaped drain region, 5a:n +semiconductor layer, 10: insulating portion, 10a: insulating layer, 10r: insulating portion, 20, 20-1 to 20-9: conductive portion, 20a: conductive layer, 30: gate electrode, 30a: conductive layer, 30r: gate electrode, 30r1: gate electrode, 30r2: gate electrode, 31, 31-1 to 31-3: first electrode portion, 32, 32-1 to 32-9: second electrode portion, 35: gate insulating layer, 35a: insulating layer, 35r: gate insulating layer, 36: insulating layer, 36a: insulating layer, 37: contact portion, 38: gate wiring layer, 40: drain electrode, 40a: aluminum layer, 50: source electrode, 50a: barrier metal, 50b: aluminum layer, 51: first extension portion, 52: second extension portion, 60: Gate pad, 61: Gate wiring, 100, 100r1, 100r2, 110-150: Semiconductor device, OP1-OP3: Openings

Claims

1. A first electrode; a first semiconductor region of a first conductivity type provided on the first electrode and electrically connected to the first electrode; a plurality of conductive portions provided in the first semiconductor region with insulating portions interposed therebetween, the conductive portions being provided in a second direction perpendicular to a first direction from the first electrode toward the first semiconductor region, and in a third direction perpendicular to the first direction and intersecting the second direction; a second semiconductor region of a second conductivity type provided on a portion of the first semiconductor region; a third semiconductor region of the first conductivity type provided on a portion of the second semiconductor region; a gate electrode provided on the second semiconductor region via a gate insulating layer; a second electrode provided on the second semiconductor region, the third semiconductor region, and the gate electrode, and electrically connected to the second semiconductor region, the third semiconductor region, and the plurality of conductive portions; Equipped with a plurality of the second semiconductor regions and a plurality of the third semiconductor regions are provided around one of the plurality of conductive portions on a first plane perpendicular to the first direction; Semiconductor device.

2. the first semiconductor region includes a first region aligned with the second semiconductor region in the first surface; The semiconductor device according to claim 1 , wherein the first region and the second semiconductor region are alternately provided around the one of the plurality of conductive portions.

3. the plurality of conductive portions include a pair of the conductive portions adjacent to each other in the second direction, the gate electrode includes a first electrode portion; 3. The semiconductor device according to claim 1, wherein the position of the first electrode portion in the second direction is between the position of one of the pair of conductive portions in the second direction and the position of the other of the pair of conductive portions in the second direction.

4. the first electrode portion extends in an extension direction intersecting a direction connecting the pair of conductive portions, the gate electrode further includes a second electrode portion connected to one end of the first electrode portion in the extending direction, 4. The semiconductor device according to claim 3, wherein the position of the second electrode portion in the second direction is between the position of the one of the pair of conductive portions and the position of the first electrode portion.

5. A first electrode; a first semiconductor region of a first conductivity type provided on the first electrode and electrically connected to the first electrode; a plurality of conductive portions provided in the first semiconductor region with insulating portions interposed therebetween, the conductive portions being provided in a second direction perpendicular to a first direction from the first electrode toward the first semiconductor region, and in a third direction perpendicular to the first direction and intersecting the second direction; a second semiconductor region of a second conductivity type provided on a portion of the first semiconductor region; a third semiconductor region of the first conductivity type provided on a portion of the second semiconductor region; a gate electrode provided on the second semiconductor region via a gate insulating layer; a second electrode provided on the second semiconductor region, the third semiconductor region, and the gate electrode, and electrically connected to the second semiconductor region, the third semiconductor region, and the plurality of conductive portions; Equipped with the plurality of conductive portions include a pair of conductive portions adjacent to each other in the second direction, the gate electrode includes a first electrode portion extending in an extension direction intersecting a direction connecting the pair of conductive portions, and a second electrode portion connected to one end of the first electrode portion in the extension direction, a position of the first electrode portion in the second direction is between a position of one of the pair of conductive portions in the second direction and a position of the other of the pair of conductive portions in the second direction, a position of the second electrode portion in the second direction is between the position of one of the pair of conductive portions and the position of the first electrode portion; Semiconductor device.

6. The semiconductor device according to claim 4 , wherein the first electrode portion and the second electrode portion are located above the second semiconductor region via the gate insulating layer.

7. the second electrode includes a first extension portion extending in the first direction, the first extension portion being a region surrounded by the first electrode portion and the plurality of second electrode portions on a first surface perpendicular to the first direction; 7. The semiconductor device according to claim 4, wherein said first extending portion is in contact with said third semiconductor region.

8. The first semiconductor region is a first region aligned with the second semiconductor region in a first plane perpendicular to the first direction; a second region located below the second semiconductor region; Including, 8. The semiconductor device according to claim 1, wherein the first region has a higher impurity concentration of the first conductivity type than the second region.

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