Semiconductor circuit device and logic circuit design support device

Abstract

To provide a semiconductor circuit device and a logic circuit design support device that can link control of the power source of a nonvolatile flip-flop with an acquisition circuit controlled by different enable signals.SOLUTION: A nonvolatile flip-flop NF11 is clock-gated by an enable signal EN11. A flip-flop FF12 is clock-gated by an enable signal EN12. In the nonvolatile flip-flop NF11, a power gating circuit 17 is formed. In the power gating circuit 17, an enable signal EN11 as a power source control signal, an enable signal EN12, and a gated clock signal GCK11 with a CLK signal controlled by the enable signal EN11 are input. Power supply to the nonvolatile flip-flop NF11 is controlled.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor circuit device and a logic circuit design support device. [Background technology]

[0002] Power gating, which cuts off the power supply to unused circuits, is known as a technology for suppressing leakage current and reducing power consumption, while clock gating, which stops the clock supply to unused circuits, is known as a technology for suppressing dynamic power consumption.

[0003] The semiconductor logic circuit device described in Patent Document 1 has multiple circuit modules, each of which is provided with a clock gating circuit and a power gating circuit. Each circuit module includes two nonvolatile flip-flops (hereinafter referred to as nonvolatile flip-flops) connected to the input and output sides of a combinational circuit. The combinational circuit performs a logical operation on data output from the input nonvolatile flip-flop, and the output nonvolatile flip-flop acquires the result. The clock gating circuit and power gating circuit of each circuit module receive a clock control enable signal (clock control signal) for the corresponding circuit module. When the enable signal is active, power is supplied to the circuit module and a clock pulse is input. An arithmetic processing circuit provided in the semiconductor logic circuit device analyzes an operating program to determine whether to enable or disable the clock signal for each circuit module. The enable signal for the circuit module that should be enabled is activated, and the enable signals for the other circuit modules are deactivated.

[0004] On the other hand, nonvolatile latches and flip-flops are known that store input data nonvolatilely when a clock pulse of a predetermined pulse width or greater is input, and automatically restore the data when power supply is resumed (see Non-Patent Document 1 and Patent Document 2). [Prior art documents] [Non-patent literature]

[0005] [Non-Patent Document 1] T. Endoh, S. Togashi, F. Iga, Y. Yoshida, T. Ohsawa, H. Koike, S. Fukami, S. Ikeda, N. Kasai, N. Sakimura, T. Hanyu, and H. Ohno, "A 600MHz MTJ-based nonvolatile latch making use of incubation time in MTJ switching", 2011 International Electron Devices Meeting, 2011, pp. 4.3.1-4.3.4, doi: 10.1109 / IEDM.2011.6131487. [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Laid-Open No. 2015-099451 [Patent Document 2] International Publication No. 2013 / 099536 Summary of the Invention [Problem to be solved by the invention]

[0007] For nonvolatile flip-flops controlled by different enable signals and acquisition circuits that directly or indirectly acquire data from these nonvolatile flip-flops, if the arithmetic processing circuit of Patent Document 1 were to distinguish between each circuit module and control the enable signals of the nonvolatile flip-flop circuits by analyzing the operating program, the analysis would become complicated. Also, if a generation circuit that generates an enable signal were configured, the circuit configuration of the generation circuit would become complicated.

[0008] The present invention has been made in consideration of the above circumstances, and aims to provide a semiconductor circuit device and a logic circuit design support device that can link the power supply control of a non-volatile flip-flop with an acquisition circuit that is controlled by a different enable signal. [Means for solving the problem]

[0009] In order to achieve the above object, the semiconductor circuit device of the present invention comprises: a first clock gating circuit that outputs a first gated clock signal that controls the clock signal in accordance with a first enable signal that controls the enable and disable of the clock signal; a non-volatile first flip-flop that operates in response to clock pulses of the first gated clock signal; an acquisition circuit that receives data from the first flip-flop directly or via a combinational circuit and acquires the input data in accordance with a second enable signal that controls the enable and disable of data acquisition; and a power gating circuit that has a power switch provided on a power line to the first flip-flop, receives the first enable signal and the second enable signal as power control signals, and turns on the power switch to supply power to the first flip-flop when the first enable signal is a logical value that enables the clock signal or the second enable signal is a logical value that enables data acquisition.

[0010] The semiconductor circuit device of the present invention includes a first clock gating circuit that outputs a first gated clock signal obtained by controlling the clock signal in response to a first enable signal that controls whether the clock signal is enabled or disabled; a convolution operation unit that outputs convolution operation result data each time convolution operation result data that becomes element data of a channel of a next hierarchy obtained by performing a convolution operation on each convolution area of ​​a plurality of channels of a previous hierarchy so that element data in a pooling area of ​​the channel of a next hierarchy is continuously output sequentially; a register that holds data using a plurality of nonvolatile first flip-flops that operates as a flip-flop in response to clock pulses of the first gated clock signal when power is supplied, stores input data in a nonvolatile manner in response to input of a clock pulse having a predetermined pulse width or more, and outputs the nonvolatilely stored data when power supply is resumed; a comparator that compares the convolution operation result data from the convolution operation unit with the held data held in the register; a pooling selector that receives input of the convolution operation result data and the held data, and selects data with a larger value from the input data based on a comparison result of the comparator, and stores the data as new held data in the register; a pooling processing unit that, for each pooling area, outputs the held data held in the register after input of each of the convolution operation result data of the pooling area as pooled data to an acquisition circuit that acquires the input data in accordance with a second enable signal that controls enable / disable of data acquisition; an interruption avoidance circuit that selects one of an interruption avoidance mode in which power is not interrupted and an interruption tolerant mode in which power is interrupted, and outputs an interruption avoidance signal with a logical value corresponding to the selected mode; a clock generation unit that generates a first clock signal having a clock pulse with a predetermined pulse width or more and a second clock signal having a frequency higher than that of the first clock signal and a pulse width smaller than the predetermined pulse width;a clock circuit having a clock selector that selects the second clock signal when the logic value corresponds to the shutdown avoidance mode and outputs it as the clock signal; a mode control unit that causes the shutdown avoidance circuit to select the shutdown allowable mode when an output interval of the convolution operation result data from the convolution operation unit is equal to or greater than a predetermined threshold, and causes the shutdown avoidance circuit to select the shutdown avoidance mode when the output interval is shorter than the predetermined threshold; and a power gating circuit that has a power switch provided on a power line to the plurality of first flip-flops, to which the first enable signal, the second enable signal, and the shutdown avoidance signal are input as power control signals, and that keeps the power switch on during a period when the shutdown avoidance signal is at a logic value corresponding to the shutdown avoidance mode, and controls the power switch on and off in accordance with the other power control signals when the logic value corresponds to the shutdown allowable mode, and turns on the power switch to supply power to the first flip-flops when the first enable signal is at a logic value that enables the clock signal or the second enable signal is at a logic value that enables acquisition of data.

[0011] The logic circuit design assistance device of the present invention includes a replacement target designation unit that designates a replacement target flip-flop to be replaced with a non-volatile flip-flop among the flip-flops in a circuit described in a netlist, and a logic circuit replacement unit that modifies the netlist to replace the replacement target flip-flop with the non-volatile flip-flop to which a power gating circuit is added, and adds connections so that a first enable signal that controls the enable and disable of a clock signal input to a first clock gating circuit that outputs a first gated clock signal that controls a clock signal, and a second enable signal that controls the enable and disable of data acquisition of an acquisition circuit to which data from the replacement target flip-flop is input directly or via a combinational circuit, are respectively input to the power gating circuit as power supply control signals. [Effects of the Invention]

[0012] According to the semiconductor circuit device of the present invention, a first enable signal that controls the enable and disable of a clock signal for a non-volatile first flip-flop and a second enable signal of an acquisition circuit that acquires data from the first flip-flop directly or via a combinational circuit are input to the power gating circuit of the first flip-flop to control the power supply, so that the power supply of the first flip-flop can be easily controlled in cooperation with the acquisition circuit that is controlled by an enable signal different from that of the first flip-flop.

[0013] According to the logic circuit design support device of the present invention, a non-non-volatile flip-flop controlled by a different enable signal can be replaced with a first non-volatile flip-flop, and a circuit configuration can be easily generated that performs power supply control in cooperation with the non-non-volatile flip-flop. [Brief explanation of the drawings]

[0014] [Figure 1] 1 is a circuit diagram showing a semiconductor circuit device according to a first embodiment. [Figure 2] FIG. 2 is a circuit diagram showing a clock gating circuit. [Figure 3] FIG. 1 is a circuit diagram showing a configuration of a nonvolatile flip-flop. [Figure 4] 10 is a timing chart showing changes in each signal when an enable signal of a nonvolatile flip-flop is made active. [Figure 5] 10 is a timing chart showing changes in each signal when an enable signal for a flip-flop at the next stage is made active. [Figure 6] FIG. 10 is a circuit diagram showing an example in which an auxiliary signal generating circuit is provided. [Figure 7] FIG. 10 is a circuit diagram showing an example in which the auxiliary signal generating circuit is configured with a low latch. [Figure 8] FIG. 10 is a circuit diagram showing an example in which a common switching signal is used for each nonvolatile flip-flop controlled by a common enable signal. [Figure 9]FIG. 10 is a circuit diagram showing an example in which an auxiliary signal generating circuit is provided in a configuration in which a common switching signal is used for each nonvolatile flip-flop controlled by a common enable signal. [Figure 10] FIG. 10 is a circuit diagram showing an example of power gating for a combinational circuit connected to a nonvolatile flip-flop. [Figure 11] FIG. 10 is a circuit diagram showing an example in which a plurality of nonvolatile flip-flops are provided with a combinational circuit sandwiched therebetween. [Figure 12] 12 is a timing chart showing an example of changes in each signal in the example of FIG. 11. [Figure 13] FIG. 10 is a circuit diagram showing an example in which a cutoff avoidance signal is input to a power gating circuit. [Figure 14] FIG. 10 is a circuit diagram showing an example in which changes in some signals are suppressed when the cutoff avoidance signal is active. [Figure 15] FIG. 10 is a block diagram illustrating an example of switching the frequency of a clock signal in response to a cutoff avoidance signal. [Figure 16] 16 is a timing chart showing an example of changes in each signal in the example of FIG. 15. [Figure 17] 10 is a circuit diagram showing an example in which a plurality of nonvolatile flip-flops are provided with a combinational circuit interposed therebetween, and the frequency of a clock signal is switched in response to a cutoff avoidance signal. [Figure 18] FIG. 10 is a circuit diagram showing an example in which a high-frequency clock signal is always supplied to a group of circuits that are always operated at high speed. [Figure 19] FIG. 10 is a circuit diagram showing an example of power gating of a nonvolatile flip-flop in a circuit that generates an enable signal for the nonvolatile flip-flop. [Figure 20] FIG. 10 is a block diagram showing an outline of a semiconductor circuit device that performs convolution operations and pooling processes according to a second embodiment. [Figure 21] FIG. 1 is an explanatory diagram illustrating an example of connected layers of a convolutional neural network. [Figure 22] FIG. 10 is an explanatory diagram showing the relationship between the movement of the position of the convolution region and the pooling region. [Figure 23]FIG. 2 is a block diagram showing the configuration of a calculation unit. [Figure 24] FIG. 10 is an explanatory diagram showing the state of convolution calculation processing when calculation is performed on the first channel in channel parallelism. [Figure 25] FIG. 10 is an explanatory diagram showing the state of convolution calculation processing when calculation is performed on the second channel in channel parallelism. [Figure 26] FIG. 10 is a block diagram showing the configuration of a logic circuit design assistance device according to a third embodiment. [Figure 27] FIG. 10 is an explanatory diagram showing an example of replacement by the logic circuit design assistance device; [Figure 28] FIG. 10 is an explanatory diagram showing another example of replacement by the logic circuit design assistance device. DETAILED DESCRIPTION OF THE INVENTION

[0015] In FIG. 1, a semiconductor circuit device (hereinafter simply referred to as a circuit device) 10 includes a logic circuit section S1 composed of various logic gates, sequential circuits, etc., and a clock circuit S2 that generates and outputs a clock signal (hereinafter referred to as a CLK signal). The logic circuit section S1 includes a flip-flop (hereinafter referred to as a non-volatile flip-flop) NF11 that has the function of non-volatilely storing data (logical values ​​("1" or "0")), a flip-flop FF12, combinational circuits 13 and 14, clock gating circuits 15 and 16, a power gating circuit 17, and signal generating circuits (not shown) that generate enable signals EN11 and EN12 (described later). The logic circuit section S1 receives an input of the CLK signal and operates in synchronization with the CLK signal. The clock circuit S2 may be provided external to the circuit device 10.

[0016] The nonvolatile flip-flop NF11 as the first flip-flop is a nonvolatile flip-flop that is provided with the function of storing data nonvolatilely, as described above. When a clock pulse (in this example, the signal portion from rising to falling) having a predetermined pulse width or more is input during an operation mode in which power is supplied, the nonvolatile flip-flop NF11 stores the input data nonvolatilely. When the power supply is resumed, that is, when the mode shifts from the shutdown mode in which power supply is cut off to the operation mode, the nonvolatile flip-flop NF11 enters a state in which it outputs the data stored nonvolatilely.

[0017] In this example, the nonvolatile flip-flop NF11 normally operates in almost the same way as a positive-edge D flip-flop, but the timing at which it outputs the held data is different. That is, the nonvolatile flip-flop NF11 holds the data input to the D terminal (input terminal) at the rising edge of the clock pulse input to the CLK terminal, and outputs the held data from the Q terminal (output terminal) after the clock pulse is input (after the falling edge).

[0018] The nonvolatile flip-flop NF11 has a D terminal connected to the combinational circuit 13 and a Q terminal connected to the combinational circuit 14. As a result, data from the combinational circuit 13 is input to the nonvolatile flip-flop NF11, and data output from the nonvolatile flip-flop NF11 is input to the combinational circuit 14. Note that a configuration may also be adopted in which data from a circuit other than a combinational circuit is input to the nonvolatile flip-flop NF11.

[0019] Furthermore, the CLK terminal of the non-volatile flip-flop NF11 is connected to the clock gating circuit 15, and receives the gated clock signal GCK11 controlled by the clock gating circuit 15. As a result, the non-volatile flip-flop NF11 acquires data from the combinational circuit 13 at the rising edge of the clock pulse of the gated clock signal GCK11, and outputs the data from the Q terminal. In other words, the non-volatile flip-flop NF11 operates in response to the clock pulse of the gated clock signal GCK11.

[0020] The combinational circuits 13 and 14 are circuits whose output data is determined solely by the data input thereto, and whose output does not depend on previous operations. Therefore, the combinational circuits 13 and 14 are logic circuits whose output data is uniquely determined by the input data or the combination of input data.

[0021] Flip-flop FF12 is an acquisition circuit at the next stage relative to non-volatile flip-flop NF11, and is a second flip-flop that acquires data from non-volatile flip-flop NF11. In this example, flip-flop FF12 is a positive-edge D flip-flop and does not have the function of storing data non-volatilely like non-volatile flip-flop NF11. The D terminal of flip-flop FF12 is connected to combinational circuit 14, and data output from combinational circuit 14 is input to flip-flop FF12.

[0022] Furthermore, the CLK terminal of the flip-flop FF12 is connected to the clock gating circuit 16, and receives the gated clock signal GCK12 controlled by the clock gating circuit 16. As a result, the flip-flop FF12 holds data from the combinational circuit 14 at the rising edge of the clock pulse of the gated clock signal GCK12, and outputs the held data from the Q terminal. That is, the flip-flop FF12 operates in response to the clock pulse of the gated clock signal GCK12, and acquires the data output from the non-volatile flip-flop NF11 via the combinational circuit 14. The Q terminal of the flip-flop FF12 is connected to a subsequent circuit (not shown).

[0023] In this example, the flip-flop FF12 acquires data from the non-volatile flip-flop NF11 via the combinational circuit 14, but the Q terminal of the non-volatile flip-flop NF11 may be connected to the D terminal of the flip-flop FF12 to directly acquire the data output from the non-volatile flip-flop NF11. Also, as will be described later, a second flip-flop that acquires data from the non-volatile flip-flop NF11 may be a non-volatile flip-flop similar to the non-volatile flip-flop NF11.

[0024] The clock gating circuit 15, which serves as a first clock gating circuit, controls the CLK signal, i.e., controls the blocking or passing of the clock pulse of the CLK signal, in response to an enable signal EN11, which serves as a first enable signal that controls the enable and disable of the CLK signal, and supplies the signal to the non-volatile flip-flop NF11. This clock gating control reduces dynamic power consumption in the non-volatile flip-flop NF11. The clock gating circuit 15 receives the enable signal EN11 and the CLK signal from the clock circuit S2 as input, and outputs a gated clock signal GCK11, which serves as a first gated clock signal, by controlling the CLK signal in response to the enable signal EN11.

[0025] Similarly, the clock gating circuit 16 as a second clock gating circuit reduces dynamic power consumption in the flip-flop FF12 by controlling the CLK signal in response to an enable signal EN12 as a second enable signal that controls whether data acquisition is enabled or disabled. The clock gating circuit 16 receives the enable signal EN12 and the CLK signal, and outputs a gated clock signal GCK12 as a second gated clock signal obtained by controlling the CLK signal in response to the enable signal EN12.

[0026] The enable signal EN11 is made active so that a clock pulse (rising edge) is input to the non-volatile flip-flop NF11 when the non-volatile flip-flop NF11 acquires data from the combinational circuit 13. Similarly, the enable signal EN12 is made active so that a clock pulse (rising edge) is input to the flip-flop FF12 when the flip-flop FF12 acquires data from the combinational circuit 14. These enable signals EN11 and EN12 are generated by a combinational circuit or the like, and the timing of their active and inactive states is controlled in synchronization with the CLK signal. In this example, they change from inactive to active and from active to inactive while the CLK signal is at H level. Note that the enable signals EN11 and EN12 only need to be determined before the CLK signal rises, and do not necessarily need to change when the CLK signal is at H level.

[0027] The enable signals EN11 and EN12 are independent signals, and the non-volatile flip-flop NF11 and flip-flop FF12 are circuits controlled by different enable signals. The logical values ​​of the enable signals EN11 and EN12 will be described as active and inactive. Some other signals will also be described as active and inactive.

[0028] The power gating circuit 17 reduces the static power consumption of the nonvolatile flip-flop NF11 by power gating, i.e., cutting off the power supply to the nonvolatile flip-flop NF11. In this example, the power gating circuit 17 is composed of a NOR gate P17 as a control circuit and a transistor Tr17 as a power switch. The transistor Tr17 is a p-type MOS transistor and is provided on a power supply line that applies a power supply voltage to the nonvolatile flip-flop NF11 so as to open and close the power supply line. The output terminal of the NOR gate P17 is connected to the gate. The output of the NOR gate P17 is a switching signal PG11, and the on / off of the transistor Tr17 is controlled by this switching signal PG11. When the switching signal PG11 is active (L level), the transistor Tr17 is turned on, supplying power to the nonvolatile flip-flop NF11. When the switching signal PG11 is inactive (H level), the transistor Tr17 is turned off, cutting off the power supply to the nonvolatile flip-flop NF11.

[0029] The NOR gate P17 receives enable signals EN11, EN12, and gated clock signal GCK11 as power supply control signals. When any of the enable signals EN11, EN12, and gated clock signal GCK11 is active (H level), the NOR gate P17 outputs a switching signal PG11 that is active (L level) to turn on transistor Tr17, and when all of them are inactive (L level), the NOR gate P17 outputs a switching signal PG11 that is inactive (H level) to turn off transistor Tr17. In this example, flip-flop FF12 is not a non-volatile flip-flop and therefore does not perform power gating.

[0030] The enable signal EN11 is input to the NOR gate P17 mainly for the purpose of putting the nonvolatile flip-flop NF11 into an operation mode to acquire data from the combinational circuit 13. The enable signal EN12 is input to the NOR gate P17 in order to put the nonvolatile flip-flop NF11 into an operation mode to output data when the flip-flop FF12 acquires data from the nonvolatile flip-flop NF11 via the combinational circuit 14.

[0031] Furthermore, the gated clock signal GCK11 is input to the NOR gate P17 as an auxiliary signal for maintaining the operation mode of the non-volatile flip-flop NF11 while the clock pulse of the gated clock signal GCK11 is being input. As a result, when the gated clock signal GCK11 rises while the enable signal EN11 is active, the transistor Tr17 remains on until the gated clock signal GCK11 falls, regardless of the timing when the enable signal EN11 becomes inactive. In this example, the clock gating circuit 15 is an auxiliary signal generating circuit that generates an auxiliary signal.

[0032] The clock circuit S2 generates and outputs a CLK signal. In this example, the pulse width of the clock pulse of the CLK signal output by the clock circuit S2 (the time during which the clock signal CLK is at H level) is set to be equal to or longer than the time required for the nonvolatile flip-flop NF11 to store data in a nonvolatile manner (hereinafter referred to as the rewrite request time). Therefore, the nonvolatile flip-flop NF11 stores the input data in a nonvolatile manner every time a clock pulse of the gated clock signal GCK11 is input.

[0033] 2, the clock gating circuit 15 is composed of a low-active D-type latch (hereinafter referred to as the low latch) 15a and an AND gate 15b. The low latch 15a receives an enable signal EN11 at its input terminal (D terminal) and a CLK signal at its CLK terminal. The AND gate 15b receives the output signal from the output terminal (Q terminal) of the low latch 15a and the CLK signal. As a result, the clock gating circuit 15 outputs a gated clock signal GCK11, which is the CLK signal gating-controlled in accordance with the enable signal EN11.

[0034] The low latch 15a holds the signal level of the enable signal EN11 at the rising edge of the CLK signal, and outputs the held signal level until the CLK signal goes low. Therefore, if the CLK signal rises while the enable signal EN11 is active (high), an output signal that becomes active between the rising edge and the falling edge of the CLK signal can be obtained from the low latch 15a. By inputting the output signal of the low latch 15a and the CLK signal to the AND gate 15b, a clock pulse of the gated clock signal GCK11 with a perfect pulse shape, i.e., the same pulse shape as the CLK signal, can be obtained in response to the enable signal EN11 going active.

[0035] The clock gating circuit 16 has the same configuration as the clock gating circuit 15, and receives an enable signal EN12 instead of the enable signal EN11. As a result, the clock gating circuit 16 outputs a clock pulse of the gated clock signal GCK12 having a perfect pulse shape in response to the enable signal EN12 being active.

[0036] 3 shows an example of the configuration of the nonvolatile flip-flop NF11. The nonvolatile flip-flop NF11 is configured as a master-slave type having a master latch 11a and a slave latch 11b. The master latch 11a is a D-type latch, and a combinational circuit 13 is connected to its D terminal. Furthermore, the master latch 11a receives an inverted gated clock signal GCKB11, which is an inverted version of the gated clock signal GCK11, at its CLK terminal.

[0037] As a result, when the gated clock signal GCK11 is at L level (the inverted gated clock signal GCKB11 is at H level), master latch 11a outputs the data input from combinational circuit 13 as is from the Q terminal, and when the gated clock signal GCK11 becomes H level (the inverted gated clock signal GCKB11 is at L level), master latch 11a holds and outputs the data that was output immediately before (that was input from combinational circuit 13). Data that is the inversion of the data output from the Q terminal is output from the QB terminal of master latch 11a.

[0038] The slave latch 11b is composed of a basic circuit 21, a nonvolatile memory circuit 22, and transfer transistors 24 to 27, which are n-type MOSFETs. The basic circuit 21 is composed of a first latch 31 and a second latch 32, and the nonvolatile memory circuit 22 is composed of MTJ (Magnetic Tunnel Junction) elements 33 and 34.

[0039] The first latch 31 includes p-type MOSFET transistors 36 and 37, and n-type MOSFET transistors 38, 39, and 41. The source of the transistor 36 is connected to the source of the transfer transistor 24, and the drain is connected to the drain of the transistor 38. The source of the transistor 37 is connected to the source of the transfer transistor 25, and the drain is connected to the drain of the transistor 39. The sources of the transistors 38 and 39 are connected to the drain of the transistor 41. The gates of the transistors 36 and 37 receive the gated clock signal GCK11. The gate of the transistor 38 is connected to the drain of the transistor 39, and the gate of the transistor 39 is connected to the drain of the transistor 38. The source of the transistor 41 is connected to ground, and the inverted gated clock signal GCKB11 is input to the gate of the transistor 41.

[0040] The second latch 32 includes p-type MOSFET transistors 42 to 45, 46. The drain of the transistor 42 is connected to the source of the transfer transistor 26, and the source is connected to the drain of the transistor 44. The drain of the transistor 43 is connected to the source of the transfer transistor 27, and the source is connected to the drain of the transistor 45. The sources of the transistors 44 and 45 are each connected to the drain of the transistor Tr17 of the power gating circuit 17, and the power supply voltage is applied via this transistor Tr17.

[0041] A gated clock signal GCK11 is input to the gates of the transistors 42 and 43. The gate of the transistor 44 is connected to a connection point N2 between the source of the transistor 43 and the drain of the transistor 45, and the gate of the transistor 45 is connected to a connection point NB2 between the source of the transistor 42 and the drain of the transistor 44. The connection point N2 serves as the output terminal (Q terminal) of the second latch 32, i.e., the non-volatile flip-flop NF11, and the potential of the connection point N2 is output as the output signal (data) of the non-volatile flip-flop NF11. One of the source and drain of the transistor 46 is connected to the connection point N2, and the other is connected to the connection point NB2. An inverted gated clock signal GCKB11 is input to the gate of the transistor 46.

[0042] The drains of the transfer transistors 24 and 27 are connected to the Q terminal of the master latch 11a, and the drains of the transfer transistors 25 and 26 are connected to the QB terminal of the master latch 11a. The gated clock signal GCK11 is input to the gates of the transfer transistors 24 to 27.

[0043] The MTJ elements 33 and 34 in this example are of the spin injection type and have a structure in which a magnetization fixed layer, whose magnetization direction is fixed, and a magnetization free layer, whose magnetization direction can be changed, are stacked with an insulating film sandwiched between them. In this example, the MTJ elements 33 and 34 are of the in-plane magnetization type, in which the magnetization directions of the magnetization fixed layer and the magnetization free layer are in-plane, but they may also be of the perpendicular magnetization type, in which the magnetization direction is perpendicular to the in-plane direction.

[0044] The magnetization direction of the magnetization free layer can be changed by passing a write current through the MTJ elements 33 and 34 that is longer than the rewrite request time, and the magnetization direction is determined by the direction of the write current. The rewrite request time can be defined as the sum of the incubation time from when the voltage applied to the MTJ elements 33 and 34 rises to when the magnetization direction of the magnetization free layer in the MTJ elements 33 and 34 starts to reverse, and the transit time from when the reversal of the magnetization direction starts to complete. The rewrite request time also varies depending on the applied voltage (magnitude of the write current), but in this example, it is assumed that a constant voltage is applied and the rewrite request time is a predetermined constant value.

[0045] The MTJ elements 33 and 34 can be placed in either a parallel state, in which the magnetization direction of the magnetization free layer is the same as that of the magnetization fixed layer, or an antiparallel state, in which the magnetization direction of the magnetization free layer is opposite to that of the magnetization fixed layer. The magnetization direction of the magnetization free layer is maintained until a write current is passed through it to change its direction. This allows data ("1" or "0") to be stored nonvolatilely in the MTJ elements 33 and 34 by controlling the parallel and antiparallel states. The MTJ elements 33 and 34 have relatively low resistance in the parallel state and relatively high resistance in the antiparallel state. The MTJ elements 33 and 34 are placed in the antiparallel state by passing a write current from the magnetization fixed layer to the magnetization free layer, and are placed in the parallel state by passing a write current from the magnetization free layer to the magnetization fixed layer.

[0046] The MTJ element 33 has its magnetization fixed layer connected to the source of the transfer transistor 24 and its magnetization free layer connected to the source of the transfer transistor 26, while the MTJ element 34 has its magnetization fixed layer connected to the source of the transfer transistor 25 and its magnetization free layer connected to the source of the transfer transistor 27. Therefore, the MTJ element 33 is connected between the transistor 36 of the first latch 31 and the transistor 42 of the second latch 32, and the MTJ element 34 is connected between the transistor 37 of the first latch 31 and the transistor 43 of the second latch 32. Furthermore, these MTJ elements 33 and 34 are connected in opposite directions between the Q terminal and QB terminal of the master latch 11a via the transfer transistors 24 to 27.

[0047] The operation of the nonvolatile flip-flop NF11 will now be described. With power supplied via the on-transistor Tr17, when the gated clock signal GCK11 is at L level (the inverted gated clock signal GCKB11 is at H level), the input data input from the combinational circuit 13 is output from the Q terminal of the master latch 11a, and inverted input data, which is the inverted version of the input data, is output from the QB terminal. When a clock pulse of the gated clock signal GCK11 is input to the nonvolatile flip-flop NF11, that is, when the gated clock signal GCK11 rises to H level, the master latch 11a holds the input data at that time and outputs it from the Q terminal, and inverted input data, which is the inverted version of the held input data, from the QB terminal.

[0048] In the slave latch 11b, the gated clock signal GCK11 is at the H level and the inverted gated clock signal GCKB11 is at the L level, so that the transfer transistors 24 to 27 are on, the transistors 36, 37, 41 to 43 are off, and the transistor 46 is on. As a result, the first latch 31 and the second latch 32 do not operate. Meanwhile, the MTJ element 33 is connected with its free magnetization layer to the QB terminal of the master latch 11a and its fixed magnetization layer to the Q terminal of the master latch 11a. The MTJ element 34 is connected with its free magnetization layer to the Q terminal of the master latch 11a and its fixed magnetization layer to the QB terminal of the master latch 11a.

[0049] As a result, a voltage is applied to the MTJ elements 33 and 34 in a direction according to the input data, causing a write current to flow. At this time, the MTJ elements 33 and 34 are applied with voltages in opposite directions, so that a write current flows from the magnetization fixed layer to the magnetization free layer in one MTJ element, and a write current flows from the magnetization free layer to the magnetization fixed layer in the other MTJ element.

[0050] Since the pulse width of the clock pulse of the gated clock signal GCK11 is set to be equal to or longer than the requested rewrite time, a write current flows through the MTJ elements 33 and 34 for a time equal to or longer than the requested rewrite time, and the magnetization directions of the MTJ elements 33 and 34 correspond to the write current. As a result, one of the MTJ elements 33 and 34 becomes parallel and the other becomes antiparallel according to the input data, and the input data is written and stored nonvolatilely in the nonvolatile memory circuit 22.

[0051] For example, when the input data is "1," the Q terminal of the master latch 11a is at the H level and the QB terminal is at the L level. Therefore, a write current flows through the MTJ element 33 in the direction from the magnetization fixed layer to the magnetization free layer, and a write current flows through the MTJ element 34 in the direction from the magnetization free layer to the magnetization fixed layer. As a result, the MTJ element 33 is in the antiparallel state and the MTJ element 34 is in the parallel state. On the other hand, when the input data is "0," the Q terminal of the master latch 11a is at the L level and the QB terminal is at the H level, so that a write current flows through the MTJ elements 33 and 34 in the direction opposite to when the input data is "1." As a result, the MTJ element 33 is in the parallel state and the MTJ element 34 is in the antiparallel state.

[0052] After the write is complete, when the gated clock signal GCK11 transitions to the L level, the transfer transistors 24 to 27 and 46 are turned off and the transistors 36, 37, 41 to 43 are turned on. As a result, the first latch 31 and the second latch 32 are activated. The input data previously input is held as a charge in the parasitic capacitances of the input nodes (the connection points between the MTJ elements 33 and 34 and the transfer transistors 24 to 27). Due to the difference in the amount of charge, the input data is latched into the first latch 31 and the second latch 32 regardless of the state of the MTJ elements 33 and 34. This causes the nonvolatile flip-flop NF11 to output the input data previously input. Therefore, when the previous input data is "1," the connection point N2 goes to the H level, and the nonvolatile flip-flop NF11 outputs data "1." On the other hand, if the immediately preceding input data is "0", the node N2 goes to L level, and the nonvolatile flip-flop NF11 outputs data "0".

[0053] As described above, the non-volatile flip-flop NF11 holds and outputs the input data at the rising edge of the clock pulse of the gated clock signal GCK11, and stores the input data in a non-volatile manner in response to the input of a clock pulse having a pulse width equal to or greater than the requested rewrite time.

[0054] When a clock pulse of the gated clock signal GCK11 having a pulse width shorter than the rewrite request time is input, a write current flows through the MTJ elements 33 and 34 in a direction corresponding to the input data, as described above. However, the magnetization direction of the magnetization free layer does not reverse, and the magnetization direction of the magnetization free layer does not change. Therefore, the input data is not stored nonvolatilely. Also in this case, when the gated clock signal GCK11 transitions to the L level, the input data is latched into the first latch 31 and the second latch 32 regardless of the state of the MTJ elements 33 and 34 due to the difference in the amount of charge accumulated in the parasitic capacitance of the input node. Therefore, the input data previously input is output from the nonvolatile flip-flop NF11.

[0055] Next, the operation of the non-volatile flip-flop NF11 when the power supply is resumed will be described. In response to the enable signal EN11 or EN12 becoming active, the transistor Tr17 changes from off to on, and the power supply to the non-volatile flip-flop NF11 is resumed.

[0056] As described above, enable signals EN11 and EN12 change in synchronization with the CLK signal and change from inactive to active while the CLK signal is at H or L level. Therefore, the gated clock signal GCK11 does not change from inactive to active simultaneously with enable signal EN11 or enable signal EN12. In other words, when power supply to non-volatile flip-flop NF11 is resumed, the clock pulse of gated clock signal GCK11 is not input to non-volatile flip-flop NF11. Therefore, when transistor Tr17 is turned on, gated clock signal GCK11 is at L level and inverted gated clock signal GCKB11 is at H level.

[0057] Because the gated clock signal GCK11 is at L level and the inverted gated clock signal GCKB11 is at H level, the transfer transistors 24 to 27 are off, the transistors 36, 37, 41 to 43 are on, and the transistor 46 is off. As a result, the first latch 31 and the second latch 32 are activated.

[0058] When the MTJ elements 33 and 34 are written as described above, one has high resistance (antiparallel state) and the other has low resistance (parallel state). This causes a difference in current flow between the circuit on the MTJ element 33 side and the circuit on the MTJ element 34 side of the activated first latch 31 and second latch 32. This causes a difference in potential between the gates of transistors 38 and 39 in the first latch 31 and the gates of transistors 44 and 45 (nodes N2 and NB2) in the second latch 32. This difference in potential is amplified and stabilized by the positive feedback action of the first latch 31 and the second latch 32. At this time, the potential of the node N2 or NB2 on the path through which the larger current flows becomes higher than the potential of the other node.

[0059] For example, when the MTJ element 33 has a high resistance and the MTJ element 34 has a low resistance, a larger current flows through the MTJ element 34 than through the MTJ element 33, and the potential of the connection point N2 becomes higher than the potential of the connection point NB2, so that the connection point N2 reaches an H level and the connection point NB2 reaches an L level and stabilizes. As a result, the nonvolatile flip-flop NF11 outputs an H level, i.e., data "1".

[0060] On the other hand, when the MTJ element 33 has a low resistance and the MTJ element 34 has a high resistance, the current flowing through the MTJ element 33 is larger than that of the MTJ element 34, and the potential of the connection point NB2 becomes higher than the potential of the connection point N2, so that the connection point N2 reaches an L level and the connection point NB2 reaches an H level and stabilizes. As a result, the nonvolatile flip-flop NF11 outputs an L level, i.e., data "0".

[0061] As described above, when the power supply to the nonvolatile flip-flop NF11 is resumed, the data nonvolatilely stored in the nonvolatile memory circuit 22 composed of the MTJ elements 33 and 34 is restored and held in the basic circuit 21 composed of the first latch 31 and the second latch 32, and the held data is then output.

[0062] Details of the latch configuration of the slave latch 11b including the MTJ elements 33 and 34 are described in Non-Patent Document 1 and Patent Document 1. The configuration of the non-volatile flip-flop NF11 is just an example, and the configuration described in Patent Document 1 may also be used.

[0063] In the circuit device 10 configured as described above, when the non-volatile flip-flop NF11 acquires data from the combinational circuit 13, the enable signal EN11 becomes active (time T11) while the CLK signal is at H level, for example, while the data is being output from the combinational circuit 13, as shown in FIG. 4. When the enable signal EN11 becomes active, the switching signal PG11 from the NOR gate P17 becomes active, and the transistor Tr17 turns on. This starts the supply of power to the non-volatile flip-flop NF11.

[0064] In response to the falling edge of the CLK signal while the enable signal EN11 is active, the output of the low latch 15a goes high (time T12). This high-level output of the low latch 15a continues until the enable signal EN11 becomes inactive and the CLK signal falls again while it is inactive.

[0065] As described above, when the CLK signal rises while the output of the low latch 15a is at H level (time T13), the gated clock signal GCK11, which is the output of the AND gate 15b, becomes active (H level). After this, while the CLK signal is at H level, the enable signal EN11 becomes inactive (time T14). However, because the output of the low latch 15a maintains H level until the next falling edge of the CLK signal, the gated clock signal GCK11 maintains H level until time T15 when the CLK signal falls. As a result, in synchronization with the rising edge of the CLK signal while the enable signal EN11 is active, a clock pulse of the gated clock signal GCK11, which has the same pulse shape as the CLK signal, is output from the clock gating circuit 15, and this clock pulse is input to the non-volatile flip-flop NF11.

[0066] When the clock pulse of the gated clock signal GCK11 is input to the nonvolatile flip-flop NF11 as described above, the pulse width of the clock pulse is equal to or greater than the requested rewrite time, and therefore the input data is stored in a nonvolatile manner in the nonvolatile memory circuit 22 as described above. Because the gated clock signal GCK11 is also input to the NOR gate P17, the transistor Tr17 remains on while the clock pulse of the gated clock signal GCK11 is being input. Therefore, even if the enable signal EN11 becomes inactive during the write period, power continues to be supplied to the nonvolatile flip-flop NF11, and data is normally written to the nonvolatile memory circuit 22.

[0067] When the gated clock signal GCK11 goes low (time T15), the signals input to the NOR gate P17 become inactive, turning off the transistor Tr17 and cutting off the power supply to the nonvolatile flip-flop NF11.

[0068] 5, when the flip-flop FF12 acquires data from the combinational circuit 14, the enable signal EN12 is activated while the CLK signal is at H level (time T17). When the enable signal EN12 becomes active, the switching signal PG11 from the NOR gate P17 becomes active and the transistor Tr17 turns on. This starts the supply of power to the non-volatile flip-flop NF11.

[0069] When power supply starts, in nonvolatile flip-flop NF11, the gated clock signal GCK11 is at L level, so that the data written in nonvolatile memory circuit 22 immediately before power supply was cut off is restored and held in basic circuit 21, and the held data is output to combinational circuit 14. Then, data determined by the data input from nonvolatile flip-flop NF11 is input from combinational circuit 14 to flip-flop FF12.

[0070] A clock pulse of the GCK12 signal, which has the same pulse shape as the CLK signal, is input to the flip-flop FF12 in synchronization with the rising edge of the CLK signal while the enable signal EN12 is active. As a result, a clock pulse of the gated clock signal GCK12 is input to the flip-flop FF12 while data determined by the data from the non-volatile flip-flop NF11 is being output from the combinational circuit 14. The flip-flop FF12 acquires data from the combinational circuit 14 at the rising edge of the clock pulse of the gated clock signal GCK12 (time T18).

[0071] After the flip-flop FF12 acquires the data, the enable signal EN12 becomes inactive, turning off the transistor Tr17 and stopping the power supply to the non-volatile flip-flop NF11 (time T19).

[0072] As described above, the power supply to nonvolatile flip-flop NF11 is controlled using the enable signal EN11 for nonvolatile flip-flop NF11 and the enable signal EN12 for flip-flop FF12, which is the next stage of nonvolatile flip-flop NF11, so the control of enable signal EN11 and the circuitry therefor do not become complicated.Furthermore, the power supply to nonvolatile flip-flop NF11 is controlled using the gated clock signal GCK11 as an auxiliary signal, so normal operation for nonvolatile storage of nonvolatile flip-flop NF11 is ensured without waste.

[0073] 6 shows an example in which a circuit for generating an auxiliary signal is provided separately from the clock gating circuit. In this example, the logic circuit section S1 is provided with an auxiliary signal generation circuit 51 that generates an auxiliary signal. This auxiliary signal generation circuit 51 generates an auxiliary signal from the CLK signal and the enable signal EN11. The auxiliary signal generation circuit 51 is active (high level) at least while the clock pulse of the gated clock signal GCK11 is being input to the non-volatile flip-flop NF11, and inputs the generated auxiliary signal to the NOR gate P17.

[0074] Specifically, as shown in FIG. 7, the auxiliary signal generation circuit 51 is composed of a low latch 51a, which is a low-active D-type latch. The low latch 51a receives the enable signal EN11 at its input terminal (D terminal) and the CLK signal at its CLK terminal, and outputs a signal from its output terminal (Q terminal) as the auxiliary signal. Therefore, the auxiliary signal output from the auxiliary signal generation circuit 51 is the same as that of the low latch 15a of the clock gating circuit 15. It goes high in response to the falling edge of the CLK signal while the enable signal EN11 is active, and continues until the enable signal EN11 becomes inactive and the CLK signal falls again while inactive. This auxiliary signal also ensures the normal operation of the nonvolatile storage of the nonvolatile flip-flop NF11 without any waste.

[0075] The auxiliary signal generating circuit 51 may have the same circuit configuration as the clock gating circuit 15. Alternatively, the output of the low latch 15a of the clock gating circuit 15 may be used as the auxiliary signal.

[0076] A common switching signal can be used to power-gate multiple nonvolatile flip-flops that share a common logical enable signal. In the example shown in FIG. 8, nonvolatile flip-flop NF11 is provided along with nonvolatile flip-flop NF11A and NF11B, which acquire data from combinational circuit 13 common to nonvolatile flip-flop NF11 and output data to combinational circuit 14. A common enable signal EN11 is used for the nonvolatile flip-flops NF11, NF11A, and NF11B connected in this manner. Transistors Tr17A and Tr17B are provided in nonvolatile flip-flop NF11A and NF11B, respectively, as power switches. A switching signal PG11 is supplied from a single NOR gate P17 to transistors Tr17, Tr17A, and Tr17B of nonvolatile flip-flop NF11.

[0077] 8, a gated clock signal is supplied to the non-volatile flip-flops NF11A and NF11B from a clock gating circuit 15A provided separately from the clock gating circuit 15 of the non-volatile flip-flop NF11, but a configuration in which the gated clock signal GCK11 from the clock gating circuit 15 is input to the non-volatile flip-flops NF11, NF11A, and NF11B may also be used. Also, as shown in FIG. 9, a configuration in which an auxiliary signal generation circuit 51 is provided separately from the clock gating circuit may also be used. In the example of FIG. 9, a low latch 51a is used as the auxiliary signal generation circuit 51.

[0078] When the only circuits connected to the input or output side of a combinational circuit are non-volatile flip-flops that use a common enable signal as a power supply control signal, the power supply for the combinational circuit can be controlled using the same switching signal as the non-volatile flip-flop. Figure 10 shows an example in which the power supply for the combinational circuit is controlled using the same switching signal as the non-volatile flip-flop. The example in Figure 10 is the same as the example in Figure 9 except that power supply control is performed for combinational circuits 13 and 14.

[0079] 10, the combinational circuit 13 is provided with a transistor Tr13 as a power switch. By turning on and off this transistor Tr13, power is supplied to and cut off from the combinational circuit 13. Similarly, the combinational circuit 14 is provided with a transistor Tr14, and by turning on and off this transistor Tr14, power is supplied to and cut off from the combinational circuit 14.

[0080] The combinational circuit 13 has only nonvolatile flip-flops NF11, NF11A, and NF11B connected as its output side circuits, and the enable signals used as power supply control signals for these nonvolatile flip-flops NF11, NF11A, and NF11B are enable signals EN11 and EN12. When power is not supplied to the nonvolatile flip-flops NF11, NF11A, and NF11B, there is no problem even if the combinational circuit 13 does not output data or if the output of the combinational circuit 13 is undefined, so the power supply to the combinational circuit 13 may be cut off. Therefore, the transistor Tr13 provided for the combinational circuit 13 is turned on and off using a switching signal from a NOR gate P17 that is shared with the nonvolatile flip-flops NF11, NF11A, and NF11B, to control the power supply of the combinational circuit 13.

[0081] The combinational circuit 14 is connected only to the nonvolatile flip-flops NF11, NF11A, and NF11B as input circuits. The enable signals used as power control signals for these nonvolatile flip-flops NF11, NF11A, and NF11B are enable signals EN11 and EN12. When power is not supplied to the nonvolatile flip-flops NF11, NF11A, and NF11B, even if the combinational circuit 14 does not output data or even if the output of the combinational circuit 14 is undefined, there is no problem with the input to the next-stage circuit (flip-flop FF12 in this example), so the power supply to the combinational circuit 14 may be cut off. Therefore, the transistor Tr14 provided for the combinational circuit 14 is turned on and off using a switching signal from a NOR gate P17 shared with the nonvolatile flip-flops NF11, NF11A, and NF11B.

[0082] In the above example, the next-stage flip-flop that acquires data from the non-volatile flip-flop is not non-volatile, but the next-stage flip-flop may be a non-volatile flip-flop, and power supply control can be performed for the next-stage non-volatile flip-flop in the same manner. In the example shown in Figure 11, non-volatile flip-flop NF53 is connected in the next stage of non-volatile flip-flop NF11 with combinational circuit 14 in between, and non-volatile flip-flop NF55 is connected in the next stage of non-volatile flip-flop NF53 with combinational circuit 54 in between.

[0083] Similar to the clock gating circuit 15 and power gating circuit 17 for the nonvolatile flip-flop NF11, the nonvolatile flip-flops NF53 and NF55 are provided with clock gating circuits 56 and 57 and power gating circuits 58 and 59. The clock gating circuits 56 and 57 and the power gating circuits 58 and 59 have the same configuration as the clock gating circuit 15 and the power gating circuit 17, and the power gating circuits 58 and 59 are each composed of NOR gates P58 and P59 and transistors Tr58 and Tr59.

[0084] The clock gating circuit 56 generates a gated clock signal GCK53 from an enable signal EN53 for the non-volatile flip-flop NF53 and the CLK signal, and outputs the gated clock signal GCK53 to the non-volatile flip-flop NF53 and the power gating circuit 58. Similarly, the clock gating circuit 57 generates a gated clock signal GCK55 from an enable signal EN55 for the non-volatile flip-flop NF55 and the CLK signal, and outputs the gated clock signal GCK55 to the non-volatile flip-flop NF55 and the power gating circuit 59.

[0085] An enable signal EN11, an enable signal EN53 for the nonvolatile flip-flop NF53, and a gated clock signal GCK11 are input as power supply control signals to a NOR gate P17 of the power gating circuit 17. An enable signal EN53 and a gated clock signal GCK53 for the nonvolatile flip-flop NF53, and an enable signal EN55 for the nonvolatile flip-flop NF55 are input as power supply control signals to a NOR gate P58 provided in the power gating circuit 58. An enable signal EN55 and a gated clock signal GCK55 for the nonvolatile flip-flop NF55, and an enable signal ENx for an acquisition circuit such as a flip-flop in the next stage of the nonvolatile flip-flop NF55 are input as power supply control signals to a NOR gate P59 of the power gating circuit 59.

[0086] In the above configuration, power supply control is performed for the nonvolatile flip-flops NF11, NF53, and NF55 using enable signals for themselves and the nonvolatile flip-flops in the next stage. An example of the changes in each signal is shown in Figure 12. In this example, the enable signals EN11, EN53, and EN55 are controlled to be active when the CLK signal is at H level, and the enable signal EN53 rises almost simultaneously with the falling edge of the enable signal EN11, and the enable signal EN53 rises almost simultaneously with the falling edge of the enable signal EN53, so that the nonvolatile flip-flops NF11, NF53, and NF55 acquire data consecutively in sequence.

[0087] Fig. 13 shows an example in which a shutdown avoidance signal is input as one of the power supply control signals. In the example of Fig. 13, shutdown avoidance circuit 61 outputs a shutdown avoidance signal whose logical value is controlled to be active (H level) or inactive (L level), and this shutdown avoidance signal is input to NOR gate P17 together with enable signals EN11 and EN12 and gated clock signal GCK11. Note that although the gated clock signal GCK11 is input to NOR gate P17 as an auxiliary signal, an auxiliary signal from an auxiliary signal generation circuit may be input instead.

[0088] The shutdown avoidance circuit 61 selects between a shutdown avoidance mode and a shutdown allowance mode, and activates a shutdown avoidance signal when the shutdown avoidance mode is selected, and deactivates the shutdown avoidance signal when the shutdown allowance mode is selected. The selection between the shutdown avoidance mode and the shutdown allowance mode in the shutdown avoidance circuit 61 can be configured to be made by a switch that is manually turned on and off, or can be configured to be made automatically based on the operating status of the circuit device 10 or the equipment incorporating the logic circuit device 10, the remaining capacity of the battery that serves as the power source, etc.

[0089] When the shutdown allowable mode is selected and the shutdown avoidance signal becomes inactive, power gating of the nonvolatile flip-flop NF11 is performed by the enable signals EN11, EN12 and the gated clock signal GCK11, as in the above-mentioned examples. On the other hand, when the shutdown avoidance mode is selected and the shutdown avoidance signal becomes active, power gating is not performed, i.e., the power supply is not cut off, because the transistor Tr17 is on while the shutdown avoidance signal is active, regardless of the enable signals EN11, EN12 and the gated clock signal GCK11.

[0090] Fig. 14 shows an example of suppressing dynamic power consumption by always keeping some of the power control signals input to the NOR gate inactive while the cutoff avoidance signal is active. Other than those explained below, it is the same as the example in Fig. 6.

[0091] In this example, a gating circuit 63 is provided that gates the enable signal EN11 input to the NOR gate P17 and the auxiliary signal generation circuit 51. The gating circuit 63 is composed of a NOT gate 63a and an AND gate 63b. The shutdown avoidance signal from the shutdown avoidance circuit 61 is input to the NOR gate P17 as one of the power supply control signals and is also input to the AND gate 63b via the NOT gate 63a. The enable signal EN11 is input to the clock gating circuit 15 and is also input to the AND gate 63b. A signal output from the AND gate 63b (hereinafter referred to as a gated enable signal GEN11) is input to the auxiliary signal generation circuit 51 and the NOR gate P17 in place of the enable signal EN11. The auxiliary signal generation circuit 51 may be configured as a low latch as described above, or may have the same configuration as the clock gating circuit.

[0092] According to this example, while the shutdown avoidance signal is active, the gated enable signal GEN11, which is the output of the AND gate 63b, is always maintained at L level (inactive). Furthermore, by maintaining the gated enable signal GEN11 inactive, the auxiliary signal, which is the output of the auxiliary signal generation circuit 51, is maintained inactive (L level). Therefore, the gated enable signal GEN11 and the auxiliary signal do not transition between H level and L level, respectively, and dynamic power consumption can be reduced.

[0093] During the period when the cutoff avoidance signal is inactive, the gated enable signal GEN11 exhibits the same changes as the EN1 signal, and therefore the power supply to the non-volatile flip-flop NF11 is controlled by the power gating circuit 17 in the same manner as in the above example.

[0094] FIG. 15 shows an example in which the frequency of the CLK signal is switched in response to the cutoff avoidance signal. The clock circuit S2 in this example has an oscillator S2a and an N-divider circuit (divider) S2b, which constitute a clock generating unit, and a selector S2c. The oscillator S2a generates a clock signal (hereinafter referred to as the CLK0 signal) with a constant frequency f. The CLK0 signal has a pulse width that is smaller than the requested rewrite time. The N-divider circuit S2b divides the CLK0 signal by N to generate a clock signal (hereinafter referred to as the CLK1 signal) with a frequency N·f whose pulse width is equal to or greater than the requested rewrite time. In this example, the CLK0 signal is the second clock signal, and the CLK1 signal is the first clock signal.

[0095] The selector S2c receives the CLK0 signal and the CLK1 signal as input, and selects one of the CLK0 signal and the CLK1 signal in accordance with the shutdown avoidance signal from the shutdown avoidance circuit 61, and outputs the selected signal as the CLK signal. When the shutdown avoidance signal is active, the selector S2c selects the CLK0 signal and outputs the selected CLK0 signal as the CLK signal. On the other hand, when the shutdown avoidance signal is inactive, the selector S2c selects the CLK1 signal and outputs the selected CLK1 signal as the CLK signal. As a result, when power gating of the non-volatile flip-flops in the logic circuit unit S1 is not performed, the CLK0 signal, which has a relatively high frequency, is used as the CLK signal to operate the logic circuit unit S1 at high speed, and when power gating is performed, the CLK1 signal, which has a relatively low frequency, is used as the CLK signal to non-volatilely store data in the non-volatile flip-flops in the logic circuit unit S1. In other words, by selecting between the shutdown avoidance mode and the shutdown tolerance mode in the shutdown avoidance circuit 61, a high-speed mode in which the logic circuit section S1 operates at high speed without power gating, or a power-saving mode in which the logic circuit section S1 operates slower than the high-speed mode but uses power gating to reduce power consumption, is selected.

[0096] FIG. 16 shows an example of changes in various signals when the nonvolatile flip-flop acquires data from the combinational circuit, when the shutdown avoidance signal is inactive and active. FIG. 16(A) shows the case when the shutdown avoidance signal is inactive, and FIG. 16(B) shows the case when the shutdown avoidance signal is active. Note that FIG. 16 shows the case where the logic circuit unit S1 has the circuit configuration shown in FIG. 1. In this example, the pulse width of the CLK1 signal is set to the same as the rewrite request time Tq, and the pulse width of the CLK0 signal is Tp / N, which is shorter than the rewrite request time. Therefore, when the shutdown avoidance signal is inactive, the pulse width of the gated clock signal GCK11 is Tp, and data is nonvolatilely stored in the nonvolatile flip-flop. However, when the shutdown avoidance signal is active, the pulse width of the gated clock signal GCK11 is Tp / N, and data is not nonvolatilely stored in the nonvolatile flip-flop. The timing of relative changes of the enable signals EN11, EN12, gated clock signal GCK11, etc. with respect to the CLK signal is the same whether inactive or active.

[0097] In the example of Fig. 15, the circuit configuration of the logic circuit unit S1 is not limited, and for example, as shown in Fig. 17, the circuit configuration of the logic circuit unit S1 can be the same as that of the example of Fig. 11. As shown in Fig. 18, if the logic circuit unit S1 contains a circuit group S1a that includes a non-volatile flip-flop as described above and switches between the CLK0 signal and the CLK1 signal, and a circuit group S1b that always operates at high speed using only the CLK0 signal, one of the CLK0 signal and the CLK1 signal selected by the selector S2c can be supplied to the circuit group S1a as the CLK signal, and only the CLK0 signal from the oscillator S2a can be supplied to the circuit group S1b without being selected by the selector S2c.

[0098] FIG. 19 shows an example of power gating a non-volatile flip-flop (hereinafter sometimes referred to as a control-side non-volatile flip-flop) in a circuit that generates an enable signal for a non-volatile flip-flop (hereinafter sometimes referred to as a target-side non-volatile flip-flop).

[0099] In this example, the first sub-enable signal EN11a is generated in a circuit that does not include a non-volatile flip-flop, i.e., is not power-gated, and the second sub-enable signal EN11b is generated in a circuit that includes a control-side non-volatile flip-flop that is power-gated, so that the logical product of the first sub-enable signal EN11a and the second sub-enable signal EN11b corresponds to the enable signal EN11 for the non-volatile flip-flop NF11, which is the target-side non-volatile flip-flop shown in the example of Figure 1, etc., and a circuit or an equivalent circuit is provided that performs clock gating for the non-volatile flip-flop NF11 using each of these enable signals, and the first sub-enable signal EN11a is used as one of the power control signals for the control-side non-volatile flip-flop.

[0100] The logic circuit unit S1 is provided with an enable signal generation circuit 70 that generates an enable signal for the nonvolatile flip-flop NF11 serving as the target nonvolatile flip-flop. The enable signal generation circuit 70 is provided with a first generation circuit 71 that generates a first sub-enable signal EN11a and a second generation circuit 72 that generates a second sub-enable signal EN11b.

[0101] The first generation circuit 71 is configured as a circuit that does not include a nonvolatile flip-flop, i.e., a circuit that is not power-gated. On the other hand, the second generation circuit 72 is configured as a circuit that includes a nonvolatile flip-flop NF73 as a control-side nonvolatile flip-flop that is power-gated. In other words, the enable signal generation circuit 70 is configured so that the circuit is divided into the first generation circuit 71 that is not power-gated and the second generation circuit 72 that includes a control-side nonvolatile flip-flop that is power-gated.

[0102] In the illustrated example, the second generation circuit 72 includes a combinational circuit 74 connected to the input side of the non-volatile flip-flop NF73 and a combinational circuit 75 connected to the output side. The output signal of the combinational circuit 75 corresponding to the data output from the non-volatile flip-flop NF73 is the second sub-enable signal EN11b. Whether the second sub-enable signal EN11b is active or inactive depends on the input of the combinational circuit 75, i.e., the output of the non-volatile flip-flop NF73. When the power supply to the non-volatile flip-flop NF73 is cut off, the output of the non-volatile flip-flop NF73 becomes an undefined value, and the second sub-enable signal EN11b also becomes an undefined value. For example, the second sub-enable signal EN11b is active when it is at an H level and inactive when it is at an L level. Note that the combinational circuit 75 may be configured so that when the power supply to the non-volatile flip-flop NF73 is cut off, its output, the second sub-enable signal EN11b, becomes active or inactive.

[0103] The second generation circuit 72 is provided with a clock gating circuit 76 and a power gating circuit 77 corresponding to the non-volatile flip-flop NF73. An enable signal EN73 from another circuit is input to the clock gating circuit 76 together with the CLK signal, and clock gating is performed on the non-volatile flip-flop NF73.

[0104] Like the above-described power gating circuits, the power gating circuit 77 turns on and off the transistor Tr77 based on a power control signal (power control signal for enable signal) input to the NOR gate P77, thereby controlling the supply and cut-off of power to the non-volatile flip-flop NF73. The NOR gate P77 receives the enable signal EN73 as a power control signal, the gated clock signal GCK73 from the clock gating circuit 76 as an auxiliary signal, and the first sub-enable signal EN11a as a power control signal.

[0105] To perform clock gating using the first sub-enable signal EN11a, the first sub-enable signal EN11a is input as an enable signal to the clock gating circuit 15 of the non-volatile flip-flop NF11. Also, the first sub-enable signal EN11a, an enable signal EN12 for the next-stage flip-flop, and a gated clock signal GCK11 from the clock gating circuit 15 are input to the NOR gate P17 of the power gating circuit 17.

[0106] A multiplexer 78 is provided as a selector to realize a logic function equivalent to clock gating using the second sub-enable signal EN11b. The multiplexer 78 has one input terminal connected to the combinational circuit 13 and the other input terminal connected to the Q output terminal of the non-volatile flip-flop NF11. The multiplexer 78 also receives the second sub-enable signal EN11b as a selection control signal. When the second sub-enable signal EN11b is active, the multiplexer 78 selects and outputs data (new data) from the combinational circuit 13, and when the second sub-enable signal EN11b is inactive, the multiplexer 78 selects and outputs data from the Q output terminal of the non-volatile flip-flop NF11. As a result, when the second sub-enable signal EN11b is inactive, a feedback loop is formed to retain the data held by the non-volatile flip-flop NF11 as is, and data from the combinational circuit 13 is input to the non-volatile flip-flop NF11 only when the second sub-enable signal EN11b is active, resulting in a circuit configuration in which clock gating is performed using the second sub-enable signal EN11b.

[0107] In this example, the second sub-enable signal EN11b is active when it is a logical value (signal level) that the multiplexer 78 selects data from the combinational circuit 13 and inputs to the non-volatile flip-flop NF11, as described above, and is inactive when it is a logical value (signal level) that forms a feedback loop. Therefore, the second sub-enable signal EN11b can also be configured so that the relationship between active / inactive and H level / L level is reversed from that described above.

[0108] With the above configuration, when the first sub-enable signal EN11a and the second sub-enable signal EN11b become active, power is supplied and a clock pulse of the gated clock signal GCK11 is input to the non-volatile flip-flop NF11 to which data is input from the combinational circuit 13. Therefore, the data from the combinational circuit 13 is acquired by the non-volatile flip-flop NF11.

[0109] Furthermore, when the first sub-enable signal EN11a becomes active while the second sub-enable signal EN11b is inactive, a clock pulse of the gated clock signal GCK11 is input to the non-volatile flip-flop NF11, which is powered by the active first sub-enable signal EN11a, and the non-volatile flip-flop NF11 acquires the data being input. However, since the data held by the non-volatile flip-flop NF11 itself is input via the multiplexer 78, the data held by the non-volatile flip-flop NF11 is ultimately maintained. Therefore, a logical function equivalent to clock gating is realized.

[0110] When the first sub-enable signal EN11a is inactive, the clock pulse of the gated clock signal GCK11 is not output from the clock gating circuit 15 regardless of whether the second sub-enable signal EN11b is active or inactive, so even if power is being supplied, the non-volatile flip-flop NF11 does not acquire new data and the data it holds is maintained.

[0111] As described above, when both the first sub-enable signal EN11a and the second sub-enable signal EN11b are active, the same result as in the configuration in which clock gating is performed with an enable signal that is active is obtained.

[0112] Whether the second sub-enable signal EN11b is active or inactive is determined by the data held in the non-volatile flip-flop NF73. However, since the non-volatile flip-flop NF73 is power-controlled, when the power supply to it is cut off, a normal second sub-enable signal EN11b cannot be obtained.

[0113] However, in the enable signal generation circuit 70 configured as described above, the first sub-enable signal EN11a is input to the NOR gate P77 as a power supply control signal, so that when at least the first sub-enable signal EN11a becomes active, power is supplied to the non-volatile flip-flop NF73, and the second sub-enable signal EN11b is normally generated and output by the combinational circuit 75 in accordance with the data held by the non-volatile flip-flop NF73. Then, under the active first sub-enable signal EN11a, the acquisition of data from the non-volatile flip-flop NF11 is controlled as described above in accordance with the active / inactive state of the second sub-enable signal EN11b.

[0114] On the other hand, when the first sub-enable signal EN11a is inactive, whether power is supplied to the non-volatile flip-flop NF73, i.e., whether the second sub-enable signal EN11b is generated normally, depends on the power control signals other than the first sub-enable signal EN11a input to the NOR gate P77. However, when the first sub-enable signal EN11a is inactive, as described above, the clock pulse of the gated clock signal GCK11 is not input to the non-volatile flip-flop NF11. Therefore, even if the second sub-enable signal EN11b is not generated normally, i.e., regardless of whether the second sub-enable signal EN11b is active or inactive, the non-volatile flip-flop NF11 does not acquire and hold the input data, and this does not pose a problem.

[0115] If the power gating of the control-side nonvolatile flip-flop is configured to be performed using an enable signal that becomes active when both the first sub-enable signal EN11a and the second sub-enable signal EN11b are active as one of the power control signals, the power control of the control-side nonvolatile flip-flop itself will be involved, and the enable signal will not be generated correctly. However, with the above configuration, it is possible to easily perform power gating of the nonvolatile flip-flop NF73 in the enable signal generation circuit 70 in relation to the operation of the nonvolatile flip-flop NF11.

[0116] The configuration of this example can be used in the circuit configurations of the above examples.

[0117] In each of the above examples, the next-stage acquisition circuit is a flip-flop, but any circuit other than a flip-flop, such as a latch, memory, or other circuit, may be used as long as data acquisition is controlled by an enable signal. Also, the enable signal for the acquisition circuit does not have to control the CLK signal.

[0118] [Second embodiment] The second embodiment is an example of a circuit device that performs convolution operations used in a convolutional neural network and pooling processing on the results of the convolution operations. Note that components that are essentially the same as those in the first embodiment are given the same reference numerals, and detailed descriptions thereof will be omitted.

[0119] 20, a circuit device 80 performs convolutional calculation processing and pooling processing using a convolution filter on a channel (also called a feature plane) based on a convolutional neural network. The circuit device 80 includes a calculation unit 81, a memory unit 82, and a control unit 83.

[0120] The arithmetic unit 81 has k (k is an integer equal to or greater than 2) arithmetic units 85 arranged in parallel, each performing a convolution operation using a convolution filter and a pooling operation. The memory unit 82 stores weight data for the convolution filter and element data (also referred to as pixels) for each channel of the hierarchical layer to which the convolution operation is applied, and also stores convolution operation result data and pooling data, i.e., element data for each channel of the hierarchical layer generated by the convolution operation and pooling operation. For hierarchical layers to be pooled, the element data obtained by the convolution operation is handed over to the pooling process within the arithmetic unit 85 and is not written to the memory unit 82. The control unit 83 controls the arithmetic units 85 and the memory unit 82.

[0121] The convolutional neural network on which the circuit device 80 is based has multiple layers connected together. Each layer has one or more channels. The first layer is an input layer, which is, for example, an image composed of each channel of RGB.

[0122] 21 shows an example of a convolutional neural network in which first to fourth layers are connected. The first layer has three channels ch1-1 to ch1-3, the second layer has four channels ch2-1 to ch2-4, the third layer has three channels ch3-1 to ch3-3, and the fourth layer has three channels ch4-1 to ch4-3.

[0123] For example, of the first to fourth layers, the first and second layers are layers that are subject to convolution processing, which generates second layer channels ch2-1 to ch2-4 from first layer channels ch1-1 to ch1-3 and third layer channels ch3-1 to ch3-3 from second layer channels ch2-1 to ch2-4. The third layer is a layer that is subject to pooling processing, which generates fourth layer channels ch4-1 to ch4-3 from third layer channels ch3-1 to ch3-3.

[0124] The number of layers and the layers to be subjected to the convolution operation are arbitrary. Generally, the pooling process is repeated after one or more convolution operations. In addition, a layer generated by the pooling process may be further pooled. Each layer may have one or more channels. In addition, in the convolution operation, the number of channels may increase or decrease between the previous and next layers, or the number of channels may remain unchanged. In the pooling process, the number of channels in the previous and next layers is usually the same.

[0125] As described above, in a convolutional neural network, the (n+1)th layer is generated by performing convolutional calculations or pooling on channels in the nth layer, where n is an integer greater than or equal to 1. Generating a layer means generating each channel that makes up the layer, and generating a channel means calculating each element data that makes up the channel. In the following description, the nth layer may be referred to as the previous layer relative to the (n+1)th layer, and the (n+1)th layer may be referred to as the next layer relative to the nth layer. Therefore, channels in the next layer are generated by performing convolutional calculations or pooling on channels in the previous layer.

[0126] A channel is composed of a plurality of element data arranged two-dimensionally. The array of element data is a data structural arrangement, meaning that the position of each element data is specified in a plurality of variables (two variables, row and column, in this explanation), and that position information is assigned so that the positional relationship between the element data is specified. The same applies to the load data described later. The size of each channel, i.e., the number of element data in the row and column directions, is arbitrary and is not particularly limited. Note that in this example, a two-dimensional channel will be explained, but it may also be a one-dimensional or three- or more-dimensional channel.

[0127] In the convolution operation process, the convolution operation result data (element data) is calculated by a convolution operation. The convolution operation result data is the value obtained by adding the results of applying a convolution filter to each element data in the convolution area for each channel of the previous layer, for each convolution area at the same position in each channel. Applying a convolution filter is to find the result of a product-sum operation of the element data in the convolution area and the weight data of the convolution filter.

[0128] A convolution filter is an arrangement of weight data that serves as weights for element data. In this example, one convolution filter is made up of weight data that is two-dimensionally arranged in a 3x3 (3 rows and 3 columns) array. Each weight data of a convolution filter is set to a value that corresponds to the purpose of the convolution filter.

[0129] The convolution region defines the range on the channel to which the convolution filter is applied, and has the same array size as the convolution filter (3 rows and 3 columns in this example). In the convolution operation, the weight data of the convolution filter and the element data of the convolution region are multiplied at corresponding positions. In the convolution operation process, the convolution region is moved so as to scan the entire area of ​​the channel, moving the region position by one element data at a time, and a convolution operation is performed each time the convolution region is moved.

[0130] For example, for each channel in the next layer, a convolution operation is performed using all channels in the previous layer, and a convolution operation is performed using a convolution filter corresponding to a combination of a channel in the previous layer and a channel in the next layer.

[0131] In the example shown in Fig. 21, when generating channel ch3-1 in the third layer, for example, a convolution filter is applied to channel ch2-1 using a convolution filter associated with the combination of channel ch2-1 and channel ch3-1, and a convolution filter is applied to channel ch2-2 using a convolution filter associated with the combination of channel ch2-2 and channel ch3-1. In this way, when generating channel ch3-1, convolution calculations are performed using four convolution filters corresponding to the four combinations of channel ch3-1 and channels ch2-1 to ch2-4. Similarly, when generating channel ch3-2, convolution calculations are performed using four convolution filters corresponding to the four combinations of channel ch3-2 and channels ch2-1 to ch2-4, and when generating channel ch3-3, convolution calculations are performed using four convolution filters corresponding to the four combinations of channel ch3-3 and channels ch2-1 to ch2-4.

[0132] In the convolution calculation process, any number of channels in the previous layer can be used to generate one channel in the next layer, and one channel in the previous layer can be used to generate one channel in the next layer. Also, all or some of the multiple convolution filters used in one layer may have a common weight array. Furthermore, when the weight array of the convolution filters is common, one convolution filter with the common weight array may be prepared and used to calculate multiple channels.

[0133] The convolution region Ra in the example shown in FIG. 22 has three rows and three columns. When calculating the convolution operation result data of channel ChB of the layer (next layer, the third layer in the example of FIG. 21) to be subjected to pooling processing, the calculation unit 81 sequentially moves the convolution region Ra of channel ChA of the previous layer to the position shown in FIG. 22(A), a position shifted by one data element in the row direction from the position shown in FIG. 22(A) as shown in FIG. 22(B), a position shifted by one data element in the column direction from the position shown in FIG. 22(A) as shown in FIG. 22(C), and a position shifted by one data element in the row direction from the position shown in FIG. 22(C) as shown in FIG. 22(D). In this way, the convolution operation result data in one pooling region Rb of channel ChB of the next layer is continuously calculated. Note that, as long as the convolution operation result data in one pooling region Rb is continuously calculated, the order in which the convolution region Ra is shifted is not limited to the above order.

[0134] As an example, the pooling process generates channels in the next layer by reducing the row and column sizes of each channel in the previous layer. The calculation unit 81 performs maximum value pooling, extracting the maximum value from a 2-row, 2-column pooling area. To achieve this, each channel is divided into multiple 2-row, 2-column pooling areas that do not overlap with each other, and the element data of the maximum value within each of these pooling areas is output as the pooling process result. Note that the size of the pooling area is not limited to 2 rows and 2 columns. One of p and q may be an integer greater than or equal to 1, and the other may be an integer greater than or equal to 2, resulting in a pooling area of ​​p rows and q columns. The pooling areas can also be divided so that they partially overlap with each other. In this case, the pooling process can be performed to generate channels in the next layer that have the same row and column sizes as the channels in the previous layer.

[0135] 23, the arithmetic unit 85 includes a convolution operation unit 86, a pooling processing unit 87, a clock gating circuit 88 as a first clock gating circuit, and a power gating circuit 89. The arithmetic unit 85 also includes an activation function processing unit that converts the convolution operation result data output from the convolution operation unit 86 using an activation function, a bit number adjustment circuit that converts the data length to a predetermined data length, and the like (all of which are not shown).

[0136] The convolution calculation unit 86 calculates one piece of convolution calculation result data by one convolution calculation. When calculating one piece of convolution calculation result data, the convolution calculation unit 86 sequentially switches between the channels of the previous layer, and receives as input nine pieces of element data in the convolution region and nine pieces of weight data of the convolution filter for each channel of the previous layer. Therefore, the time required for the convolution calculation unit 86 to calculate one piece of convolution calculation result data varies depending on the number of channels of the previous layer. The convolution calculation result data calculated by the convolution calculation unit 86 is sent to the memory unit 82 and pooling processing unit 87 as element data of the next layer.

[0137] The convolution operation unit 86 is composed of, for example, the same number of multipliers as the weight data of the convolution filter (9 in this example), a selector that selects and outputs one of the multiplication results from each multiplier, an adder that adds the multiplication result output from the selector to the data held in a register, and a register that holds the addition result of the adder.Each multiplier receives element data and weight data as input and outputs the multiplication result obtained by multiplying them.The element data of each channel of the previous hierarchical level and the weight data of the convolution filter are input sequentially to the convolution operation unit 86 as described above, and the addition result held in the register is finally output as convolution operation result data (element data).

[0138] The convolution operation unit 86 outputs an enable signal ENc as a first enable signal. The enable signal ENc is inactive (L level) while the convolution operation unit 86 is performing a convolution operation, and becomes active (H level) when the convolution operation result data is held in a register and output. The timing at which the enable signal ENc becomes active relative to the CLK signal is the same as that of the enable signal EN11 (see FIG. 1) in the first embodiment. The enable signal ENc is used for clock gating and power gating.

[0139] The pooling processing unit 87 performs the pooling process described above and outputs pooled data (element data) that is the maximum value in the pooling area. The pooling processing unit 87 has a comparator 91, a multiplexer 92, and a register 93. The comparator 91 receives the convolution operation result data from the convolution operation unit 86 and the data (retained data) held in the register 93. The comparator 91 compares the two input data and outputs a selection signal to the multiplexer 92 to select the data with the larger value. The multiplexer 92 functions as a selector and selects and outputs one of the two input data based on the selection signal.

[0140] The register 93 is a storage register composed of a plurality of nonvolatile flip-flops NF93a, and holds the convolution operation result data output from the multiplexer 92. That is, a nonvolatile flip-flop NF93a is provided corresponding to each bit of the convolution operation result data, and each nonvolatile flip-flop NF93a holds a corresponding bit of the convolution operation result data. The nonvolatile flip-flop NF93a has a configuration similar to that of the nonvolatile flip-flop in the first embodiment. Therefore, the register 93 is configured as a nonvolatile register that can store the convolution operation result data in a nonvolatile manner and output the stored data when power is cut off by resuming the power supply. The register 93 is reset each time the output of the maximum value of the pooling region is completed, and the data is set to an initial value (e.g., the smallest value).

[0141] By continuously and sequentially inputting each convolution calculation result data of the pooling area calculated by the convolution calculation unit 86 to the pooling processing unit 87 configured as described above, the convolution calculation result data that is finally the maximum value in the pooling area is held in the register 93, and the held element data is output as pooling data for one pooling area.

[0142] A clock gating circuit 88 and a power gating circuit 89 are provided for the register 93. The clock gating circuit 88 receives the CLK signal and the enable signal ENc. This clock gating circuit 88 has a configuration similar to that of the clock gating circuit 15 of the first embodiment (see FIG. 1), and outputs a gated clock signal GCKp as a first gated clock signal obtained by clock-gating the CLK signal using the enable signal ENc. The gated clock signal GCKp is input to the CLK terminal of each non-volatile flip-flop NF93a. That is, the enable signal from the convolution operation unit 86 controls whether the clock signal for the register 93 is enabled or disabled in synchronization with the output of the convolution operation result data.

[0143] The power gating circuit 89 is similar to the power gating circuit 17 (see FIG. 1) of the first embodiment, and controls the power supply to each nonvolatile flip-flop NF93a by turning on and off the transistor Tr89 using a NOR gate P89. An enable signal ENc, an enable signal ENm1 (described later), a gated clock signal GCKp, and a cutoff avoidance signal are input to the NOR gate P89 as power supply control signals. In this example, the gated clock signal GCKp is an auxiliary signal. The enable signal ENm1 and the cutoff avoidance signal are output from the control unit 83.

[0144] The memory unit 82, which serves as an acquisition circuit, includes a register 82a that acquires and temporarily stores element data to be stored in the memory unit 82, and a clock gating circuit 82b that serves as a second clock gating circuit that performs clock gating on the register 82a. The register 82a is a storage register composed of multiple flip-flops. In this example, each nonvolatile flip-flop NF93a of the register 93 is a first flip-flop, and each flip-flop of the register 82a is a second flip-flop.

[0145] The clock gating circuit 82b has a configuration similar to that of the clock gating circuit 15, and receives as input the CLK signal and enable signals ENm1 and ENm2 for the memory unit 82. The enable signal ENm1 as a second enable signal is an enable signal for the memory unit 82 when pooling data is stored in the memory unit 82, and the enable signal ENm2 is an enable signal for the memory unit 82 when convolution operation result data is stored in the memory unit 82.

[0146] The register 82a receives the clock pulses of the gated clock signal GCKm generated from the CLK signal and the enable signal ENm1 or ENm2, thereby acquiring the convolution operation result data from the convolution operation unit 86 or the pooling data from the register 93. The convolution operation result data or the pooling data acquired by the register 82a is written to a memory array (not shown) of the memory unit 82.

[0147] The control unit 83 has a clock circuit S2, an interruption avoidance circuit 61, and an arithmetic control unit 94. The interruption avoidance circuit 61 outputs an interruption avoidance signal under the control of the arithmetic control unit 94, which functions as a mode control unit. When performing pooling processing, the arithmetic control unit 94 controls to select an interruption avoidance mode or an interruption avoidance mode depending on the interval (time) at which convolution calculation result data is output, which is determined depending on the number of channels in the hierarchy, and switches the interruption avoidance signal between active and inactive. Specifically, when the output interval of the convolution calculation result data is equal to or longer than a predetermined threshold time, the interruption tolerance mode is selected and the interruption avoidance signal is made inactive, and when it is shorter than the predetermined threshold time, the interruption avoidance mode is selected and the interruption avoidance signal is made active. Note that when convolution calculation processing is performed without pooling processing, the interruption avoidance signal is made inactive.

[0148] This prevents frequent power cutoffs so that the increase in power consumption due to power cutoff is less than the decrease in static power consumption in the non-volatile flip-flop NF93a caused by power cutoff. In this circuit device 80, a convolution operation is performed in channel parallel, as described below, and the interval at which the convolution operation result data is output is determined by the hierarchical level that is the target of the pooling process, so that the interval can be known in advance.

[0149] In the channel-parallel convolution operation, the interval at which the convolution operation result data is output becomes longer as the number of channels in the layer that is the target of the pooling process increases. Therefore, the cutoff avoidance signal can be controlled to be inactive according to the number of channels in the layer that is the target of the pooling process, that is, when the number of channels is equal to or greater than a predetermined threshold, and to be active when the number is less than the predetermined threshold.

[0150] The clock circuit S2 operates the arithmetic section including the arithmetic unit 85 at high speed by outputting the CLK0 signal having a relatively high frequency as the CLK signal when the shutdown avoidance signal is active, and outputs the CLK1 signal having a relatively low frequency as the CLK signal when the shutdown avoidance signal is inactive, thereby enabling power gating in the register 93. The arithmetic control section 94 controls the shutdown avoidance circuit 61 as described above, and outputs enable signals ENm1 and ENm2.

[0151] Using the above configuration, an example will be described in which channel-parallel convolution processing is performed on the nth layer to generate the (n+1)th layer, and pooling processing is performed on the (n+1)th layer. As shown in Figures 24 and 25, the nth layer is composed of channels ChA1, ChA2, ..., and channels ChB1, ChB2, ... of the (n+1)th layer are generated from this nth layer.

[0152] First, each arithmetic unit 85 of the arithmetic section 81 performs an operation to apply a convolution filter to the convolution region Ra of the first channel ChA1 on the nth layer. Nine element data of the convolution region Ra of channel ChA1 are read from the memory section 82 and input to the convolution operation section 86 of each arithmetic unit 85. Furthermore, nine weight data of one convolution filter are input to one convolution operation section 86, and weight data of convolution filters FA1B1, FA1B2, ... corresponding to the first channel ChA1 and the first to kth channels ChB1, ChB2, ... on the next layer are read from the memory section 82 and input to the convolution operation section 86 of each arithmetic unit 85, respectively. As a result, each convolution calculation unit 86 multiplies the element data of the convolution area Ra of channel ChA1 input thereto by the corresponding data and the weight data of the convolution filter, and stores the sum of the multiplication results, which are the sums of the multiplication results, in the registers (Figure 24(A)).

[0153] Next, each arithmetic unit 85 performs a calculation to apply a convolution filter to convolution region Ra in the second channel ChA2 on the nth layer, which is at the same position as the first channel ChA1. Nine element data of convolution region Ra in channel ChA2 are input to the convolution calculation unit 86 of each arithmetic unit 85, and weight data of convolution filters FA2B1, FA2B2, ... corresponding to the second channel ChA2 and the first to kth channels ChB1, ChB2, ... on the next layer are input to each arithmetic unit 85.

[0154] Each arithmetic unit 85 corresponds to one channel in the next hierarchy, and the corresponding channel in the next hierarchy does not change, until calculation of all element data of, for example, k channels is completed. For this reason, for example, to a arithmetic unit 85 to which weight data of a convolution filter FA1B1 corresponding to a second channel ChB1 is input during calculation of the first channel ChA1 in the previous hierarchy, weight data of a convolution filter FA2B2 corresponding to a second channel ChB2 is also input during calculation of the second channel ChA2.

[0155] As described above, the element data and weight data are input to each calculation unit 85, and a value obtained by adding the product-sum result obtained by applying a convolution filter to the convolution region Ra of channel ChA2 to the product-sum result obtained by applying a convolution filter to the convolution region Ra of channel ChA1 is stored in the register of each convolution calculation unit 86 (FIG. 24(B)).

[0156] Similarly, the convolution calculation unit 86 of each calculation unit 85 sequentially performs calculations to apply a convolution filter to the convolution area Ra at the same position as the first channel ChA1 for each channel from the third channel onwards on the nth layer. When the calculation to apply the convolution filter to the convolution area Ra of the final channel on the nth layer is completed, the register of each convolution calculation unit 86 stores the sum of the product-sum results obtained by applying the convolution filter to the convolution area Ra of each channel on the previous layer, i.e., the first convolution calculation result data for each of the first to kth channels on the next layer. The first convolution calculation result data (element data) obtained in this way is output from the convolution calculation unit 86.

[0157] After calculating the first convolution calculation result data as described above, the convolution calculation unit 86 of each calculation unit 85 shifts the convolution region Ra by one element data unit in the row direction, as shown in Figure 25(A), and performs a calculation to apply convolution filters FA1B1, FA1B2, ... to the convolution region Ra of the first channel ChA1 on the previous layer using the same procedure as described above. Thereafter, using the same procedure, the convolution calculation unit 86 performs a calculation to apply convolution filters FA2B1, FA2B2, ... to the convolution region Ra of the second channel ChA2 on the previous layer, as shown in Figure 25(B). Thereafter, similarly, a calculation to apply a convolution filter to the convolution region Ra for each of the third and subsequent channels on the previous layer is performed in sequence, and second convolution calculation result data is calculated for each of the first to k-th channels and output from the convolution calculation unit 86.

[0158] After calculating the second convolution operation result data, the convolution region Ra is shifted by one data element in the column direction from the initial position, and the third convolution operation result data is calculated and output by the convolution operation unit 86 using the same procedure as above. After calculating the third convolution operation result data, the convolution region Ra is shifted by one data element in the row direction, and the fourth convolution operation result data is calculated and output by the convolution operation unit 86 using the same procedure as above. In this way, four convolution operation result data of the first pooling region that is the target of pooling processing are successively calculated.

[0159] After outputting the four convolution operation result data of the first pooling area as described above, the convolution area Ra is further moved, and the four convolution operation result data of the second pooling area are calculated sequentially in the same manner as described above. The convolution operation result data of the third and subsequent pooling areas are also calculated in the same manner.

[0160] When performing convolution calculations in channel parallel as described above, one convolution calculation unit 86 outputs one piece of convolution calculation result data by sequentially performing convolution calculations on each channel in the nth layer that is the target of the convolution calculation and adding up the results of the convolution calculations. Therefore, the number of convolution calculations performed by the convolution calculation unit 86 varies depending on the number of channels in the nth layer, and the interval at which one piece of convolution calculation result data is output increases or decreases, and the interval becomes longer as the number of channels increases.

[0161] When the output interval of the convolution operation result data in the nth layer that is the target of the convolution operation process is equal to or longer than a predetermined threshold time, for example, the shutdown avoidance signal becomes inactive. Because the shutdown avoidance signal is inactive, in the pooling processing unit 87, during the period when the convolution operation unit 86 is performing the convolution operation, the enable signal ENm1, enable signal ENc, and gated clock signal GCKp are inactive, and therefore the power supply to each non-volatile flip-flop NF93a of the register 93 is cut off. Also, because the shutdown avoidance signal is inactive, the CLK1 signal, which has a relatively low frequency, is output as the CLK signal from the clock circuit S2.

[0162] In response to the first convolution operation result data of the first pooling area being output from the convolution operation unit 86, the enable signal ENc becomes active. This causes power to be supplied to each nonvolatile flip-flop NF93a of the register 93. When power supply is started in this manner, in each nonvolatile flip-flop NF93a, when the gated clock signal GCKp is at L level until the next time the CLK signal rises and goes to H level, the data written in the nonvolatile memory circuit is restored to the basic circuit and held therein. The held data is then output from each nonvolatile flip-flop NF93a. This causes the register 93 to output the data that was nonvolatilely written before the power was shut off.

[0163] As a result, the comparator 91 and the multiplexer 92 are respectively input with the data from the register 93 and the convolution operation result data from the convolution operation unit 86. The register 93 is reset when the convolution operation process is started and stores the initial value in a non-volatile manner, so that the convolution operation result data is selected by the multiplexer 92 based on the comparison result of the comparator 91, and the convolution operation result data is input to the register 93. Note that after the enable signal ENc becomes active and before the CLK signal rises, the convolution operation result data selected by the multiplexer 92 is input to the register 93.

[0164] In synchronization with the subsequent clock pulse of the CLK signal, a clock pulse of the gated clock signal GCKp is input from the clock gating circuit 88 to each non-volatile flip-flop NF93a of the register 93. The CLK signal is the CLK1 signal with a relatively low frequency, and its pulse width is the same as the rewrite request time. Therefore, in each non-volatile flip-flop NF93a, the data of the corresponding bit of the convolution operation result data input from the multiplexer 92 is written to the non-volatile memory circuit. At this time, since the gated clock signal GCKp is input to the NOR gate P89 as an auxiliary signal, even if the enable signal ENc becomes inactive during writing to the non-volatile memory circuit, the writing is completed normally. After the writing in each non-volatile flip-flop NF93a is completed, the gated clock signal GCKp as an auxiliary signal becomes inactive (L level).

[0165] When the gated clock signal GCKp becomes inactive as described above, the enable signals ENc, ENm1 and cutoff avoidance signal are inactive, so that the power supply to each nonvolatile flip-flop NF93a is cut off.

[0166] While the convolution operation for calculating the second convolution operation result data of the first pooling area is being performed in the convolution operation unit 86 and the pooling processing unit 87 is waiting for the input of the second convolution operation result data, the enable signals ENc, ENm1, the gated clock signal GCKp, and the cutoff avoidance signal are all maintained inactive, and therefore the power supply to each non-volatile flip-flop NF93a is maintained in a cutoff state.

[0167] In response to the second convolution operation result data being output from the convolution operation unit 86, the enable signal ENc becomes active, and power supply to each non-volatile flip-flop NF93a of the register 93 begins. When the power supply is resumed, the register 93 restores the data held before the power was cut off, as in the case described above, and outputs that data. Therefore, the first convolution operation result data from the register 93 and the second convolution operation result data from the convolution operation unit 86 are input to the comparator 91 and the multiplexer 92.

[0168] Comparator 91 compares the first convolution operation result data with the second convolution operation result data, and the convolution operation result data having the larger value among the convolution operation result data is selected by multiplexer 92, and the selected convolution operation result data is input to register 93. As in the case of writing the first convolution operation result data, clock pulses of gated clock signal GCKp are then input to each non-volatile flip-flop NF93a, causing the data of each bit of the convolution operation result data input from multiplexer 92 to be written to the non-volatile memory circuit of each non-volatile flip-flop NF93a. Then, gated clock signal GCKp becomes inactive, and power supply to each non-volatile flip-flop NF93a of register 93 is cut off.

[0169] Similarly, each time the third and fourth convolution operation result data are output, power supply to each nonvolatile flip-flop NF93a is resumed, and the convolution operation result data output from the register 93 is compared with the convolution operation result data output from the convolution operation unit 86. Then, after each bit of the convolution operation result data with a larger value is written to the nonvolatile memory circuit of each nonvolatile flip-flop NF93a, power supply to each nonvolatile flip-flop NF93a is cut off. In this way, the operation result data with the maximum value for the first pooling area is written nonvolatilely to the register 93.

[0170] After the maximum value of the calculation result data is written to the register 93 and power supply is cut off, an enable signal ENm1 that enables the register 82a of the memory unit 82 is activated. When the enable signal ENm1 becomes active, power supply to each non-volatile flip-flop NF93a begins, and the maximum value of the convolution calculation result data for the first pooling area is output from the register 93. In other words, pooled data is output from the register 93. After this, when a clock pulse of the gated clock signal GCKm is input, the register 82a of the memory unit 82 obtains the pooled data from the register 93, and this pooled data is stored in the memory unit 82 as one element data of one channel in the (n+2)th layer. When the enable signal ENm1 becomes inactive, power supply to each non-volatile flip-flop NF93a is cut off.

[0171] For the second and subsequent pooling areas, the same procedure is followed to obtain pooling data while power-gating each non-volatile flip-flop NF93a of register 93, and all element data for each of the 1st to kth channels of the n+2th layer is obtained and written to memory unit 82.

[0172] If there are channels from the k+1th onwards in the n+2th layer, the same procedure as above is repeated to calculate all element data for each of all channels.

[0173] When only the convolution operation is being performed, or when the convolution operation is accompanied by the pooling operation as described above and the output interval of the convolution operation result data is shorter than a predetermined threshold time, the operation control unit 94 activates the shutdown avoidance signal. In this case, while the convolution operation and the pooling operation are being performed, the transistor Tr89 is always on, and power continues to be supplied to each non-volatile flip-flop NF93a of the register 93. Furthermore, because the shutdown avoidance signal is active, the clock circuit S2 outputs the CLK0 signal, which has a relatively high frequency, as the CLK signal.

[0174] Therefore, the pooling processing unit 87 performs the same operation as when the interruption avoidance signal is inactive, except that nonvolatile writing and restoring of each nonvolatile flip-flop NF93a is not performed in the register 93. That is, each time a clock pulse of the gated clock signal GCKp is input, the convolution operation result data from the convolution operation unit 86 is compared with the data held in the register 93, and the convolution operation result data with the larger value among the compared data is held in the register 93 and output. Then, when the operation result data with the maximum value for one pooling area is held in the register 93 and the held operation result data is output as pooled data, the pooled data output from the register 93 is acquired and stored in the memory unit 82 as one element data of one channel in the (n+2)th layer. At this time, each unit of the operation unit 85 operates at high speed using the high-frequency CLK0 signal as the CLK signal.

[0175] As described above, whether or not power to the pooling processing unit 87 needs to be cut off is controlled based on the interval at which the convolution operation result data is output, so that the power consumption of the nonvolatile flip-flop NF93a of the register 93 is reduced.

[0176] [Third embodiment] The third embodiment is an example of a logic circuit design support device that supports the design of a semiconductor circuit device including a nonvolatile flip-flop. Note that components, circuits, etc. that are substantially the same as those in the first embodiment are denoted by the same reference numerals, and detailed descriptions thereof will be omitted.

[0177] 26, logic circuit design assistance device 100 designates a non-volatile flip-flop and replaces the designated flip-flop with a non-volatile flip-flop, including a power gating circuit. Logic circuit design assistance device 100 includes logic circuit replacement unit 101, library 102, replacement target designation unit 105, and cutoff avoidance signal designation unit 106. Logic circuit design assistance device 100 functions as each unit of logic circuit design assistance device 100, for example, by installing a logic circuit design assistance program in a computer. Logic circuit design assistance device 100 can be part of a logic synthesis device.

[0178] A netlist 110 generated by logic synthesis is input to the logic circuit replacement unit 101. The netlist 110 describes hardware by connecting various logic gates, flip-flops, etc., i.e., it is code that describes hardware at the gate level. This netlist 110 is generated by logically synthesizing an HDL source that describes circuit operations abstracted at the register transfer level (RTL) in HDL (hardware description language).

[0179] The flip-flops described in the netlist 110 do not include non-volatile flip-flops. The logic circuit replacement unit 101 modifies the netlist 110, replacing the flip-flops specified by the replacement target specification unit 105 with non-volatile flip-flops together with the power gating circuits, and outputs a replacement netlist (hereinafter referred to as a replaced netlist) 111 in which the connections have been changed so that power gating is performed as in the first embodiment. Furthermore, when a shutdown avoidance signal is specified by the shutdown avoidance signal specification unit 106, the logic circuit replacement unit 101 connects the signal (signal line or circuit output) to the power gating circuit as a shutdown avoidance signal on the replaced netlist 111.

[0180] The library 102 stores cells such as nonvolatile flip-flops to which power gating circuits are added, and is referred to when the logic circuit replacement unit 101 performs replacement, as will be described later.

[0181] The replacement target designation unit 105 designates a replacement target flip-flop to be a non-volatile flip-flop among non-volatile flip-flops described in the netlist 110. Furthermore, the cutoff avoidance signal designation unit 106 designates a signal to be a cutoff avoidance signal. The designation methods used by the replacement target designation unit 105 and the cutoff avoidance signal designation unit 106 are not limited. For example, the logic circuit design assistance device 100 has a circuit display function that displays a circuit diagram shown in the netlist 110, and flip-flops and signal lines in the circuit diagram displayed thereby may be designated using operation members such as a mouse or a keyboard.

[0182] When modifying the netlist 110 to generate the replaced netlist 111, the logic circuit replacement unit 101 replaces the replacement-target flip-flop with a non-volatile flip-flop to which a power gating circuit consisting of a NOR gate and a transistor is added. The logic circuit replacement unit 101 also performs a modification to add connections so that an enable signal input to a clock gating circuit of the replacement-target flip-flop, a gated clock signal output from the clock gating circuit, and an enable signal for a flip-flop subsequent to the replacement-target flip-flop are input to the NOR gate as power supply control signals. If a signal is specified by the shutdown avoidance signal designation unit 106, the logic circuit replacement unit 101 also performs a modification to add connections so that the specified signal is input to the NOR gate as a shutdown avoidance signal. In this way, the logic circuit replacement unit 101 regularly modifies the netlist 110 to generate the replaced netlist 111.

[0183] 27 schematically shows an example of replacement of the netlist 110 with the replaced netlist 111 by the logic circuit replacement unit 101. In this example, the netlist 110 has a combinational circuit 114 connected to the input side of a flip-flop FF113 and a combinational circuit 115 connected to the output side, and a flip-flop FF116 connected to the flip-flop FF113 with the combinational circuit 115 in between. Clock gating circuits 117 and 118 are connected to the flip-flops FF113 and FF116. An enable signal EN113 and a CLK signal corresponding to the flip-flop FF113 are input to the clock gating circuit 117, and an enable signal EN116 and a CLK signal corresponding to the flip-flop FF116 are input to the clock gating circuit 118. Furthermore, a circuit 119 is provided for switching an output signal between active and inactive.

[0184] When the flip-flop FF113 is designated as the replacement target, the logic circuit replacement unit 101 replaces the designated flip-flop FF113 with a circuit cell 125 configured with a non-volatile flip-flop NF121 and a power gating circuit 122 consisting of a NOR gate P122 and a transistor Tr122. At this time, a modification is made to add a connection so that an enable signal EN113 serving as an enable signal for the non-volatile flip-flop NF121, an enable signal EN116 for the flip-flop FF116 in the next stage of the non-volatile flip-flop NF121, and a gated clock signal GCK113 output from the clock gating circuit 117 are input to the NOR gate P122 as power supply control signals. In addition, when the shutdown avoidance signal designation unit 106 designates an output signal of the circuit 119, a modification is made to add a connection so that the output signal is input to the NOR gate P122 as a shutdown avoidance signal.

[0185] 28, when the flip-flop FF113 to be replaced is replaced with the non-volatile flip-flop NF121 to which the power gating circuit 122 is added, an auxiliary signal generation circuit 51 may be added. In this case, the connections are modified so that the auxiliary signal of the auxiliary signal generation circuit 51 is input to the NOR gate P122 instead of the gated clock signal GCK113. The logic circuit replacement unit 101 also performs modifications to add connections so that the enable signal EN113 input to the clock gating circuit 117 is input to the NOR gate P122 and the auxiliary signal generation circuit 51, and the enable signal EN116 for the next-stage flip-flop FF116 is input to the NOR gate P122 and the CLK signal is input to the auxiliary signal generation circuit 51.

[0186] As described above, the replacement of the flip-flop FF113 with the non-volatile flip-flop NF121 including the power gating circuit 122 is regular, including the modification of the connection of the enable signal EN116 of the next-stage flip-flop FF116, and the replacement can be easily performed. [Explanation of symbols]

[0187] 10, 80 circuit device 13, 14, 54, 74, 75, 114, 115 Combinational circuits 15, 15A, 16, 56, 57, 76, 82b, 88, 117, 118 Clock gating circuit 17, 58, 59, 77, 89, 122 Power gating circuits 51 Auxiliary signal generation circuit 61 Circuit to avoid interruption 70 Enable signal generation circuit 71 1st generation circuit 72 Second generation circuit 78 Multiplexer 86 Convolution Calculation Unit 87 Pooling processing unit 93 Registers 100 Logic circuit design support device 101 Logic circuit replacement unit 102 Library 105 Replacement target specification part 106 Blockage avoidance signal designation section 114 Combinational Circuits 115 Combinational Circuits 122 Power Gating Circuit 125 circuit cells NF11, NF11A, NF121, NF53, NF55, NF73, NF93a non-volatile flip-flops

Claims

1. a first clock gating circuit that outputs a first gated clock signal obtained by controlling the clock signal in response to a first enable signal that controls whether the clock signal is enabled or disabled; a first non-volatile flip-flop that operates in response to clock pulses of the first gated clock signal; an acquisition circuit that receives data from the first flip-flop directly or via a combinational circuit, and whose enable / disable of data acquisition is controlled by a second enable signal, and acquires the input data in response to the second enable signal; a power gating circuit having a power switch provided on a power line to the first flip-flop, the first enable signal and the second enable signal being input as power control signals, and turning on the power switch to supply power to the first flip-flop when the first enable signal is a logical value that enables the clock signal or the second enable signal is a logical value that enables acquisition of data; A semiconductor circuit device comprising:

2. an auxiliary signal generating circuit that outputs an auxiliary signal that maintains a logic value that turns on the power switch during a period in which a clock pulse of the first gated clock signal is being output; The power gating circuit receives the first enable signal, the second enable signal, and the auxiliary signal as the power supply control signals, and turns on the power switch to supply power to the first flip-flop when the first enable signal is a logical value that enables the clock signal, the second enable signal is a logical value that enables data acquisition, or the auxiliary signal is a logical value that turns on the power switch.

2. The semiconductor circuit device according to claim 1.

3. 3. The semiconductor circuit device according to claim 2, wherein the auxiliary signal generating circuit is the first clock gating circuit, and inputs the first gated clock signal as the auxiliary signal to the power gating circuit.

4. a shutdown avoidance circuit for selecting one of a shutdown avoidance mode in which the power supply is not shut off and a shutdown allowance mode in which the power supply is allowed to be shut off, and outputting a shutdown avoidance signal of a logical value corresponding to the selected mode; The power gating circuit receives the shutdown avoidance signal as one of the power supply control signals, and maintains the power switch on during a period in which the shutdown avoidance signal has a logic value corresponding to the shutdown avoidance mode, and controls the power switch on and off in response to other power supply control signals when the shutdown avoidance signal has a logic value corresponding to the shutdown allowance mode.

4. The semiconductor circuit device according to claim 1, wherein:

5. The first flip-flop stores input data in a non-volatile manner when a clock pulse having a predetermined pulse width or more is input while power is being supplied, and outputs the non-volatilely stored data when power supply is resumed.

5. The semiconductor circuit device according to claim 1, wherein the first and second electrodes are electrically connected to each other.

6. a shutdown avoidance circuit that selects one of a shutdown avoidance mode in which the power supply is not shut off and a shutdown allowance mode in which the power supply is allowed to be shut off, and outputs a shutdown avoidance signal of a logical value corresponding to the selected mode; a clock circuit including: a clock generating unit that generates a first clock signal having a clock pulse with a predetermined pulse width or more, and a second clock signal having a frequency higher than that of the first clock signal and a pulse width smaller than the predetermined pulse width; and a selector that receives the first clock signal and the second clock signal, selects the first clock signal when the shutdown avoidance signal has a logical value corresponding to the shutdown allowable mode, and selects the second clock signal when the shutdown avoidance signal has a logical value corresponding to the shutdown avoidance mode, and outputs the selected clock signal as the clock signal; Equipped with the first flip-flop stores input data in a non-volatile manner in response to an input of a clock pulse having a pulse width equal to or greater than the predetermined pulse width while being powered on, and outputs the non-volatilely stored data when power supply is resumed; The power gating circuit receives the shutdown avoidance signal as one of the power supply control signals, and maintains the power switch on while the shutdown avoidance signal has a logical value corresponding to the shutdown avoidance mode, and controls the power switch on and off in response to other power supply control signals when the shutdown avoidance signal has a logical value corresponding to the shutdown allowance mode.

4. The semiconductor circuit device according to claim 1, wherein the first and second electrodes are electrically connected to each other.

7. a second clock gating circuit that controls the clock signal in response to the second enable signal and outputs a second gated clock signal; The acquisition circuit is a second flip-flop that operates in response to clock pulses of the second gated clock signal.

7. The semiconductor circuit device according to claim 1, wherein the first and second electrodes are electrically connected to each other.

8. a first clock gating circuit that outputs a first gated clock signal obtained by controlling the clock signal in response to a first enable signal that controls whether the clock signal is enabled or disabled; a convolution calculation unit that outputs convolution calculation result data each time it calculates convolution calculation result data that becomes element data of a channel of a next layer obtained by performing a convolution calculation on each convolution region of a plurality of channels of a previous layer so that element data in a pooling region of the channel of the next layer are continuously output in sequence; a register that holds data using a plurality of first nonvolatile flip-flops that operate as flip-flops in response to clock pulses of the first gated clock signal when power is supplied, and that nonvolatilely store input data when a clock pulse having a predetermined pulse width or more is input, and that output the nonvolatilely stored data when power is supplied again; a comparator that compares the convolution operation result data from the convolution operation unit with the held data held in the register; and a pooling selector that receives the convolution operation result data from the convolution operation unit and the held data, and selects data with a larger value from the input data based on a comparison result of the comparator, and causes the register to hold the data as new held data, and a pooling processing unit that, for each pooling area, outputs the held data held in the register as pooling data to an acquisition circuit that is controlled by a second enable signal to enable or disable data acquisition and that acquires the input data in response to the second enable signal; a shutdown avoidance circuit that selects one of a shutdown avoidance mode in which the power supply is not shut off and a shutdown allowance mode in which the power supply is allowed to be shut off, and outputs a shutdown avoidance signal of a logical value corresponding to the selected mode; a clock circuit including: a clock generating unit that generates a first clock signal having a clock pulse with a predetermined pulse width or more, and a second clock signal having a frequency higher than that of the first clock signal and a pulse width smaller than the predetermined pulse width; and a clock selector that receives the first clock signal and the second clock signal, selects the first clock signal when the shutdown avoidance signal has a logical value corresponding to the shutdown allowable mode, and selects the second clock signal when the shutdown avoidance signal has a logical value corresponding to the shutdown avoidance mode, and outputs the selected clock signal as the clock signal; a mode control unit that causes the shutdown avoidance circuit to select the shutdown tolerant mode when an output interval of the convolution operation result data from the convolution operation unit is equal to or greater than a predetermined threshold, and causes the shutdown avoidance circuit to select the shutdown avoidance mode when the output interval is shorter than the predetermined threshold; a power gating circuit having a power switch provided on a power line to the plurality of first flip-flops, the first enable signal, the second enable signal, and the shutdown avoidance signal being input as power control signals, the power switch being kept on during a period in which the shutdown avoidance signal has a logical value corresponding to the shutdown avoidance mode, and when the shutdown avoidance signal has a logical value corresponding to the shutdown tolerant mode, controlling the power switch to be on or off in accordance with the other power control signals, and turning on the power switch to supply power to the first flip-flops when the first enable signal has a logical value that enables the clock signal or the second enable signal has a logical value that enables acquisition of data; A semiconductor circuit device comprising:

9. an auxiliary signal generating circuit that outputs an auxiliary signal that maintains a logic value that turns on the power switch during a period in which a clock pulse of the first gated clock signal is being output; 9. The semiconductor circuit device according to claim 8, wherein when the auxiliary signal is input as one of the power supply control signals and the auxiliary signal has a logical value that turns on the power switch, the power gating circuit turns on the power switch and supplies power to the first flip-flop regardless of the logical values ​​of the other power supply control signals.

10. an enable signal generation circuit provided corresponding to the first flip-flop, the enable signal generation circuit comprising: a first generation circuit configured with a circuit that is not power-gated, generating a first sub-enable signal and outputting the first sub-enable signal as the first enable signal; and a second generation circuit configured with a circuit including a control-side non-volatile flip-flop whose power supply is controlled by an enable signal power supply control signal including the first sub-enable signal and which is supplied with power at least when the first sub-enable signal is active, generating a second sub-enable signal; a selector which receives new data and the data output from the first flip-flop, and receives the second sub-enable signal as a selection control signal, and selects and outputs the new data when the second sub-enable signal is active, and selects and outputs the data output from the first flip-flop when the second sub-enable signal is inactive; 10. The semiconductor circuit device according to claim 1, further comprising:

11. a combinational circuit connected to the input side or the output side of the first flip-flop; a power switch for the combination circuit, which is provided on a power line to the combination circuit and is turned on and off by a switching signal that controls the on and off of the power switch; 11. The semiconductor circuit device according to claim 1, further comprising:

12. a replacement target specifying unit for specifying a replacement target flip-flop to be replaced with a nonvolatile flip-flop among the flip-flops in the circuit described in the netlist; a logic circuit replacement unit that replaces the replacement target flip-flop with the non-volatile flip-flop to which a power gating circuit is added, and modifies the netlist so as to add connections so that a first enable signal that controls enable and disable of a clock signal input to a first clock gating circuit that is provided for the replacement target flip-flop and outputs a first gated clock signal that controls a clock signal, and a second enable signal that controls enable and disable of data acquisition of an acquisition circuit to which data from the replacement target flip-flop is input directly or via a combinational circuit, are input to the power gating circuit as power supply control signals, respectively; A logic circuit design support device comprising:

13. 13. The logic circuit design support device according to claim 12, wherein the logic circuit replacement unit modifies the netlist and adds a connection so that the first gated clock signal is input to the power gating circuit as one of the power supply control signals.

14. 13. The logic circuit design assistance device according to claim 12, wherein the logic circuit replacement unit adds an auxiliary signal generation circuit that outputs an auxiliary signal that maintains power supply to the non-volatile flip-flop during a period in which a clock pulse of the first gated clock signal is output, and adds a connection so that the auxiliary signal is input to the power gating circuit as one of the power supply control signals.

15. a cutoff avoidance signal designation unit that designates an output signal to be a cutoff avoidance signal that is input to the power gating circuit as one of the power supply control signals and that selects between a cutoff avoidance mode that maintains power supply to the nonvolatile flip-flop regardless of other power supply control signals and a cutoff allowance mode that controls power supply in accordance with the other power supply control signals; 15. The logic circuit design assistance device according to claim 12, wherein the logic circuit replacement unit adds a connection so that the output signal designated by the cutoff avoidance signal designation unit is input to the power gating circuit as one of the power supply control signals.

Images