Semiconductor device manufacturing method

Abstract

To suppress the increase in contact resistance between a trench gate drawer electrode and a gate drawer contact member.SOLUTION: When forming a trench gate drawer electrode TGI in a trench TRCW, it is assumed that a natural oxide film SSM may be formed on a polysilicon film PSF that will become the trench gate drawer electrode TGI. If the natural oxide film SSM is formed, the natural oxide film SSM may protrude when a top surface of the trench gate drawer electrode TGI is retracted. The protruding natural oxide film SSM is removed by applying isotropic dry etching processing.SELECTED DRAWING: Figure 17

Description

[Technical Field]

[0001] The present invention relates to a method for manufacturing a semiconductor device, and is suitable for use in, for example, a semiconductor device including an electron injection enhanced trench insulated gate bipolar transistor. [Background technology]

[0002] Among power semiconductor devices, there are semiconductor devices equipped with trench insulated gate bipolar transistors (IGBTs) as switching elements, and some of these semiconductor devices have an enhanced injection enhancement (IE) effect (electron injection enhancement effect) to reduce the on-state voltage (Patent Document 1).

[0003] This type of semiconductor device has a region that prevents holes injected from the collector side from escaping to the emitter (electrode) side. This increases the concentration of holes accumulated in the drift layer in the semiconductor substrate, promoting the injection of electrons from the emitter side and increasing the electron concentration. The increased concentration of carriers (electrons and holes) causes conductivity modulation, which can reduce the on-state voltage.

[0004] The IGBT is formed in the cell region. A trench gate extraction electrode electrically connected to the trench gate electrode of the IGBT is formed in an area outside the cell region. The trench gate extraction electrode is formed to have a width (wide portion) wider than the width of the trench gate electrode. The trench gate extraction electrode is electrically connected to the gate electrode via a gate extraction contact member connected to the wide portion and a gate extraction wiring. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Publication No. 2018-46053 Summary of the Invention [Problem to be solved by the invention]

[0006] In this type of semiconductor device, the trench gate lead electrode is formed by filling a wide trench with a polysilicon film. At this time, a natural oxide film is likely to form on the surface of the polysilicon film. If a natural oxide film is formed, the gate lead contact member may not make good contact with the trench gate lead electrode, resulting in increased contact resistance.

[0007] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0008] A method for manufacturing a semiconductor device according to one embodiment is a method for manufacturing a semiconductor device having a switching element, the method comprising the steps of: preparing a semiconductor substrate having first and second main surfaces facing each other; forming a plurality of trenches; forming a conductive film covering the first main surface so as to fill the plurality of trenches; forming trench electrodes in each of the plurality of trenches; forming an interlayer insulating film covering the first main surface of the semiconductor substrate; forming a plurality of contact openings; etching the first trench electrodes exposed at the bottoms of the first contact openings and the second trench electrodes exposed at the bottoms of the second contact openings; and forming contact members in each of the plurality of contact openings. The step of forming the plurality of trenches includes forming, from the first main surface toward the second main surface of the semiconductor substrate, first trenches having a first width and second trenches having a second width wider than the first width. The step of forming a trench electrode in each of the plurality of trenches includes the step of etching the conductive film to remove the conductive film located on the first main surface, thereby forming a first trench electrode with the conductive film remaining in the first trench and forming a second trench electrode with the conductive film remaining in the second trench. The step of forming a plurality of contact openings includes the step of forming a first contact opening through the interlayer insulating film to expose the first trench electrode, and the step of forming a second contact opening through the interlayer insulating film to expose the second trench electrode. The step of forming a contact member in each of the plurality of contact openings includes the step of forming a first contact member in the first contact opening and the step of forming a second contact member in the second contact opening. The step of forming the first contact opening includes the step of forming the first contact opening so as to straddle the first trench electrode and a first region of the semiconductor substrate. The etching process includes a first etching process for recessing the surfaces of the first trench electrode and the second trench electrode, and a second etching process for removing residues from the first trench electrode and the second trench electrode that have been subjected to the first etching process. [Effects of the Invention]

[0009] According to the method for manufacturing a semiconductor device according to one embodiment, an increase in contact resistance can be suppressed. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 is a plan view illustrating an example of a semiconductor device according to each embodiment. [Figure 2] 1 is a partial plan view showing an example of a planar structure of a semiconductor device according to a first embodiment. [Figure 3] 3 is a cross-sectional view showing the cross-sectional structures along the cross-sectional lines IIIa-IIIa, IIIb-IIIb, and IIIc-IIIc shown in FIG. 2 in the embodiment. [Figure 4] 2 is a cross-sectional view showing one step of a method for manufacturing a semiconductor device in the embodiment. FIG. [Figure 5] 5 is a cross-sectional view showing a step performed after the step shown in FIG. 4 in the embodiment. [Figure 6] 6 is a cross-sectional view showing a step performed after the step shown in FIG. 5 in the embodiment. [Figure 7] 7 is a cross-sectional view showing a step performed after the step shown in FIG. 6 in the embodiment. [Figure 8] 8 is a cross-sectional view showing a step performed after the step shown in FIG. 7 in the embodiment. [Figure 9] 9 is a cross-sectional view showing a step performed after the step shown in FIG. 8 in the embodiment. [Figure 10] 10 is a cross-sectional view showing a step performed after the step shown in FIG. 9 in the embodiment. [Figure 11] 11 is a cross-sectional view showing a step performed after the step shown in FIG. 10 in the embodiment. [Figure 12] 12 is a cross-sectional view showing a step performed after the step shown in FIG. 11 in the embodiment. [Figure 13]13 is a cross-sectional view showing a step performed after the step shown in FIG. 12 in the embodiment. [Figure 14] 14 is a cross-sectional view showing a step performed after the step shown in FIG. 13 in the embodiment. [Figure 15] 15 is a cross-sectional view showing a step performed after the step shown in FIG. 14 in the embodiment. [Figure 16] 16 is a cross-sectional view showing a step performed after the step shown in FIG. 15 in the embodiment. [Figure 17] 17 is a cross-sectional view showing a step performed after the step shown in FIG. 16 in the embodiment. [Figure 18] 18 is a cross-sectional view showing a step performed after the step shown in FIG. 17 in the embodiment. [Figure 19] 19 is a cross-sectional view showing a step performed after the step shown in FIG. 18 in the embodiment. [Figure 20] 20 is a cross-sectional view showing a step performed after the step shown in FIG. 19 in the embodiment. [Figure 21] 21 is a cross-sectional view showing a step performed after the step shown in FIG. 20 in the embodiment. [Figure 22] FIG. 10 is a partial cross-sectional view showing a step of another mode of forming a polysilicon film in the embodiment. [Figure 23] 23 is a partial cross-sectional view showing a step performed after the step shown in FIG. 22 in the embodiment. FIG. [Figure 24] 24 is a partial cross-sectional view showing a step performed after the step shown in FIG. 23 in the embodiment. [Figure 25] FIG. 10 is a partial cross-sectional view showing a step of still another mode of forming a polysilicon film in the embodiment. [Figure 26] 26 is a partial cross-sectional view showing a step performed after the step shown in FIG. 25 in the embodiment. [Figure 27] 27 is a partial cross-sectional view showing a step performed after the step shown in FIG. 26 in the embodiment. FIG. [Figure 28]FIG. 10 is a partial plan view showing an example of the planar structure of a semiconductor device according to a second embodiment. [Figure 29] 29 is a cross-sectional view showing the cross-sectional structures along the cross-sectional lines XXIXa-XXIXa, XXIXb-XXIXb, and XXIXc-XXIXc shown in FIG. 28 in the embodiment. [Figure 30] 2 is a cross-sectional view showing one step of a method for manufacturing a semiconductor device in the embodiment. FIG. [Figure 31] 31 is a cross-sectional view showing a step performed after the step shown in FIG. 30 in the embodiment. [Figure 32] 32 is a cross-sectional view showing a step performed after the step shown in FIG. 31 in this embodiment. [Figure 33] 33 is a cross-sectional view showing a step performed after the step shown in FIG. 32 in this embodiment. [Figure 34] FIG. 34 is a cross-sectional view showing a step performed after the step shown in FIG. 33 in this embodiment. [Figure 35] FIG. 35 is a cross-sectional view showing a step performed after the step shown in FIG. 34 in this embodiment. [Figure 36] FIG. 36 is a cross-sectional view showing a step performed after the step shown in FIG. 35 in this embodiment. [Figure 37] FIG. 11 is a cross-sectional view showing an example of a cross-sectional structure of a semiconductor device according to a third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0011] Semiconductor devices equipped with IE-type trench insulated gate bipolar transistors, such as GE-type semiconductor devices that emphasize reducing on-state voltage, have a structure in which a trench gate electrode electrically connected to a gate electrode and a trench emitter electrode electrically connected to an emitter electrode are arranged at a distance from each other.

[0012] Furthermore, a semiconductor device that emphasizes operational stability and balance is the GGEE type semiconductor device. The GGEE type has a structure in which one trench emitter electrode and another trench emitter electrode are arranged at a distance from each other, and one trench gate electrode and another trench gate electrode are arranged at a distance from each other. The one trench emitter electrode and another trench emitter electrode, and the one trench gate electrode and another trench gate electrode are arranged at a predetermined distance from each other.

[0013] Furthermore, semiconductor devices that prioritize high-speed performance include EGE type semiconductor devices. The EGE type has a structure in which one trench emitter electrode, a trench gate electrode, and another trench emitter electrode are arranged with a gap between them. This will be explained in detail below.

[0014] First, an example of the overall structure of a semiconductor device including an IE-type trench insulated gate bipolar transistor will be described. As shown in Figure 1, a semiconductor device SED (semiconductor substrate SUB) includes a cell region CER and a gate wiring lead-out region MGR.

[0015] An IE-type trench insulated gate bipolar transistor is formed in the cell region CER. An emitter electrode MEE is formed in the cell region CER so as to cover the cell region CER. The emitter electrode MEE is exposed at the bottom of an opening HK1 formed in an insulating film (not shown) covering the emitter electrode MEE (semiconductor substrate SUB).

[0016] The gate wiring lead-out region MGR is arranged to surround the cell region CER. Gate wiring lead-out lines MGI and gate electrodes MGE are formed in the gate wiring lead-out region MGR. The gate wiring lead-out lines MGI are electrically connected to the gate electrodes MGE. The gate electrodes MGE are exposed at the bottom of openings HK2 formed in an insulating film (not shown) covering the gate electrodes MGE (semiconductor substrate SUB).

[0017] Furthermore, the semiconductor device SED (semiconductor substrate SUB) has defined therein a peripheral element region PDR in which peripheral elements such as protection diodes or temperature sensing diodes are formed.

[0018] Embodiment 1 Here, an example of a GE type semiconductor device SED will be described. First, the cell region CER will be described. As shown in Figures 2 and 3, in the cell region CER, a trench gate electrode TGE (third trench electrode) and a trench emitter electrode TEE (first trench electrode) are arranged at a distance in one direction. The trench gate electrode TGE and the trench emitter electrode TEE each extend in another direction intersecting the one direction.

[0019] The trench gate electrode TGE has an insulating film GI F The trench emitter electrode TEE is formed by interposing an insulating film EIF( No. 1 The trench TRC is formed with an insulating film interposed therebetween. The trench TRC is formed from the first main surface toward the second main surface of the semiconductor substrate SUB having an N-type region NSR (drift layer).

[0020] In a region (first region) of the semiconductor substrate SUB located between the trench gate electrode TGE and the trench emitter electrode TEE, an N+ type source diffusion layer SDR is formed from the first main surface to a predetermined depth. A P-type base diffusion layer BDR is formed from the bottom of the source diffusion layer SDR to a further predetermined depth. A P+ layer PPR having a higher P-type impurity concentration is formed in the base diffusion layer BDR. An N-type hole barrier layer HBR is formed from the bottom of the base diffusion layer BDR to a further predetermined depth. The hole barrier layer HBR is formed to reach the bottoms (lower ends) of the trench gate electrode TGE and the trench emitter electrode TEE. The region where the hole barrier layer HBR is formed is called an active region.

[0021] In a region of the semiconductor substrate SUB located on the opposite side of the trench gate electrode TGE from the side on which the trench emitter electrode TEE is located, a P-type floating diffusion layer FPR is formed from the first main surface to a position deeper than the bottom (lower end) of the trench gate electrode TGE. Also, in a region of the semiconductor substrate SUB located on the opposite side of the trench emitter electrode TGE from the side on which the trench gate electrode TGE is located, a P-type floating diffusion layer FPR is formed from the first main surface to a position deeper than the bottom (lower end) of the trench emitter electrode TEE. The floating diffusion layer FPR is called an inactive region.

[0022] An interlayer insulating film CIL is formed so as to cover the trench gate electrode TGE, the trench emitter electrode TEE, the source diffusion layer SDR, etc. A common contact member CCN penetrates the interlayer insulating film CIL so as to be in contact with the trench emitter electrode TEE, the base diffusion layer BDR (P+ layer PPR), the source diffusion layer SDR, etc. (Ko The common contact member CCN includes a barrier metal film BME and a tungsten plug WPG.

[0023] A recess portion RCS recessed from the first main surface toward the second main surface is formed in the trench emitter electrode TEE, the base diffusion layer BDR, and the insulating film EIF. The shared contact member CCN protrudes from the first main surface toward the second main surface in contact with the recess portion RCS. A distance L1 between the trench emitter electrode TEE and the trench gate electrode TGE is set to a distance such that the shared contact member CCN does not contact the trench gate electrode TGE.

[0024] An emitter electrode MEE is formed so as to be in contact with the surface (upper surface) of the interlayer insulating film CIL. The common contact member CCN is electrically connected to the emitter electrode MEE. The emitter electrode MEE is formed of, for example, an aluminum film or the like.

[0025] On the other hand, a P-type collector diffusion layer CDR and an N-type buffer layer NBR are formed on the second main surface side of the semiconductor substrate SUB. An N-type region NSR serving as a drift layer is located between the floating diffusion layer FPR and the buffer layer NBR. A collector electrode BEL (back electrode) is formed so as to be in contact with the collector diffusion layer CDR (the second main surface of the semiconductor substrate SUB).

[0026] Next, the gate wiring lead-out region MGR will be described. In the gate wiring lead-out region MGR, a trench gate lead-out electrode TGI (second trench electrode) is formed. The trench gate lead-out electrode TGI is formed in the trench TRCW (second trench) with an insulating film GIF interposed therebetween. As shown in FIGS. 2 and 3, the trench gate lead-out electrode TGI is electrically connected to the trench gate electrode TGE. The trench gate lead-out electrode TGI (trench TRCW (second trench)) has a first part TGN set to a first width W1 that is the same as the width of the trench gate electrode TGE (trench TRC (third trench)), and a second part TGW set to a second width W2 that is wider than the first width W1.

[0027] A gate lead contact member GCN is formed through the interlayer insulating film CIL so as to be in contact with the second part TGW of the trench gate lead electrode TGI. (Ko A gate lead-out contact member (GCN) is formed on the interlayer insulating film CIL. The gate lead-out contact member GCN includes a barrier metal film BME and a tungsten plug WPG. A gate lead-out wiring MGI is formed so as to be in contact with the surface (upper surface) of the interlayer insulating film CIL. The gate lead-out contact member GCN is electrically connected to the gate lead-out wiring MGI. The gate lead-out wiring MGI is formed of, for example, an aluminum film or the like.

[0028] Next, the peripheral element region PDR will be described. In the peripheral element region PDR, wiring PIC is formed on the first main surface of the semiconductor substrate SUB with an insulating film IF and a silicon oxide film HDL interposed therebetween. The wiring PIC is electrically connected to a peripheral element (not shown), such as a protection diode or a temperature sensing diode. A contact member DCN is formed so as to penetrate the interlayer insulating film CIL and contact the wiring PIC. A conductive layer MPL is formed on the surface of the interlayer insulating film CIL and is electrically connected to the wiring PIC via the contact member DCN.

[0029] In the semiconductor device SED described above, it is assumed that a natural oxide film SSM is formed on the surface of the polysilicon film, particularly when the trench gate extraction electrode TGI is formed. When the natural oxide film SSM is formed, a desired etching process is performed so that the natural oxide film SSM does not protrude beyond the upper surface of the trench gate extraction electrode TGI (the upper surface of the polysilicon film).

[0030] Next, an example of a method for manufacturing the above-mentioned semiconductor device SED will be described. As shown in Fig. 4, a silicon oxide film SOF1 is formed so as to cover the first main surface of the semiconductor substrate SUB. Next, with the silicon oxide film SOF1 formed, a P-type region PR that will become a floating diffusion layer is formed by injecting P-type impurities. Furthermore, an N-type region NR that will become a hole barrier layer is formed by injecting N-type impurities.

[0031] Next, a hard mask (not shown) is formed to form trenches. Next, the semiconductor substrate SUB is etched using the hard mask as an etching mask to form trenches TRC (first trench, third trench) and trench TRCW (second trench) (see FIG. 5). Thereafter, the hard mask is removed. As a result, as shown in FIG. 5, the first main surface of the semiconductor substrate SUB in which the trenches TRC and TRCW are formed is exposed. The trenches TRCW are formed to have a width wider than that of the trenches TRC.

[0032] Next, a predetermined heat treatment is performed to diffuse the P-type impurities in the P-type region PR, thereby forming a floating diffusion layer FPR. Also, the N-type impurities in the N-type region NR are diffused to form a hole barrier layer HBR (see FIG. 6). Next, as shown in FIG. 6, a thermal oxidation treatment is performed to form an insulating film IF on the first main surface of the semiconductor substrate SUB, including the inner wall surfaces of the trenches TRC and TRCW.

[0033] Next, a polysilicon film PSF (see FIG. 8) is formed so as to cover the semiconductor substrate SUB and to fill the trenches TRC and TRCW. Here, an example will be given in which the polysilicon film PSF is formed in two steps in order to reduce the grain size, etc.

[0034] As shown in Figure 7, first, a first-layer polysilicon film PS1 is formed. The semiconductor substrate SUB on which the polysilicon film PS1 has been formed is removed from a film-forming apparatus (not shown) and temporarily exposed to the atmosphere. At this time, it is expected that a native oxide film SSM will be formed on the surface of the polysilicon film PS1. Next, as shown in Figure 8, a second-layer polysilicon film PS2 is formed to cover the polysilicon film PS1.

[0035] In this way, a polysilicon film PSF consisting of two layers, the polysilicon film PS1 and the polysilicon film PS2, is formed. At this time, the position of the upper surface of the polysilicon film PSF covering the relatively wide trench TRCW is lower than the position of the upper surface of the polysilicon film PSF covering the relatively narrow trench TRC.

[0036] Next, as shown in FIG. 9, the entire surface of the polysilicon film PSF is etched to remove the portion of the polysilicon film PSF located on the first main surface of the semiconductor substrate SUB. At this time, the native oxide film SSM formed on the surface of the first-layer polysilicon film PS1 is exposed. As shown in FIG. 10, the polysilicon film PSF is then over-etched. As a result, the upper surfaces of the polysilicon film PSF remaining in the trenches TRC and TRCW are positioned lower than the first main surface of the semiconductor substrate SUB.

[0037] At this time, with the polysilicon film PSF formed, the position of the polysilicon film PSF covering the trench TRCW is lower than the position of the polysilicon film PSF covering the trench TRC. Therefore, after the entire surface etching process is performed, the position of the upper surface of the polysilicon film PSF left in the trench TRCW is lower than the position of the upper surface of the polysilicon film PSF left in the trench TRC. A native oxide film SSM is left so as to protrude from the upper surface of the polysilicon film PSF in the trench TRCW. Note that the thickness corresponding to the difference in height (thickness) of the polysilicon film PSF is referred to as thickness TK.

[0038] 11, a silicon oxide film HDL is formed to cover the insulating film IF. Next, a polysilicon film PSF2 is formed to cover the silicon oxide film HDL. Next, a photolithography process is performed to form a photoresist pattern PHR1 for patterning wiring.

[0039] 12, the polysilicon film PSF2 is etched using the photoresist pattern PHR1 as an etching mask, thereby forming the wiring PIC. Next, as shown in FIG. 13, the silicon oxide film HDL is etched using the photoresist pattern PHR1 as an etching mask, and further, the insulating film IF is etched, thereby removing the portion of the silicon oxide film HDL and the portion of the insulating film IF located on the first main surface of the semiconductor substrate SUB. At this time, the native oxide film SSM protruding from the upper surface of the polysilicon film PSF is also removed together with the insulating film IF. Thereafter, the photoresist pattern PHR1 is removed.

[0040] As a result, a trench emitter electrode TEE (first trench electrode) is formed in the trench TRC with an insulating film EIF (insulating film IF) interposed therebetween. A trench gate electrode TGE (third trench electrode) is formed in the trench TRC with an insulating film GIF (insulating film IF) interposed therebetween. A trench gate lead electrode TGI (second trench electrode) is formed in the trench TRCW with an insulating film GIF (insulating film IF) interposed therebetween.

[0041] 14, a silicon oxide film SOF2 is formed to cover the first main surface of the semiconductor substrate SUB. Next, a predetermined photolithography process is performed to form a photoresist pattern (not shown) for forming a source diffusion layer and a base diffusion layer. Next, P-type impurities are implanted using the photoresist pattern as an implantation mask. Furthermore, N-type impurities are implanted. Thereafter, the photoresist pattern is removed.

[0042] As a result, the region of the semiconductor substrate SUB located between the trench emitter electrode TEE and the trench gate electrode TGE is In the area A source diffusion layer SDR and a base diffusion layer BDR are formed. The source diffusion layer SDR is formed to a predetermined depth from the first main surface. The base diffusion layer BDR is formed to an even deeper position from the bottom of the base diffusion layer BDR. Thereafter, the silicon oxide film SOF2 is removed.

[0043] Next, an interlayer insulating film CIL is formed so as to cover the first main surface of the semiconductor substrate SUB (see FIG. 15). As the interlayer insulating film CIL, for example, a PSG film (Phospho Silicate Glass) is formed. Next, a predetermined photolithography process is performed to form a photoresist pattern PHR2 for forming contact openings in the interlayer insulating film CIL (see FIG. 15).

[0044] Next, as shown in FIG. 15, the interlayer insulating film CIL is etched using the photoresist pattern PHR2 as an etching mask. By this etching, a contact opening CH1 (first contact opening mouth) , contact opening CH2 (second contact opening mouth) and contact opening CH 3 is , are formed simultaneously.

[0045] Here, since the contact opening depth is large relative to its width and the aspect ratio (opening depth DC / opening width WC: approximately 1.4 to 2.5) is high, an anisotropic etching process is applied as the etching process. In this anisotropic etching, conditions are set such that the etching selectivity ratio of the etching rate of the interlayer insulating film CIL (insulating film EIF) to the etching rate of the semiconductor substrate SUB (trench emitter electrode TEE) is high. By this anisotropic etching process, the contact openings CH1 and the like are formed in a tapered shape.

[0046] Furthermore, as described above, the position of the upper surface of the trench gate extraction electrode TGI (polysilicon film PSF) formed in the trench TRCW is lower by the thickness TK than the position of the upper surface of the trench emitter electrode TEE (polysilicon film PSF) formed in the trench TRC.

[0047] Therefore, in this anisotropic etching, when the upper surface of the trench emitter electrode TEE is exposed, the trench gate extraction electrode TGI is still covered with the interlayer insulating film CIL of thickness TK. Then, after the trench emitter electrode TEE is exposed, the insulating film EIF interposed between the trench emitter electrode TEE and the base diffusion layer BDR (semiconductor substrate SUB) is also etched before the trench gate extraction electrode TGI is exposed. This causes the upper surface of the insulating film EIF to recede, and the area of ​​the exposed base diffusion layer BDR to increase. Then, the photoresist pattern PHR2 is removed.

[0048] Next, as shown in FIG. 16, anisotropic etching is performed on the exposed portions at the bottoms of the contact openings CH1, CH2, and CH3. (workman The surface is then subjected to etching treatment.

[0049] At the bottom of the contact opening CH1, anisotropic etching is performed on the exposed trench emitter electrode TEE, base diffusion layer BDR, and source diffusion layer SDR, so that part of the upper surface of the trench emitter electrode TEE and part of the upper surface of the base diffusion layer BDR are recessed. At this time, since the upper surface of the trench emitter electrode TEE is initially located lower than the first main surface of the semiconductor substrate SUB (the upper surface of the base diffusion layer BDR), the recessed upper surface of the trench emitter electrode TEE is located lower than the upper surface of the recessed base diffusion layer BDR.

[0050] At the bottom of the contact opening CH2, an anisotropic etching process is performed on the exposed trench gate extraction electrode TGI, thereby causing the upper surface of the trench gate extraction electrode TGI to recede.At the bottom of the contact opening CH3, an anisotropic etching process is performed on the exposed wiring PIC, thereby causing the upper surface of the wiring PIC to recede.

[0051] This anisotropic etching leaves a part of the insulating film EIF and a part of the silicon (semiconductor substrate SUB, polysilicon) as a residue RES at the bottom of the contact opening CH1. Also, at the bottom of the contact opening CH2, the exposed upper surface of the trench gate extraction electrode TGI recedes, so that the native oxide film SSM is exposed as a residue RES.

[0052] Next, as shown in FIG. 17, the portions exposed at the bottoms of the contact openings CH1 and CH2 and the like and subjected to the anisotropic etching are further etched. Reason Here, an isotropic dry etching process using a gas containing CF4 is performed as the etching process. By this isotropic dry etching process, the native oxide film SSM exposed as a residue RES is removed at the bottom of the contact opening CH2. Furthermore, the residue RES is removed at the bottom of the contact opening CH1, and a recess portion RCS is formed.

[0053] 18, P+ type impurities are implanted through the contact openings CH1 to CH3. At this time, a P+ layer PPR having an impurity concentration higher than the impurity concentration of the base diffusion layer BDR is formed in the P-type base diffusion layer BDR exposed at the bottom (recess portion RCS) of the contact opening CH1. This reduces the contact resistance between the shared contact member CCN and the P+ layer PPR (base diffusion layer BDR).

[0054] On the other hand, at the bottom of the contact opening CH1, the P+ type impurities are also implanted into the side surface of the N-type source diffusion layer SDR exposed in the recess portion RCS. As a result, the N-type impurities in the source diffusion layer SDR, which comes into contact with the shared contact member CCN, are neutralized by the P+ type impurities, which may increase the contact resistance between the source diffusion layer SDR and the shared contact member CCN.

[0055] 19, the interlayer insulating film CIL is subjected to a wet etching process to widen the opening width of the contact opening CH1 and the like. By widening the opening width of the contact opening CH1, the upper surface of the source diffusion layer SDR into which P+ type impurities are not implanted is exposed. This reduces the contact resistance between the shared contact member CCN and the source diffusion layer SDR.

[0056] 20, a barrier metal film BME is formed so as to cover the interlayer insulating film CIL including the inner wall surfaces of the contact openings CH1 to CH3. As the barrier metal film BME, for example, a stacked film of titanium nitride (TiN) and titanium (Ti) is formed. Next, a tungsten film WF is formed so as to cover the barrier metal film BME. Next, the tungsten film WF and the barrier metal film BME located on the upper surface of the interlayer insulating film CIL are removed by performing an etch-back process on the entire surface of the tungsten film WF and the like.

[0057] 21, the tungsten film WF and the barrier metal film BME left in the contact opening CHI form a common contact member CCN. The tungsten film WF and the barrier metal film BME left in the contact opening CH2 form a gate lead-out contact member GCN. The tungsten film WF and the barrier metal film BME left in the contact opening CH3 form a contact member DCN.

[0058] Thereafter, for example, an aluminum film (not shown) is formed so as to cover the interlayer insulating film CIL, and the aluminum film is patterned to form an emitter electrode MEE, a gate lead-out wiring MGI, a gate electrode MGE, etc. (See FIG. 3, etc.). Next, an N-type buffer layer NBR and a P-type collector diffusion layer CDR are formed on the second main surface side of the semiconductor substrate SUB. Furthermore, a collector electrode BEL (back electrode) is formed, thereby completing the semiconductor device SED.

[0059] Next, the operation of the semiconductor device SED described above will be explained. First, when the trench insulated gate bipolar transistor is turned on, a voltage equal to or higher than the threshold voltage is applied to the gate electrode MGE. As a result, electrons are injected from the source diffusion layer SDR through the channel into the N-type region NSR (drift layer) in the semiconductor substrate SUB, the PN junction between the N-type region NSR and the collector diffusion layer CDR is forward biased, and holes are injected from the collector diffusion layer CDR into the N-type region NSR.

[0060] The injected holes are prevented from escaping to the source diffusion layer SDR (emitter) side by the P-type floating diffusion layer FPR, and holes accumulate in the N-type region NSR and floating diffusion layer FPR, increasing the hole concentration. When the hole concentration in the N-type region NSR etc. increases, the injection of electrons from the source diffusion layer SDR is promoted, and the electron concentration also increases. In this way, the increase in the carrier concentration in the N-type region NSR etc. causes conductivity modulation, resulting in an on-state.

[0061] Next, to turn off the trench insulated gate bipolar transistor, a voltage lower than the threshold voltage is applied to the gate electrode MGE. This causes the channel to disappear. The carriers (holes) accumulated in the N-type region NSR and other regions are discharged to the emitter electrode MEE by the parasitic P-channel MOSFET (floating diffusion layer FPR, trench emitter electrode TEE at the emitter potential, base diffusion layer BDR, etc.) formed on the trench emitter electrode TEE side, turning the transistor off.

[0062] In the semiconductor device SED described above, when the polysilicon film PSF is formed, the polysilicon film PSF is formed in two stages in order to reduce the grain size, etc. At this time, it is assumed that a native oxide film SSM is formed on the surface of the first-layer polysilicon film PS1. The second-layer polysilicon film PS2 is formed so as to cover the native oxide film SSM.

[0063] Therefore, in the steps after the polysilicon film PSF is formed, the semiconductor substrate SUB is subjected to each process in sequence with the native oxide film SSM interposed between the polysilicon film PS1 and the polysilicon film PS2.

[0064] After the etching process is performed on the entire surface of the polysilicon film PSF, the native oxide film SSM protrudes from the surface of the polysilicon film PSF (see FIGS. 9 and 10). The native oxide film SSM protruding from the surface of the polysilicon film PSF is removed when the silicon oxide film HDL and the insulating film IF are removed (see FIG. 13).

[0065] After the contact opening CH2 is formed, the surface of the polysilicon film PSF from which the protruding native oxide film SSM has been removed is exposed at the bottom of the contact opening CH2. The surface of the polysilicon film PSF exposed at the bottom of the contact opening CH2 will protrude again when the upper surface of the trench gate extraction electrode TGI (polysilicon film PSF) is recessed by anisotropic etching (see FIG. 16).

[0066] The native oxide film SSM protruding from the trench gate lead electrode TGI (polysilicon film PSF) is finally removed by an isotropic dry etching process using a gas containing CF4 (see FIG. 18). By removing the protruding native oxide film SSM, the native oxide film SSM is no longer positioned beyond the upper surface of the trench gate lead electrode TGI.

[0067] 21 (FIG. 3), the gate lead contact member GCN comes into good contact with the trench gate lead electrode TGI, which in turn makes it possible to suppress an increase in contact resistance between the trench gate lead electrode TGI and the gate lead contact member GCN.

[0068] Furthermore, in the above-described method for manufacturing a semiconductor device, the contact opening CH2 exposing the surface of the polysilicon film PSF is formed simultaneously with the other contact openings CH1 and CH3, thereby preventing an increase in the number of steps for forming the contact openings CH1 to CH3.

[0069] Furthermore, when forming the contact openings CH1 to CH3, after the trench emitter electrode TEE is exposed at the bottom of the contact opening CH1, the insulating film EIF interposed between the trench emitter electrode TEE and the base diffusion layer BDR is also etched at the same time until the trench gate extraction electrode TGI is exposed at the bottom of the contact opening CH2, causing the upper surface of the insulating film EIF to recede.

[0070] This increases the area of ​​the exposed base diffusion layer BDR, increases the contact area between the common contact member CCN and the base diffusion layer BDR, and reduces the contact resistance between the common contact member CCN and the base diffusion layer BDR. As a result, this can be achieved in the process of forming the contact openings CH1 to CH3 without adding a separate process for increasing the contact area, which can contribute to reducing production costs.

[0071] In the above-described method for manufacturing a semiconductor device, an example has been given in which the polysilicon film PSF is formed in two separate steps, and a native oxide film SSM is formed on the surface of the first-layer polysilicon film PS1.

[0072] As a form of forming the polysilicon film PSF, there is a case where the polysilicon film PSF is formed by a single film formation. Even in such a case, it is assumed that a natural oxide film is formed on the surface of the polysilicon film PSF. The deposition of the polysilicon film PSF in the trench TRCW is shown in chronological order in FIGS. 22, 23, and 24.

[0073] 22, 23, and 24, the polysilicon film PSF is gradually deposited from one opposing sidewall surface and the other opposing sidewall surface of the trench TRCW toward the center of the trench TRCW. Therefore, when the trench TRCW is filled with the polysilicon film PSF, a seam SL with weak intermolecular bonds exists in the polysilicon film PSF located at the center of the trench TRCW. Oxygen diffuses through this seam SL, forming a native oxide film SSM.

[0074] In this way, even if a native oxide film SSM is formed in the seam SL of the polysilicon film PSF, the native oxide film SSM will ultimately be removed by performing an isotropic dry etching process using a gas containing CF4, just as in the case where the polysilicon film PSF is formed in two separate steps.

[0075] In addition, as a forming mode of the polysilicon film PSF, in order to improve the embedding characteristics, an etch-back process may be performed on the entire surface of the polysilicon film PSF during the formation of the polysilicon film PSF. Even in such a case, it is expected that a native oxide film SSM will be formed on the surface of the polysilicon film PSF. The deposition of the polysilicon film PSF in the trench TRCW is shown in chronological order in FIGS. 25, 26, and 27.

[0076] As shown in Fig. 25, after the polysilicon film PSF is formed partway, an etch-back process is performed on the entire surface of the polysilicon film PSF as shown in Fig. 26. Next, as shown in Fig. 27, a further polysilicon film PSF is formed so as to cover the polysilicon film PSF that has been subjected to the etch-back process.

[0077] In this formation mode of the polysilicon film PSF, it is assumed that a natural oxide film SSM is formed at the interface between the polysilicon film PSF that has been subjected to the etch-back process on the entire surface and the polysilicon film PSF that covers the polysilicon film PSF.

[0078] In this way, even if a native oxide film SSM is formed at the interface between the polysilicon films PSF, the native oxide film SSM will ultimately be removed by performing an isotropic dry etching process using a gas containing CF4, just as in the case where the polysilicon film PSF is formed in two separate steps.

[0079] Embodiment 2 Here, an example of a GGEE-type semiconductor device will be described. The GGEE-type semiconductor device is applied to applications requiring stable operation, etc. First, the cell region CER will be described. As shown in FIGS. 28 and 29, one trench emitter electrode TEE (first trench electrode) and another trench emitter electrode TEE (fourth trench electrode) are arranged at a distance in one direction. The distance between the one trench emitter electrode TEE and the other trench emitter electrode TEE is distance L2. The one trench emitter electrode TEE and the other trench emitter electrode TEE each extend in another direction intersecting the one direction.

[0080] One trench gate electrode TGE (fifth trench electrode) and another trench gate electrode (sixth trench electrode) are arranged at a distance in one direction. The distance between the one trench gate electrode TGE and the other trench gate electrode is distance L3. The one trench gate electrode TGE and the other trench gate electrode each extend in another direction intersecting the one direction.

[0081] Moreover, the one trench emitter electrode TEE and the other trench emitter electrode TEE, and the one trench gate electrode TGE and the other trench gate electrode are arranged at a distance in one direction.

[0082] A region of the semiconductor substrate SUB located between one trench emitter electrode TEE and another trench emitter electrode TEE In the area A P-type base diffusion layer BDR is formed from the first main surface to a predetermined depth. A P+ layer PPR having a higher P-type impurity concentration is formed in the base diffusion layer BDR.

[0083] A region of the semiconductor substrate SUB located between one trench gate electrode TGE and another trench gate electrode In the area An N+ type source diffusion layer SDR is formed in the first region 10. A P type base diffusion layer BDR is formed from the bottom of the source diffusion layer SDR to a predetermined depth.

[0084] An interlayer insulating film CIL is formed to cover the first main surface of the semiconductor substrate SUB. A common contact member CCN, a gate contact member GDC, and a gate lead-out contact member GCN are formed to penetrate the interlayer insulating film CIL. Other configurations are similar to those of the semiconductor device SED shown in Figures 2 and 3, so the same members are denoted by the same reference numerals, and descriptions thereof will not be repeated unless necessary.

[0085] In the semiconductor device SED described above, it is assumed that a natural oxide film SSM is formed on the surface of the polysilicon film, particularly when the trench gate extraction electrode TGI is formed. When the natural oxide film SSM is formed, a desired etching process is performed so that the natural oxide film SSM does not protrude beyond the upper surface of the trench gate extraction electrode TGI (the upper surface of the polysilicon film).

[0086] Next, an example of a manufacturing method of the above-mentioned semiconductor device SED will be described. The semiconductor device SED is manufactured by substantially the same manufacturing method as the manufacturing method of the above-mentioned semiconductor device SED, except that the arrangement pattern of the trench gate electrode TGE (trench TRC) and the trench emitter electrode TEE (trench TRC) is different from the arrangement pattern of the trench gate electrode TGE and the trench emitter electrode TEE in the above-mentioned semiconductor device SED.

[0087] 4 to 13, a silicon oxide film SOF2 is formed to cover the first main surface of the semiconductor substrate SUB, as shown in Fig. 30. Next, a predetermined photolithography process is performed to form a photoresist pattern (not shown) for forming the base diffusion layer BDR. Next, using the photoresist pattern as an implantation mask, P-type impurities are implanted to form the base diffusion layer BDR.

[0088] Next, after the photoresist pattern is removed, a photoresist pattern (not shown) for forming the source diffusion layer SDR is formed by performing a predetermined photolithography process. Next, using the photoresist pattern as an implantation mask, N-type impurities are implanted to form the source diffusion layer SDR. Thereafter, the photoresist pattern is removed.

[0089] As a result, a base diffusion layer BDR is formed in a region (first region) of the semiconductor substrate SUB located between one trench emitter electrode TEE and another trench emitter electrode TEE adjacent to each other. Also, a base diffusion layer BDR is formed in a region (first region) of the semiconductor substrate SUB located between one trench gate electrode TGE and another trench gate electrode TGE adjacent to each other. In the area , the base diffusion layer BDR and the source diffusion layer SDR are formed. After that, the silicon oxide film SOF2 is removed.

[0090] Next, an interlayer insulating film CIL is formed so as to cover the first main surface of the semiconductor substrate SUB (see FIG. 31). Next, a predetermined photolithography process is performed to form a photoresist pattern PHR2 for forming a contact opening in the interlayer insulating film CIL. Next, as shown in FIG. 31, the interlayer insulating film CIL is etched using the photoresist pattern PHR2 as an etching mask. By this etching process, a contact opening CH1 (first contact opening mouth) , contact opening CH2 (second contact opening mouth) , contact opening CH 3O and contact opening CH4 (third contact opening mouth)are formed simultaneously.

[0091] At this time, as explained for the step shown in FIG. 15, an anisotropic etching process is applied as the etching process because the aspect ratio (opening depth DC / opening width WC: approximately 1.4 to 2.5) is high. By this anisotropic etching process, the contact openings CH1 and the like are formed in a tapered shape. Furthermore, since the position of the upper surface of the trench gate extraction electrode TGI (polysilicon film PSF) is lower by the thickness TK than the position of the upper surface of the trench emitter electrode TEE (polysilicon film PSF), while etching the amount corresponding to the thickness TK, the upper surface of the insulating film EIF drops (retreats), and the area of ​​the exposed base diffusion layer BDR increases. Thereafter, the photoresist pattern PHR2 is removed.

[0092] Next, an anisotropic etching process is performed similarly to the process shown in Fig. 16. As a result, as shown in Fig. 32, the upper surface of the trench emitter electrode TEE exposed at the bottom of the contact opening CH1 is recessed, and the upper surface of the base diffusion layer BDR is also recessed. The upper surface of the trench gate extraction electrode TGI exposed at the bottom of the contact opening CH2 is recessed. The upper surface of the source diffusion layer SDR exposed at the bottom of the contact opening CH4 is recessed, exposing the base diffusion layer BDR. The upper surface of the wiring PIC exposed at the bottom of the contact opening CH3 is recessed.

[0093] This anisotropic etching leaves a part of the insulating film EIF and a part of the silicon (semiconductor substrate SUB, polysilicon) as a residue RES at the bottom of the contact opening CH1. Also, at the bottom of the contact opening CH2, the exposed upper surface of the trench gate extraction electrode TGI recedes, so that the native oxide film SSM is exposed as a residue RES.

[0094] Next, similarly to the process shown in Fig. 17, an isotropic dry etching process is performed using a gas containing CF4. As a result, the native oxide film SSM exposed as residue RES at the bottom of the contact opening CH2 is removed by the isotropic dry etching process, as shown in Fig. 33. Furthermore, at the bottom of the contact opening CH1, the residue RES is removed, and a recess portion RCS is formed.

[0095] Next, P+ type impurities are implanted through the contact openings CH1 to CH4. As a result, a P+ layer PPR is formed in the base diffusion layer BDR exposed at the bottom of the contact opening CH1. Also, a P+ layer PPR is formed in the base diffusion layer BDR exposed at the bottom of the contact opening CH4.

[0096] Next, the interlayer insulating film CIL is subjected to a wet etching process, similar to the process shown in Fig. 19. As a result, the opening widths of the contact openings CH1 and CH4 are widened, and the upper surface of the source diffusion layer SDR into which P+ type impurities have not been implanted is exposed, as shown in Fig. 34.

[0097] 20, a barrier metal film BME is formed to cover the interlayer insulating film CIL including the inner wall surfaces of the contact openings CH1 to CH4, as shown in Fig. 35. Next, a tungsten film WF is formed to cover the barrier metal film BME. Next, an etch-back process is performed on the entire surface of the tungsten film WF, etc., to remove the tungsten film WF and the barrier metal film BME located on the upper surface of the interlayer insulating film CIL.

[0098] 36, a common contact member CCN is formed in the contact opening CH1. A gate lead-out contact member GCN is formed in the contact opening CH2. A contact member DCN is formed in the contact opening CH3. A gate contact member GDC is formed in the contact opening CH4. Thereafter, the semiconductor device SED is completed through steps of forming the emitter electrode MEE, the gate lead-out wiring MGI, the gate electrode MGE, etc.

[0099] In the above-described semiconductor device SED, it is assumed that a natural oxide film SSM is formed on the surface of the polysilicon film PS1 and that the natural oxide film SSM is interposed between the polysilicon film PS1 and the polysilicon film PS2. In this case, it is assumed that when the upper surface of the trench gate extraction electrode TGI is recessed, the natural oxide film SSM protrudes from the upper surface.

[0100] In the manufacturing method of the semiconductor device SED described above, the native oxide film SSM protruding from the upper surface of the trench gate extraction electrode TGI is finally removed by an isotropic dry etching process using a gas containing CF4 (see FIG. 33). By removing the protruding native oxide film SSM, the native oxide film SSM is no longer positioned beyond the upper surface of the trench gate extraction electrode TGI.

[0101] 36 (FIG. 29), the gate lead contact member GCN comes into good contact with the trench gate lead electrode TGI, which in turn makes it possible to suppress an increase in contact resistance between the trench gate lead electrode TGI and the gate lead contact member GCN.

[0102] In the above-described method for manufacturing a semiconductor device, the contact opening CH2 is formed simultaneously with the other contact openings CH1, CH3, and CH4, thereby preventing an increase in the number of steps for forming the contact openings CH1 to CH4.

[0103] Furthermore, when forming the contact openings CH1 to CH4, after the trench emitter electrode TEE is exposed at the bottom of the contact opening CH1, the insulating film EIF interposed between the trench emitter electrode TEE and the base diffusion layer BDR is also etched at the same time until the trench gate extraction electrode TGI is exposed at the bottom of the contact opening CH2, causing the upper surface of the insulating film EIF to recede.

[0104] This increases the area of ​​the exposed base diffusion layer BDR, increases the contact area between the shared contact member CCN and the base diffusion layer BDR, and reduces the contact resistance between the shared contact member CCN and the base diffusion layer BDR. As a result, this can be achieved in the process of forming the contact openings CH1 to CH4 without adding a separate process for increasing the contact area, which can contribute to reducing production costs.

[0105] In addition, even in the case where a natural oxide film SSM is formed due to the formation of a seam in the polysilicon film PSF (see Figures 23 to 25), the protruding natural oxide film SSM can be finally removed by performing an isotropic dry etching process using a gas containing CF4.

[0106] Furthermore, even in the case where a natural oxide film SSM is formed due to the etching back process being performed on the polysilicon film PSF (see Figures 26 to 28), the protruding natural oxide film SSM can be finally removed by performing an isotropic dry etching process using a gas containing CF4.

[0107] Embodiment 3 Here, an example of an EGE type semiconductor device will be described. The EGE type semiconductor device SED is used for applications requiring high speed. As shown in Fig. 37, in the cell region CER, one trench emitter electrode TEE (first trench electrode), a trench gate electrode TGE (third trench electrode), and another trench emitter electrode TEE are formed.

[0108] The one trench emitter electrode TEE, the trench gate electrode TGE, and the other trench emitter electrode TEE are formed at a distance (spacing L1) from each other, with the trench gate electrode TGE located between the one trench emitter electrode TEE and the other trench emitter electrode TEE. Note that other configurations are similar to those of the semiconductor device SED shown in Figures 2 and 3, and therefore the same members are denoted by the same reference numerals, and their description will not be repeated unless necessary.

[0109] In the semiconductor device SED described above, it is assumed that a natural oxide film SSM is formed on the surface of the polysilicon film, particularly when the trench gate extraction electrode TGI is formed. When the natural oxide film SSM is formed, a desired etching process is performed so that the natural oxide film SSM does not protrude beyond the upper surface of the trench gate extraction electrode TGI (the upper surface of the polysilicon film).

[0110] Next, an example of a manufacturing method of the semiconductor device SED described above will be described. The semiconductor device SED is manufactured by substantially the same manufacturing method as the manufacturing method of the semiconductor device SED described in the first embodiment, except that the layout pattern of the trench gate electrode TGE (trench TRC) and the trench emitter electrode TEE (trench TRC) is different from the layout pattern of the trench gate electrode TGE and the trench emitter electrode TEE in the semiconductor device SED shown in FIG.

[0111] In the above-described semiconductor device SED, it is assumed that a native oxide film SSM is formed on the polysilicon film PSF, and that the native oxide film SSM protrudes from the upper surface of the trench gate extraction electrode TGI. In this case, as in the first embodiment, the native oxide film SSM protruding from the upper surface of the trench gate extraction electrode TGI is finally removed by an isotropic dry etching process using a gas containing CF4 (see FIG. 17). By removing the protruding native oxide film SSM, the native oxide film SSM is no longer positioned beyond the upper surface of the trench gate extraction electrode TGI.

[0112] 37, the gate lead contact member GCN comes into good contact with the trench gate lead electrode TGI. As a result, it is possible to suppress an increase in contact resistance between the trench gate lead electrode TGI and the gate lead contact member GCN.

[0113] In each embodiment, the trench gate extraction electrode TGI and the like have been described as being formed of a polysilicon film PSF as a conductive film. The conductive film is not limited to the polysilicon film PSF, and as long as it is a conductive film on which a natural oxide film is formed, the increase in contact resistance can be suppressed by applying the above-described method.

[0114] In addition, although the case of removing the native oxide film SSM as residue has been described, it is also possible to remove foreign matter such as oxide or silicon attached to the upper surface of the trench gate extraction electrode TGI, etc. Furthermore, although the case of removing the native oxide film SSM by an isotropic dry etching process using a gas containing CF4 has been described, the gas is not limited to one containing CF4 as long as it can remove the native oxide film SSM.

[0115] The semiconductor devices and manufacturing methods thereof described in the respective embodiments can be variously combined as necessary, and the dependent claims are intended to correspond to such combinations.

[0116] The invention made by the inventor has been specifically described above based on an embodiment, but it goes without saying that the present invention is not limited to the above embodiment and can be modified in various ways without departing from the gist of the invention. [Explanation of symbols]

[0117] SED semiconductor device, CER cell region, MGR gate wiring lead-out region, PDR peripheral element region, MEE emitter electrode, MGE gate electrode, MGI gate lead-out line, SUB semiconductor substrate, TRC trench, GIF insulating film, TGE trench gate electrode, EIF insulating film, TEE trench emitter electrode, SDR source diffusion layer, BDR base diffusion layer, PPR P+ layer, HBR hole barrier layer, FPR floating diffusion layer, NBR N buffer layer, CDR collector diffusion layer, NSR N-type region, BEL collector electrode, CIL interlayer insulating film, CH1 contact opening, CCN common contact material, WPG tungsten plug, BME barrier metal, GDC gate contact material, CH2 contact opening, GCN gate lead-out contact material, TGI trench gate lead-out electrode, TGN Part 1, TGW Part 2, TRCW trench, CH3 contact opening, DCN contact area, PIC wiring, MPL Conductive layer, SOF1 silicon oxide film, NR N-type region, PR P-type region, IF insulating film, PSF, PS1, PS2 polysilicon film, SSM native oxide film, SL seam, TK thickness difference, HLD silicon oxide film, PSF2 polysilicon film, PHR1 photoresist, SOF2 silicon oxide film, PHR2 photoresist, RES residue, BME barrier metal layer, WF tungsten film, W1 first width, W2 second width, L1, L2, L3 spacing, WC opening width, DC opening depth.

Claims

1. (a) forming a first trench having a first width and a second trench having a second width wider than the first width in a semiconductor substrate having a first main surface and a second main surface opposite the first main surface; (b) sequentially stacking and filling the first trench with a first conductive film and a second conductive film to form a first trench electrode and a second trench electrode, respectively; (c) forming an interlayer insulating film on the first main surface; (d) forming a first contact opening that penetrates the interlayer insulating film and exposes a portion of the first trench electrode and a portion of the first main surface, and a second contact opening that penetrates the interlayer insulating film and exposes the second trench electrode; (e) etching the exposed upper surface of the first trench electrode, a portion of the first main surface, and the upper surface of the second trench electrode; (f) filling the first contact opening and the second contact opening with a contact material; and The step (e) is (e1) recessing an upper surface of the first trench electrode in the first contact opening, and an upper surface of the second trench electrode and a portion of the first main surface in the second contact opening, in a thickness direction of the semiconductor substrate; (e2) removing residues remaining in the first contact opening and the second contact opening after the step (e1).

2. The method for manufacturing a semiconductor device according to claim 1, wherein in step (e2), the removal of the residue is carried out by isotropic dry etching using a gas containing CF 4 .

3. A method for manufacturing a semiconductor device as described in claim 1, wherein in step (b), a natural oxide film is formed between the first conductive film and the second conductive film, and the residue removed in step (e2) is part of the natural oxide film.

4. A method for manufacturing a semiconductor device as described in claim 1, wherein in step (d), the first contact opening is formed so as to straddle a portion of the first trench electrode and a portion of the first main surface in a planar view.

5. The semiconductor substrate is of a first conductivity type, (g) before the step (c), further comprising a step of forming a first impurity region of a second conductivity type opposite to the first conductivity type in the first main surface, the first impurity region being in contact with the first trench; 2. The method for manufacturing a semiconductor device according to claim 1, wherein in the step (d), a part of the first main surface of the semiconductor substrate is included in the first impurity region.

6. (b1) A method for manufacturing a semiconductor device as described in claim 1, further comprising the step of performing an etch-back process in the process of sequentially stacking the first conductive film and the second conductive film in the (b) step.

7. A method for manufacturing a semiconductor device as described in claim 1, wherein the first conductive film and the second conductive film are polysilicon films.

8. In the step (b), the first trench electrode is embedded in the first trench via a first insulating film; 2. The method for manufacturing a semiconductor device according to claim 1, wherein in the step (e), an upper surface of said first insulating film exposed at the bottom of said first contact opening is recessed.

9. A method for manufacturing a semiconductor device as described in claim 1, wherein in step (d), the first contact opening and the second contact opening are formed simultaneously.

10. In the step (a), a third trench is further formed, the third trench having the first width, contacting a portion of the first main surface of the semiconductor substrate and spaced apart from the first trench by a portion of the first main surface therebetween; 2. The method for manufacturing a semiconductor device according to claim 1, wherein in the step (b), the first conductive film and the second conductive film are stacked in order to fill the third trench, thereby forming a third trench electrode.

11. In the step (a), a fourth trench having the first width, contacting a portion of the first main surface of the semiconductor substrate, and separated from the first trench with a portion of the first main surface interposed therebetween; a fifth trench and a sixth trench are further formed, the fifth trench and sixth trench having the first width and spaced apart from each other; in the step (b), the first conductive film and the second conductive film are sequentially stacked and filled into the fourth trench, the fifth trench, and the sixth trench, and a fourth trench electrode, a fifth trench electrode, and a sixth trench electrode are further formed, respectively; In the step (d), a third contact opening is further formed which penetrates the interlayer insulating film and exposes a portion of the first main surface of the semiconductor substrate located between the fifth trench electrode and the sixth trench electrode; In the step (f), the contact member is embedded in the third contact opening; 2. The method for manufacturing a semiconductor device according to claim 1, wherein in the step (e1), a part of said first main surface within said third contact opening is recessed.

12. A method for manufacturing a semiconductor device as described in claim 11, wherein in step (d), the first contact opening, the second contact opening, and the third contact opening are formed simultaneously.

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