Correction system for eliminating the effects of phase noise and analog-to-digital conversion device including the same

Abstract

To provide a correction system.SOLUTION: A correction system includes a jitter-capturing analog-to-digital converter (ADC) that samples a sampled clock signal on the basis of an operating clock signal to generate a first quantized output, a correction value generation circuit used to receive the first quantization output and the second quantization output of the corrected ADC and generate a correction value, and a first arithmetic circuit coupled to the correction value generation circuit and subtracting the correction value from the second quantization output to generate a third quantization output, and the operating clock signal is used to drive sampling of the corrected ADC, and the correction value is related to the phase noise of the operating clock signal.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a correction technique for an analog-to-digital converter (ADC), and more particularly to a correction system for removing the effects of phase noise and an analog-to-digital conversion device including the correction system. [Background technology]

[0002] Phase-locked loops are commonly used in various high-speed circuits. For example, phase-locked loops are used for frequency synthesis, generating an output signal with a frequency that is an integer multiple of the input signal frequency. The clock signal generated by a phase-locked loop can be used to drive sampling by an analog-to-digital converter (ADC). However, it generally has jitter and cannot meet the clock signal stability requirements of high-speed ADCs. Meanwhile, clock generators capable of generating low-jitter signals, such as crystal oscillators, are generally expensive. Summary of the Invention [Problem to be solved by the invention]

[0003] In view of this, how to improve the sampling error caused by jitter phenomenon of the clock signal of the analog-to-digital converter (ADC) is a problem that must be solved. [Means for solving the problem]

[0004] The present disclosure provides a correction system including a jitter capture analog-to-digital converter (ADC) for sampling a sampled clock signal based on an operating clock signal to generate a first quantized output, a correction value generation circuit used to receive the first quantized output and a second quantized output of the corrected ADC and generate a correction value, and a first calculation circuit coupled to the correction value generation circuit for subtracting the correction value from the second quantized output to generate a third quantized output, wherein the operating clock signal is used to drive the sampling of the corrected ADC and the correction value is related to phase noise of the operating clock signal.

[0005] The present disclosure provides a correction system including a jitter capture ADC for sampling a sampled clock signal based on an operating clock signal to generate a first quantized output, a correction value generation circuit used to receive the first quantized output and a second quantized output of the corrected ADC and generate a correction value, and a first calculation circuit, wherein the sampled clock signal is used to drive the sampling of the corrected ADC, and the correction value is related to the phase noise of the sampled clock signal.

[0006] The present disclosure provides an analog-to-digital conversion device comprising: a clock generator; at least one corrected ADC, each used to generate a second quantized output, one of which samples based on the output of the clock generator to generate the second quantized output; and a correction system that receives an input of the clock generator, the output of the clock generator, and the second quantized output of one of the at least one corrected ADC, generates a correction value, and corrects the second quantized output of each corrected ADC based on the correction value to generate a third quantized output, wherein the correction value is related to the phase noise of the output of the clock generator. [Effects of the Invention]

[0007] One of the advantages of the above-described correction system and analog-to-digital conversion device is that it can improve or eliminate sampling errors caused by phase noise in the clock signal at the quantized output. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a simplified functional block diagram of an analog-to-digital conversion device according to one embodiment of the present disclosure. [Figure 2] FIG. 1 is a simplified functional block diagram of a correction value generation circuit according to one embodiment of the present disclosure. [Figure 3] 1 is a simplified functional block diagram of an analog-to-digital conversion device according to one embodiment of the present disclosure. [Figure 4] 1 is a simplified functional block diagram of an analog-to-digital conversion device according to one embodiment of the present disclosure. [Figure 5] 1 is a simplified functional block diagram of an analog-to-digital conversion device according to one embodiment of the present disclosure. [Figure 6] 1 is a simplified functional block diagram of an analog-to-digital conversion device according to one embodiment of the present disclosure. [Figure 7] 1 is a simplified functional block diagram of an analog-to-digital conversion device according to one embodiment of the present disclosure. [Figure 8] 1 is a simplified functional block diagram of an analog-to-digital conversion device according to one embodiment of the present disclosure. [Figure 9] 1 is a simplified functional block diagram of an analog-to-digital conversion device according to one embodiment of the present disclosure. [Figure 10] FIG. 10 is a spectrum diagram of a quantized output according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0009] The embodiments of the present disclosure are described below in conjunction with the accompanying drawings, in which like numbers represent the same or similar elements or methods or steps.

[0010] FIG. 1 is a simplified functional block diagram of an analog-to-digital conversion apparatus 100 according to one embodiment of the present disclosure. The analog-to-digital conversion apparatus 100 includes a clock generator 110, a corrected analog-to-digital converter (ADC) 120, and a correction system 130. The clock generator 110 receives a clock signal CKin and generates a clock signal CKs_0. In one embodiment, the frequency of the clock signal CKin is M times the frequency of the clock signal CKs_0, i.e., the period of the clock signal CKs_0 is M times the period of the clock signal CKin, where M is a positive number (e.g., 4 / 19). In one embodiment, the clock generator 110 includes a phase-locked loop. The corrected ADC 120 is coupled to the clock generator 110 and the correction system 130. The corrected ADC 120 samples an input signal In_0 based on the clock signal CKs_0 and outputs a corrected quantized output Qtb_0 to the correction system 130. The correction system 130 is used to correct the quantized output Qtb_0 to improve or eliminate the sampling error caused by the phase noise of the clock signal CKs_0 in the quantized output Qtb_0, and further generate the quantized output Qout_0. The phase noise may be understood as a signal jitter phenomenon in the time domain of the clock signal CKs_0. In one embodiment, the sampling error is the voltage difference between the accurate sampling result of the corrected ADC 120 and the actual sampling result.

[0011] In an embodiment, the quantized output Qtb_0 of the corrected ADC 120 may be expressed by the following Equation 1, which can be rewritten as the following Equation 2 based on the addition theorem of trigonometric functions. In Equation 1 and Equation 2, the symbol "Fin_0" represents the frequency of the input signal In_0, the symbol "n" represents the n-th sampling, where n is a positive integer, the symbol "Ts" represents the period of the clock signal CKs_0, and the symbol "t_jn" represents the sampling time error caused by the phase noise of the clock signal CKs_0 of the corrected ADC 120.

number

number

[0012] In the following paragraphs, for brevity, the exact sampling result of the corrected ADC 120 in the equation (i.e., sin[2×π×Fin_0×(n×Ts)] in Equation 2) is represented by the symbol “X(n).” In one embodiment, Equation 2 can be further rewritten as the following Equation 3 because the value of the sampling time error t_jn due to phase noise is typically very small, e.g., close to zero. It should be noted that for high-speed ADCs, the sampled signals typically have frequencies on the megahertz (MHz) or gigahertz (GHz) level, so even a small sampling time error t_jn can cause the ADC to produce significantly different outputs. As can be seen from Equation 3, the quantized output Qtb_0 is essentially the sum of (1) the exact sampling result (symbol “X(n)”) and (2) the product of the slope of the exact sampling result (symbol “dX(n) / dt”) and the sampling time error t_jn.

number

[0013] In one embodiment, the correction system 130 includes a jitter capture ADC 132, a correction value generation circuit 134, and an arithmetic circuit 136. The jitter capture ADC 132 is used to sample the clock signal CKin based on the clock signal CKs_0 to generate a quantized output Qjit, that is, to sample the input of the clock generator 110 based on the output of the clock generator 110.

[0014] The correction value generation circuit 134 is used to receive the quantized output Qjit from the jitter capture ADC 132 and the quantized output Qtb_0 from the corrected ADC 120. The correction value generation circuit 134 is further used to generate a correction value Vc based on the quantized outputs Qjit and Qtb_0. In one embodiment, the correction value Vc is related to the phase noise of the clock signal CKs_0, that is, related to the sampling time error t_jn in the above-mentioned "Equation 3." The calculation circuit 136 is coupled to the corrected ADC 120 and the correction value generation circuit 134, and is used to subtract the correction value Vc from the quantized output Qtb_0 to correct the sampling error and obtain a quantized output Qout_0, which is substantially the accurate sampling result of the corrected ADC 120.

[0015] Next, the calculation form of the correction voltage Vc will be described. For ease of understanding, in the embodiments in the following paragraphs, M is set as a positive integer, but the present disclosure is not limited thereto. In one embodiment, the quantized output Qjit of the jitter capture ADC 132 may be expressed by the following Equation 4, and Equation 4 can be rewritten as the following Equation 5 based on the addition theorem of trigonometric functions. In Equation 4 and Equation 5, the symbol "Fs" represents the frequency of the clock signal CKs_0, while "M×Fs" is the frequency of the clock signal CKin.

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[0016] In an embodiment where M is a positive integer, Equation 5 can be rewritten as the following Equation 6: As can be seen from Equation 6, since the period of clock signal CKs_0 and M are known parameters, the quantized output Qjit is essentially a constant (e.g., 0) plus a constant multiple of the sampling time error t_jn.

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[0017] FIG. 2 is a simplified functional block diagram of a correction value generation circuit 200 according to one embodiment of the present disclosure. The correction value generation circuit 200 can be used to implement the correction value generation circuit 134 of FIG. 1. The correction value generation circuit 200 includes an error capture circuit 210, a differentiation circuit 220, and an arithmetic circuit 230. The error capture circuit 210 receives the quantized output Qjit from the jitter capture ADC 132 and calculates the sampling time error t_jn from the quantized output Qjit based on the period of the clock signal CKs_0. In one embodiment, the error capture circuit 210 obtains the product of the sampling time error t_jn and a constant from the quantized output Qjit, and then obtains the sampling time error t_jn. As can be seen from Equation 6, this constant is 2×π×M×(1 / Ts), which is negatively correlated with the period of the clock signal CKs_0 and positively correlated with M.

[0018] The differentiating circuit 220 receives the quantized output Qtb_0 from the corrected ADC 120 and calculates the slope of the quantized output Qtb_0. In one embodiment, the differentiating circuit 220 calculates the slope based on the (n-1)th and (n+1)th sampling results of the quantized output Qtb_0. However, the present disclosure is not limited thereto, and the (n-2)th and (n+2)th sampling results, or even the (n-3)th and (n+3)th sampling results, may be used. Because the influence of jitter in the clock signal CKs_0 may be ignored within a short time interval, the (n-1)th and (n+1)th sampling results may be regarded as accurate sampling results (hereinafter, represented by the symbols "X(n-1)" and "X(n+1)," respectively). Therefore, the slope of the quantized output Qtb_0 calculated by the differentiating circuit 220 is substantially the slope of the accurate sampling result in Equation 3. The differentiating circuit 220 can calculate the slope using the following "Equation 7."

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[0019] The calculation circuit 230 is used to multiply the sampling time error t_jn by the slope of the accurate sampling result to obtain a correction value Vc, i.e., Vc=(dX(n) / dt)×t_jn. Then, the calculation circuit 230 can provide the correction value Vc to the calculation circuit 136 in FIG.

[0020] 3 is a simplified functional block diagram of an analog-to-digital conversion apparatus 300 according to one embodiment of the present disclosure. The analog-to-digital conversion apparatus 300 includes a clock generator 310, a corrected ADC 320, and a correction system 330. The analog-to-digital conversion apparatus 300 is similar to the analog-to-digital conversion apparatus 100 of FIG. 1, and for the sake of brevity, only the differences will be described below.

[0021] The correction system 330 includes a jitter capture ADC 332, a correction value generation circuit 334, an arithmetic circuit 336, and a signal processing circuit 338. The signal processing circuit 338 is coupled between the input of the clock generator 310 and the input of the jitter capture ADC 332. The signal processing circuit 338 receives the clock signal CKin and performs one or more signal processing operations, such as amplification, frequency division, and slope adjustment, on the clock signal CKin before the clock signal CKin is input to the jitter capture ADC 332. In one embodiment, the clock signal CKin processed by the signal processing circuit 338 has a ramp waveform or a sawtooth waveform. The signal processing circuit 338 controls the waveform and frequency of the clock signal CKin to control the value of M, improve the signal-to-noise ratio of the clock signal CKin, stabilize the values ​​of the constants in Equation 6, and improve the accuracy of the sampling time error t_jn obtained by the correction system 330.

[0022] The jitter capture ADC 332 is used to sample the clock signal CKin output by the signal processing circuit 338 based on the clock signal CKs_0, generate a quantized output Qjit, and output it to the correction value generation circuit 334. The elements, connections, and operations of the correction value generation circuit 334 and the calculation circuit 336 are similar to those of the correction value generation circuit 134 and the calculation circuit 136 in FIG. 1, respectively, and will not be described again here for the sake of brevity.

[0023] FIG. 4 is a simplified functional block diagram of an analog-to-digital conversion device 400 according to one embodiment of the present disclosure. The analog-to-digital conversion device 400 includes a clock generator 410, a plurality of corrected ADCs 420_0 through 420_n-1, and a correction system 430. The clock generator 410 is similar to the clock generator 110 of FIG. 1 and will not be described again here for brevity. The corrected ADCs 420_0 through 420_n-1 are adapted to receive input signals In_0 through In_n-1, respectively, although the present disclosure is not limited thereto and do not need to receive different input signals. The corrected ADCs 420_0 through 420_n-1 are adapted to sample the input signals In_0 through In_n-1 based on a clock signal CKs_0 to generate quantized outputs Qtb_0 through Qtb_n-1, respectively. That is, all of the corrected ADCs 420_0 to 420_n-1 perform sampling based on the clock signal CKs_0.

[0024] The correction system 430 is used to correct the quantized outputs Qout_0 to Qout_n-1 to improve or eliminate sampling errors in the quantized outputs Qout_0 to Qout_n-1 caused by phase noise of the clock signal CKs_0. The correction system 430 includes a jitter capture ADC 432, a correction value generation circuit 434, and a plurality of arithmetic circuits 436_0 to 436_n-1. The arithmetic circuits 436_0 to 436_n-1 are used to receive the quantized outputs Qtb_0 to Qtb_n-1, respectively, and to receive a correction value Vc from the correction value generation circuit 434. The arithmetic circuits 436_0 to 436_n-1 are further used to subtract the correction value Vc from each of the quantized outputs Qtb_0 to Qtb_n-1 to generate the quantized outputs Qout_0 to Qout_n-1, respectively. The quantized outputs Qout_0 to Qout_n-1 are essentially accurate sampling results of the corrected ADCs 420_0 to 420_n-1, respectively.

[0025] The elements, connections, and operations of the jitter capture ADC 432 and the correction value generation circuit 434 are similar to those of the jitter capture ADC 132 and the correction value generation circuit 134 in Figure 1, respectively, and will not be described again here for the sake of brevity. It should be noted that the correction value generation circuit 434 can calculate the correction value Vc using any of the quantized outputs Qtb_0 to Qtb_n-1.

[0026] 5 is a simplified functional block diagram of an analog-to-digital conversion device 500 according to one embodiment of the present disclosure. The analog-to-digital conversion device 500 includes a clock generator 510, a plurality of corrected ADCs 520_0 through 520_n-1, and a correction system 530. The correction system 530 includes a jitter capture ADC 532, a correction value generation circuit 534, and a plurality of arithmetic circuits 536_0 through 536_n-1. Because the analog-to-digital conversion device 500 is similar to the analog-to-digital conversion device 400 of FIG. 4, only the differences will be described below.

[0027] The corrected ADCs 520_0 to 520_n-1 are used to sample the input signal In_0 based on a plurality of clock signals CKs_0 to CKs_n-1, respectively, and generate quantized outputs Qtb_0 to Qtb_n-1, respectively. The clock signals CKs_0 to CKs_n-1 are time-interleaved clock signals. In one embodiment, the analog-to-digital conversion device 500 can be used to achieve a time-interleaved ADC and may include a multiplexer (not shown in FIG. 5) to generate digital output signals based on the quantized outputs Qout_0 to Qout_n-1. The corrected ADC 520_0 and the jitter capture ADC 532 sample based on the clock signal CKs_0. In one embodiment, the phase of the clock signal CKs_0 leads the phases of the other time-interleaved clock signals CKs_1 to CKs_n-1.

[0028] In an embodiment, the correction system 430 of Fig. 4 or the correction system 530 of Fig. 5 further includes a signal processing circuit (not shown), which is used to perform one or more signal processing operations such as amplification, frequency division, and slope adjustment on the clock signal CKin before the clock signal CKin is input to the jitter capture ADC 432 of Fig. 4 or the jitter capture ADC 532 of Fig. 5. In addition, the clock signal CKs_0 provided to the jitter capture ADC 432 of Fig. 4 or the jitter capture ADC 532 of Fig. 5 by the signal processing circuit may have a ramp waveform or a sawtooth waveform.

[0029] 6 is a simplified functional block diagram of an analog-to-digital conversion apparatus 600 according to one embodiment of the present disclosure. The analog-to-digital conversion apparatus 600 includes a clock generator 610, a corrected ADC 620, and a correction system 630. The clock generator 610 and the corrected ADC 620 are similar to the clock generator 110 and the corrected ADC 120 of FIG. 1, respectively, and for brevity, will not be described again here. The correction system 630 is used to correct the quantized output Qtb_0 to improve or eliminate sampling errors in the quantized output Qtb_0 due to phase noise of the clock signal CKs_0, and further generate the quantized output Qout_0.

[0030] The correction system 630 includes a jitter capture ADC 632, a correction value generation circuit 634, and an arithmetic circuit 636. The jitter capture ADC 632 is used to sample the clock signal CKs_0 based on the clock signal CKin to generate a quantized output Qjit, that is, to sample the output of the clock generator 610 based on the input of the clock generator 610.

[0031] The correction value generation circuit 634 is used to receive the quantized output Qjit from the jitter capture ADC 632 and the quantized output Qtb_0 from the corrected ADC 620. The correction value generation circuit 634 is further used to generate a correction value Vc based on the quantized outputs Qjit and Qtb_0. In one embodiment, the correction value Vc is related to the phase noise of the clock signal CKs_0, i.e., the sampling error time t_jn in Equation 3 above. The calculation circuit 636 is coupled to the corrected ADC 620 and the correction value generation circuit 634, and is used to subtract the correction value Vc from the quantized output Qtb_0 to correct the sampling error and obtain the quantized output Qout_0, which is essentially the accurate sampling result of the corrected ADC 620.

[0032] Next, the calculation form of the correction voltage Vc will be described. In an embodiment, the quantized output Qjit of the jitter capture ADC 632 may be expressed by the following Equation 8, and Equation 8 can be rewritten as the following Equation 9 based on the addition theorem of trigonometric functions. In Equation 8 and Equation 9, the symbol "Tcin" represents the period of the clock signal CKin, and "(1 / M)×Tcin" is the period of the clock signal CKs_0.

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[0033] In an embodiment where 1 / M is a positive integer, Equation 9 can be rewritten as the following Equation 10: As can be seen from Equation 10, since the period of clock signal CKin and M are known parameters, the quantized output Qjit is essentially a constant (e.g., 0) plus a constant multiple of the sampling time error t_jn.

number

[0034] In one embodiment, the correction value generation circuit 634 can be implemented by the correction value generation circuit 200 of Figure 2. Referring simultaneously to Figures 2 and 6, in this case, the error capture circuit 210 can be used to receive the quantized output Qjit from the jitter capture ADC 632 and calculate the sampling time error t_jn from the quantized output Qjit based on the period of the clock signal CKin. In one embodiment, the error capture circuit 210 obtains the product of the sampling time error t_jn and a constant from the quantized output Qjit, and further obtains the sampling time error t_jn. As can be seen from Equation 10, this constant is 2 x π x (1 / M) x (1 / Tcin), that is, it is negatively correlated with the period of the clock signal CKin and negatively correlated with M.

[0035] Next, the correction value generating circuit 634 calculates the correction value Vc based on the sampling time error t_jn, and other calculation processes are similar to those described above in conjunction with FIG. 2 and will not be described again here for brevity. The correction value generating circuit 634 can provide the correction value Vc to the calculation circuit 636.

[0036] 7 is a simplified functional block diagram of an analog-to-digital conversion apparatus 700 according to one embodiment of the present disclosure. The analog-to-digital conversion apparatus 700 includes a clock generator 710, a corrected ADC 720, and a correction system 730. The analog-to-digital conversion apparatus 700 is similar to the analog-to-digital conversion apparatus 600 of FIG. 6, and for the sake of brevity, only the differences will be described below.

[0037] The correction system 730 includes a jitter capture ADC 732, a correction value generation circuit 734, an arithmetic circuit 736, and a signal processing circuit 738. The signal processing circuit 738 is coupled between the output of the clock generator 710 and the input of the jitter capture ADC 732. The signal processing circuit 738 receives the clock signal CKs_0 and performs one or more signal processing operations, such as amplification, frequency division, and slope adjustment, on the clock signal CKs_0 before the clock signal CKs_0 is input to the jitter capture ADC 732. In one embodiment, the clock signal CKs_0 processed by the signal processing circuit 738 has a ramp waveform or a sawtooth waveform. The signal processing circuit 738 controls the waveform and frequency of the clock signal CKs_0 to control the value of M, improve the signal-to-noise ratio of the clock signal CKs_0, stabilize the values ​​of the constants in Equation 10, and improve the accuracy of the sampling time error t_jn obtained by the correction system 730.

[0038] The jitter capture ADC 732 samples the clock signal CKs_0 output by the signal processing circuit 738 based on the clock signal CKin, and generates a quantized output Qjit, which can be output to the correction value generation circuit 734. The elements, connections, and operations of the correction value generation circuit 734 and the arithmetic circuit 736 are similar to those of the correction value generation circuit 634 and the arithmetic circuit 636 in Figure 6, respectively, and will not be described again here for the sake of brevity.

[0039] FIG. 8 is a simplified functional block diagram of an analog-to-digital conversion device 800 according to one embodiment of the present disclosure. The analog-to-digital conversion device 800 includes a clock generator 810, a plurality of corrected ADCs 820_0 through 820_n-1, and a correction system 830. The clock generator 810 is similar to the clock generator 110 of FIG. 1 and will not be described again here for brevity. The corrected ADCs 820_0 through 820_n-1 are adapted to receive input signals In_0 through In_n-1, respectively, although the present disclosure is not limited thereto and the corrected ADCs 820_0 through 820_n-1 do not need to receive different input signals. The corrected ADCs 820_0 through 820_n-1 are adapted to sample the input signals In_0 through In_n-1 based on a clock signal CKs_0 to generate quantized outputs Qtb_0 through Qtb_n-1, respectively. That is, all of the corrected ADCs 820_0 to 820_n-1 perform sampling based on the clock signal CKs_0.

[0040] The correction system 830 is used to correct the quantized outputs Qout_0 to Qout_n-1 to improve or eliminate sampling errors in the quantized outputs Qout_0 to Qout_n-1 caused by phase noise of the clock signal CKs_0. The correction system 830 includes a jitter capture ADC 832, a correction value generation circuit 834, and a plurality of arithmetic circuits 836_0 to 836_n-1. The arithmetic circuits 836_0 to 836_n-1 are used to receive the quantized outputs Qtb_0 to Qtb_n-1, respectively, and to receive a correction value Vc from the correction value generation circuit 834. The arithmetic circuits 836_0 to 836_n-1 are further used to subtract the correction value Vc from each of the quantized outputs Qtb_0 to Qtb_n-1 to generate the quantized outputs Qout_0 to Qout_n-1, respectively. The quantized outputs Qout_0 to Qout_n-1 are essentially accurate sampling results of the corrected ADCs 820_0 to 820_n-1, respectively.

[0041] The elements, connections, and operations of the jitter capture ADC 832 and the correction value generation circuit 834 are similar to those of the jitter capture ADC 632 and the correction value generation circuit 634 in Figure 6, respectively, and will not be described again here for the sake of brevity. It should be noted that the correction value generation circuit 834 can calculate the correction value Vc using any of the quantized outputs Qtb_0 to Qtb_n-1.

[0042] 9 is a simplified functional block diagram of an analog-to-digital conversion device 900 according to one embodiment of the present disclosure. The analog-to-digital conversion device 900 includes a clock generator 910, a plurality of corrected ADCs 920_0 through 920_n-1, and a correction system 930. The correction system 930 includes a jitter capture ADC 932, a correction value generation circuit 934, and a plurality of arithmetic circuits 936_0 through 936_n-1. Because the analog-to-digital conversion device 900 is similar to the analog-to-digital conversion device 800 of FIG. 8, only the differences will be described below.

[0043] The corrected ADCs 920_0 to 920_n-1 are used to sample the input signal In_0 based on a plurality of clock signals CKs_0 to CKs_n-1, respectively, to generate quantized outputs Qtb_0 to Qtb_n-1, respectively. The clock signals CKs_0 to CKs_n-1 are time-interleaved clock signals. That is, in one embodiment, the analog-to-digital conversion device 900 can be used to achieve a time-interleaved ADC and may include a multiplexer (not shown in FIG. 9 ) to generate digital output signals based on the quantized outputs Qout_0 to Qout_n-1. The corrected ADC 920_0 samples based on the clock signal CKs_0. In one embodiment, the phase of the clock signal CKs_0 leads the phases of the other time-interleaved clock signals CKs_1 to CKs_n-1.

[0044] In an embodiment, the correction system 830 of Figure 8 or the correction system 930 of Figure 9 further includes a signal processing circuit (not shown), which is used to perform one or more signal processing operations such as amplification, frequency division, and slope adjustment on the clock signal CKs_0 before the clock signal CKs_0 is input to the jitter capture ADC 832 of Figure 8 or the jitter capture ADC 932 of Figure 9. In addition, the clock signal CKs_0 provided to the jitter capture ADC 832 of Figure 8 or the jitter capture ADC 932 of Figure 9 by the signal processing circuit may have a ramp waveform or a sawtooth waveform.

[0045] In the above-described embodiments, the corrected ADC and the jitter capture ADC may have the same or different circuit structures.

[0046] 1 and 10, FIG. 10 is a schematic diagram of a spectrum of a quantized output according to one embodiment of the present disclosure. In the embodiment of FIG. 10, the frequency of the clock signal CKin is 52 MHz, and the frequency of the clock signal CKs_0 is 247 MHz. Spectrum 10, which has a ramp shape, corresponds to the corrected quantized output Qtb_0 in FIG. 1. The ramp shape of spectrum 10 indicates that the quantized output Qtb_0 has sampling errors due to the influence of phase noise. Meanwhile, spectrum 20 corresponds to the corrected quantized output Qout_0 in FIG. 1. The fact that spectrum 20 does not have a ramp shape proves that the corrected quantized output Qout_0 is not or barely affected by phase noise.

[0047] In the specification and claims, certain terms refer to specific elements. However, those skilled in the art should understand that similar elements may be referred to by different nouns. The specification and claims do not distinguish between elements based on differences in name, but on functional differences between elements. The term "comprises" used in the specification and claims is an open term and should be interpreted as meaning "including, but not limited to." Furthermore, the term "coupled" includes any direct or indirect connection means. Therefore, when a first element is said to be coupled to a second element in this specification, it means that the first element can be directly connected to the second element by an electrical connection or a signal connection form such as wireless transmission or optical transmission, or can be indirectly electrically or signal-connected to the second element by another element or connection means.

[0048] As used herein, the term "and / or" includes any combination of one or more of the listed items. Also, unless otherwise indicated in the specification, any singular term also includes the plural.

[0049] The foregoing is merely a preferred embodiment of the present disclosure, and various modifications and equivalent changes may be made to the structure of the present disclosure without departing from the scope or spirit of the present disclosure. In summary, any modifications and equivalent changes made to the present disclosure within the scope of the following claims are included within the scope of the present disclosure. [Explanation of symbols]

[0050] 100, 300, 400, 500, 600, 700, 800, 900 Analog-to-Digital Conversion Device 110, 310, 410, 510, 610, 710, 810, 910 Clock Generator 120, 320, 420, 520, 620, 720, 820, 920 Corrected Analog-to-Digital Converter (ADC) 130, 330, 430, 530, 630, 730, 830, 930 Correction System 132, 332, 432, 532, 632, 732, 832, 932 Jitter Capture ADC 134, 334, 434, 534, 634, 734, 834, 934 Correction value generation circuit 136, 336, 636, 736 arithmetic circuit 436_0~436_n-1 arithmetic circuit 536_0~536_n-1 arithmetic circuit 836_0~836_n-1 arithmetic circuit 936_0~936_n-1 arithmetic circuit 200 Correction value generation circuit 210 Error capture circuit 220 Differential circuit 230 Arithmetic circuit dX(n) / dt The slope of the exact sampling result t_jn Sampling time error 338, 738 Signal processing circuit In_0~In_n-1 Input signal Qtb_0~Qtb_n-1, Qjit, Qout_0~Qout_n-1 quantization output CKin, CKs_0 to CKs_n-1 clock signals Vc correction value 10, 20 Spectrum

Claims

1. a jitter capture analog-to-digital converter (ADC) for sampling the sampled clock signal based on the operating clock signal to generate a first quantized output; a correction value generating circuit that receives the first quantized output and the second quantized output of the corrected ADC and is used to generate a correction value; a first arithmetic circuit coupled to the correction value generation circuit for subtracting the correction value from the second quantized output to generate a third quantized output; the sampled clock signal is used to drive sampling of the corrected ADC, and the correction value is related to phase noise of the sampled clock signal; The correction value generating circuit an error capture circuit adapted to receive the first quantized output and obtain a sampling time error of the corrected ADC from the first quantized output; a differentiating circuit for receiving the second quantized output and calculating a slope of the second quantized output; a second arithmetic circuit for generating the correction value by multiplying the sampling time error by the slope; the sampling time error is related to the phase noise; the error capture circuit obtains a product of the sampling time error and a constant from the first quantized output, and further obtains the sampling time error, the constant being negatively correlated with the period of the operating clock signal; Compensation system.

2. 2. The correction system of claim 1, wherein the period of the sampled clock signal is 1 / M times the period of the operating clock signal, M is a positive number, and the constant is negatively correlated with M.

3. The correction system comprises:

2. The correction system of claim 1, further comprising a signal processing circuit for performing one or more of amplification, frequency division, and slope adjustment on the sampled clock signal before the sampled clock signal is input to the jitter capture ADC.

4. 4. The correction system of claim 3, wherein the operational clock signal is used as an input to a clock generator, and the sampled clock signal is generated by the clock generator based on the operational clock signal.

5. 4. The correction system according to claim 3, wherein the sampled clock signal output from the signal processing circuit has a ramp waveform or a sawtooth waveform.

6. a clock generator; at least one corrected analog-to-digital converter (ADC), each used to generate a second quantized output, one corrected ADC sampling based on the output of the clock generator to generate the second quantized output; a correction system for receiving the input of the clock generator, the output of the clock generator, and the second quantized output of the one corrected ADC of the at least one corrected ADC to generate a correction value, and correcting the second quantized output of each corrected ADC based on the correction value to generate a third quantized output; Equipped with the correction value is related to the phase noise of the output of the clock generator; the at least one corrected ADC includes a plurality of corrected ADCs, The correction system comprises: a jitter capture ADC for sampling the output of the clock generator based on the input of the clock generator to generate a first quantized output; a correction value generating circuit for receiving the first quantized output and the second quantized output of the one corrected ADC of the at least one corrected ADC and generating the correction value; a plurality of first arithmetic circuits coupled to the correction value generating circuit and coupled to the plurality of corrected ADCs, respectively, and used to subtract the correction value from the second quantized output of a corresponding one of the plurality of corrected ADCs to generate the third quantized output; Including, the output of the clock generator is a sampled clock signal and the input of the clock generator is an operating clock signal; The correction value generating circuit an error capture circuit adapted to receive the first quantized output and obtain a sampling time error of the corrected ADC from the first quantized output; a differentiating circuit for receiving the second quantized output and calculating a slope of the second quantized output; a second arithmetic circuit for generating the correction value by multiplying the sampling time error by the slope; Including, the sampling time error is related to the phase noise; the error capture circuit obtains a product of the sampling time error and a constant from the first quantized output, and further obtains the sampling time error, the constant being negatively correlated with the period of the operating clock signal; Analog-to-digital conversion device.

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