Processing equipment

Abstract

To provide a memory circuit and a processing circuit that enable parallel processing.SOLUTION: A memory circuit includes: a plurality of memory cells arranged in a matrix with a plurality of rows and columns and each having a pair of complementary memory nodes; and a plurality of bit lines connected to the memory cell arranged in the column direction, wherein at least two bit line are provided in each of the plurality of columns. The plurality of rows are divided into a plurality of blocks each having at least two rows, in each of the plurality of blocks, each of the at least two bit lines is connected to at least one of the pair of memory nodes in the memory cell provided in one of the at least two rows in the block and is not connected to the memory cells provided in the remaining rows of the at least two rows.SELECTED DRAWING: Figure 46

Description

[Technical Field]

[0001] The present invention provides Processing equipment Regarding. [Background technology]

[0002] Pseudo-nonvolatile static random access memory (SRAM) (VNR-SRAM) or ultra-low voltage (ULV) retention static random access memory (SRAM) (ULVR-SRAM) is known, which uses an inverter composed of complementary metal oxide semiconductor (CMOS) without using nonvolatile memory elements (see, for example, Patent Document 1). VNR-SRAM uses a dual-mode inverter that can switch between a Schmitt trigger (ST) mode that enables ULV retention and a boosted inverter (BI) mode that can achieve circuit performance equivalent to that of SRAM at normal voltage. This ULV retention SRAM can be used for so-called power gating (PG).

[0003] Also known is a memory circuit that uses a memory cell (NV-SRAM) that has a bistable circuit and a nonvolatile memory element (see, for example, Patent Document 2). In NV-SRAM, data from the bistable circuit is stored in the nonvolatile memory element, reducing power consumption, and when necessary, the data from the nonvolatile memory element is restored to the bistable circuit, making the data available.

[0004] Furthermore, studies are being conducted to speed up neural network processing by combining an SRAM for storing coefficients such as weighting coefficients of the neural network with a calculation circuit for product sums and evaluation functions (for example, Non-Patent Document 1). [Prior art documents] [Patent documents]

[0005] [Patent Document 1] International Publication No. 2016 / 158691 [Patent Document 2] International Publication No. 2009 / 028298 [Non-patent literature]

[0006] [Non-Patent Document 1] IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 53, pp,983-994, 2018. Summary of the Invention [Problem to be solved by the invention]

[0007] The VNR-SRAM of Patent Document 1 uses ULV retention to reduce standby power consumption without losing the stored contents of the cell. However, VNR-SRAM uses 14 or 10 transistors per memory cell (hereinafter referred to as a 14T cell or a 10T cell, respectively). This results in a first problem: the memory cell becomes larger or the cell area increases. Furthermore, reducing the number of transistors, such as in a 10T cell, reduces the stability (noise margin) of ULV retention.

[0008] Furthermore, the NV-SRAM of Patent Document 2 uses a nonvolatile memory element in the memory cell, which allows the power supply to the memory cell to be cut off during standby, thereby reducing standby power consumption. However, each memory cell uses eight transistors in addition to the nonvolatile memory element. This poses a second problem: it is difficult to miniaturize the memory cell, or the cell area increases.

[0009] In view of the first or second object, the present invention has an object to provide a memory circuit that can be miniaturized or that can have a reduced number of transistors. [Means for solving the problem]

[0010] The present invention provides a memory circuit comprising: a plurality of memory cells arranged in a matrix of a plurality of rows and a plurality of columns, each memory cell having a complementary pair of memory nodes; at least two bit lines provided in each of the plurality of columns, the plurality of bit lines connected to the memory cells arranged in the column direction; the plurality of rows being divided into a plurality of blocks, each block having at least two rows, and in each of the plurality of blocks, each of the at least two bit lines being connected to at least one of the pair of memory nodes in a memory cell provided in one of the at least two rows in the block, and not connected to a memory cell provided in the remaining row of the at least two rows. [Effects of the Invention]

[0011] According to the present invention, it is possible to provide a memory circuit that can be miniaturized or that has a reduced number of transistors. [Brief explanation of the drawings]

[0012] [Figure 1] FIG. 1 is a circuit diagram showing a loop of memory cells in a first comparative example. [Figure 2] FIG. 2 is a circuit diagram showing a cross-coupled memory cell in the first comparative example. [Figure 3] FIG. 3 is a circuit diagram showing a loop of memory cells in Comparative Example 2. In FIG. [Figure 4] FIG. 4 is a circuit diagram showing a cross-coupled memory cell in the second comparative example. [Figure 5] FIG. 5 is a circuit diagram showing a loop of memory cells in the first embodiment. [Figure 6] FIG. 6 is a circuit diagram showing a cross-coupled memory cell in the first embodiment. [Figure 7A] FIG. 7A is a block diagram of a memory array according to the first embodiment. [Figure 7B] FIG. 7B is a diagram illustrating the power switches and the selection circuit according to the first embodiment. [Figure 7C]FIG. 7C is a block diagram illustrating another example of the memory array according to the first embodiment. [Figure 8] 8(a) and 8(b) are diagrams showing SNM and standby power for WLP and WFB in the VDD retention state in Example 1. FIG. [Figure 9] 9(a) and 9(b) are diagrams showing SNM and standby power with respect to VWL in the VDD retention state and read in the read / write state in Example 1 and Comparative Example 3. FIG. [Figure 10] 10(a) to 10(c) are diagrams showing SNM in the VDD retention state and the read / write state in Example 1 and Comparative Examples 2 and 3. FIG. [Figure 11] FIG. 11 is a diagram showing the transfer characteristics of the inverter circuit in the ULV retention state of the first embodiment. [Figure 12] 12(a) and 12(b) are circuit diagrams of the bistable circuit in the first embodiment. [Figure 13] 13(a) and 13(b) are diagrams showing butterfly curves of the bistable circuits in the ULV retention state of Example 1 and Comparative Examples 2 and 3. FIG. [Figure 14] FIG. 14(a) is a diagram showing SNM in the ULV retention state of Example 1 and Comparative Examples 2 and 3, and FIG. 14(b) is a diagram showing SNM and standby power with respect to VVDD in the ULV retention state of Example 1. [Figure 15] FIG. 15 is a diagram showing the standby power in Example 1 and Comparative Example 3. In FIG. [Figure 16] FIG. 16 is a circuit diagram showing a loop of memory cells in the first modification of the first embodiment. [Figure 17] FIG. 17 is a circuit diagram showing a cross-coupled memory cell in the first modification of the first embodiment. [Figure 18] FIG. 18 is a circuit diagram showing a loop of memory cells in the second modification of the first embodiment. [Figure 19]FIG. 19 is a circuit diagram showing a cross-coupled memory cell in the second modification of the first embodiment. [Figure 20] FIG. 20 is a diagram showing butterfly curves of the bistable circuits in the ULV retention state of the first embodiment and the second modification thereof. [Figure 21] 21(a) and 21(b) are diagrams showing the voltages of the header PS·PDFB·Type 1 and the footer PS·PUFB·Type 1, respectively. [Figure 22] FIG. 22 is a circuit diagram of a memory cell of the virtual power supply system in the second embodiment. [Figure 23] FIG. 23 is a diagram illustrating a power switch and a selection circuit in a virtual power supply system according to the second embodiment. [Figure 24] FIG. 24 is a circuit diagram of a memory cell of the virtual ground system according to the second embodiment. [Figure 25] FIG. 25 is a diagram illustrating a power switch and a selection circuit in the virtual ground system of the second embodiment. [Figure 26] FIG. 26 is a block diagram of a memory array according to the second embodiment. [Figure 27] 27(a) to 27(c) are diagrams showing the operation of a memory cell in the second embodiment. [Figure 28] 28(a) to 28(c) are diagrams showing the operation of a memory cell in the second embodiment. [Figure 29] FIG. 29 is a diagram illustrating the operation of a memory cell in the second embodiment. [Figure 30] FIG. 30 is a diagram showing SNM and standby power for WLP in the hold state in simulation 3. [Figure 31] FIG. 31 is a diagram showing SNM with respect to VWL in a read operation and a hold state in simulation 3. In FIG. [Figure 32] 32(a) and 32(b) are diagrams showing the currents Im1 and SNM, respectively, versus the voltage VSR of the H-store operation in Simulation 3. FIG. [Figure 33]33(a) and 33(b) are diagrams showing the currents Im2 and SNM, respectively, versus the voltage Vc of the L-store operation in Simulation 3. FIG. [Figure 34] 34(a) and 34(b) are diagrams showing SNM with respect to the voltage VSR of the FF and the FS, respectively, in the restore operation in Simulation 3. FIG. [Figure 35] 35(a) is a diagram showing the SNM in Example 2, and FIG. 35(b) is a diagram showing the standby power in Example 2 and Comparative Example 3. In FIG. [Figure 36] FIG. 36 is a circuit diagram of a memory cell according to a first modification of the second embodiment. [Figure 37] FIG. 37 is a diagram illustrating a BNN model in the third embodiment. [Figure 38] FIG. 38 is a block diagram of an arithmetic circuit that performs calculations for n-to-1 connections in the third embodiment. [Figure 39] FIG. 39(a) is a block diagram of an arithmetic circuit that performs 1-to-n connection calculations in the third embodiment, and FIG. 39(b) is a block diagram of an accumulator. [Figure 40] FIG. 40 is a block diagram of a BNN device according to the third embodiment. [Figure 41] FIG. 41 is a flowchart showing the n-to-1 connection processing performed by the processing unit 52 in the third embodiment. [Figure 42] FIG. 42 is a flowchart showing the processing of the 1-to-n connection performed by the processing unit 62 in the third embodiment. [Figure 43] FIG. 43 is a diagram illustrating processing over time in the third embodiment. [Figure 44] FIG. 44 is a block diagram illustrating an example of a memory according to the second embodiment. [Figure 45] FIG. 45 is a block diagram of a BNN device according to a first modification of the third embodiment. [Figure 46] FIG. 46 is a diagram illustrating an example of a memory according to the first modification of the third embodiment. [Figure 47]FIG. 47 is a circuit diagram showing an example of a 2R1W NV-SRAM memory cell in the second modification of the third embodiment. [Figure 48] FIG. 48 is a circuit diagram showing an example of a 2R1W type ULVR-SRAM memory cell in the second modification of the third embodiment. [Figure 49] Figure 49(a) is a diagram showing SNM versus VWWL of a 2R1W type NV-SRAM memory cell during a read operation in variant example 2 of embodiment 3, and Figure 49(b) is a diagram showing SNM versus VWWL of a 2R1W type ULVR-SRAM memory cell during a read operation. [Figure 50] FIG. 50 is a circuit diagram showing an example of a 2RW NV-SRAM memory cell in the second modification of the third embodiment. [Figure 51] FIG. 51 is a circuit diagram showing an example of a 2RW type ULVR-SRAM memory cell in the second modification of the third embodiment. [Figure 52] FIG. 52 is a diagram illustrating an example of a 2R1W type memory according to the second modification of the third embodiment. [Figure 53] FIG. 53 is a diagram illustrating an example of a 2RW memory according to the second modification of the third embodiment. [Figure 54] FIG. 54 is a diagram illustrating processing over time in a modification of the third embodiment. [Figure 55] 55(a) to 55(c) are diagrams showing the normalized processing time versus the number of layers m. [Figure 56] FIG. 56 is a circuit diagram of an NV-SRAM memory cell according to the fourth modification of the third embodiment. [Figure 57] FIG. 57 is a circuit diagram of an ULVR-SRAM memory cell according to the fourth modification of the third embodiment. [Figure 58] FIG. 58 is a block diagram of a BNN device according to the fourth modification of the third embodiment. [Figure 59] 59(a) and 59(b) are block diagrams of the vicinity of the power switch of Comparative Example 4 and Modification 5 of Example 3, respectively. [Figure 60] FIG. 60 is a circuit diagram of a 6T cell according to the fifth modification of the third embodiment. [Figure 61] 61(a) and 61(b) are diagrams showing SNM and standby power with respect to VDDL in Comparative Example 4 and Modification 5 of Example 3, respectively. DETAILED DESCRIPTION OF THE INVENTION

[0013] Figures 1 and 2: Comparative Example 1 Figures 3 and 4: Comparative Example 2 Figures 5 to 7C: Example 1 8(a) to 10(c): Simulation 1, Comparative Examples 2 and 3, Example 1 11 to 15: Simulation 2, Comparative Examples 2 and 3, Example 1 16 and 17: Modification 1 of Example 1 18 to 20: Modification 2 of Example 1 FIG. 21: Example 1 and its modifications Figures 22 to 29: Example 2 Figures 30 to 35(b): Simulation 3, Example 2 FIG. 36: Modification 1 of Example 2 Figures 37 to 44: Example 3 45-46: Modification 1 of Example 3 47 to 53: Modification 2 of Example 3 54 to 55(c): Simulations of Example 3 and its Modifications 1 to 3 Figures 56 to 58: Modification 4 of Example 3 Figures 59(a) to 61(b): Modification 5 of Example 3

[0014] Before describing the examples, comparative examples will be described.

[0015] [Comparative Example 1] Comparative Example 1 differs from Patent Document 1 in the conductivity type of the feedback transistor and the connection destination of the gate. Figures 1 and 2 are circuit diagrams of a memory cell 10 in Comparative Example 1. Figure 1 is a circuit diagram with a loop display, and Figure 2 is a circuit diagram with a cross-couple display. Although Figures 1 and 2 show the same circuit, the loop display in Figure 1 is easier to understand when explaining operation, and the cross-couple display in Figure 2 is easier to understand when explaining the circuit area, etc.

[0016] 1 and 2, the inverter circuits 14 and 16 include FETs m1 to m3 and m1a to m3a. The FETs m1, m2, and m3a are N-channel MOSFETs, and the FETs m1a, m2a, and m3 are P-channel MOSFETs.

[0017] FETs m1, m2, m1a, and m2a are connected in series between a ground line 15b and a power line 15a (virtual power line). The gates of FETs m1, m2, m1a, and m2a are connected to an input node N1. An output node N2 is located between FETs m2 and m2a. FETs m1 and m2 are drivers for inverter circuits 14 and 16, and FETs m1a and m2a are loads.

[0018] FET m3 is connected between an intermediate node N3 between FET m1 and m2 and a bias node N4, and FET m3a is connected between an intermediate node N3a between FET m1a and m2a and a bias node N4a. The gates of FET m3 and m3a are connected to the input node N1. FET m3 and m3a are feedback transistors FBTr.

[0019] The storage nodes Q1 and Q2 are connected to the bit lines BL and BLB, respectively, via a FET m5. The gate of the FET m5 is connected to the word line WL. The FET m5 is an N-channel FET and a pass transistor.

[0020] The driver 26 includes inverters 27a and 27b. The inverter 27a inverts the control signal VCTRL to generate a signal VFN, which is output to the bias node N4, and the inverter 27b inverts the signal VFN to generate a signal VFP, which is output to the bias node N4a. The power switch (PS) 30 converts the voltage VDD of the power supply 15c into a virtual power supply voltage VVDD and supplies it to the power supply line 15a. The power switch 30 switches the virtual power supply voltage VVDD in response to a control signal from a control circuit (not shown).

[0021] In the memory cell according to Comparative Example 1, the mode of the inverter circuits 14 and 16 can be changed between the ST mode and the BI mode by the control signal VCTRL. When the control signal VCTRL is at a high level (VVDDH, for example, 1.2 V), the inverter circuits 14 and 16 are in the BI mode. When the control signal VCTRL is at a low level (VGND, for example, 0 V), the inverter circuits 14 and 16 are in the ST mode.

[0022] The ST mode is a mode in which the transfer characteristics of the inverter circuits 14 and 16 have hysteresis, while the BI mode is a mode in which the transfer characteristics of the inverter circuits 14 and 16 have substantially no hysteresis. In the ST mode, if the virtual power supply voltage VVDD-VGND applied to the inverter circuits 14 and 16 is a normal voltage (e.g., 1.2 V), the leakage current becomes large. In the BI mode, even if the voltage VVDD-VGND is a normal voltage, the leakage current is smaller than in the ST mode. Note that having substantially no hysteresis means that there is no intentional hysteresis like in the ST mode, and unintentional hysteresis is allowed.

[0023] In the BI mode, the memory cell 10 functions as a normal SRAM cell. In the ST mode, the bistable circuit 12 retains data even if the voltage (VVDD-VGND) is set to, for example, 0.2 V, an ultralow voltage (ULV).

[0024] Table 1 shows the state in Comparative Example 1.

[0025] [Table 1]

[0026] The state in which data is read from and written to the memory cell 10 is the read / write state. In the read / write state, the control signal VCTRL is at high level H. This puts the inverter circuits 14 and 16 into BI mode. The power switch 30 sets the virtual power supply voltage VVDD to VVDDH (e.g., 1.2V). The voltage (VVDD-VGND) becomes VH (e.g., 1.2V). By setting the voltage VWL of the word line WL of the memory cell 10 to be read from or written to high level (e.g., 1.2V), the FET m5 turns on, making it possible to read or write data from the bistable circuit 12.

[0027] During normal operation, the state in which data is held is the VDD retention state. In the VDD retention state, the control signal VCTRL is at high level H, and the inverter circuits 14 and 16 are in BI mode. The virtual power supply voltage VVDD is VVDDH (e.g., 1.2 V), and the voltage (VVDD-VGND) is VH (e.g., 1.2 V). Since no read or write is being performed, the voltage VWL of the word line WL is at low level (e.g., 0 V), and FET m5 is off.

[0028] The state in which data in the memory cell 10 is retained at an ultra-low voltage is the ULV retention state. In the ULV retention state, the control signal VCTRL is at low level L, and the inverter circuits 14 and 16 are in ST mode. The power switch 30 sets the virtual power supply voltage VVDD to VVDDL (e.g., 0.2 V). The voltage (VVDD-VGND) becomes VL (e.g., 0.2 V), which is lower than VH. The voltage VWL is at low level (e.g., 0 V), and the FET m5 is off.

[0029] Comparative Example 2 3 and 4 are circuit diagrams of the memory cell 10 in Comparative Example 2. Fig. 3 is a circuit diagram showing a loop, and Fig. 4 is a circuit diagram showing a cross-couple.

[0030] 3 and 4, the second comparative example does not include FETs m2a and m3a and the driver 26. The other configurations are the same as those of the first comparative example.

[0031] Table 2 shows the state in Comparative Example 2.

[0032] [Table 2]

[0033] As shown in Table 2, the voltage of bias node N4 is constant at VFN (e.g., 0.2V) regardless of the mode. In the read / write state, a control signal from a control circuit (not shown) causes power switch 30 to set virtual power supply voltage VVDD to VVDDH (e.g., 1.2V). The virtual power supply voltage (VVDD-VGND) applied to bistable circuit 12 becomes VH (e.g., 1.2V). At this time, inverter circuits 14 and 16 are in BI mode. The voltage VWL of word line WL is high (e.g., 1.2V). In the VDD retention state, the virtual power supply voltage VVDD is VVDDH (e.g., 1.2V), the voltage (VVDD-VGND) is VH (e.g., 1.2V), and inverter circuits 14 and 16 are in BI mode. The voltage VWL of word line WL is low (0V).

[0034] In the ULV retention state, the power switch 30 sets the virtual power supply voltage VVDD to VVDDL (e.g., 0.2V). The voltage (VVDD-VGND) becomes VL (e.g., 0.2V), which is lower than VH. At this time, the inverter circuits 14 and 16 are in ST mode. The voltage VWL is at a low level (e.g., 0V). As in Comparative Example 1, power consumption can be reduced in the ULV retention state.

[0035] A type in which FETm3 is provided as a feedback transistor FBTr between N-channel FETs m1 and m2 is called pull-down feedback PDFB. A type in which FETm3a is provided as a feedback transistor FBTr between P-channel FETs m1a and m2a is called pull-up feedback PUFB. A type in which both FETs m3 and m3a are provided is called pull-up pull-down feedback PUPDFB. Comparative Example 1 is PUPDFB, and Comparative Example 2 is PDFB.

[0036] When FBTr and the FET to which FBTr are connected have different conductivity type channels, they are called different conductivity type channel FBTr. In Comparative Example 2, which is PDFB, FETm3, which is FBTr, has a P-type channel, and FETsm1 and m2 to which FETm3 is connected have N-type channels. Therefore, when FBTr has a P-type channel in PDFB, it is called different conductivity type channel FBTr. When FBTr has an N-type channel in PUFB, it is called different conductivity type channel FBTr. When FBTr and the FET to which FBTr are connected have the same conductivity type channels, they are called same conductivity type channel FBTr. When FBTr has an N-type channel in PDFB, and when FBTr has a P-type channel in PUFB, it is called same conductivity type channel FBTr.

[0037] In a different conductivity type channel FBTr, the gate is connected to the input node of the same inverter circuit or the output node of the other inverter circuit. In a same conductivity type channel FBTr, the gate is connected to the output node of the same inverter circuit or the input node of the other inverter circuit. Comparative Examples 1 and 2 are different conductivity type channel FBTrs. Patent Document 1 discloses a same conductivity type channel FBTr.

[0038] A system in which a power switch 30 is provided between the power supply line 15a and the power supply 15c, the power switch 30 sets a virtual power supply voltage VVDD, and the voltage VVDD-VGND is used as the power supply voltage for the memory cell 10 is called a header PS. A system in which a power switch 30 is provided between the ground line 15b and ground, the power switch 30 sets a virtual ground voltage VVGND, and VDD-VVGND is used as the power supply voltage for the memory cell 10 is called a footer PS. A system in which a power switch 30 is provided both between the power supply line 15a and the power supply 15c and between the ground line 15b and ground, the power switch 30 sets a virtual power supply voltage VVDD and a virtual ground voltage VVGND, and VVDD-VVGND is used as the power supply voltage for the memory cell 10 is called a dual PS. Comparative Examples 1 and 2 are header PSs.

[0039] A method in which a driver 26 is provided and high and low levels are applied to bias nodes N4 and N4a by a control signal VCTRL to switch between ST mode and BI mode is called Type 2. A method in which a driver 26 is not provided and bias node N4 is set to a constant voltage (constant bias) is called Type 1. Comparative Example 1 is Type 2, and Comparative Example 2 is Type 1.

[0040] In summary, Comparative Example 1 includes a PUPDFB, a different conductivity type channel FBTr, a header PS, and Type 2. Comparative Example 2 includes a PDFB, a different conductivity type channel FBTr, a header PS, and Type 1.

[0041] It will be explained that the different conductivity type channel FBTr improves the operational stability (for example, noise margin) of the bistable circuit 12 in the ULV retention state compared to the same conductivity type channel FBTr.

[0042] For example, in Comparative Example 2, if FETm3 has an N-type channel (i.e., a channel of the same conductivity type), the gates of FETm3 in inverter circuits 14 and 16 are connected to output node N2 of inverter circuits 14 and 16, respectively. In the ULV retention state, for example, when storage nodes Q1 and Q2 are at low and high levels, respectively, FETm3 in inverter circuit 14 turns on, and intermediate node N3 is charged from bias node N4 of voltage VFN. However, because FETm3 has an N-type channel and its threshold voltage Vth is positive, the charging potential from bias node N4 is insufficient. This may reduce the feedback effect of FETm3, which is an FBTr, and may reduce the operational stability of the bistable circuit in the ULV retention state.

[0043] On the other hand, when FETm3 is a P-type channel (i.e., a channel of a different conductivity type) as in Comparative Example 2, for example, when storage nodes Q1 and Q2 are at low and high levels, respectively, FETm3 of inverter circuit 14 turns on. Intermediate node N3 is charged from bias node N4, whose voltage is VFN. Because FETm3 is a P-type channel and a voltage sufficiently low relative to the source and drain is applied to the gate of FETm3, intermediate node N3 can be pulled up to VFN. This effectively generates the feedback effect of FETm3. This improves the operational stability of the bistable circuit in the ULV retention state.

[0044] Next, we will explain why Comparative Example 2 is Type 1. In Comparative Example 2, VFN is set to a constant bias of approximately VVDDL. When VVDDH is applied to power supply line 15a, VFN is sufficiently lower than VVDDH, so inverter circuits 14 and 16 are in BI mode. When VVDDL is applied to power supply line 15a, VFN is higher than VGND and is equal to or close to VVDDL, so inverter circuits 14 and 16 are in ST mode. In this way, the PDFB header PS does not require driver 26. Similarly, the PUFB footer PS does not require driver 26.

[0045] In Comparative Example 1, the number of transistors in the memory cell 10 is 14, and a driver 26 is provided. This increases the circuit area, as shown in FIG. 2. Feedback is applied by FBTr (FETs m3 and m3a) on both the pull-up side and the pull-down side of the inverter circuits 14 and 16, increasing the noise margin in the ULV retention state. This allows VVDDL to be set to, for example, 0.15 V, potentially reducing power consumption.

[0046] In Comparative Example 2, the number of transistors in the memory cell 10 is 10, and the driver 26 is not required. This allows the circuit area to be reduced as shown in FIG. 4. However, since feedback is applied only by the pull-down side FBTr (FETm3), the noise margin in the ULV retention state is smaller than in Comparative Example 1. As a result, VVDDL becomes, for example, 0.2 V. Therefore, power consumption is greater than in Comparative Example 1. [Example]

[0047] Example 1 is an example of PDFB, different conductivity type channel FBTr, header PS, type 1. In Example 1, the load FETm1a and pass transistor FETm5 of Comparative Example 2 are combined into one FETm4. This allows the number of transistors in memory cell 10 to be reduced to eight, further reducing the number compared to Comparative Example 2. Furthermore, the noise margin in ULV retention can be increased.

[0048] [Memory cell description] 5 and 6 are circuit diagrams of a memory cell in Example 1. Fig. 5 is a circuit diagram showing a loop, and Fig. 6 is a circuit diagram showing a cross-couple.

[0049] As shown in FIGS. 5 and 6, the memory cell 10 mainly includes inverter circuits 14 and 16. The inverter circuits 14 and 16 are connected in a loop to form a bistable circuit 12. The inverter circuits 14 and 16 each include FETs m1 to m4. The FETs m1 and m2 are N-channel MOSFETs, and the FETs m3 and m4 are P-channel MOSFETs. The FETs m1 to m4 are, for example, normally-off transistors.

[0050] The source of FET m1 is connected to the ground line 15b to which the ground voltage VGND is applied, the drain is connected to the intermediate node N3, and the gate is connected to the input node N1. The source of FET m2 is connected to the intermediate node N3, the drain is connected to the output node N2, and the gate is connected to the input node N1. FETs m1 and m2 are drivers.

[0051] In FETm3, one of the source and drain is connected to the intermediate node N3, the other of the source and drain is connected to the bias node N4, and the gate is connected to the input node N1. FETm3 is a feedback transistor FBTr.

[0052] One of the source and drain of FETm4 is connected to the output node N2, the other is connected to the control line CTRL1 or CTRL2, and the gate is connected to the word line WL. FETm4 functions as a pass transistor in the read / write state and as a load transistor in the VDD retention state and ULV retention state.

[0053] The input node N1 of the inverter circuit 14 and the output node N2 of the inverter circuit 16 are connected to a storage node Q1, and the input node N1 of the inverter circuit 16 and the output node N2 of the inverter circuit 14 are connected to a storage node Q2. The storage nodes Q1 and Q2 are complementary nodes. The storage node Q1 is connected to a control line CTRL1 via a FET m4 of the inverter circuit 16, and the storage node Q2 is connected to a control line CTRL2 via a FET m4 of the inverter circuit 14.

[0054] The selection circuit 32 connects the control line CTRL1 to either the bit line BL or the power supply line 15a (virtual power supply line). The selection circuit 32a connects the control line CTRL2 to either the bit line BLB or the power supply line 15a. The power switch (PS) 30 converts the voltage VDD of the power supply 15c into a virtual power supply voltage VVDD and supplies it to the power supply line 15a.

[0055] [Memory array description] FIG. 7A is a block diagram of a memory array in Example 1. As shown in FIG. 7A, the memory array 22 is divided into multiple blocks 24 each having a memory cell 10. The number of blocks 24 can be designed as appropriate. The memory array 22 has multiple memory cells 10 arranged in a matrix of n columns. Within the memory array 22, word lines WL extend in the row direction, and control lines CTRL1 and CTRL2 extend in the column direction. Each memory cell 10 is connected to the word line WL and the control lines CTRL1 and CTRL2. In FIG. 7A, the control lines CTRL1 and CTRL2 in columns 1 to n are indicated as control lines CTRL11 and CTRL21 to CTRL1n and CTRL2n, respectively.

[0056] A control circuit 28, a power switch 30, and a peripheral circuit 38 are provided corresponding to the memory array 22. The control circuit 28 controls the power switch 30 and the peripheral circuit 38.

[0057] In response to a control signal from the control circuit 28, the power switch 30 outputs a virtual power supply voltage VVDD, which is obtained from the voltage VDD of the power supply 15c, for example, by a voltage divider circuit. The voltage VVDD-VGND is the voltage applied to the bistable circuit 12. The peripheral circuit 38 includes a WL decoder 31, a selection circuit 32b, a precharge circuit 33, and a read / write circuit 34. In FIG. 7A, the selection circuits 32 and 32a in FIGS. 5 and 6 are described as selection circuit 32b. This also applies to similar figures below.

[0058] When the memory cell 10 retains data, the selection circuit 32b switches the control lines CTRL11 and CTRL21 to CTRL1n and CTRL2n to connect the power supply line 15a. When reading or writing data from or to the memory cell 10, the selection circuit 32b switches the control lines CTRL11 and CTRL21 to CTRL1n and CTRL2n to connect the bit lines BL1 and BLB1 to BLn and BLBn, respectively. The WL decoder 31 selects a word line WL based on a row address. A column address is input to the read / write circuit 34. The read / write circuit 34 selects bit lines BL and BLB corresponding to the selected column from the bit lines BL1 and BLB1 to BLn and BLBn based on the column address. The precharge circuit 33 precharges the bit lines BL and BLB. The read / write circuit 34 writes data to or reads data from the bistable circuit 12 of the selected memory cell 10 and outputs the data to the bus 25.

[0059] Another example of the peripheral circuit will be described with reference to FIGS. 7B and 7C. FIG. 7B is a diagram showing the power switch and selection circuit in the first embodiment. As shown in FIG. 7B, the power switch 30 includes FETs PS1 and PS2. The FETs PS1 and PS2 are P-channel FETs. The FET PS1 is connected between the power supply 15cH and the power supply line 15a, and the FET PS2 is connected between the power supply 15cL and the power supply line 15a. The power supplies 15cH and 15cL are supplied with power supply voltages VDDH and VDDL, respectively.

[0060] Signals VPS1 and VPS2 are input to the gates of FETPS1 and PS2, respectively. When signals VPS1 and VPS2 are low and high, respectively, FETPS1 and PS2 are turned on and off, respectively, and the virtual power supply voltage VVDD is VDDH. The virtual power supply voltage VVDD is VDDH in the read / write state and the VDD retention state, and the voltage VVDD - VGND is, for example, 1.2 V. When signals VPS1 and VPS2 are high and low, respectively, FETPS1 and PS2 are turned off and on, respectively, and the virtual power supply voltage VVDD is VDDL. The virtual power supply voltage VVDD is VDDL in the ULV retention state, and the voltage VVDD - VGND is, for example, 0.2 V. When signals VPS1 and VPS2 are both high, both FETPS1 and PS2 are turned off, and the virtual power supply voltage VVDD is shut off. The virtual power supply voltage VVDD is shut off in the shutdown state.

[0061] A precharge / selection circuit 33a is provided between the power supply line 15a and the control lines CTRL1 and CTRL2. The precharge / selection circuit 33a includes FETs M10 to M12. FET M10 is connected between the power supply line 15a and the control line CTRL1. FET M11 is connected between the power supply line 15a and the control line CTRL2. FET M12 is connected between the control lines CTRL1 and CTRL2. FETs M10 to M12 are P-channel FETs. A selection signal Sel is input to the gates of FETs M10 to M12. A selection circuit 32b is provided between the control lines CTRL1 and CTRL2 and the bit lines BL and BLB connected to the read / write circuit 34. The selection circuit 32b includes transfer gates M13 and M14. Transfer gate M13 is connected between the bit line BL and the control line CTRL1. Transfer gate M14 is connected between the bit line BLB and the control line CTRL2. The select signal Sel' and the complementary signal SelB' of Sel' are input to the transfer gates M13 and M14.

[0062] Fig. 7C is a block diagram showing another example of the memory array in Example 1. As shown in Fig. 7C, a precharge / selection circuit 33a is provided between the power switch 30 and the memory array 22. The precharge / selection circuit 33a includes the FETs M10 to M12 shown in Fig. 7B, and the selection circuit 32b includes the transfer gates M13 and M14 shown in Fig. 7B.

[0063] When the selection signal Sel is low, the FETs M10 to M12 are turned on, and the virtual power supply voltage VVDD is supplied to the control lines CTRL1 and CTRL2. When the selection signal Sel is high, the FETs M10 to M12 are turned off. When the FETs M10 to M12 are off and the selection signal Sel' is high, the transfer gates M13 and M14 are turned on, and the control lines CTRL1 and CTRL2 function as the bit lines BL and BLB. When the FETs M10 to M12 are on and the selection signal Sel' is low, the transfer gates M13 and M14 are turned off, and the control lines CTRL1 and CTRL2 are disconnected from the bit lines BL and BLB. As described above, the precharge / selection circuit 33a may be connected to the ends of the control lines CTRL1 and CTRL2, and the selection circuit 32b may be connected to the other ends of the control lines CTRL1 and CTRL2.

[0064] 7A and 7C controls the power switch 30 to make the voltage VL (0.2 V) of the voltages VVDD-VGND in Table 3 of Example 1 lower than the voltage VH (1.2 V) in the read / write state (second state) when the bistable circuit 12 is in the ULV retention state, in which the bistable circuit 12 retains data. This reduces power consumption in the ULV retention state.

[0065] Table 3 shows the conditions in the first embodiment.

[0066] [Table 3]

[0067] The bias node N4 is at a constant voltage VFN (e.g., 0.2 V). In the read / write state, the selection circuit 32b connects the bit line BL (bit lines BL and BLB in FIGS. 5 and 6) to the control line CTRL (control lines CTRL1 and CTRL2 in FIGS. 5 and 6). The power switch 30 sets the virtual power supply voltage VVDD to VVDDH (e.g., 1.2 V). The voltage VVDD-VGND is VH (e.g., 1.2 V). In the read state, the bit lines BL and BLB are approximately VVDDH. In the write state, one of the bit lines BL and BLB is approximately VVDDH, and the other is approximately VGND. The high level of the storage nodes Q1 and Q2 is approximately VVDDH, and the low level is approximately VGND. The inverter circuits 14 and 16 are in BI mode.

[0068] The voltage VWL of the word line WL of the memory cell 10 to be read or written is set to voltage V1 (e.g., 0.25 V). Voltage V1 is set to a voltage that turns on FET m4 when storage nodes Q1 and Q2 are at both high and low levels. This allows data to be read from and written to the memory cell 10.

[0069] In the VDD retention state, the selection circuit 32b connects the power supply line 15a to the control line CTRL (control lines CTRL1 and CTRL2 in FIGS. 5 and 6). The power switch 30 sets the virtual power supply voltage VVDD to VVDDH (e.g., 1.2 V). The voltage VVDD-VGND becomes VH (e.g., 1.2 V). The inverter circuits 14 and 16 are in the BI mode.

[0070] The voltage VWL of the word line WL is set to voltage V2 (e.g., 1.1 V). Because voltage V2 is slightly lower than VVDDH, FETm4 is slightly turned on whether storage nodes Q1 and Q2 are at high or low levels. This causes FETm4 to function as a load for inverter circuits 14 and 16. In the VDD retention state, the data in the bistable circuit 12 is retained.

[0071] In the ULV retention state, the selection circuit 32b connects the power supply line 15a to the control line CTRL (control lines CTRL1 and CTRL2 in FIGS. 5 and 6). The power switch 30 sets the virtual power supply voltage VVDD to VVDDL (e.g., 0.2 V). The voltage VVDD-VGND becomes VL (e.g., 0.2 V). The inverter circuits 14 and 16 enter the ST mode.

[0072] The voltage VWL of the word line WL is set to voltage V3 (e.g., 0.2 V). When voltage V3 is applied to the gate, FET m4 turns off whether storage nodes Q1 and Q2 are at high or low level. However, due to the leakage current of FET m4, FET m4 functions as a load for inverter circuits 14 and 16. In the ULV retention state, data in the bistable circuit 12 is retained at an ultra-low voltage. This reduces power consumption due to leakage current.

[0073] [Simulation 1] Simulation 1 is a simulation of SNM (Static Noise Margin) and standby power during reading in the VDD retention state and read / write state.

[0074] The simulation was carried out for Example 1, Comparative Example 2, and Comparative Example 3, which is an SRAM cell using six transistors (6T). The simulation conditions are as follows.

[0075] The channel width W / length L of each FET in Example 1 is as follows:

[0076] FETm1, m2 (driver): 100nm / 60nm FETm3 (feedback transistor): WFB / 60nm FETm4 (pass transistor / load): WLP / 60nm The voltages in the first embodiment are as follows:

[0077] VVDDH=1.2V VGND=0V VFN=0.2V VWL=1.1V or 0.25V

[0078] The channel width W / length L of each FET in Comparative Example 2 is as follows:

[0079] FETm1, m2 (driver): 165nm / 60nm FETm1a (load): 100nm / 60nm FETm3 (feedback transistor): 120nm / 60nm FETm5 (pass transistor): 100nm / 60nm The voltages in Comparative Example 2 are as follows:

[0080] VVDDH=1.2V VGND=0V VFN=0.2V The channel width W / length L of each FET in Comparative Example 3 is as follows:

[0081] Driver: 150nm / 60nm Load: 100nm / 60nm Pass transistor: 100nm / 60nm The voltages in Comparative Example 3 are as follows:

[0082] VVDD=1.2V VGND=0V

[0083] In the first embodiment, a virtual power supply voltage VVDD is supplied to the memory cell 10 from the control lines CTRL1 and CTRL2. Therefore, the noise margin and standby power consumption are determined by the size of FETm4 and the voltage VWL of the word line WL in the VDD retention state. Furthermore, because VFN is biased at a constant level, feedback is applied by FETm3 even in BI mode, although it is weaker than in ST mode. Therefore, the noise margin can be designed by adjusting the size of FETm3.

[0084] Therefore, we varied the size of FETm4 (channel width WLP) and the size of FETm3 (channel width WFB) to simulate the SNM (Static Noise Margin) and standby power in the VDD retention state. Standby power is equivalent to the sum of the leakage currents of each FET when data is retained. We also varied the voltage VWL of the word line WL to simulate the SNM and standby power in the VDD retention state. SNM is the noise margin; if SNM is small, the data in the bistable circuit 12 is more likely to be inverted by noise, etc., and if SNM is large, the data in the bistable circuit 12 is less likely to be inverted by noise, etc. We aimed for an SNM of 80mV or more as an indicator of SNM.

[0085] 8(a) and 8(b) show the SNM and standby power for WLP and WFB in the VDD retention state in Example 1. The TT of SNM is the SNM when the threshold voltages of the PFET and NFET are typical. The FF of SNM is the SNM when the threshold voltages of both the PFET and NFET deviate from the typical value by 3σ toward the Fast (F) side (lower) due to process variation. The SS of SNM is the SNM when the threshold voltages of both the PFET and NFET deviate from the typical value by 3σ toward the Slow (S) side (higher) due to process variation. The FS and SF of SNM are the SNM when one of the threshold voltages of the PFET and NFET deviates from the typical value by 3σ toward the Fast side and the other deviates from the typical value by 3σ toward the S side. If the SNMs of TT, FF, SS, FS, and SF are ensured, SNM can be ensured even if the threshold voltages of the PFET and NFET vary within a ±3σ range. In Comparative Example 3, the channel width W of the pass transistor is constant.

[0086] As shown in Figure 8(a), when WFB = 230 nm and VWL = 1.1 V, WLP is changed from 100 nm to 300 nm. As WLP increases, SNM increases. When WLP is 100 nm or more, all SNMs are 80 mV or more. As SNM increases, standby power increases. The standby power of Example 1 becomes smaller than that of Comparative Example 3 (6T) when WLP is 110 nm or less. Therefore, WLP is set to 110 nm.

[0087] As shown in Figure 8(b), when WLP = 110 nm and VWL = 1.1 V, WFB is changed from 100 nm to 300 nm. As WFB increases, SNM increases. When WFB is 230 nm or more, all SNMs are 80 mV or more. The standby power of Example 1 is independent of WFB and is smaller than that of Comparative Example 3 at all WFBs. For these reasons, WFB is set to 230 nm.

[0088] 9(a) and 9(b) are graphs showing SNM and standby power versus VWL in the VDD retention state and read / write state for Example 1 and Comparative Example 3. FIG. 9(b) is an enlarged view of the VWL of FIG. 9(a) near 1.1V. The goal was to achieve SNM of 80mV or higher. SNM=80mV is indicated by a dashed line.

[0089] As shown in Figure 9(a), when WLP = 110 nm and WFB = 230 nm, VWL is changed from 0 V to 1.2 V. SNM peaks around VWL = 0.7 V, and decreases when VWL is smaller than 0.7 V, and decreases when VWL is larger than 0.7 V. As VWL decreases, the standby power increases.

[0090] 9(b), when VWL is 1.1 V or higher, the standby power of Example 1 is smaller than that of Comparative Example 3. When VWL is 1.15 V or lower, all SNMs are 80 mV or higher. Therefore, VWL in the VDD retention state was set to 1.1 V.

[0091] In the read / write state, VWL is set low to turn on FETm4. However, it is preferable that SNM is large. As shown in Figure 9(a), when VWL is 0.25V or higher, all SNMs are 80mV or higher. Therefore, VWL was set to 0.25V.

[0092] SNM in the read / write state and the VDD retention state was simulated for Example 1 and Comparative Examples 2 and 3. In Example 1, WLP was set to 110 nm, WFP was set to 230 nm, VWL was set to 1.1 V in the VDD retention state, and VWL was set to 0.25 V in the read / write state.

[0093] 10(a) to 10(c) are diagrams showing SNM in the VDD retention state and the read / write state for Example 1 and Comparative Examples 2 and 3. Fig. 10(a) shows the SNM in the VDD retention state, Fig. 10(b) shows the SNM during reading in the read / write state, and Fig. 10(c) shows the SNM during writing in the read / write state.

[0094] As shown in Figure 10(a), in the VDD retention state, the SNM of Example 1 is smaller than that of Comparative Examples 2 and 3, but is greater than 80 mV for all SNMs. As shown in Figure 10(b), in the read state, the SNM of Example 1 is almost the same as that of Comparative Examples 2 and 3, and is greater than 80 mV for all SNMs. As shown in Figure 10(c), in the write state, the SNM of Example 1 is greater than that of Comparative Examples 2 and 3, and is greater than 80 mV for all SNMs. As described above, in Example 1, all SNMs are greater than 80 mV. Furthermore, the SNM for TT is greater than 100 mV. Thus, in Example 1, sufficient noise margins can be ensured in the read / write state and the VDD retention state. While the VWL optimization in Figures 9(a) and 9(b) is performed in the VDD retention state and in the read / write state, the SNM can also be increased in the write state in the read / write state, as shown in Figures 10(a) to 10(c).

[0095] [Simulation 2] Simulation 2 is a simulation of the transfer characteristics of the inverter circuits 14 and 16, the butterfly curve of the bistable circuit 12, SNM, and standby power in the ULV retention state.

[0096] Unless otherwise specified, the channel width W / length L and each voltage of each FET are the same as those in Simulation 1. In Example 1, WLP=110 nm and WFP=230 nm. In Comparative Example 3, VVDD=0.2 V.

[0097] In the first embodiment, the voltage VWL of the word line WL was changed and the transfer characteristics of the inverter circuits 14 and 16 in the ULV retention state were simulated.

[0098] FIG. 11 is a diagram showing the transfer characteristics of the inverter circuit in the ULV retention state of the first embodiment, and is a diagram showing the output voltage Vout (output node N2) relative to the input voltage Vin (voltage at input node N1) of the inverter circuits 14 and 16.

[0099] As shown in Figure 11, in a forward sweep where Vin is increased, increasing VWL causes the threshold voltage at which the output voltage Vout shifts from high to low to shift higher toward Vin. In a backward sweep where Vin is decreased, increasing VWL causes the threshold voltage at which the output voltage Vout shifts from low to high to shift lower toward Vin. In a backward sweep, increasing VWL causes the threshold voltage to shift further toward lower Vin.

[0100] 12(a) and 12(b) are circuit diagrams of the bistable circuit in Example 1. The circuit of the bistable circuit 12 is shown in the ULV retention state in FIGS. 5 and 6, and is displayed to make the principle easier to understand. The input voltage Vin and output voltage Vout of the inverter circuit 14 in FIGS. 12(a) and 12(b) will be described.

[0101] The forward sweep will be described with reference to FIG. 12(a). In the initial state, the input voltage Vin is low (e.g., 0 V), and the output voltage Vout is high (e.g., 0.2 V). In this state, in the inverter circuit 14, FETs m1 and m2 are off, and FET m3 is on. FET m4 is off when VWL=0.2 V, but a leakage current flows through it. When VWL is lower than 0.2 V, FET m4 is on. Therefore, the output node N2 is charged from VVDDL of the control line CTRL1 by the leakage current or on-current of FET m4, as indicated by the dotted arrow 92, and the intermediate node N3 is charged by VFN of the bias node N4, as indicated by the dotted arrow 93.

[0102] When the input voltage Vin increases, in order to set the output voltage Vout to a low level, discharge is performed from the output node N2 to the intermediate node N3 as indicated by the solid line arrow 90. However, unless discharge is performed from the intermediate node N3 to the ground line 15b as indicated by the solid line arrow 91, discharge from the output node N2 to the intermediate node N3 is not possible. For this reason, the output node N2 discharges after the intermediate node N3 discharges, and the threshold voltage at which the output voltage Vout becomes a low level shifts toward a higher Vin.

[0103] Referring to FIG. 12(b), the backward sweep will be described. In the initial state, the input voltage Vin is at a high level (e.g., 0.2 V), and the output voltage Vout is at a low level (e.g., 0 V). In this state, in the inverter circuit 14, FETs m1 and m2 are on, and FETs m3 and m4 are off. Therefore, the intermediate node N3 is discharged to the ground line 15b as indicated by the dotted arrow 95. Although FET m4 is off when VWL=0.2 V, a leakage current flows through FET m4. When VWL is lower than 0.2 V, FET m4 is weakly turned on. Because the discharge via FET m2 indicated by the dotted arrow 94 is faster than the charge via FET m4 indicated by the dotted arrow 96, the output node N2 is discharged to the intermediate node N3.

[0104] When the input voltage Vin decreases, FETm1 turns off and FETm3 turns on, causing intermediate node N3 to be charged by VFN of bias node N4, as indicated by solid arrow 97. When FETm2 turns off and FETm4 is off or weakly on, output node N2 is charged by VVDDL of control line CTRL1, as indicated by dotted arrow 96. However, because output node N2 is charged with a current close to the off current of FETm4, the charging depends on VWL. As a result, the threshold voltage at which the output voltage Vout becomes high shifts toward lower Vin when VWL is increased. In particular, VWL is applied to the gate of FETm4. Therefore, the magnitude of the current indicated by dotted arrow 96 depends on VWL. When VWL is high, the current through FETm4 is small, causing the threshold voltage to shift toward lower Vin.

[0105] Simulations were performed on butterfly curves in the bistable circuits 12 of Example 1 and Comparative Examples 2 and 3. In Example 1, VWL=0.2V.

[0106] 13(a) and 13(b) are diagrams showing butterfly curves of the bistable circuits in the ULV retention state of Example 1 and Comparative Examples 2 and 3. In Fig. 13(a), the operating point is when Q1 is at a low level and Q2 is at a high level, and in Fig. 13(b), the operating point is when Q1 is at a high level and Q2 is at a low level.

[0107] As shown in Figures 13(a) and 13(b), the 6T-SRAM of Comparative Example 3 has a narrow lobe of the butterfly curve and a small noise margin. In Comparative Example 2, the lobe on the operating point side is wide, and the noise margin is large. In Example 1, the lobe on the operating point side is even wider than in Comparative Example 2, and the noise margin is even larger than in Comparative Example 2.

[0108] SNM under ULV retention conditions in Example 1 and Comparative Examples 2 and 3 was simulated.

[0109] FIG. 14(a) shows the SNM in the ULV retention state for Example 1 and Comparative Examples 2 and 3. As shown in FIG. 14(a), in Comparative Example 3, all SNMs are less than 80 mV, resulting in a small noise margin. In Comparative Example 2, all SNMs are 80 mV or more, resulting in a large noise margin. In Example 1, all SNMs are 130 mV or more, resulting in a larger noise margin than in Comparative Example 2. If a practical SNM is 80 mV, then in Example 1, VVDD can be set lower than 0.2 V. If VVDD is set to 0.2 V, then SNM is 130 mV or more, making the bistable circuit 12 more stable than when VVDD is set lower than 0.2 V.

[0110] In the ULV retention state of Example 1, VVDD was changed to simulate SNM and standby power.

[0111] FIG. 14(b) is a diagram showing SNM and standby power versus VVDD in the ULV retention state of Example 1. As shown in FIG. 14(b), in Example 1, VVDD is varied from 0.1 to 0.2 V. As VVDD increases, SNM increases and standby power also increases. When VVDD is 0.15 V or higher, all SNMs are 80 mV or higher. Therefore, VVDD (i.e., VVDDL) in the ULV retention state can be set to 0.15 V.

[0112] For Example 1 and Comparative Example 3, the standby power for each VVDD was simulated.

[0113] 15 is a diagram showing the standby power in Example 1 and Comparative Example 3. The numbers indicate the reduction rate of the standby power relative to the standby power when VVDD=1.2 V in Comparative Example 3.

[0114] As shown in Figure 15, in Comparative Example 3, VVDD = 1.2V in the normal state where read / write is performed. At this time, the standby power is approximately 4.4nW. In Comparative Example 3, in the sleep state where no read or write is performed and data is retained, VVDD = 0.8V. At this time, the standby power reduction rate is 44%.

[0115] In Example 1, in the VDD retention state, VVDD=1.2V. At this time, the standby power reduction rate is 7%. In the ULV retention state, if VVDD=0.2V, the standby power reduction rate is 95%. Furthermore, if VVDD=0.15V, the standby power reduction rate is 97%.

[0116] In Comparative Example 2, the number of transistors in the memory cell 10 is 10, but in Example 1, the number of transistors in the memory cell 10 can be reduced to 8. This allows the circuit area to be reduced as shown in a comparison between FIG. 4 and FIG. 6. Furthermore, as shown in FIG. 14(a), the noise margin in the ULV retention state can be made larger than that of Comparative Example 2. If the noise margin is the same as that of Comparative Example 2, VVDDL can be made lower than that of Comparative Example 2. This allows the standby power to be further reduced.

[0117] [Modification 1 of Example 1] Variation 1 of Example 1 is an example of PUFB, a different conductivity type channel FBTr, a footer PS, and Type 1. FIGS. 16 and 17 are circuit diagrams of a memory cell 10 in Variation 1 of Example 1. FIG. 16 is a circuit diagram showing a loop, and FIG. 17 is a circuit diagram showing a cross-couple. Note that PUFB and footer PS are in a VSS retention state rather than a VDD retention state, but are referred to as a VDD retention state here to match Example 1.

[0118] 16 and 17, the inverter circuits 14 and 16 each include FETs m1a to m4a. The FETs m1a and m2a are P-channel MOSFETs, and the FETs m3a and m4a are N-channel MOSFETs.

[0119] The source of FETm1a is connected to a power supply line 15a to which a power supply voltage VDD is applied. A selection circuit 32 connects a control line CTRL1 to either a bit line BL or a ground line 15b (virtual ground line). A selection circuit 32a connects a control line CTRL2 to either a bit line BLB or a ground line 15b. A power switch (PS) 30 converts the voltage VGND of the ground 15d into a virtual ground voltage VVGND and supplies it to the ground line 15b. A constant bias VFP is applied to a bias node N4. The other circuit configurations are the same as those of the circuits in FIGS. 5 and 6 of the first embodiment, with FETs m1a to m4a replacing FETs m1a to m4a, respectively.

[0120] Table 4 shows the state in the first modification of the first embodiment.

[0121] [Table 4]

[0122] The bias node N4 is at a constant voltage VFP (e.g., 1.0 V). In the read / write state, the selection circuits 32 and 32a connect the bit lines BL and BLB to the control lines CTRL1 and CTRL2, respectively. The power switch 30 sets the virtual ground voltage VVGND to VVGNDL (e.g., 0 V). The virtual power supply voltage VDD-VVGND applied to the bistable circuit 12 is VH (e.g., 1.2 V). In the read state, the bit lines BL and BLB can be set to approximately VVGNDL. In the write state, one of the bit lines BL and BLB can be set to approximately VVGNDL, and the other can be set to approximately VDD. The high level of the storage nodes Q1 and Q2 is approximately VDD, and the low level is approximately VVGNDL. The inverter circuits 14 and 16 are in BI mode. The voltage VWL of the word line WL of the memory cell 10 to be read or written is set to voltage V1 (e.g., 0.9 V).

[0123] In the VDD retention state, the selection circuits 32 and 32a connect the ground line 15b to the control lines CTRL1 and CTRL2. The power switch 30 sets the virtual ground voltage VVGND to VVGNDL (e.g., 0V). The voltage VDD-VVGND becomes VH (e.g., 1.2V). The inverter circuits 14 and 16 are in the BI mode. The voltage VWL of the word line WL is set to voltage V2 (e.g., 0.1V).

[0124] In the ULV retention state, the selection circuits 32 and 32a connect the ground line 15b to the control lines CTRL1 and CTRL2. The power switch 30 sets the virtual ground voltage VVGND to VVGNDH (e.g., 1.0V). The voltage VDD-VVGND becomes VL (e.g., 0.2V). The inverter circuits 14 and 16 enter the ST mode. The voltage VWL of the word line WL is set to voltage V3 (e.g., 1.0V). In the ULV retention state, the data in the bistable circuit 12 is held at an ultra-low voltage. This reduces power consumption due to leakage current.

[0125] [Modification 2 of Example 1] Modification 2 of Example 1 is an example of PDFB, same conductivity type channel FBTr, header PS, and Type 1. Figures 18 and 19 are circuit diagrams of a memory cell 10 in Modification 2 of Example 1. Figure 18 is a circuit diagram showing a loop, and Figure 19 is a circuit diagram showing a cross-coupled.

[0126] 18 and 19, in inverter circuits 14 and 16, FETm3 is an N-channel FET. The gate of FETm3 in inverter circuit 14 is connected to output node N2 of inverter circuit 14 or input node N1 of inverter circuit 16, and the gate of FETm3 in inverter circuit 16 is connected to output node N2 of inverter circuit 16 or input node N1 of inverter circuit 14. The other circuit configurations are the same as those in FIGS. 5 and 6 of the first embodiment. Note that, as in FIG. 7B, part of selection circuits 32 and 32a may be precharge / selection circuit 33a provided between power switch 30 and control lines CTRL1 and CTRL2, and other part of selection circuits 32 and 32a may be selection circuit 32b provided between read / write circuit 34 and control lines CTRL1 and CTRL2.

[0127] A butterfly curve in the ULV retention state of Modification 2 of Example 1 was simulated. The simulation conditions were almost the same as those of Simulation 2 of Example 1. VVDD was set to 0.2 V. In Modification 2 of Example 1, VWL was set to 0.1 V because the noise margin is largest when VWL=0.1 V.

[0128] Fig. 20 shows butterfly curves of the bistable circuits in the ULV retention state of Example 1 and Modification 2. In Fig. 20, the operating point is when Q1 is at a low level and Q2 is at a high level. The butterfly curves of Example 1 are the same as those in Fig. 13(a).

[0129] As shown in FIG. 20, in the second modification of the first embodiment, the opening on the operating point side is smaller than the opening on the operating point side in the first embodiment. As such, when the feedback transistor (FET m3) has the same conductivity type channel as FETs m1 and m3, the noise margin is smaller than when it has a different conductivity type channel. The opening on the operating point side is wider than in the third comparative example in FIG. 13(a). Therefore, ULV retention can reduce power consumption more than in the third comparative example. Furthermore, the circuit area can be reduced more than in the second comparative example.

[0130] According to the first embodiment and its modifications, in the inverter circuit 14 (first inverter circuit) and the inverter circuit 16 (second inverter circuit), the source of the FETm1 (first FET) (or FETm1a) is connected to the ground line 15b (or the power supply line 15a), the drain is connected to the intermediate node N3, and the gate is connected to the input node N1. In a PDFB such as the first embodiment and its modification 2, the ground line 15b corresponds to the power supply line, and in a PUFB such as the modification 1 of the first embodiment, the power supply line 15a corresponds to the power supply line.

[0131] In FETm2 (second FET) (or FETm2a), the source is connected to the intermediate node N3, and the drain is connected to the output node N2. In FETm3 (third FET) (or FETm3a), one of the source and the drain is connected to the intermediate node N3, and the other of the source and the drain is connected to the bias node N4. In FETm4 (fourth FET) (or FETm4a), one of the source and the drain is connected to the output node N2, and the other of the source and the drain is connected to the control line CTRL1 or CTRL2. The conductivity type (second conductivity type) of FETm4 (or m4a) is opposite to the conductivity type (first conductivity type) of FETm1 and m2 (or FETm1a and m2a).

[0132] At storage node Q1 (first storage node), input node N1 of inverter circuit 14 and output node N2 of inverter circuit 16 are connected, and at storage node Q2 (second storage node), output node N2 of inverter circuit 14 and input node N1 of inverter circuit 16 are connected, thereby forming bistable circuit 12.

[0133] The gates of FETm4 (or FETm4a) of inverter circuits 14 and 16 are connected to word line WL. The gate of FETm3 (or FETm3a) of inverter circuit 14 is connected to any one of input node N1 and output node N2 of inverter circuit 14, and input node N1 and output node N2 of inverter circuit 16. The gate of FETm3 (or FETm3a) of inverter circuit 16 is connected to any one of input node N1 and output node N2 of inverter circuit 16, and input node N1 and output node N2 of inverter circuit 14.

[0134] With the circuit configuration described above, FETm4 (or FETm4a) can be used as both the load and pass transistors of the inverter circuits 14 and 16. This allows for a reduction in circuit area compared to Comparative Example 2. Furthermore, FETm3 (or FETm3a), which is an FBTr, provides a wider noise margin in the ULV retention state than Comparative Example 3. This allows for a reduction in power consumption.

[0135] In the first embodiment and its first modification, FET m3 (or FET m3a) has a second conductivity type channel opposite to the first conductivity type channel of FET m1 and m2 (or FET m1a and m2a). That is, FBTr has a different conductivity type channel. In this case, the gate of FET m3 (or FET m3a) of inverter circuit 14 is connected to input node N1 of inverter circuit 14 or output node N2 of inverter circuit 16, and the gate of FET m3 (or FET m3a) of inverter circuit 16 is connected to input node N1 of inverter circuit 16 or output node N2 of inverter circuit 14.

[0136] As a result, as in Simulation 2 of Example 1, the noise margin in the ULV retention state can be made larger than that of Comparative Example 2. Furthermore, by lowering VVDDL, power consumption can be suppressed.

[0137] As in the second modification of the first embodiment, the FET m3 has the same first conductivity type channel as the FETs m1 and m2. That is, the FBTr has the same conductivity type channel. In this case, the gate of the FET m3 in the inverter circuit 14 is connected to the output node N2 of the inverter circuit 14 or the input node N1 of the inverter circuit 16, and the gate of the FET m3 in the inverter circuit 16 is connected to the output node N2 of the inverter circuit 16 or the input node N1 of the inverter circuit 14.

[0138] This makes it possible to increase the noise margin in the ULV retention state compared to Comparative Example 3. Furthermore, by lowering VVDDL, power consumption can be reduced.

[0139] 7A and 7C controls the power switch 30 (power supply circuit) to make the voltage VL (first voltage) of voltage VVDD-VGND in Table 3 of Example 1 and voltage VVDD-VVGND in Table 4 of Variation 1 of Example 1 lower than the voltage VH (second voltage) in the read / write state (second state) in the ULV retention state (first state) in which the bistable circuit 12 retains data. This makes it possible to reduce power consumption in the ULV retention state.

[0140] Voltage VL corresponds to the voltage VVDD-VGND between ground line 15b and control lines CTRL1 and CTRL2 in the ULV retention state in Example 1, and corresponds to the voltage VDD-VVGND between power supply line 15a and control lines CTRL1 and CTRL2 in the ULV retention state in Modification 1 of Example 1. Voltage VH corresponds to the voltage between storage nodes Q1 and Q2 in the read / write state.

[0141] The voltage VL may be smaller than the voltage VH, but from the viewpoint of ensuring SNM and suppressing power consumption in the ULV retention state, the voltage VL is preferably 1 / 2 or less of the voltage VH, more preferably 1 / 4 or less, even more preferably 1 / 5 or less, and even more preferably 1 / 6 or less. In particular, from the viewpoint of suppressing power consumption, it is preferably about 1 / 10. The voltage VL is greater than 0V.

[0142] The control circuit 28 controls the selection circuit 32b to connect the bit lines BL and BLB for reading or writing data from the bistable circuit 12 to the control lines CTRL1 and CTRL2 in the read / write state. That is, the control lines CTRL1 and CTRL2 are set to the bit lines BL and BLB. This allows data to be read or written from the bistable circuit 12 via the control lines CTRL1 and CTRL2.

[0143] In the case of PDFB (i.e., when the first conductivity type is N-type) as in the first embodiment and its second modification, FETm4 is P-type. Therefore, in order to turn on FETm4 in the read / write state, the voltage VWL of the word line WL is generally set to the voltage VGND (e.g., 0 V) ​​of the ground line 15b. However, when VWL is set to 0 V as in FIG. 9(a), the SNM becomes small.

[0144] Therefore, in the read / write state, the control circuit 28 sets the voltage VWL of the word line WL of the power switch 30 higher than the voltage of the ground line 15b. For example, in the first embodiment and its second modification, VWL is set to 0.25V while VGND is set to 0V. This makes it possible to prevent the SNM from becoming smaller than the target 80mV, as shown in FIG. 9(a).

[0145] In the case of PUFB (i.e., when the first conductivity type is P type) as in the first modification of the first embodiment, the control circuit 28 sets the voltage VWL of the word line WL lower than the voltage VDD of the power supply line 15a. For example, in the first modification of the first embodiment, VWL is set to 0.9V when VDD is 1.2V. This makes it possible to prevent the SNM from becoming smaller, similar to PDFB.

[0146] In the VDD retention and read / write states, if VWL is too close to the voltage of the ground line 15b (or power supply line 15a), SNM during reads will not increase. Therefore, the difference between the voltage of the ground line 15b (or power supply line 15a) and VWL is preferably 1 / 10 or more of VH, more preferably 1 / 5 or more, and even more preferably about 1 / 2 as shown in Figure 9(a).

[0147] In the ULV retention state, if VWL becomes too high, FETm4 will not turn on, resulting in a decrease in operating speed. Therefore, the difference between the voltage of ground line 15b (or power line 15a) and VWL is preferably 1 / 2 or less of voltage VH, more preferably 1 / 4 or less, and even more preferably 1 / 5 or less. In Example 1, the difference between the voltage of ground line 15b and VWL is set to about 1 / 6, prioritizing speed performance.

[0148] In the ULV retention state, in FIGS. 12(a) and 12(b), it is preferable that FET m4 be turned off when the output node N2 is at a low level (e.g., GND=0V) and that FET m4 be turned on when the output node N2 is at a high level (e.g., VVDDL=0.2V). Therefore, it is preferable that VWL be equal to or higher than VGND and equal to or lower than VVDDL. That is, it is preferable that the control circuit 28 sets the voltage between the word line WL and the ground line 15b (or the power supply line 15a) to voltage VL or lower than voltage VL. For example, in the first embodiment, VL=0.2V and VWL-VGND=0.2V. In the first modification of the first embodiment, VL=0.2V and VDD-VWL=0.2V. In the second modification of the first embodiment, VL=0.2V and VWL-VGND=0.1V.

[0149] As shown in Figure 11, in the first embodiment, if VWL is too close to VGND, the noise margin becomes small. Therefore, the voltage between the word line WL and the ground line 15b (or the power supply line 15a) is preferably at least ¼ of the voltage VL, and more preferably at least ½ of the voltage VL. In Figure 11, the voltage between the word line WL and the ground line 15b (or the power supply line 15a) may be the voltage VL so that the noise margin is maximized when VWL = 0.2V.

[0150] In the case of PDFB (i.e., when the first conductivity type is N-type) as in the first embodiment and its second modification, FETm4 is P-type. Therefore, in the VDD retention state in which the voltage between the ground line 15b and the control lines CTRL1 and CTRL2 is VVDD-VGND=VH (e.g., 1.2 V), the voltage VWL of the word line WL is generally set to VVDD (e.g., 1.2 V) to turn off FETm4. However, when VWL is set to 1.2 V as in FIG. 9(b), the SNM becomes smaller.

[0151] Therefore, in the VDD retention state (third state), the control circuit 28 makes the voltage between the word line WL and the ground line 15b smaller than VH. For example, in the first embodiment and its second modification, VH=1.2V and VWL-VGND=1.1V. This makes it possible to prevent the SNM from becoming smaller, as shown in FIG. 9(b).

[0152] In the case of PUFB (i.e., when the first conductivity type is P type) as in the first modification of the first embodiment, the control circuit 28 makes the voltage between the word line WL and the power supply line 15a smaller than VH. For example, in the first modification of the first embodiment, VH=1.2V and VDD-VWL=1.1V. This makes it possible to prevent the SNM from becoming smaller.

[0153] If VWL is too close to the voltage of the ground line 15b (or power line 15a), SNM will not be large. Therefore, the difference between the voltage of the ground line 15b (or power line 15a) and VWL is preferably 49 / 50 or less of VH, more preferably 19 / 20 or less, and even more preferably 9 / 10 or less.

[0154] 9(b), a lower VWL results in a higher standby power. Therefore, the difference between the voltage of the ground line 15b (or the power line 15a) and VWL is preferably at least 1 / 2 of the voltage VH, more preferably at least 3 / 4, and even more preferably at least 4 / 5.

[0155] In any of the ULV retention state, VDD retention state, and read / write state, a constant bias VFN or VFP is supplied to the bias node N4. This eliminates the need for the driver 26 and reduces the circuit area. We will now consider the preferred ranges of the voltages VFN and VFP supplied to the bias node N4.

[0156] 21(a) and 21(b) are diagrams showing the voltages of the header PS·PDFB·Type 1 and the footer PS·PUFB·Type 1, respectively. In FIG. 21(a), VVDDH and VVDDL relative to VGND are shown vertically, and in FIG. 21(b), VVGNDL and VVGNDH relative to VDD are shown vertically.

[0157] 21(a), in the header PS, in the read / write state and the VDD retention state, VVDDH is supplied to the power supply line 15a and VGND is supplied to the ground line 15b. At this time, if VFN is set to a constant bias of approximately VVDDL, VFN is sufficiently lower than VVDDH, so the inverter circuits 14 and 16 are in the BI mode. In the ULV retention state, VVDDL is supplied to the power supply line 15a and VGND is supplied to the ground line 15b. At this time, if VFN is set to approximately VVDDL, VFN is higher than VGND, so the inverter circuits 14 and 16 are in the ST mode.

[0158] The constant voltage VFN should be smaller than VVDDH and larger than VGND. That is, VFN should be between the voltages of storage nodes Q1 and Q2 in the read / write state (range 40 in FIG. 21(a)). If the constant voltage VFN is too close to VVDDH, the inverter circuits 14 and 16 are unlikely to enter the BI mode when the virtual power supply voltage VVDD is set to VVDDH. If the constant voltage VFN is too close to VGND, the inverter circuits 14 and 16 are unlikely to enter the ST mode when the virtual power supply voltage VVDD is set to VVDDL. Therefore, to automatically switch the mode of the bistable circuit 12 using the virtual power supply voltage VVDD, the constant voltage VFN is preferably equal to or lower than the voltage at the midpoint between VVDDH and VGND (i.e., equal to or lower than (VVDDH-VGND) / 2), more preferably equal to or lower than the voltage obtained by adding half the voltage difference between VVDDL and VGND to VVDDL (i.e., equal to or lower than VVDDL+(VVDDL-VGND) / 2), and further preferably between (VVDDH-VGND) / 2 and the voltage at the midpoint between VVDDL and VGND (i.e., about (VVDDL-VGND) / 2) (range 41 in Figure 21(a)), and preferably between VVDDL+(VVDDL-VGND) / 2 and about (VVDDL-VGND) / 2 (range 42 in Figure 21(a)). Furthermore, about VVDDL is preferable.

[0159] As shown in Figure 21(b), in the footer PS, in the read / write state and the VDD retention state, VVGNDL is supplied to the ground line 15b and VDD is supplied to the power supply line 15a. At this time, if VFP is set to a constant bias of approximately VVGNDH, VFP is sufficiently higher than VVGNDL, so the inverter circuits 14 and 16 are in the BI mode. In the ULV retention state, VVGNDH is supplied to the ground line 15b and VDD is supplied to the power supply line 15a. At this time, if VFP is set to approximately VVGNDH, VFP is lower than VDD, so the inverter circuits 14 and 16 are in the ST mode.

[0160] The constant voltage VFP should be greater than VVGNDL and less than VDD. That is, VFP should be between the voltages of storage nodes Q1 and Q2 in the read / write state (range 40 in FIG. 21(b)). If the constant voltage VFP is too close to VVGNDL, the inverter circuits 14 and 16 are unlikely to enter the BI mode when the virtual ground voltage VVGND is set to VVGNDL. If the constant voltage VFP is too close to VDD, the inverter circuits 14 and 16 are unlikely to enter the ST mode when the virtual ground voltage VVGND is set to VVGNDH. Therefore, in order to automatically switch the mode of the bistable circuit 12 using the virtual ground voltage VVGND, the constant voltage VFP is preferably equal to or higher than the voltage at the midpoint between VDD and VVGNDL (i.e., equal to or higher than (VDD-VVGNDL) / 2), more preferably equal to or higher than the voltage obtained by subtracting half the voltage difference between VDD and VVGNDH from VVGNDH (i.e., equal to or higher than VVGNDH-(VDD-VVGNDH) / 2), and further preferably between (VDD-VVGNDL) / 2 and the voltage at the midpoint between VDD and VVGNDH (i.e., approximately VVGNDH+(VDD-VVGNDH) / 2) (range 41 in FIG. 21(b)). A range 42 in FIG. 21(b) between approximately VVGNDH-(VDD-VVGNDH) / 2 and VVGNDH+(VDD-VVGNDH) / 2 is more preferable.

[0161] In the first embodiment and its modified examples, Type 1 is described as an example in which the driver 26 is not provided, but Type 2 in which the driver 26 is provided may also be used. The combinations of PDFB and PUFB, different conductivity type channels and same conductivity type channels, and header PS, footer PS, and dual PS can be set arbitrarily.

[0162] Although an SRAM cell has been described as an example, the bistable circuit of the first embodiment and its modifications may be used in a flip-flop circuit such as a master-slave flip-flop circuit. In the master-slave flip-flop circuit, a switch such as a pass gate that turns on and off in synchronization with a clock signal may be provided in the loop of the bistable circuit 12. [Example]

[0163] The second embodiment is an example in which the memory cell has a nonvolatile memory element. [Explanation of virtual power supply memory cells] 22 is a circuit diagram of a memory cell of a virtual power supply system using a virtual power supply voltage VVDD in Example 2. As shown in Fig. 22, in the virtual power supply system, a power switch 30 is provided between a power supply line 15a (virtual power supply line) and a power supply 15c. A memory cell 10 mainly includes inverter circuits 14 and 16, FETs M5 and M6, and spin-transfer torque magnetic tunnel junction elements (STT-MTJs: hereinafter simply referred to as ferromagnetic tunnel junction elements) MTJ1 and MTJ2 as nonvolatile memory elements.

[0164] Inverter circuits 14 and 16 are connected in a loop to form a bistable circuit 12. Inverter circuit 14 includes FETs M2 and M4. Inverter circuit 16 includes FETs M1 and M3. FETs M1, M2, M5, and M6 are N-channel MOSFETs, and FETs M3 and M4 are P-channel MOSFETs.

[0165] The sources of FETs M1 (first FET) and M2 (second FET) are connected to a ground line 15b to which a ground voltage VGND is applied, the drains are connected to storage nodes Q1 (first storage node) and Q2 (second storage node), respectively, and the gates are connected to storage nodes Q2 and Q1, respectively. The storage nodes Q1 and Q2 are complementary nodes. The FETs M1 and M2 are drivers.

[0166] In FETs M3 (third FET) and M4 (fourth FET), one of the source and drain is connected to storage nodes Q1 and Q2, the other of the source and drain is connected to control lines CTRL1 (first control line) and CTRL2 (second control line), and the gate is connected to word line WL. FETs M3 and M4 function as pass transistors during read and write operations, and function as load transistors during hold, store, and restore operations.

[0167] FET M5 and ferromagnetic tunnel junction element MTJ1 are connected between storage node Q1 and control line CTRL0, and FET M6 and ferromagnetic tunnel junction element MTJ2 are connected between storage node Q2 and control line CTRL0. In FET M5 (first switch) and M6 (second switch), one of the source and the drain is connected to storage nodes Q1 and Q2, respectively, and the other of the source and the drain is connected to ferromagnetic tunnel junction elements MTJ1 and MTJ2, respectively. The gate is connected to switch line SR.

[0168] Ferromagnetic tunnel junction elements MTJ1 (first nonvolatile memory element) and MTJ2 (second nonvolatile memory element) each have a free layer 17, a tunnel insulating film 18, and a pinned layer 19. The free layer 17 is connected to a control line CTRL0, and the pinned layer 19 is connected to FETs M5 and M6. The free layer 17 and the pinned layer 19 are made of ferromagnetic materials. When the magnetization directions of the free layer 17 and the pinned layer 19 are parallel (parallel state), the resistance values ​​of MTJ1 and MTJ2 are low. When the magnetization directions of the free layer 17 and the pinned layer 19 are antiparallel (antiparallel state), the resistance values ​​of MTJ1 and MTJ2 are higher than in the parallel state. MTJ1 and MTJ2 store data based on the magnetization states (i.e., resistance values) of MTJ1 and MTJ2. Although an MTJ will be used as an example of a nonvolatile memory element, the nonvolatile memory element may also be a giant magnetoresistive (GMR) element, a variable resistance element such as that used in ReRAM (Resistance Random Access Memory), or a phase change element such as that used in PRAM (Phase change RAM).

[0169] The selection circuit 32 connects the control line CTRL1 to either the bit line BL or the power supply line 15a. The selection circuit 32a connects the control line CTRL2 to either the bit line BLB or the power supply line 15a. The power switch (PS) 30 converts the voltage VDD of the power supply 15c into a virtual power supply voltage VVDD and supplies it to the power supply line 15a.

[0170] FIG. 23 is a diagram showing power switches and a selection circuit in a virtual power supply system using a virtual power supply voltage according to the second embodiment. As shown in FIG. 23, the memory cell 10 is an NV-SRAM cell. Other circuit configurations are the same as those in FIG. 7B. In the second embodiment, the virtual power supply voltage VVDD becomes VDDH during store and restore operations, and the voltage VVDD-VGND is, for example, 1.2 V. The virtual power supply voltage VVDD becomes VDDL during a hold state, and the voltage VVDD-VGND is, for example, 1.0 V. The FETs M10 to M12 are turned off during read and write operations.

[0171] [Explanation of virtual ground memory cells] 24 is a circuit diagram of a virtual ground memory cell 10 in Example 2. As shown in FIG. 24, in the virtual ground system, a power switch 30 is provided between a ground line 15b (virtual ground line) and a ground 15d. FETs M1a to M6a are provided instead of FETs M1 to M6. FETs M1a, M2a, M5a, and M6a are P-channel FETs, and FETs M3a and M4a are N-channel FETs.

[0172] The sources of FETs M1a and M2a are connected to a power supply line 15a. The pinned layers 19 of MTJ1 and MTJ2 are connected to a control line CTRL0, and the free layers 17 are connected to FETs M5 and M6. A selection circuit 32 connects the control line CTRL1 to either the bit line BL or the ground line 15b. A selection circuit 32a connects the control line CTRL2 to either the bit line BLB or the ground line 15b. A power switch (PS) 30 converts the voltage VGND of the ground 15d into a virtual ground voltage VVGND and supplies it to the ground line 15b. The rest of the configuration is the same as that of the virtual power supply system shown in Figure 22, so a description thereof will be omitted.

[0173] FIG. 25 is a diagram illustrating a power switch and a selection circuit in the virtual ground system of the second embodiment. As shown in FIG. 25, the selection circuit 32b connects either the bit lines BL and BLB connected to the read / write circuit 34 or the ground line 15b to the control lines CTRL1 and CTRL2. The power switch 30 includes FETs PS1a and PS2a. The FETs PS1a and PS2a are N-channel FETs. The FET PS1a is connected between the ground 15dL and the ground line 15b, and the FET PS2a is connected between the ground 15dH and the ground line 15b. The grounds 15dL and 15dH are supplied with the ground voltages VGNDL and VGNDH, respectively.

[0174] Signals VPS1 and VPS2 are input to the gates of FETs PS1a and PS2a, respectively. When signals VPS1 and VPS2 are high and low, respectively, FETs PS1a and PS2a are turned on and off, respectively, and the virtual ground voltage VVGND is VGNDL. The virtual ground voltage VVGND is VGNDL during store and restore operations, and VDD-VVGND is, for example, 1.2 V. When signals VPS1 and VPS2 are low and high, respectively, FETs PS1a and PS2a are turned off and on, respectively, and the virtual ground voltage VVGND is VGNDH. The virtual ground voltage VVGND is VGNDH during the hold state, and VDD-VVGND is, for example, 1.0 V. When signals VPS1a and VPS2a are both low, both FETs PS1a and PS2a are turned off, and the virtual ground voltage VVGND is cut off. The virtual ground voltage VVGND is cut off during the shutdown state.

[0175] The precharge / selection circuit 33a includes FETs M10 to M12. FET M10 is connected between the power supply 15c and the control line CTRL1. FET M11 is connected between the power supply 15c and the control line CTRL2. FET M12 is connected between the control lines CTRL1 and CTRL2. A selection signal Sel is input to the gates of FETs M10 to M12. When the selection signal Sel is low, FETs M10 to M12 are turned on, and a power supply voltage VDD is applied to the control lines CTRL1 and CTRL2. FETs M10 to M12 are turned on during precharge for a read operation. When the selection signal Sel is high, FETs M10 to M12 are turned off, and the selection circuit 32b connects the control lines CTRL1 and CTRL2 to the bit lines BL and BLB or the ground line 15b.

[0176] The memory array and operation of the second embodiment will be described below using the virtual power supply system as an example.

[0177] [Memory array description] FIG. 26 is a block diagram of a memory array in Example 2. As shown in FIG. 26, the memory array 22 is divided into a plurality of blocks 24 each having a memory cell 10. The number of blocks 24 can be designed as appropriate. A plurality of memory cells 10 are arranged in a matrix in the memory array 22. Word lines WL and switch lines SR extend in the row direction in the memory array 22, and control lines CTRL0 to CTRL2 extend in the column direction. Word lines WL, switch lines SR, and control lines CTRL0 to CTRL2 are connected to each memory cell 10. In FIG. 26, the control lines CTRL1 and CTRL2 in columns 1 to n are indicated as control lines CTRL11 and CTRL21 to CTRL1n and CTRL2n, respectively.

[0178] A control circuit 28, a power switch 30, and a peripheral circuit 38 are provided corresponding to the memory array 22. The control circuit 28 controls the power switch 30 and the peripheral circuit 38. The peripheral circuit 38 includes a WL decoder 31, a selection circuit 32b, a precharge / selection circuit 33a, a read / write circuit 34, an SR decoder 35, and a column decoder 36.

[0179] In read and write operations, the selection circuit 32b connects the bit lines BL1, BLB1 to BLn and BLBn to the control lines CTRL11, CTRL21 to CTRL1n and CTRL2n, respectively. The WL decoder 31 selects the word line WL based on the row address. The read / write circuit 34 selects the bit lines BL and BLB corresponding to the selected column from the bit lines BL1, BLB1 to BLn and BLBn based on the column address. The precharge / selection circuit 33a precharges the bit lines BL and BLB. The read / write circuit 34 writes data to or reads data from the bistable circuit 12 of the selected memory cell 10 and outputs the data to the bus 25.

[0180] In store and restore operations, the selection circuit 32b connects the power supply line 15a to the control lines CTRL11 and CTRL21 to CTRL1n and CTRL2n. In store operations, the SR decoder 35 selects the switch line SR based on the row address. The column decoder 36 selects the control line CTRL0 based on the column address. In the memory cell 10 selected by the WL decoder 31 and the column decoder 36, the data of the bistable circuit 12 is stored in a nonvolatile manner in the ferromagnetic tunnel junction devices MTJ1 and MTJ2.

[0181] [Explanation of operation] 27(a) to 29 are diagrams showing the operation of a memory cell in Example 2. H indicates a high level, L indicates a low level, and the values ​​in parentheses indicate examples of voltages.

[0182] As shown in FIG. 27(a), a case will be described in which the voltages of storage nodes Q1 and Q2 in the bistable circuit 12 are set to H (e.g., 1.2 V) and L (e.g., 0 V), respectively. During a read operation to read data from the bistable circuit 12, the control circuit 28 causes the selection circuit 32b to use the control lines CTRL1 and CTRL2 as bit lines BL and BLB. For example, the control circuit 28 turns off FETs M10 to M12 in FIG. 23 and turns on transfer gates M13 and M14. The control circuit 28 sets the word line WL to L (e.g., 0 V), turns off FETs M5 and M6 (e.g., sets the switch line SR to L (e.g., 0 V)), and sets the control line CTRL0 to L (e.g., 0 V). The read / write circuit 34 sets the control lines CTRL1 and CTRL2 to H (e.g., 1.2 V) and reads data from the bistable circuit.

[0183] As shown in FIG. 27(b), a write operation for writing data to the bistable circuit 12 will be described taking as an example a case where the voltage of storage node Q1 is rewritten from H to L and the voltage of storage node Q2 is rewritten from L to H. The control circuit 28 causes the selection circuit 32b to function the control lines CTRL1 and CTRL2 as bit lines BL and BLB. The control circuit 28 sets the word line WL to L, turns off FETs M5 and M6, and sets the control line CTRL0 to L. The read / write circuit 34 sets the bit lines BL and BLB to L (e.g., 0 V) ​​and H (e.g., 1.2 V), respectively. As a result, L and H are written to storage nodes Q1 and Q2, respectively.

[0184] As shown in FIG. 27(c), when the bistable circuit 12 is in a hold state in which data is volatilely retained, the control circuit 28 controls the power switch 30 and the selection circuit 32b to apply a voltage VDDH (e.g., 1.2 V) to the control lines CTRL1 and CTRL2 as H. For example, the control circuit 28 turns on FETs M10 to M12 in FIG. 23, turns off transfer gates M13 and M14, turns on FET PS1, and turns off FET PS2. The control circuit 28 sets the word line WL to H (e.g., 1.2 V), turns off FETs M5 and M6, and sets the control line CTRL0 to L. As a result, the storage nodes Q1 and Q2 are maintained at H and L, respectively. As described above, during read operations, write operations, and the hold state, FETs M5 and M6 are off, so that MTJ1 and MTJ2 do not affect the bistable circuit 12.

[0185] The operation of non-volatilely storing data from the bistable circuit 12 in MTJ1 and MTJ2 will be described. The store operation involves an H-store operation (first store operation) that sets one of MTJ1 and MTJ2 to a high resistance, and an L-store operation (second store operation) that sets the other of MTJ1 and MTJ2 to a low resistance. Either the H-store operation or the L-store operation may be executed first. A hold state may be established between the H-store operation and the L-store operation.

[0186] As shown in FIG. 28(a), the following description will be given taking as an example the case where storage nodes Q1 and Q2 are H and L, respectively. During an H-store operation, control circuit 28 causes power switch 30 and selection circuit 32b to apply voltage VDDH to control lines CTRL1 and CTRL2 as H. Control circuit 28 sets word line WL to L, turns on FETs M5 and M6 (for example, sets voltage VSR to 0.7V), and sets control line CTRL0 to L. This causes current Im1 to flow from storage node Q1 to control line CTRL0 via MTJ1. MTJ1 is therefore in an antiparallel state and has high resistance.

[0187] As shown in FIG. 28(b), during an L-store operation, the control circuit 28 controls the power switch 30 and the selection circuit 32b to apply a voltage VDDH to the control lines CTRL1 and CTRL2 as H. The control circuit 28 sets the word line WL to H' (e.g., 0.8V), turns on FETs M5 and M6 (e.g., sets the voltage VSR to 0.7V), and sets the control line CTRL0 to Vc (e.g., 0.5V). This causes a current Im2 to flow from the control line CTRL0 to the storage node Q2 via MTJ2. MTJ2 is thus in a parallel state, resulting in a low resistance.

[0188] As shown in Figures 28(a) and 28(b), when FETs M1 and M2 are N-channel, the voltage VWL (first voltage) of the word line WL in the H-store operation (first store operation) is lower than the voltage VWL (fourth voltage) in the L-store operation (second store operation), and the voltage Vc (third voltage) of the control line CTRL0 in the H-store operation is lower than the voltage Vc (sixth voltage) in the L-store operation. The voltages (second and fifth voltages) of the control lines CTRL1 and CTRL2 in the H-store and L-store operations are higher than the voltage VGND of the ground line 15b. This allows data from the bistable circuit 12 to be stored in MTJ1 and MTJ2. Note that, as shown in Figure 24, when FETs M1a and M2a are P-channel, the first voltage is higher than the fourth voltage, and the third voltage is higher than the sixth voltage. The second and fifth voltages are lower than the voltage VDD of the power supply line 15a.

[0189] As shown in FIG. 28(c), after the store operation, the power supply is shut down (the voltage VVDD-VGND is set to 0V), which is the shutdown state. In the shutdown state, the control circuit 28 causes the power switch 30 and the selection circuit 32b to apply the voltage VGND (e.g., 0V) to the control lines CTRL1 and CTRL2 as L. The control circuit 28 sets the word line WL to L, turns off the FETs M5 and M6, and sets the control line CTRL0 to L. In this way, the control circuit 28 shuts down the power supply to the memory cell 10. In the shutdown state, the MTJ1 and MTJ2 are maintained at high resistance and low resistance, respectively. The power supplies to the control circuit 28 and the peripheral circuit 38 may or may not be shut down.

[0190] As shown in FIG. 29, the case where MTJ1 and MTJ2 are high-resistance and low-resistance, respectively, will be described as an example. During a restore operation to restore data from MTJ1 and MTJ2 to the bistable circuit 12, the control circuit 28 raises the control lines CTRL1 and CTRL2 of the power switch 30 and the selection circuit 32b from L to H' (e.g., 1.0 V). The control circuit 28 sets the word line WL to L' (e.g., 0.1 V), turns on FETs M5 and M6 (e.g., voltage VSR is set to 0.7 V), and sets the control line CTRL0 to L. A current Im3 flows from the control line CTRL1 to MTJ1 via FETs M3 and M5. Similarly, a current Im4 flows from the control line CTRL2 to MTJ2 via FETs M4 and M6. Because MTJ1 and MTJ2 are high-resistance and low-resistance, respectively, the current Im4 is greater than Im3. As a result, the voltage at storage node Q2 decreases faster than the voltage at storage node Q1. Therefore, the storage nodes Q1 and Q2 are stabilized at H and L, respectively. This completes the restore operation. After the restore operation, the bistable circuit 12 is put into a hold state, thereby volatilely retaining the data. Furthermore, read and write operations are performed.

[0191] 27(a) and 27(b), the control circuit 28 turns off FETs M5 and M6 during a write operation in which data is volatilely written to the bistable circuit 12 and a read operation in which data is read from the bistable circuit 12. As shown in FIGS. 28(a), 28(b), and 29, the control circuit 28 turns on FETs M5 and M6 during a store operation in which data is nonvolatilely stored from the bistable circuit 12 to MTJ1 and MTJ2 and during a restore operation in which data is restored from MTJ1 and MTJ2 to the bistable circuit 12. This makes it possible to suppress the influence of MTJ1 and MTJ2 on the bistable circuit 12 during write and read operations.

[0192] [Simulation 3] Appropriate channel widths and voltages in Example 2 were simulated. In Simulation 3, the following steps S1 to S5 were performed to determine each channel width and voltage. First, by analogy with Comparative Example 3 (6T-SRAM), the channel width of each FET was set as follows: The channel length of each FET was 60 nm.

[0193] FETM1, M2: WDRV=150nm FETM3,M4:WLP=100nm FETM5, M6: WSR=100nm

[0194] [Step S1] In step S1, the channel widths WLP of FETs M3 and M4 were determined from the SNM in the hold state of the 4T cells (FETs M1 to M4) of the bistable circuit 12 of Example 2. FIG. 30 is a diagram showing SNM and standby power versus WLP in the hold state in Simulation 3. The channel widths WDRV of FETs M1 and M2 are 150 nm, the voltage VWL of the word line WL is 1.2 V, and the voltage VDDH of the control lines CTRL1 and CTRL2 is 1.2 V. SNM is illustrated for TT, SS, SF, FS, and FF. For standby power, the simulation results for Example 2 (4T cell) are shown with a solid line, and the simulation results for Comparative Example 3 (6T cell) are shown with a dashed line.

[0195] As shown in Figure 30, as the WLP increases, the SNM increases, but the standby power also increases. When the WLP is 105 nm or greater, all SNMs are 80 mV or greater. When the WLP is 110 nm or greater, the standby power exceeds that of Comparative Example 3. For these reasons, we decided on a WLP of 105 nm.

[0196] [Step S2] In step S2, the word line WL voltage VWL for read, write, and hold operations was determined from the SNM for the 4T cell during read and hold operations. Figure 31 shows the SNM versus VWL for read and hold operations in Simulation 3. The channel widths WDRV of FETs M1 and M2 are 150 nm, WLP of FETs M3 and M4 are 105 nm, and the voltage VDDH of control lines CTRL1 and CTRL2 is 1.2 V. SNM is illustrated for TT, SS, SF, FS, and FF. VWL near 0 V corresponds to read and write operations that turn on FETs M3 and M4, and VWL near 1.2 V corresponds to a hold state that turns off FETs M3 and M4.

[0197] As shown in Figure 31, SNM depends on VWL. As VWL increases from 0V, SNM increases, and as VWL decreases from 1.2V, SNM increases. SNM is largest when VWL is 0.7V to 0.8V. Since SNM is 80mV or more at VWL=0V and 1.2V, we set VWL to 0V for read and write operations, and 1.2V for hold state.

[0198] [Step S3] In step S3, the current Im1 (see Figure 28(a)) for the H-store operation was designed. The target current Im1 was 1.2 times the threshold current Ic at which MTJ1 and MTJ2 switch from a parallel state to an antiparallel state. In the store operation, the control lines CTRL1 and CTRL2 are H (1.2V) to retain the data in the bistable circuit 12. To pass current Im1 from the H storage node Q1 to MTJ1, the voltage Vc of the control line CTRL0 is set to 0V. FETs M5 and M6 are turned on. FET M3 is turned on so that storage node Q1 does not go low. For this reason, the voltage VWL of the word line WL is set to 0V.

[0199] Figures 32(a) and 32(b) show the current Im1 and SNM, respectively, versus the voltage VSR for H-store operation in Simulation 3. As shown in Figure 32(a), as the voltage VSR increases, the current Im1 increases. When the voltage VSR is 0.7 V or higher, the current Im1 is 1.2 Ic or higher. As shown in Figure 32(b), as the voltage VSR increases, the SNM decreases. When the voltage VSR is 0.95 V or higher, the SNM falls below 80 mV. The voltage VSR was set to 0.7 V so that the SNM is 80 mV or higher and the current Im1 is around 1.2 Ic.

[0200] [Step S4] In step S4, the current Im2 (see Figure 28(b)) for the L-store operation was designed. The target current Im2 was 1.2 times or more the threshold current Ic at which MTJ1 and MTJ2 switch from an antiparallel state to a parallel state. To retain the data in the bistable circuit 12, the control lines CTRL1 and CTRL2 are set to H (1.2V). To pass the current Im2 from the control line CTRL0 to the L storage node Q2 via MTJ2, the voltage Vc of the control line CTRL0 is set higher than L. To turn on FETs M5 and M6, the voltage VSR is set to 0.7V, the same as for the H-store operation. The voltage VWL of the word line WL and the voltage Vc of the control line CTRL0 were changed.

[0201] Figures 33(a) and 33(b) show the currents Im2 and SNM, respectively, versus the voltage Vc for the L-store operation in Simulation 3. Because SF is the smallest, SF is shown as SNM. As shown in Figure 33(a), as the voltage Vc of the control line CTRL0 increases, the current Im2 increases, and as the voltage VWL of the word line WL increases, the current Im2 also increases. The reason why the current Im2 decreases as the voltage VWL decreases is that when the voltage VWL is near 0V, FET M4 is fully on, causing the voltage at storage node Q2 to increase.

[0202] As shown in Figure 33(b), increasing the voltage VWL from 0V increases SNM, but decreases when VWL is 0.4V or higher. At VWL of 0.9V, SNM is less than 80mV. This is because FET M4 turns off when the voltage VWL is high, making it impossible to retain data. When the voltage VWL is set to 0.5V to 0.8V, an Im2 current of 1.2Ic and an SNM of 100mV or higher can be achieved by appropriately selecting the voltage Vc. The voltage VWL was set to 0.8V and the voltage Vc to 0.5V. In this way, by setting the voltage VWL for the L-store operation higher than the voltage VWL for the H-store operation, the decrease in SNM during the L-store operation can be suppressed.

[0203] Furthermore, the voltage VWL during the L-store operation is preferably such that FETs M3 and M4 are slightly turned on. Therefore, when FETs M1 and M2 are N-channel, the voltage VWL during the L-store operation is preferably lower than the voltage of the control lines CTRL1 and CTRL2. Furthermore, when FETs M1a and M2a are P-channel, the voltage VWL during the second store operation is preferably higher than the voltage of the control lines CTRL1 and CTRL2. This allows for a larger SNM. The voltage VWL during the second store operation is preferably greater than VGND+1 / 4 (VDD-VGND) and less than VDD-1 / 4 (VDD-VGND).

[0204] [Step S5] In step S5, the voltage VSR of the switch line SR and the voltage VWL of the word line WL for the restore operation are determined. In the restore operation, the voltage Vc of the control line CTRL0 is set to 0V, and the voltages of the control lines CTRL1 and CTRL2 are increased. Data can be restored to the bistable circuit 12 without increasing the voltages of the control lines CTRL1 and CTRL2 to the voltage VDDH (1.2V). Therefore, the restore operation is terminated when the voltages of the control lines CTRL1 and CTRL2 are increased to 1.0V. After the restore operation, for example, when a hold state is to be established, the voltages of the control lines CTRL1 and CTRL2 are increased to VDDH (1.2V). This allows the voltage VSR to be set to 0V and the voltage VWL to be set to 1.0V or higher when the voltages of the control lines CTRL1 and CTRL2 are 1.0V or higher, thereby reducing power consumption.

[0205] Figures 34(a) and 34(b) show the SNM versus the voltage VSR of FF and FS, respectively, during the restore operation in Simulation 3. This graph shows the SNM when the voltages of the control lines CTRL1 and CTRL2 are 1.0 V. As shown in Figures 34(a) and 34(b), when FETs M3 and M4 are off (e.g., VWL = 0.8 V), increasing the voltage VSR of the switch line SR reduces the voltage at the high storage node Q1, thereby reducing SNM. By lowering the voltage VWL of the word line WL and turning on FETs M3 and M4, current flows from the control line CTRL1 to the high storage node Q1, maintaining the high level at storage node Q1 and increasing SNM. Lowering the voltage VWL too much increases the voltage at the low storage node Q2, reducing SNM. Taking these factors into consideration, we set the voltage VSR to 0.7 V, the same as for the store operation, and the voltage VWL to 0.1 V.

[0206] When a restore operation is performed, the voltage VWL of the word line WL is higher than the lower voltage VDD (e.g., 0 V) ​​of the storage nodes Q1 and Q2 during a write operation, and lower than the higher voltage VGND (e.g., 1.2 V) of the storage nodes Q1 and Q2. This allows SNM to be increased, as shown in Figures 34(a) and 34(b). The voltage VWL during a restore operation is preferably lower than VGND+1 / 4 (VDD-VGND) when FETs M1 and M2 are N-channel, and is preferably higher than VDD-1 / 4 (VDD-VGND) when FETs M1a and M2a are P-channel.

[0207] Table 5 shows the channel width and voltages of each FET determined based on the above steps S1 to S5.

[0208] [Table 5]

[0209] In Table 5, the voltage VWL of the word line WL in the read operation, write operation, H-store operation, and L-store operation is the voltage VWL of the accessed memory cell 10. The voltage VWL of the memory cell 10 that is not accessed is 1.2 V (high level) at which FETs M3 and M4 are turned off.

[0210] In Table 5, -0.2V, lower than L, is applied as the voltage VSR of the switch line SR during the hold state, read operation, and write operation. This is to suppress the leakage current of FETs M5 and M6. The voltage VSR may be a voltage that turns off FETs M5 and M6. To suppress the leakage current of FETs M5 and M6 during the hold state, read operation, and write operation, the voltage Vc of the control line CTRL0 may be made higher than L. For example, the voltage Vc may be set to 0.05V. The voltage VSR may be made lower than L and the voltage Vc may be made higher than L.

[0211] The voltage VSR in the H-store operation, L-store operation, and restore operation should be sufficient to turn on FETs M5 and M6. The voltage VWL of the word line WL in the hold state should be sufficient to turn off FETs M3 and M4, and the voltage VWL in the read operation, write operation, H-store operation, and restore operation should be sufficient to turn on FETs M3 and M4. The channel width and each voltage are not limited to the examples in Table 5 and can be set appropriately.

[0212] Using the values ​​in Table 5, SNM was simulated for each state and operation. Figure 35(a) shows the SNM in Example 2. As shown in Figure 35(a), the SNM of FS in the hold state is the smallest. The SNM is 80 mV or more in all states and at all corners of the operation. In TT, the SNM is 100 mV or more in all states and operations.

[0213] The standby power in Example 2 was simulated and compared with that of Comparative Example 3 (6T cell) described in Fig. 15. Fig. 35(b) is a diagram showing the standby power of Example 2 and Comparative Example 3.

[0214] As shown in Figure 35(b), in Comparative Example 3, the reduction rate in sleep mode with VVDD = 0.8V compared to normal operation with VVDD = 1.2V is 44%. The reduction rate in standby power when VVDD = 1.2V in Example 2 compared to VVDD = 1.2V in Comparative Example 3 is 11%. Furthermore, the reduction rate in standby power in shutdown mode with VVDD = 1.2V in Example 2 is 99.99%.

[0215] As described above, in Example 2, FETs M1 and M2 are FETs with channels of a first conductivity type, FETs M3 and M4 are FETs with channels of a second conductivity type opposite to the first conductivity type, and FETs M3 and M4 are used as pass transistors and loads. This allows for low standby power and the number of transistors to be reduced to six, thereby enabling miniaturization.

[0216] [Modification 1 of Example 2] FIG. 36 is a circuit diagram of a memory cell according to Modification 1 of Example 2. As shown in FIG. 36, in Modification 1 of Example 2, FETM5 and MTJ1 are connected between the storage node Q1 and the control line CTRL0 in FIG. 6 of Example 1, and FETM6 and MTJ2 are connected between the storage node Q2 and the control line CTRL0. In this manner, the bistable circuit 12 may be the bistable circuit of Example 1 and its modifications. As in FIGS. 7B and 23, a precharge / selection circuit 33a may be connected to the ends of the control lines CTRL1 and CTRL2, and a selection circuit 32b may be connected to the other ends of the control lines CTRL1 and CTRL2.

[0217] When the interval between accesses to the memory cell 10 is short, data is ULV-retained in the bistable circuit 12, and when the interval between accesses is long, data is stored in MTJ1 and MTJ2 and then shut down, thereby further reducing power consumption. [Example]

[0218] Example 3 is an example of application to a binary neural network (BNN) such as BinaryNET or XNOR-NET. BNNs can be realized with low power consumption and small memory without significantly degrading inference accuracy, and are therefore expected to be applied to edge computing. In edge computing, learning and inference are not always performed, but data such as weights stored in the BNN device must be retained in memory. Therefore, reducing the standby power consumption of the memory becomes an issue. Using ULVR-SRAM or NV-SRAM in the memory portion of the BNN device (BNN accelerator) makes it possible to reduce the standby power consumption of the memory.

[0219] 37 is a diagram illustrating a BNN model in Example 3. The following describes a BNN model using the Batch Normalization Free Technique (Y. Yonekawa and H. Nakahara, "On-chip Memory Based Binarized Convolutional Deep Neural Network Applying Batch Normalization Free Technique on an FPGA," 2017 IEEE International Parallel and Distributed Processing Symposium Workshops, pp. 98-105, 2017).

[0220] As shown in Figure 37, an example will be explained using three layers: X, Y, and Z. The number of layers may be four or more. The X layer has nodes x1 to xn, the Y layer has nodes y1 to yn, and the Z layer has nodes z1 to zn. Nodes x1 to xn, y1 to yn, and z1 to zn are each 1-bit. The output of each node x1 to xn in the X layer is multiplied by a 1-bit weight w1i to wni (i is an integer from 1 to n) and input to node yi. Furthermore, an integer bias W0i is input to node yi from node l. The output of node yi is obtained by passing this sum through an evaluation function. The data for all nodes yi can be obtained by performing the above calculation for all i (integers from 1 to n). The output of node yj in the Y layer is multiplied by a 1-bit weight w'j1 to w'jn (j is an integer from 1 to n) and input to each node zk (k is an integer from 1 to n). Node zj receives an integer bias W'j0 from node l. The above calculation is performed for all j (integers from 1 to n), and each node zj adds up the inputs. After this calculation is complete, the sum is passed through an evaluation function to obtain the output of each node zk (k = 1 to n). Each piece of data in the weight matrices w11 to wnn and w'11 to w'nn is 1 bit, and each piece of data in the integer bias sequences W01 to W0n and W'10 to W'n0 is an integer (multi-bit). The same applies if there are layers after layer Z.

[0221] In the third embodiment, the calculation to calculate the Y layer from the X layer involves calculation corresponding to the solid line from nodes x1 to xn to node y1, then calculation corresponding to the dashed line from nodes x1 to xn to node y2, and then calculation corresponding to the dotted line from nodes x1 to xn to node y3. After that, calculations are performed sequentially for nodes y4 to yn. This is called an n-to-1 connection. The calculation to calculate the Z layer from the Y layer involves calculation of the solid line from node y1 to nodes z1 to zn, then calculation of the dashed line from node y2 to nodes z1 to zn, and then calculation of the dotted line from node y3 to nodes z1 to zn. This is called a 1-to-n connection. The calculations for the solid and dashed lines of the 1-to-n connection can be performed in parallel with the calculations for the dashed and dotted lines of the n-to-1 connection, respectively.

[0222] FIG. 38 is a block diagram of an arithmetic circuit that performs an n-to-1 connection calculation in the third embodiment. As shown in FIG. 38, the arithmetic circuit 50 includes a memory 51 and a processing unit 52. The processing unit 52 includes an XNOR circuit 53, a counter 54, an adder 55, an evaluation unit 56, and an output unit 57. The input unit 48 is an n-bit latch circuit that holds data of nodes x1 to xn. The XNOR circuit 53 obtains the data of nodes x1 to xn from the input unit 48, obtains the weight sequence w1i to wni from the memory 51, and performs an XNOR operation on the data of nodes x1 to xn and the weight sequence w1i to wni. The counter 54 performs bit counting of the output of the XNOR circuit 53 and calculates the sum. In other words, it calculates the number of bits that are 1 in the output of the n XNOR circuits 53. The adder 55 obtains an integer bias W0i from the memory 51 and adds it to the output of the counter 54. The evaluation unit 56 compares the output of the adder 55 with the evaluation function f and outputs the 1-bit result as data of the node yi to the output unit 57. The output unit 57 is a 1-bit latch circuit and holds the data of the node yi.

[0223] Fig. 39(a) is a block diagram of an arithmetic circuit that performs 1-to-n connection calculations in Example 3. As shown in Fig. 39(a), arithmetic circuit 60 includes memory 61 and processing unit 62. Processing unit 62 includes XNOR circuit 63, accumulator 64, adder 65, evaluation unit 66, and output unit 67. XNOR circuit 63 obtains data of node yi from output unit 57, obtains weight sequence w'i1 to w'in from memory 61, and performs an XNOR operation on the data of node yi and weight sequence w'i1 to w'in.

[0224] Figure 39(b) is a block diagram of the accumulator. As shown in Figure 39(b), the accumulator 64 includes an adder 64c and a latch circuit 64d. The adder 64c adds the output of the latch circuit 64d and the output of the XNOR circuit 63. The latch circuit 64d holds the output of the adder 64c. The latch circuit 64d is reset in advance, and when i changes from 1 to n, it sequentially adds up the outputs of the XNOR circuit 63 for each i. Then, when i=n, ​​it outputs the numerical value of the calculation result to the adder 65. In this way, the accumulator 64 accumulates the outputs of the n XNOR circuits 63 for i=1 to n.

[0225] 39(a), adder 65 obtains integer bias sequence W'10 to W'n0 from memory 61 and adds it to the output sequence of accumulator 64. Evaluation unit 66 compares the output sequence of adder 65 with evaluation function f, and outputs each 1-bit result as data for nodes z1 to zn to output unit 67. Output unit 67 is an n-bit latch circuit, and holds the data for nodes z1 to zn.

[0226] FIG. 40 is a block diagram of a BNN device in Example 3. As shown in FIG. 40, memories 51 (first memory) and 61 (second memory) are arranged in a matrix. The memory 51 stores an integer bias sequence W01 to W0n and a weight matrix w11 to wnn. The weights w11 to wnn are each stored in a memory cell 10 (first memory cell). In the memory 51, multiple weights w1i to wni corresponding to one node yi are stored in the same row, and multiple weights corresponding to different nodes yi (for example, w11 to wn1 and w12 to wn2) are stored in different rows. The multiple memory cells 10 in the same row are respectively connected to multiple bit lines BL (first bit lines) extending in the column direction. Each integer bias (W01 to W0n) is multi-bit and is stored in the memory cell 10.

[0227] The memory 61 stores integer bias columns W'10 to W'n0 and weight matrices w'11 to w'nn. The weights w'11 to w'nn are each stored in a memory cell 10' (second memory cell). In the memory 61, multiple weights w'i1 to w'in corresponding to one second node yi are stored in the same row, and multiple weights corresponding to different second nodes yi (for example, w'11 to w'1n and w'21 to w'2n) are stored in different rows. The multiple memory cells 10' in the same row are respectively connected to multiple second bit lines BL' extending in the column direction. Each integer bias (W'10 to W'n0) is multi-bit and is stored in the memory cell 10'.

[0228] By storing the weight matrices in the memories 51 and 61 as described above, the processing unit 52 can obtain a plurality of first weights w1i to wni from the memory 51 via a plurality of bit lines BL when processing node yi. Furthermore, the processing unit 62 can obtain a plurality of weights w'i1 to w'in from the memory 61 via a second bit line BL' when processing node yi. This allows the processing units 52 and 62 to perform processing efficiently. The memory cells 10 and 10' may be 6T-SRAM cells, or may be the memory cells 10 of Examples 1 and 2 and their modifications. At least a portion of the processing units 52 and 62 may be realized as a dedicated circuit. At least a portion of the processing units 52 and 62 may be realized by a processor working in cooperation with software. In this case, at least a portion of the processing units 52 and 62 is the processor.

[0229] In the arithmetic circuit 50, XNOR circuits 53 are provided corresponding to the columns of weight matrices w11 to wnn, and perform an XNOR operation on the output data of nodes x1 to xn of the input unit 48 and the weight matrices w1i to wni. A counter 54 counts the output bits of the XNOR circuits 53. The adder 55, evaluation unit 56, and output unit 57 are the same as those described in FIG. 38.

[0230] In the arithmetic circuit 60, the XNOR circuits 63 to the output unit 67 are provided corresponding to the columns of the weight matrices w'11 to w'nn. The XNOR circuit 63 performs an XNOR operation on the output data of node yi of the output unit 57 and the weight matrix w'i1 to w'in. The operation is performed for each column from the accumulator 64 to the output unit 67. Other operations are the same as those explained in Figure 39(a). When there are four or more layers, the nodes z1 to zn of the output unit 67 become the input data string for the n-to-1 connection processing of the next layer.

[0231] FIG. 41 is a flowchart showing the n-to-1 connection processing performed by the processing unit 52 in the third embodiment. As shown in FIG. 41, the processing unit 52 sets i to 1 (step S10). The processing unit 52 acquires the weight sequence w1i to wni from the memory 51 (step S12). The processing unit 52 calculates the XNOR of the data of nodes x1 to xn and the weight sequence w1i to wni (step S14). The processing unit 52 performs bit counting of the calculation results of each XNOR and calculates the sum (step S16). The processing unit 52 acquires the weight W0i from the memory 51 and adds it to the sum (step S18) of step S16. The processing unit 52 compares the result of step S18 with the evaluation function f to calculate and store 1-bit data of node yi (step S20). The processing unit 52 determines whether i=n (step S22). If No, the processing unit 52 sets i=i+1 and proceeds to step S12 (step S24). If the answer is Yes, the n-to-1 connection process ends. The processing unit 52 may include a control circuit that controls the operation of each circuit, and the control circuit may execute steps S10 to S24.

[0232] FIG. 42 is a flowchart showing the 1-to-n connection processing performed by the processing unit 62 in the third embodiment. As shown in FIG. 42, the processing unit 62 sets i to 1 (step S30). The processing unit 62 acquires the weight sequence w′i1 to w′in from the memory 61 (step S32). The processing unit 62 acquires the data of node yi from step S20 of FIG. 41, and calculates the XNOR of the data of node yi and the weight sequence w′i1 to w′in (step S34). The processing unit 62 accumulates each of the n XNOR calculation results (step S36). The processing unit 62 determines whether i=n (step S38). If the result is No, the processing unit 62 sets i=i+1 and returns to step S32 (step S40). If the result is Yes in step S38, the processing unit 62 acquires the weights W′10 to W′n0 from the memory 61, and adds them to the n results of step S36, respectively (step S42). The processing unit 62 compares each of the n results of step S42 with the evaluation function f to calculate and store 1-bit data for each of nodes z1 to zn (step S44). Thereafter, the 1-to-n connection process ends. The data for nodes z1 to zn becomes the input data string when making the n-to-1 connection in the next layer. The processing unit 62 may include a control circuit that controls the operation of each circuit, and the control circuit may execute steps S30 to S44.

[0233] FIG. 43 is an explanatory diagram showing the processing operations of the third embodiment along a time axis. In FIG. 43, the processing operations of the third embodiment are illustrated so as to be comparable with the processing operations of Cases 1 and 2 described later. Processes 71 to 74 show calculations between layers. For example, process 71 is a process of calculating each of the nodes y1 to yn in the Y layer from each of the nodes x1 to xn in the X layer in FIG. 37, and process 72 is a process of calculating each of the nodes z1 to zn in the Z layer from each of the nodes y1 to yn in the Y layer. Process 73 is a process of calculating each of the nodes in the subsequent layer from each of the nodes z1 to zn in the Z layer. Process 74 is a process further subsequent. Process 70 shows a process corresponding to one node. In n-to-1 connection processing, process 70 corresponds to a process of calculating one node yi from n nodes x1 to xn. In 1-to-n connection processing, process 70 corresponds to a process of calculating n nodes z1 to zn from one node yi. Each of the processes 71 to 74 executes n processes 70 sequentially.

[0234] In case 1, processes 71 to 74 are all n-to-1 connection processes or all 1-to-n connection processes. In this case, processes 71 to 74 cannot be processed in parallel. In case 2, processes 71 and 73 are 1-to-n connection processes, and processes 72 and 74 are n-to-1 connection processes. In this case, processes 71 and 72 cannot be processed in parallel. Processes 72 and 73 can be processed in parallel.

[0235] In the third embodiment, processes 71 and 73 are n-to-1 connection processes, and processes 72 and 74 are 1-to-n connection processes. In this case, the (i+1)th process 70 of process 71 and the i-th process of process 72 can be processed in parallel. Therefore, processes 70 and 71 can be processed in the time it takes for n+1 processes 70. After process 72 is completed, process 73 starts. The (i+1)th process 70 of process 73 and the i-th process of process 74 can be processed in parallel.

[0236] As described above, in case 2, the processing time can be reduced more than in case 1, but in embodiment 3, the processing time can be reduced even more than in case 2.

[0237] The memory array 22 of the first embodiment shown in Fig. 7A or the memory array 22 of the second embodiment shown in Fig. 26 can be used for the memories 51 and 61 of the third embodiment, thereby reducing power consumption.

[0238] FIG. 44 is a block diagram showing an example of a memory according to the third embodiment. As shown in FIG. 44, power switches PS1 to PSn are provided for each row of memories 51 and 61. Furthermore, a power switch control circuit 58 is provided to independently control the power switches PS1 to PSn to different states. This allows virtual power supply voltages VVDD1 to VVDDn to be set for each row. During n-to-1 connection processing and 1-to-n connection processing, the power switch control circuit 58 supplies a first power supply voltage to a row in which data to be processed is stored so that the data can be read. The power switch control circuit 58 sets the other rows to a ULV retention state when the memory array of the first embodiment is used for memories 51 and 61, and to a shutdown state when the memory array of the second embodiment is used.

[0239] For example, when the processing unit 52 performs the ith process in FIG. 41 or when the processing unit 62 performs the ith process in FIG. 42, the power switch control circuit 58 sets the virtual power supply voltage VVDDi supplied to the ith row of the memory 51 or 61 to a first power supply voltage at which data can be read from the memory cell 10 or 10', and sets the virtual power supply voltage VVDDi supplied to rows other than the ith row to a second power supply voltage lower than the first power supply voltage at which the memory cell 10 or 10' can retain data, or shuts down the power supply voltage. When the memory array of Example 1 is used for the memory 51 or 61, the second power supply voltage is a voltage that results in a ULV retention state. When the memory array of Example 2 is used for the memory 51 or 61, the power supply voltage is shut down. The power switch control circuit 58 simply supplies the second power supply voltage to or shuts down the power supply voltage for at least some of the rows other than the ith row.

[0240] This control of the power switch control circuit 58 can suppress the power consumption of the memories 51 and 61. This reduces the power consumption of the entire neural network. The control of the power switches PS1 to PSn is not limited to the above-described control. Taking into consideration the recovery time from the ULV retention state of the memories 51 and 61 until data can be read, or the recovery time from the shutdown state in the memory array of the second embodiment until data can be read, power may be supplied so that rows adjacent to a row performing n-to-1 connection processing and 1-to-n connection processing can also be read. Each virtual power supply voltage VVDD1 to VVDDn may have multiple stages. In this case, power switches corresponding to the number of virtual power supply voltages are provided. In FIG. 44, a power switch is provided for each row, but a power switch may be provided for every multiple rows. Although the virtual power supply system has been described as an example, a virtual ground system may also be used.

[0241] FIG. 44 illustrates an example in which power consumption is reduced by controlling the power switches PS1 to PSn in both n-to-1 connection processing and 1-to-n connection processing in neural network processing. In the fourth aspect of the present invention, power consumption may be reduced by controlling the power switches PS1 to PSn in at least one of n-to-1 connection processing and 1-to-n connection processing. Furthermore, in a processing device having an inference unit trained by deep learning, in which n-to-1 connection processing and 1-to-n connection processing are repeated multiple times, power consumption can be reduced by controlling the power switches PS1 to PSn in at least one of the n-to-1 connection processing and 1-to-n connection processing. All of these are included in the embodiments of the fourth aspect of the present invention.

[0242] The power consumption of a BNN device was simulated when the 6T cells of Comparative Example 3 and the ULVR-SRAM cells of Example 1 were used as memory cells 10 and 10' in memories 51 and 61. When memory cells 10 and 10' were 6T cells, the power consumption of the memory was reduced by 50% to 60% when the power supply voltage was set to 70% of the normal state and the memory was placed in a sleep state. When memory cells 10 and 10' were ULVR-SRAM cells of Example 1, the power consumption of the memory was reduced by 90% to 95% compared to the normal state of 6T cells. Thus, the power consumption of a BNN device can be reduced by using the ULVR-SRAM cells of Example 1 or the NV-SRAM cells of Example 2 as memory cells 10 and 10'. Alternatively, the ULVR-SRAM cells described in Patent Document 1 or the NV-SRAM cells described in Patent Document 2 may be used as memory cells 10 and 10'. This reduces standby power consumption.

[0243] According to the third embodiment, as in step S14 of FIG. 41, the processing unit 52 (first processing unit) performs weighting on a plurality of first data corresponding to a plurality of first nodes x1 to xn in the X layer (first layer) using a plurality of first weights w1i to wni, and then performs addition as in step S18, thereby calculating data for one second node yi among a plurality of second data corresponding to a plurality of second nodes y1 to yn in the Y layer (second layer) as in steps S16, S18, and S20. The processing unit 52 performs this process for the plurality of second nodes y1 to yn to calculate a plurality of second data. As in step S32 of FIG. 42, the processing unit 62 (second processing unit) performs a process for the plurality of second nodes y1 to yn to calculate a portion of each of a plurality of third data corresponding to third nodes z1 to zn in the Z layer (third layer) by weighting data for one second node yi among the plurality of second nodes y1 to yn using a plurality of second weights w′i1 to w′in. As in steps S36 and S44, the processing unit 62 calculates data for the multiple third nodes z1 to zn by adding part of the data for the multiple third nodes z1 to zn for the multiple second nodes y1 to yn for each of the multiple third nodes z1 to zn. Then, the processing unit 62 processes another second node yi+1 of the multiple second data in parallel with the processing of one second node yi of the multiple second data performed by the processing unit 62. This makes it possible to reduce the processing time of the processing device, as shown in FIG.

[0244] The data of nodes x1 to xn, y1 to yn and z1 to zn, and the weights w11 to wnn and w'11 to w'nn each have one bit. This makes it possible to process the BNN. In the BNN, the processing unit 52 performs weighting by performing an XNOR operation on the data of the multiple first nodes x1 to xn and the multiple first weights w1i to wni, and the processing unit 62 performs weighting by performing an XNOR operation on the data of the second node yi and the multiple second weights w'i1 to w'in. This makes it possible to perform weighting in the BNN.

[0245] [Modification 1 of Example 3] 45 is a block diagram of a BNN device in a first modification of the third embodiment. As shown in FIG. 45, in the first modification of the third embodiment, a processing unit 52 is provided with XNOR circuits 53a and 53b, counters 54a and 54b, adders 55a and 55b, evaluation units 56a and 56b, and output units 57a and 57b, each corresponding to a plurality of rows of a memory 51. The processing unit 52 performs processing corresponding to a plurality of rows of the memory 51 in parallel. A processing unit 62 is provided with XNOR circuits 63a and 63b, each corresponding to a plurality of rows of a memory 61. The processing unit 62 performs processing corresponding to a plurality of rows of the memory 61 in parallel.

[0246] FIG. 46 is a diagram illustrating an example of a memory according to Modification 1 of Example 3. Peripheral circuits other than sense amplifiers 44a and 44b are omitted from FIG. 46. As shown in FIG. 46, memories 51 and 61 have memory cells 10a and 10b arranged in a matrix. Bit lines BL1 and BLB1 and bit lines BL2 and BLB2 extend in the column direction. Of memory cells 10a and 10b in the same column, memory nodes Q1 and Q2 (see FIGS. 1 and 22, etc.) of memory cell 10a are connected to bit lines BL1 and BLB1, respectively, but are not connected to bit lines BL2 and BLB2. Memory nodes Q1 and Q2 of memory cell 10b are connected to bit lines BL2 and BLB2, respectively, but are not connected to bit lines BL1 and BLB1.

[0247] A plurality of sense amplifiers 44a and 44b are provided in each column. Bit lines BL1 and BLB1 are connected to the sense amplifier 44a, and bit lines BL2 and BLB2 are connected to the sense amplifier 44b. The sense amplifiers 44a and 44b read data from memory cells 10a and 10b selected by word lines WL, respectively. The sense amplifiers 44a and 44b output the read data to the XNOR circuits 53a (or 63a) and 53b (or 63b), respectively. That is, when performing one parallel processing operation, the processing units 52 and 62 obtain weights from the memories 51 and 61 via BL1 and BLB1, respectively, and when performing another parallel processing operation, obtain weights from the memories 51 and 61 via bit lines BL2 and BLB2, respectively. This allows weight columns of multiple rows to be output in parallel from the memory 51 or 61 to the XNOR circuits 53a and 53b (or 63a and 63b) without using a multiport cell, which will be described later in a second modification of the third embodiment. The memory cell 10 may be a 6T cell such as that of Comparative Example 3, or may be the memory cell 10 of Examples 1 and 2 and their modifications.

[0248] [Modification 2 of Example 3] Modification 2 of Example 3 is an example in which multiport cells are used for memories 51 and 61. As multiport cells, a 2R1W type with one write port and two read ports and a 2RW type with two write ports and two read ports will be described.

[0249] 47 is a circuit diagram showing an example of a 2R1W NV-SRAM memory cell in Modification 2 of Example 3. As shown in FIG. 47, WWL, RWL1, and RWL2 are provided as word lines. WWL is a write word line, and RWL1 and RWL2 are read word lines. Control lines CTRL1 to CTRL3 are provided.

[0250] The gate of FET M3 is connected to WWL, one of its source and drain is connected to storage node Q1, and the other of its source and drain is connected to control line CTRL1. The gate of FET M41 is connected to RWL1, one of its source and drain is connected to storage node Q2, and the other of its source and drain is connected to control line CTRL2. The gate of FET M42 is connected to RWL2, one of its source and drain is connected to storage node Q2, and the other of its source and drain is connected to control line CTRL3. The other configurations are the same as those of Example 2, and therefore will not be described again.

[0251] Table 6 shows the voltages on each line in each state and operation.

[0252] [Table 6]

[0253] In Table 6, the voltages of the word lines WWL, RWL1, and RWL2 in the write operation, read operation 1, and read operation 2 are the voltages in the accessed memory cell 10. The voltages of the word lines WWL, RWL1, and RWL2 in the memory cells 10 that are not accessed are 1.2V.

[0254] As shown in Table 6, in the hold state, the voltages of WWL, RWL1, RWL2, and CTRL1 to CTRL3 are 1.2V (high level), and FETs M3, M41, and M42 are off. During a write operation, the voltage of WWL of the cell 10 to be written to is set to 0V (low level). This turns on FET M3 of the cell to be written to. The voltages of word lines RWL1 and RWL2 are 1.2V, and FETs M41 and M42 are off. By setting the voltage of control line CTRL1 to 1.2V or 0V, storage node Q1 becomes H or L. This allows data to be written to cell 10.

[0255] During read operation 1, the voltage of RWL1 of the cell 10 to be read is set to 0V. This turns on FET M41 of the cell 10 to be read. The voltage of RWL2 is 1.2V, and FET M42 is off. The voltage of WWL is 0.7V, which slightly turns on FET M3. By floating (FL) the voltage of control line CTRL2 from 1.2V, data at storage node Q2 is read from control line CTRL2. The voltages during read operation 2 are the same as those in read operation 1. Other operations are the same as those in Example 2.

[0256] 48 is a circuit diagram showing an example of a 2R1W type ULVR-SRAM memory cell in Modification 2 of Example 3. As shown in Fig. 48, WWL, RWL1, and RWL2 are provided as word lines. Control lines CTRL1 to CTRL3 are also provided.

[0257] The gate of FETm4 is connected to WWL, one of its source and drain is connected to storage node Q1, and the other of its source and drain is connected to control line CTRL1. The gate of FETm41 is connected to RWL1, one of its source and drain is connected to storage node Q2, and the other of its source and drain is connected to control line CTRL2. The gate of FETm42 is connected to RWL2, one of its source and drain is connected to storage node Q2, and the other of its source and drain is connected to control line CTRL3. The other configurations are the same as those in Example 1, and therefore description thereof will be omitted.

[0258] Table 7 shows the voltages on each line in each state and operation.

[0259] [Table 7]

[0260] As shown in Table 7, in the hold state, the voltages of the word lines WWL, RWL1, and RWL2 are 1.1V, the voltages of CTRL1 to CTRL3 are 1.2V, and FETs m4, m41, and m42 are off. During a write operation, the voltage of WWL of the memory cell 10 to be written is set to 0.3V. This turns on FET m3 of the memory cell 10 to be written. The voltages of the word lines RWL1 and RWL2 are 1.1V, and FETs m41 and m42 are off. By setting the voltage of the control line CTRL1 to 1.2V or 0V, the storage node Q1 becomes H or L. This causes data to be written to the memory cell 10.

[0261] During read operation 1, the voltage of RWL1 of the memory cell 10 to be read is set to 0.3V. This turns on FETm41 of the memory cell 10 to be read. The voltage of RWL2 is 1.1V, and FETm42 is off. The voltage of WWL is 0.6V, which slightly turns on FETm4. By floating (FL) the voltage of control line CTRL2 from 1.2V, data at storage node Q2 is read from control line CTRL2. Read operation 2 is the same as read operation 1. The voltages of word lines WWL, RWL1, and RWL2 of the memory cell 10 not to be accessed are 1.1V. Other operations are the same as in Example 1.

[0262] For the 2R1W type NV-SRAM cell and the 2R1W type ULVR-SRAM cell, we simulated SNM versus the word line WWL voltage VWWL during read operations 1 and 2. For the 2R1W type NV-SRAM memory cell, WLP = 105 nm, WDRV = 150 nm, and the word line RWL1 and RWL2 voltage VRWL = 0 V. For the 2R1W type ULVR-SRAM memory cell, VVDD = 1.2 V, BI mode, WLP = 110 nm, and WFB = 230 nm.

[0263] FIG. 49(a) shows the SNM versus VWWL of a 2R1W NV-SRAM memory cell in a read operation according to the second modification of the third embodiment, and FIG. 49(b) shows the SNM versus VWWL of a 2R1W ULVR-SRAM memory cell in a read operation. As shown in FIGS. 49(a) and 49(b), increasing the voltage VWWL of the word line WWL reduces the SNM. In a read operation, the write word line WWL is not selected, and FETs M3 and FETm4 are turned off. However, completely turning off FETs M3 and FETm4 reduces the SNM. Therefore, the voltage VWWL (e.g., 0.6 V) of the write word line WWL in read operations 1 and 2 is set higher than the voltage VWWL (e.g., 0.3 V) in the write operation. Furthermore, the voltage VWWL (e.g., 0.6 V) in read operation 1 is set lower than the voltage (e.g., 1.2 V) of the word line RWL1 for read operation 2. The same applies to read operation 2. This increases the SNM.

[0264] 50 is a circuit diagram showing an example of a 2RW NV-SRAM memory cell in Modification 2 of Example 3. As shown in Fig. 50, WL1 and WL2 are provided as word lines. CTRL1, CTRL1', CTRL2, and CTRL2' are provided as control lines.

[0265] The gate of FET M31 (third FET) is connected to WL1 (first word line), one of its source and drain is connected to storage node Q1 (first storage node), and the other of its source and drain is connected to control line CTRL1 (first control line). The gate of FET M32 (fifth FET) is connected to WL2 (second word line), one of its source and drain is connected to storage node Q1, and the other of its source and drain is connected to control line CTRL1' (fourth control line). The gate of FET M41 (fourth FET) is connected to WL1, one of its source and drain is connected to storage node Q2, and the other of its source and drain is connected to control line CTRL2 (second control line). The gate of FET M42 (sixth FET) is connected to WL2, one of its source and drain is connected to storage node Q2, and the other of its source and drain is connected to control line CTRL2' (fifth control line). The other configurations are the same as those in Example 2, and therefore description thereof will be omitted.

[0266] Table 8 shows the voltages on each line in each state and operation.

[0267] [Table 8]

[0268] As shown in Table 8, in the hold state, the voltages of the word lines WL1 and WL2 and the control lines CTRL1, CTRL1', CTRL2, and CTRL2' are 1.2V (high level), and FETs M31, M32, M41, and M42 are off. During write operation 1 and read operation 1, WL1, CTRL1, and CTRL2 are used to write and read data via FETs M31 and M41. WL2, CTRL1', and CTRL2' are set to 1.2V, and FETs M32 and M42 are turned off. Write operation 2 and read operation 2 are the same as write operation 1 and read operation 1. The voltages of the word lines WL1 and WL2 of the memory cells 10 that are not accessed are 1.2V. Other operations are the same as those in Example 2.

[0269] 51 is a circuit diagram showing an example of a 2RW type ULVR-SRAM memory cell in Modification 2 of Example 3. As shown in Fig. 51, WL1 and WL2 are provided as word lines. CTRL1, CTRL1', CTRL2, and CTRL2' are provided as control lines.

[0270] The gate of FETm41 (third FET, fourth FET) is connected to WL1 (first word line), one of the source and drain is connected to storage nodes Q1 and Q2, and the other of the source and drain is connected to control lines CTRL1 (first control line) and CTRL2 (second control line). The gate of FETm42 (fifth FET, sixth FET) is connected to WL2 (second word line), one of the source and drain is connected to storage nodes Q1 and Q2, and the other of the source and drain is connected to control lines CTRL1' (third control line) and CTRL2' (fourth control line). The other configurations are the same as in Example 1, and therefore description thereof will be omitted.

[0271] Table 9 shows the voltages on each line in each state and operation.

[0272] [Table 9]

[0273] As shown in Table 9, in the hold state, the voltages of WL1 and WL2 are 1.1V, the voltages of CTRL1, CTRL2, CTRL1', and CTRL2' are 1.2V, and FETm41 and m42 are off. During write operation 1 and read operation 1, WL1, CTRL1, and CTRL2 are used to write and read data via FETm41. The voltage of WL2 is set to 1.1V, and the voltages of CTRL1' and CTRL2' are set to 1.2V, turning off FETm42. Write operation 2 and read operation 2 are the same as write operation 1 and read operation 1. The voltages of word lines WL1 and WL2 of memory cells 10 that are not accessed are 1.1V. Other operations are the same as those in Example 2.

[0274] FIG. 52 is a diagram illustrating an example of a 2R1W type memory according to Modification 2 of Example 3. Peripheral circuits other than sense amplifiers 44a and 44b are omitted from FIG. 52. As shown in FIG. 52, memories 51 and 61 have memory cells 10 arranged in a matrix. The memory cells 10 are 2R1W type NV-SRAM cells or 2R1W type ULVR-SRAM cells. A control line CTRL2 is connected to the sense amplifier 44a, and a control line CTRL3 is connected to the sense amplifier 44b. The sense amplifier 44a reads data from the memory cell 10 selected by the word line RWL1, and the sense amplifier 44b reads data from the memory cell 10 selected by the word line RWL2. The sense amplifiers 44a and 44b output the read data to the XNOR circuit 53a (or 63a) and the XNOR circuit 53b (or 63b), respectively. This allows weighted columns of multiple rows to be output in parallel to the XNOR circuits 53a and 53b (or 63a and 63b) from the memory 51 or 61. The memory cells 10 may be 6T cells.

[0275] FIG. 53 is a diagram illustrating an example of a 2RW memory according to Modification 2 of Example 3. Peripheral circuits other than sense amplifiers 44a and 44b are omitted from FIG. 53. As shown in FIG. 53, the memory cell 10 is a 2RW NV-SRAM cell or a 2RW ULVR-SRAM cell. Control lines CTRL1 and CTRL2 are connected to the sense amplifier 44a, and control lines CTRL1' and CTRL2' are connected to the sense amplifier 44b. The sense amplifier 44a reads data from the memory cell 10 selected by the word line WL1, and the sense amplifier 44b reads data from the memory cell 10 selected by the word line WL2. The other configurations are the same as those in FIG. 52. The sense amplifiers 44a and 44b output the read data to the XNOR circuit 53a (or 63a) and the XNOR circuit 53b (or 63b), respectively. This allows weighted columns of multiple rows to be output in parallel from the memory 51 or 61 to the XNOR circuits 53a and 53b (or 63a and 63b). The memory cell 10 may be a 6T cell.

[0276] FIG. 54 is a diagram showing processing over time in a modification of the third embodiment. Case 1, Case 2, and Example 3 are the same as those in FIG. 43, and their explanations are omitted. In modifications 1 and 2 of the third embodiment, processing for two rows of memories 51 and 61 can be performed in parallel. This allows processing 71 to be processed in parallel with processing 71a and 71b. Similarly, processing 72a and 72b can be processed in parallel, processing 73a and 73b can be processed in parallel, and processing 74a and 74b can be processed in parallel. Therefore, the processing time can be shortened compared to the third embodiment.

[0277] In the third modification of the third embodiment, processing for four rows of memories 51 and 61 is performed in parallel. This allows processing 71 to be processed in parallel with processing 71a to 71d. Similarly, processing 72a to 72d can be processed in parallel, processing 73a to 73d can be processed in parallel, and processing 74a to 74d can be processed in parallel. Therefore, the processing time can be further reduced compared to the first and second modifications of the third embodiment.

[0278] Processing times were simulated for Example 3 and its modifications. The number of nodes in the input X layer and each of the other layers was set to n, and the number of layers excluding the X layer was set to m (m is an even number). Figures 55(a) to 55(c) show the normalized processing time T / t0 versus the number of layers m. t0 is a value used for normalization. Figures 55(a) to 55(c) show the cases where n = 256, n = 512, and n = 1024, respectively. As shown in Figures 55(a) to 55(c), regardless of n, Example 3 has shorter processing times than Cases 1 and 2. In Modifications 1 and 2 of Example 3, the processing time is approximately half that of Example 3. In Modification 3 of Example 3, the processing time is approximately one-quarter that of Example 3.

[0279] According to the first to third modifications of the third embodiment, the processing unit 52 processes in parallel at least two of the second nodes y1 to yn, and the processing unit 62 processes in parallel at least two of the second nodes y1 to yn. This allows the processing time to be reduced, as shown in FIG.

[0280] 47, 48, 50, and 51, the plurality of memory cells 10 each have a pair of complementary storage nodes Q1 and Q2, and at least one of the pair of storage nodes Q1 and Q2 is connected to control lines CTRL2 (first bit line) and CTRL3 or CTRL2' (second bit line) extending in parallel in the column direction. When performing one of the parallel processing of second data, the processing unit 52 acquires a plurality of first weights from the memory 51 via the first bit line, and when performing another processing, acquires a plurality of first weights from the memory 51 via the second bit line. This allows the processing unit 52 to execute two processes in parallel.

[0281] 47, 48, 50, and 51, when performing one of the parallel processes of the second data, the processing unit 62 acquires a plurality of first weights from the memory 61 via the control line CTRL2 (third bit line), and when performing another process, acquires a plurality of first weights from the memory 61 via the control line CTRL3 or CTRL2' (fourth bit line). This allows the processing unit 62 to execute two processes in parallel.

[0282] 47, when memory cells 10 and 10' are 2R1W NV-SRAM memory cells, the other of the source and drain of FET M3 is connected to the first control line CTRL1, and the gate is connected to the first word line WWL. The other of the source and drain of FET M41 is connected to the second control line CTRL2, and the gate is connected to the second word line RWL1. One of the source and drain of FET M42 (fifth FET) is connected to storage node Q2, the other of the source and drain is connected to the fourth control line CTRL3, and the gate is connected to the third word line RWL2.

[0283] When the memory cells 10 and 10' are 2R1W-type ULVR-SRAM memory cells, as shown in Fig. 48, in the inverter circuit 16 (second inverter circuit), the other of the source and drain of FETm4 is connected to the first control line CTRL1, and the gate is connected to the first word line WWL. In the inverter circuit 14, the other of the source and drain of FETm41 is connected to the second control line CTRL2, and the gate is connected to the second word line RWL1. One of the source and drain of FETm42 is connected to the second storage node Q2, the other of the source and the drain is connected to the third control line CTRL3, and the gate is connected to the third word line RWL2.

[0284] The control circuit 28 uses the word line WWL to turn on FETM3 in FIG. 47 or FETm4 of the inverter circuit 16 in FIG. 48, and uses the control line CTRL1 to write data to the bistable circuit 12. The control circuit 28 uses the word line RWL1 to turn on FETM41 or FETm41, uses the control line CTRL2 to read data from the bistable circuit 12, uses the word line RWL2 to turn on FETM42 or FETm42, and uses the control line CTRL3 to read data from the bistable circuit 12. This allows data to be written to the bistable circuit 12 using one control line CTRL1 in a 2R1W NV-SRAM cell and a 2R1W ULVR-SRAM cell. Also, word lines RWL1 and RWL2 can be used to select control lines CTRL2 and CTRL3 for reading data from the bistable circuit 12.

[0285] As shown in Tables 6 and 7, when FETs M1, M2, and FETs m1 and m2 are N-channel, the control circuit 28 sets the voltage of the word line WWL when reading data from the bistable circuit 12 higher than the voltage of the word line WWL when writing data to the bistable circuit 12 and lower than the higher of the voltages of the word lines RWL1 and RWL2 when reading data from the bistable circuit 12. This improves SNM during reading. The voltage of the word line WWL during a read operation is preferably (VDD-VGND) / 10 or more higher than the voltage of the word line WWL during a write operation, and is preferably (VDD-VGND) / 10 or more lower than the higher of the voltages of the word lines RWL1 and RWL2 during a read operation.

[0286] When FETs M1a, M2a, FETs m1a, and m2a are P-channel, the control circuit 28 sets the voltage of the word line WWL when reading data from the bistable circuit 12 lower than the voltage of the word line WWL when writing data to the bistable circuit 12 and higher than the lower voltage of the word lines RWL1 and RWL2 when reading data from the bistable circuit 12. This improves SNM during reading. The voltage of the word line WWL during a read operation is preferably lower by (VDD-VGND) / 10 or more than the voltage of the word line WWL during a write operation, and is preferably higher by (VDD-VGND) / 10 or more than the higher of the voltages of the word lines RWL1 and RWL2 during a read operation.

[0287] [Modification 4 of Example 3] FIG. 56 is a circuit diagram of an NV-SRAM memory cell according to Modification 4 of Example 3. As shown in FIG. 56, cells 78 and 78′ include memory cells 10 and 10′ of Example 2 and an XNOR circuit 79. The XNOR circuit 79 includes FETs M7 to M9. In FET M7, one end of the source and drain is connected to a control line CTRL1, the other end of the source and drain is connected to a node N5, and the gate is connected to a storage node Q2. In FET M8, one end of the source and drain is connected to a control line CTRL2, the other end of the source and drain is connected to a node N5, and the gate is connected to a storage node Q1. In FET M9, one end of the source and drain is connected to a ground line 15b, the other end of the source and drain is connected to an output line SAIN, and the gate is connected to a node N5.

[0288] When the memory cell 10 is in the hold state, the XNOR circuit 79 outputs the XNOR of the storage node Q1 and the control line CTRL1 (which also corresponds to the XNOR of the storage node Q2 and the control line CTRL2) to the output line SAIN. One-bit operation data (for example, H is 1.2V, L is 0V) is input to the control line CTRL1, and the complementary data of the operation data is input to the control line CTRL2. The XNOR of the operation data and the storage node Q1 is output to the output line SAIN.

[0289] 57 is a circuit diagram of an ULVR-SRAM memory cell according to Modification 4 of Example 3. As shown in Fig. 57, cells 78 and 78' include memory cells 10 and 10' of Example 1 and an XNOR circuit 79. The circuit configuration and function of XNOR circuit 79 are the same as those in Fig. 56.

[0290] FIG. 58 is a block diagram of a BNN device according to a fourth modification of the third embodiment. As shown in FIG. 58, the memory cells in memories 51 and 61 are cells 78 and 78' in FIG. 56 or 57. Processing units 52 and 62 do not include an XNOR circuit. When an XNOR is output from memory 51, data at nodes x1 to xn of input unit 48 and their complementary data are input to control lines CTRL1 and CTRL2 of memory 51, respectively. The sense amplifier of memory 51 reads data from the output line SAIN of each column and outputs it to counter 54. When an XNOR is output from memory 61, data at node yi of output unit 57 and its complementary data are input to control lines CTRL1 and CTRL2 of memory 61. The sense amplifier of memory 61 reads data from the output line SAIN of each column and outputs it to accumulator 64.

[0291] As in the fourth modification of the third embodiment, the XNOR circuit 79 may be provided in each of the cells 78 and 78'. In the first to third modifications of the third embodiment, the XNOR circuit 79 may be provided in each of the cells 78.

[0292] 56 and 57, memories 51 and 61 include XNOR circuits 79 (first XNOR circuit and second XNOR circuit) corresponding to memory cells 10 and 10'. This eliminates the need to provide XNOR circuits 53 and 63 in processing units 52 and 62.

[0293] [Modification 5 of Example 3] 59(a) and 59(b) are block diagrams of the power switch and its vicinity in Comparative Example 4 and Modification 5 of Example 3, respectively. As shown in FIG. 59(a), in Comparative Example 4, multiple 6T cells 10 are arranged in one row of the memory array. The number of cells 10 in one row is, for example, 512. The power supply lines 15a (virtual power supply lines) of the memory cells 10 in one row are commonly connected. In the power switch 30, one FETPS2 is provided between the power supply 15cL of the sleep state voltage VDDL and the power supply line 15a. The power supply 15cH of the voltage VDDH and the power switch FETPS1 are not shown. When the FETPS2 is turned on, the virtual power supply voltage VVDD of the power supply line 15a becomes VDDL.

[0294] 59(b), in the fifth modification of the third embodiment, the power switch 30 includes a FETPS2 for each memory cell 10, and each FETPS2 is connected between a power supply 15cL of a voltage VDDL for the sleep state and a power supply line 15a. Note that the power supply 15cH of a voltage VDDH and the power switch FETPS1 are not shown. When the FETPS2 is turned on, the virtual power supply voltage VVDD of the power supply line 15a becomes VDDL.

[0295] FIG. 60 is a circuit diagram of a 6T cell according to Modification 5 of Example 3. As shown in FIG. 60, in memory cells 10 and 10′, bistable circuit 12 includes inverter circuit 14 having PFET M1′ and NFET M1, and inverter circuit 16 having PFET M2′ and NFET M2. Inverter circuits 14 and 16 are connected in a loop. Pass transistors NFETs M3 and M4 are also provided. Power switch 30 includes FET PS1, which connects power supply 15cH, which supplies voltage VDDH, to power supply line 15a, and FET PS2, which connects power supply 15cL, which supplies voltage VDDL, to power supply line 15a. Voltage VDDH is a power supply voltage (second power supply voltage) during read or write operations, and is, for example, 1.2 V. Voltage VDDL is a power supply voltage (first power supply voltage) during a sleep state in which bistable circuit 12 retains data but does not perform write or read operations, and is, for example, 1 / 3 to 1 / 4 of VDDH. Each of FETPS1 (second power switch) and FETPS2 (first power switch) is connected to the virtual power line 15a of one or several (e.g., 10 or less) memory cells 10. Note that FETPS1 may be connected to more cells than FETPS2. For example, one FETPS1 may be connected to 64, 128, or 256 memory cells 10.

[0296] SNM and standby power were simulated for a case in which FETPS2 is provided in common to 512 memory cells 10 as Comparative Example 4, and a case in which FETPS2 is provided for each memory cell 10 as Modification 5 of Example 3. Figures 61(a) and 61(b) are diagrams showing SNM and standby power with respect to VDDL in Comparative Example 4 and Modification 5 of Example 3, respectively.

[0297] As shown in FIG. 61(a), in Comparative Example 4, when VDDL is 1.2V, SNM is 100mV to 180mV. Lowering VDDL reduces SNM. The minimum VDDL at which all SNMs are 80mV or higher is 0.8V. For this reason, VDDL in the sleep state is set to 0.8V. When VDDL is 0.8V, the standby power is approximately 1.6nW.

[0298] As shown in FIG. 61(b), in Modification 5 of Example 3, when VDDL is 1.2V, SNM is 300mV or more. Lowering VDDL reduces SNM. The minimum VDDL at which all SNMs are 80mV or more is 0.35V. For this reason, VDDL in the sleep state is set to 0.35V. The standby power when VDDL is 0.35V is approximately 0.5nW. In this way, Modification 5 of Example 3 of FIG. 59(b) can reduce standby power consumption compared to Comparative Example 4 of FIG. 59(a).

[0299] In this way, in variant example 5 of embodiment 3, SNM can be increased even if VDDL is lowered because, when multiple memory cells 10 are connected to FETPS2, the virtual power supply voltage VVDD becomes lower than VDDL, causing SNM to deteriorate, but when only one memory cell 10 (or a few) are connected, the virtual power supply voltage VVDD can be maintained at VDDL.

[0300] According to the fifth modification of the third embodiment, even if 6T memory cells are used as the memory cells 10 and 10', the power supply voltage for retention can be reduced. Therefore, the area of ​​the memory cells can be reduced and power consumption can be suppressed. Although the virtual power supply system has been described as an example, the virtual ground system can also be used. The fifth modification of the third embodiment may be applied to the BNN device of the third embodiment and its modifications 1 to 4. The third embodiment and its modifications can also be applied to neural network devices other than the BNN device.

[0301] Although the preferred embodiments of the present invention have been described in detail above, the present invention is not limited to such specific embodiments, and various modifications and variations are possible within the scope of the gist of the present invention as set forth in the claims. [Explanation of symbols]

[0302] 10 memory cells 12 Bistable circuit 14, 16 Inverter circuit 22 Memory Array 28 Control Circuit 30 Power Switch 32, 32a, 32b selection circuit 51, 61 memory 52, 62 Processing section 79 XNOR circuit

Claims

1. A memory cell array including a plurality of memory cells arranged in a matrix of a plurality of rows and a plurality of columns, each memory cell having a complementary pair of storage nodes; At least two bit lines are provided in each of the plurality of columns, and the plurality of bit lines are connected to memory cells arranged in the column direction; Equipped with the plurality of rows are divided into a plurality of blocks each having at least two rows; a memory that is a storage circuit, in which, in each of the plurality of blocks, each of the at least two bit lines is connected to at least one of the pair of memory nodes in a memory cell provided in one of the at least two rows in the block, and is not connected to a memory cell provided in the remaining row of the at least two rows; a processing unit that calculates one piece of second data among a plurality of second data corresponding to a plurality of second nodes in a second layer by weighting a plurality of first data corresponding to a plurality of first nodes in a first layer with a plurality of weights and then adding the weighted pieces of second data, and that calculates the plurality of second data by performing a process on the plurality of second data to process at least two pieces of second data in parallel; Equipped with the plurality of memory cells store the plurality of weights, respectively, and the plurality of weights corresponding to one second data are stored in the same row, and the plurality of weights corresponding to different second data are stored in different rows; The processing unit is a processing device that, when processing the at least two second data in parallel, reads data in parallel from the at least two bit lines in one block of the plurality of blocks.

2. A plurality of memory cells arranged in a matrix of a plurality of rows and a plurality of columns, each having a complementary pair of storage nodes; At least two bit lines are provided in each of the plurality of columns, and the plurality of bit lines are connected to memory cells arranged in the column direction; Equipped with the plurality of rows are divided into a plurality of blocks each having at least two rows; a memory that is a storage circuit, in which, in each of the plurality of blocks, each of the at least two bit lines is connected to at least one of the pair of memory nodes in a memory cell provided in one of the at least two rows in the block, and is not connected to a memory cell provided in the remaining row of the at least two rows; a processing unit that performs a process for calculating a portion of each of a plurality of second data corresponding to a plurality of second nodes in a second layer by weighting one of a plurality of first data corresponding to a plurality of first nodes in a first layer with a plurality of weights, and calculates the plurality of second data by adding the portions of the plurality of second data by the amount of the plurality of first data for each of the plurality of second data, and processes at least two of the plurality of first data in parallel; Equipped with the plurality of memory cells store the plurality of weights, respectively, and the plurality of weights corresponding to one first data are stored in the same row, and the plurality of weights corresponding to different first data are stored in different rows; The processing unit is a processing device that, when processing the at least two first data in parallel, reads data in parallel from the at least two bit lines in one block of the plurality of blocks.

3. A plurality of memory cells arranged in a matrix of a plurality of rows and a plurality of columns, each having a complementary pair of storage nodes; At least two bit lines are provided in each of the plurality of columns, and the plurality of bit lines are connected to memory cells arranged in the column direction; Equipped with the plurality of rows are divided into a plurality of blocks each having at least two rows; In each of the plurality of blocks, each of the at least two bit lines is connected to at least one of the pair of memory nodes of a memory cell provided in one of the at least two rows in the block, and is not connected to a memory cell provided in the remaining row of the at least two rows; and a first processing unit that calculates one piece of second data among a plurality of second data corresponding to a plurality of second nodes in a second layer by weighting each piece of first data corresponding to a plurality of first nodes in a first layer with a plurality of first weights and then adding the weighted pieces of second data, and that calculates the plurality of second data by performing a process on the plurality of second data to calculate one piece of second data among the plurality of second data in parallel; a second processing unit that performs a process for calculating a portion of each of a plurality of third data corresponding to a plurality of third nodes in a third layer by weighting one of the plurality of second data by a plurality of second weights, and calculates the plurality of third data by adding the portions of the plurality of third data by the plurality of second data for each of the plurality of third data, and processes at least two of the plurality of second data in parallel; Equipped with the plurality of memory cells in the first memory respectively store the plurality of first weights, and the plurality of first weights corresponding to one second data are stored in the same row, and the plurality of first weights corresponding to different second data are stored in different rows; the plurality of memory cells in the second memory respectively store the plurality of second weights, and the plurality of second weights corresponding to one second data are stored in the same row, and the plurality of second weights corresponding to different second data are stored in different rows; when the second processing unit processes one of the plurality of second data, the first processing unit processes another of the plurality of second data in parallel; the first processing unit, when processing the at least two second data in parallel, reads data in parallel from the at least two bit lines in one block of the plurality of blocks in the first memory; The second processing unit is a processing device that reads data in parallel from the at least two bit lines in one of the multiple blocks in the second memory when processing the at least two second data in parallel.

4. A processing device described in any one of claims 1 to 3, wherein in the memory circuit, data is read in parallel from at least two bit lines in one of the multiple blocks.

5. A processing device as described in Claim 4, wherein in the memory circuit, data is read in parallel from at least two bit lines in the multiple columns within the one block.

6. A processing device described in any one of claims 1 to 5, wherein the memory circuit has a plurality of first word lines provided in each of the plurality of rows and connected to memory cells arranged in the row direction.

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