Semiconductor element driving method, driving device, and power conversion device

Abstract

This semiconductor device is on / off controlled by controlling a gate voltage in response to a drive control signal (Ssw). In a turn-on operation for charging a gate in response to the transition of the drive control signal (Ssw) from a first level (0) to a second level (1), at a first time (t1) after the end of a mirror period (200) of a gate voltage (Vg), a drive signal (Sdr) is set to the first level (0) to discharge the gate, thereby providing a voltage drop period (210) in which the gate voltage (Vg) is temporarily dropped. At a second time (t2), the drive signal (Sdr) is again set to the second level (1) to start charging the gate.

Description

[Technical Field]

[0001] The present disclosure relates to a method for driving a semiconductor element, a driving device, and a power conversion device. [Background technology]

[0002] For the switching operation of voltage-driven semiconductor elements, such as MOS-FETs (Metal-Oxide-Semiconductor Field-Effect Transistors) and IGBTs (Insulated Gate Bipolar Transistors), a driving device is used that charges and discharges the gate of the semiconductor element in response to an on / off control signal.

[0003] During steady-state switching operations of such semiconductor elements, it is necessary to increase the switching speed in order to reduce switching losses that occur in the semiconductor elements when the semiconductor elements are turned on or off.

[0004] On the other hand, if an abnormality occurs in the electrical circuit to which the semiconductor element is connected, turning on the semiconductor element may form an overcurrent path including the semiconductor element. In such a case, it is also necessary to turn on and off the semiconductor element so as to avoid damage to the semiconductor element due to the influence of the overcurrent.

[0005] Specifically, to prevent a semiconductor element from being destroyed even when an overcurrent occurs, it is necessary to turn off the semiconductor element before the time until the semiconductor element is destroyed (so-called short-circuit withstand capability) has elapsed, or to suppress the surge voltage generated in the process of cutting off the overcurrent to below the withstand voltage capability of the semiconductor element. To satisfy this condition, a slow switching speed is desirable, as opposed to steady-state switching operation.

[0006] As described above, with regard to the switching speed of semiconductor elements, there is a trade-off between reducing switching losses during normal operation and reducing the possibility of damage to the semiconductor elements during abnormal operation.

[0007] Japanese Patent Laid-Open Publication No. 2010-119184 (Patent Document 1) describes a semiconductor driver that enables an active gate drive method, which suppresses the generation of surge current by performing turn-on slowly until the mirror period, and then speeds up turn-on once the mirror period is exceeded to reduce switching loss, even when the mirror period cannot be detected accurately. Specifically, it describes that both surge current and switching loss are reduced by PWM (Pulse Width Modulation) control of the gate input signal in accordance with the mirror period at turn-on or turn-off. [Prior art documents] [Patent documents]

[0008] [Patent Document 1] Japanese Patent Application Laid-Open No. 2010-119184 Summary of the Invention [Problem to be solved by the invention]

[0009] The semiconductor driver device in Patent Document 1 is primarily aimed at reducing power loss and current surges during steady-state switching, and does not mention how to deal with cases in which an overcurrent path is formed when a semiconductor element is turned on. For this reason, there are concerns that the gate voltage control described in Patent Document 1 is not very effective in reducing the possibility of damage to the semiconductor element in the event of an abnormality in which an overcurrent occurs.

[0010] If we may venture to say, in Patent Document 1, the adoption of PWM control increases the total turn-on time or turn-off time, which is expected to contribute to a reduction in the equivalent switching speed, thereby reducing the possibility of semiconductor element damage when an overcurrent occurs. However, this reduction in switching speed increases switching loss during steady state operation, and therefore does not contribute to improving the trade-off between reducing switching loss during steady state operation and reducing the possibility of semiconductor element damage during an abnormal state in which an overcurrent occurs.

[0011] The present disclosure has been made to solve such problems, and the purpose of the present disclosure is to control the switching of semiconductor elements so as to reduce the possibility of damage during an overcurrent abnormality while suppressing the impact on switching loss during normal operation. [Means for solving the problem]

[0012] In one aspect of the present disclosure, a method for driving a semiconductor device is provided. The method for turning a semiconductor element on and off in accordance with a drive control signal includes: (a) initiating a turn-on operation to charge a gate of an off-state semiconductor element in response to a turn-on command in which the drive control signal transitions from a first level to a second level; (b) initiating a turn-off operation to discharge a gate of an on-state semiconductor element in response to a turn-off command in which the drive control signal transitions from the second level to the first level; and (c) providing at least one of a voltage drop period during which the drive control signal is maintained at the second level after the start of the turn-on operation and a voltage rise period during which the drive control signal is maintained at the first level after the start of the turn-off operation. The voltage drop period is provided so that the gate voltage temporarily drops due to gate discharge after the end of the mirror period. The voltage rise period is provided so that the gate voltage temporarily rises due to gate charging during a period in which the current of the semiconductor element is decreasing.

[0013] Another aspect of the present disclosure provides a semiconductor device driver. The semiconductor device driver for turning a semiconductor device on and off in accordance with a drive control signal includes a drive adjustment unit and a drive circuit. The drive adjustment unit generates drive signals for controlling a turn-on operation that charges a gate of an off-state semiconductor device and a turn-off operation that discharges a gate of an on-state semiconductor device in response to a turn-on command in which the drive control signal transitions from a first level to a second level and a turn-off command in which the drive control signal transitions from the second level to the first level. The drive circuit charges or discharges the gate in accordance with the drive signal. The drive adjustment unit generates the drive signals so as to include at least one of a voltage drop period that is provided within a period in which the drive control signal is maintained at the second level after the start of the turn-on operation and a voltage rise period that is provided within a period in which the drive control signal is maintained at the first level after the start of the turn-off operation. The voltage drop period is provided so that the gate voltage temporarily drops due to gate discharge after the end of the mirror period. The voltage rise period is set so that the gate voltage temporarily rises due to charging of the gate during the period when the current of the semiconductor element is decreasing.

[0014] In yet another aspect of the present disclosure, there is provided a power conversion device. The power conversion device includes a main conversion circuit including at least one semiconductor element that converts input power and outputs the converted power, and a control circuit that outputs control signals to the main conversion circuit to control the main conversion circuit. The control signals include drive control signals for each semiconductor element. The main conversion circuit further includes the above-mentioned drive devices arranged corresponding to each semiconductor element. The drive devices control the on / off of each semiconductor element in accordance with the drive control signals. [Effects of the Invention]

[0015] According to the present disclosure, by temporarily providing a voltage drop period after the end of the mirror period during turn-on operation, it is possible to suppress an increase in the drain current of the semiconductor element in a short-circuit state, and by temporarily providing a voltage rise period during turn-off operation, it is possible to suppress the surge voltage that occurs when the semiconductor element is turned off in a short-circuit state.Therefore, it is possible to control the switching of the semiconductor element so as to reduce the possibility of damage in the event of an overcurrent abnormality while suppressing the impact on switching loss during normal operation. [Brief explanation of the drawings]

[0016] [Figure 1] FIG. 2 is a block diagram for explaining functions of a drive device according to the present embodiment. [Figure 2] 1 is a diagram showing typical operational waveforms during a normal turn-on operation of a semiconductor device. [Figure 3] FIG. 10 is a general operational waveform diagram of a turn-on operation when an abnormality occurs in a semiconductor element. [Figure 4] 10 is a graph illustrating the relationship between the gate voltage and the drain current when a short-circuit current flows through a semiconductor element. [Figure 5] 1 is a block diagram for explaining a configuration example of a drive device according to a first embodiment. [Figure 6] 4 is a waveform diagram illustrating the normal operation of a semiconductor device turned on by the driving device according to the first embodiment. FIG. [Figure 7] 4 is an operational waveform diagram of a semiconductor element turned on by the driving device according to the first embodiment when an abnormality occurs. FIG. [Figure 8] 10 is an operational waveform diagram of a semiconductor element turned on by a driving device according to a modification of the first embodiment when an abnormality occurs. FIG. [Figure 9] FIG. 10 is a block diagram illustrating a configuration example of a drive device according to a second embodiment. [Figure 10] FIG. 1 is a diagram showing a general drain voltage-drain current characteristic of a semiconductor element. [Figure 11] FIG. 10 is an operational waveform diagram for explaining variable adjustment of a drop period using a drain voltage as an information amount in a driving device according to a second embodiment. [Figure 12] 10 is a first flowchart illustrating a control process for variably adjusting a decrease period in a drive device according to a second embodiment. [Figure 13] FIG. 10 is an operational waveform diagram for explaining variable adjustment of a decrease period using a drain current as an information amount in a driving device according to a second embodiment. [Figure 14] 5 is a graph illustrating the temperature dependency of FIG. 4. [Figure 15] FIG. 10 is an operational waveform diagram for explaining variable adjustment of the drop period using the element temperature as information amount in the driving device according to the second embodiment. [Figure 16] 10 is an operational waveform diagram for explaining variable adjustment of a drop period using a gate voltage as an information amount in a driving device according to a second embodiment. FIG. [Figure 17] 10 is a second flowchart illustrating the control process for variably adjusting the decrease period based on the amount of information about the operating state of the semiconductor element in the drive device according to the second embodiment. [Figure 18] FIG. 10 is a general operational waveform diagram of a turn-off operation when an abnormality occurs in a semiconductor element. [Figure 19] FIG. 10 is a block diagram illustrating a configuration example of a drive device according to a third embodiment. [Figure 20] 10 is an operational waveform diagram when an abnormality occurs in a semiconductor element that is turned off by the driving device according to the third embodiment. FIG. [Figure 21] FIG. 10 is a block diagram illustrating a configuration example of a drive device according to a fourth embodiment. [Figure 22] 10 is a flowchart illustrating a control process for variably adjusting the rise period based on the amount of information on the operating state of a semiconductor element in a drive device according to a fourth embodiment. [Figure 23] 10 is a flowchart illustrating a control process for selecting the arrangement of voltage rise periods in the drive device according to the fourth embodiment. [Figure 24] FIG. 11 is a block diagram showing a configuration of a power conversion system to which a power conversion device according to a fifth embodiment is applied. DETAILED DESCRIPTION OF THE INVENTION

[0017]

[0014] The following describes in detail embodiments of the present disclosure with reference to the drawings. While multiple embodiments will be described below, it should be noted that it was originally intended to combine the configurations described in each embodiment, including combinations not directly described in the specification, as long as no technical contradictions arise. In the following, identical or corresponding parts in the drawings will be designated by the same reference numerals, and their descriptions will not be repeated in principle.

[0018] Embodiment 1 FIG. 1 is a block diagram for explaining the function of a drive device according to the present embodiment.

[0019] The driving device 100 controls the on / off, ie, switching operation, of the semiconductor element 10 connected between the high voltage terminal N1 and the low voltage terminal N2 in accordance with the driving control signal Ssw from the control circuit 20.

[0020] The semiconductor element 10 has a drain 11 and a source 12 that are main electrodes, and a gate 15 that is a control electrode. The drain is connected to a high-voltage terminal N1, and the source 12 is connected to a low-voltage terminal N2. When the semiconductor element 10 is turned on, a current path is formed that includes the semiconductor element 10 in the on state and a load (not shown) electrically connected to the high-voltage terminal N1 or the low-voltage terminal N2. In this embodiment, a MOS-FET is used as an example of the semiconductor element 10 having a gate, but the semiconductor element 10 can also be an IGBT. In this case, the collector and emitter are used as main electrodes instead of the drain and source.

[0021] The semiconductor element 10 is controlled in accordance with the gate-source voltage (hereinafter also simply referred to as the "gate voltage") to be in either a connected state (ON state) in which a current flows between the main electrodes, i.e., between the drain 11 and the source 12, or an OFF state in which the drain 11 and the source 12 are disconnected. The driving device 100 controls the gate voltage so that the semiconductor element 10 is turned ON or OFF in accordance with the driving control signal Ssw.

[0022] The drive control signal Ssw is set to "1" during the period when the semiconductor element 10 should be turned on, and is set to "0" during the period when the semiconductor element 10 should be turned off. In other words, the drive control signal is a binary signal that is set to either "0" corresponding to a "first level" or "1" corresponding to a "second level." For example, the control circuit 20 can be configured as a pulse width modulation (PWM) pulse output circuit for turning the semiconductor element 10 on and off according to PWM control.

[0023] The semiconductor device 10 turns on when the gate voltage becomes a positive voltage exceeding a predetermined threshold voltage Vth. Therefore, while the drive control signal Ssw is "1," the drive device 100 drives the gate 15 so that the gate voltage becomes a positive voltage exceeding the threshold voltage Vth. On the other hand, while the drive control signal Ssw is "0," the drive device 100 drives the gate 15 so that the gate voltage becomes a voltage equal to or lower than the threshold voltage, for example, 0 or a negative voltage.

[0024] When the drive control signal Ssw changes from "0" to "1", the driver 100 drives the gate 15 to increase the gate voltage in order to perform a turn-on operation that changes the semiconductor device 10 from an off state to an on state. That is, when turning on, the driver 100 charges the gate 15.

[0025] On the other hand, when the drive control signal Ssw changes from "1" to "0", the drive device 100 drives the gate 15 to lower the gate voltage in order to perform a turn-off operation that changes the semiconductor device 10 from an on state to an off state. That is, at the time of turn-off, the drive device 100 discharges the gate 15.

[0026] It is known that the semiconductor element 10 itself consumes energy during its switching operation, i.e., during its turn-on and turn-off operations. Hereinafter, this energy consumption will also be referred to as switching loss. Since switching loss can cause the semiconductor element 10 to generate heat, it is desirable to minimize switching loss.

[0027] 2 is a typical operational waveform diagram illustrating the normal turn-on operation of a semiconductor device. When the semiconductor device 10 is turned on, as described above, a current flows through the semiconductor device 10 along a current path including a load (not shown). Note that the voltages and currents in the waveform diagrams below, including FIG. 2, represent voltages and currents measured from outside the semiconductor device 10 via the gate terminal, drain terminal, and source terminal.

[0028] Referring to FIG. 2, before time ts, the semiconductor element 10 is in an off state with the main electrodes (drain-source) disconnected, the drain-source voltage Vds (hereinafter also simply referred to as the "drain voltage Vds"), which is the voltage between the main electrodes, is (Vdd-Vss), and the drain-source current Id (hereinafter also simply referred to as the "drain current Id"), which is the current between the main electrodes, is 0.

[0029] At time ts, the drive control signal Ssw changes from "0" to "1," and the drive device 100 starts charging the gate 15. That is, the turn-on operation starts at time ts. For example, while Ssw="1," the gate 15 is connected to the power supply node that supplies a predetermined on-voltage VH. As a result, the gate voltage starts to rise from time ts.

[0030] At time ta, the gate voltage Vg exceeds the threshold voltage Vth, causing the drain voltage Vds to start decreasing and the drain current Id to start increasing. After time ta, the drain voltage Vds gradually decreases and the drain current Id gradually increases, causing the semiconductor device 10 to gradually become conductive.

[0031] After time ts, the gate voltage Vg rises along with the charging of the parasitic capacitance of the gate 15. Therefore, even if charging of the gate 15 starts in response to a change in the drive control signal Ssw, the gate voltage Vg does not rise immediately, but exhibits the voltage behavior shown in FIG.

[0032] It is known that the parasitic capacitance (gate capacitance) of the gate 15 is not constant but depends on the drain voltage Vds. In particular, when the drain voltage Vds decreases, the feedback capacitance, which is the capacitance between the gate and the drain, is added to the gate capacitance as an apparent gate capacitance (so-called Miller capacitance).

[0033] The mirror capacitance has drain voltage dependency, increasing as the drain voltage Vds decreases, but stops increasing once the drain voltage Vds is sufficiently reduced. Therefore, the gate voltage Vg does not change uniformly, and a period called the mirror period 200 occurs during which the gate voltage Vg does not increase between times tb and tc, which corresponds to the period until the increase in the mirror capacitance stops. In other words, the start and end times of the mirror period are times tb and tc. Hereinafter, the gate voltage Vg during the mirror period 200 will also be referred to as the mirror voltage Vp.

[0034] During the mirror period 200, the drain voltage Vds continues to decrease, but as soon as the mirror period 200 ends, Vds becomes approximately 0. Therefore, at time tc when the mirror period 200 ends, conduction occurs between the main electrodes (drain and source) of the semiconductor element 10, completing the turn-on. After the mirror period 200 ends, the gate voltage Vg continues to increase, and then reaches a predetermined voltage (the charging voltage by the driver 100) and saturates.

[0035] Because both the drain current Id and the drain voltage Vds have finite values, the semiconductor device 10 consumes power (Vds·Id) equivalent to the product of the two when turned on. Before time ta (before turn-on), the drain current Id is cut off (Id=0), so the switching power Psw=0. However, after time ta, (Vds·Id)>0, and power loss occurs. In Figure 2, the integral value of the power loss at turn-on is shown as "generated loss." This generated loss corresponds to the switching loss described above.

[0036] After the end of the mirror period 200, the drain voltage Vds becomes 0, and (Vds·Id) becomes 0 again. Therefore, it can be understood that the energy consumed when the semiconductor element 10 is turned on is the switching loss Lsw obtained by integrating (Vds·Id) between times ta and tc. In other words, after time tc when Vds becomes 0, i.e., after the mirror period 200, no power loss occurs.

[0037] 3 shows a typical operational waveform diagram in a case where an overcurrent occurs in response to turning on of the semiconductor element 10 (hereinafter also referred to as a turn-on operation in an abnormal state). As a typical example of an overcurrent, FIG. 3 illustrates an operational waveform in a case where a short circuit path is formed by turning on the semiconductor element 10.

[0038] In Fig. 3, the behavior of the gate voltage Vg, drain voltage Vds, and drain current Id from time ts to time ta is the same as in Fig. 2 (normal state), but the behavior of the gate voltage Vg after time ta is significantly different from that of Fig. 2 (normal state). Specifically, after time ta, the gate voltage Vg continues to rise until it reaches a predetermined voltage (charge voltage by drive device 100), including times tb to tc, similar to Fig. 2.

[0039] This is because at time tb, a short circuit path is formed by turning on the semiconductor element 10, so the drain voltage Vds remains almost unchanged and the Miller period 200 shown in FIG. 2 does not occur. In other words, the feedback capacitance between the gate and the drain does not change, so the parasitic capacitance (gate capacitance) of the gate 15 does not increase and remains almost constant. Therefore, the gate capacitance when a short circuit path is formed by turning on the semiconductor element 10 is smaller than that during normal turn-on operation (FIG. 2).

[0040] FIG. 4 shows a graph illustrating the relationship between the gate voltage Vg and the drain current Id when a short-circuit current flows through the semiconductor device 10.

[0041] As can be seen from FIG. 4, the drain current Id varies depending on the gate voltage Vg. Specifically, the drain current Id exhibits a characteristic of increasing as the gate voltage Vg increases. Therefore, during the turn-on operation of the semiconductor device 10 in the event of an abnormality, as shown in the example of the operational waveforms in FIG. 3, the drain current Id also continues to increase as the gate voltage Vg increases while the drive circuit 150 continues to charge the gate 15. Furthermore, when the gate voltage Vg is saturated, the drain current Id also saturates at a magnitude that depends on the gate voltage Vg.

[0042] As a result, as shown in Figure 3, when an overcurrent occurs due to the semiconductor device 10 being turned on, the loss generated by the semiconductor device becomes much larger than that during normal turn-on operation as shown in Figure 2. If the loss generated at this time exceeds the breakdown energy of the semiconductor device 10, the semiconductor device 10 will be destroyed.

[0043] Typically, a protection circuit is provided for the semiconductor element 10 to prevent damage due to an overcurrent, and the protection circuit turns off the semiconductor element 10 or cuts off the path of the short-circuit current in response to the detection of an overcurrent. However, as described above, if the time from the start of turn-on to the time when the generated loss reaches the destructive energy of the semiconductor element 10 during an abnormality is short, there is a concern that the semiconductor element 10 will be destroyed before the protection circuit can operate effectively.

[0044] When the semiconductor device 10 is turned on normally, the drain current Id does not have the dependency on the gate voltage Vg as shown in Fig. 4. Therefore, in the operating waveforms of Fig. 2, after the mirror period 200, the gate voltage Vg increases, but the drain current Id does not increase and maintains the current value at the mirror period 200.

[0045] The loss generated when the semiconductor element 10 is turned on decreases as the switching speed increases during normal turn-on operation as shown in Fig. 2. On the other hand, during abnormal turn-on operation as shown in Fig. 3, the higher the switching speed, the faster the gate voltage rises, resulting in a larger drain current Id and therefore a faster rate at which the loss increases. As a result, the higher the switching speed, the shorter the time from the start of turn-on until the loss reaches the destructive energy of the semiconductor element 10.

[0046] That is, while increasing the switching speed of the semiconductor element 10 reduces losses during normal operation, it increases the possibility of damage to the semiconductor element 10 during an abnormal event accompanied by the generation of an overcurrent. In the first embodiment, switching control at turn-on to improve this trade-off will be described.

[0047] Fig. 5 shows a block diagram for explaining a configuration example of driving device 100 according to embodiment 1. Fig. 6 shows an operational waveform diagram of a normal turn-on operation of a semiconductor element that is on / off controlled by driving device 100 shown in Fig. 5.

[0048] Referring to FIG. 5, the drive device 100 includes a drive adjustment unit 110 and a drive circuit 150.

[0049] 6 and 2, the driving device 100 according to the first embodiment drives the semiconductor device 10 so that, at the time of turn-on when the drive control signal Ssw transitions from "0" to "1," a voltage drop period 210 is provided in which the drive control signal Ssw is maintained at "1" while the drive signal Sdr is set to "0." As shown in FIG. 6, during the voltage drop period 210, the semiconductor device 10 is driven so that the gate voltage Vg begins to decrease.

[0050] 5, the drive adjustment unit 110 generates the drive signal Sdr having the above-mentioned voltage drop period 210 (FIG. 6) based on the drive control signal Ssw. The drive adjustment unit 110 has an edge detection unit 120, a delay circuit 130, a memory 135, an insertion pulse generation unit 140, and a signal synthesis unit 145. The functions of each element of the drive adjustment unit 110 may be realized by a dedicated electronic circuit (hardware) or by program processing (software).

[0051] The memory 135 is a concept representing an element for recording time, and as will be described later, stores in advance a predetermined length (length of time) of time elapsed from the start of turn-on. Specifically, the memory 135 is configured to store lengths of time Ta and Tb that respectively define the start and end timings of the voltage drop period 210 in Fig. 6. That is, there is a relationship between Ta and Tb, Tb>Ta.

[0052] The memory 135 can be configured to include a digital circuit that stores the above Ta and Tb as digital values, or can be configured to include an analog circuit that provides delay times corresponding to Ta and Tb, which are determined by the circuit constants of passive elements or the number of inverter stages, etc.

[0053] When the drive control signal Ssw changes from "0" to "1" at time ts, the edge detection unit 120 detects a turn-on command and generates a one-shot pulse. That is, time ts corresponds to the turn-on start timing. The one-shot pulse from the edge detection unit 120 is input to the delay circuit 130. Furthermore, the edge detection unit 120 transmits the drive control signal Ssw to the signal synthesis unit 145.

[0054] The delay circuit 130 generates a first pulse P1 by delaying the one-shot pulse from the edge detection unit 120 by Ta, and a second pulse P2 by delaying the one-shot pulse from the edge detection unit 120 by Tb, and inputs them to the insertion pulse generation unit 140.

[0055] The insertion pulse generation unit 140 can use the first pulse P1 and the second pulse P2 to detect the start and end timings of the voltage drop period 210. For example, during a turn-on operation, the insertion pulse generation unit 140 generates an off-pulse signal Pof that is set to "0" from the time the first pulse P1 is received until the time the second pulse is received, and is set to "1" during the rest of the period.

[0056] The time lengths Ta and Tb, which respectively define the start and end timings of the voltage drop period 210, are set based on the operating waveforms of the semiconductor device 10 when it is normally turned on after time ts and when the drive signal Sdr is fixed to "1," as shown in FIG. 2. In the first embodiment, the voltage drop period 210 is determined to be set after the mirror period 200 (times tb to tc). The time length of the voltage drop period 210, i.e., (Tb-Ta), is set so that a period occurs during which the gate voltage Vg starts to drop.

[0057] The signal synthesis unit 145 in Fig. 5 generates the drive signal Sdr by performing a logical AND operation on the drive control signal Ssw and the off-pulse signal Pof from the insertion pulse generation unit 140. As a result, as shown in Fig. 6, the drive signal Sdr has a waveform in which it is set to "0" from time t1, which is a time length Ta after time ts, to time t2, which is a time length Tb after time ts, and is set to "1" during the other periods. This provides a voltage drop period 210 in the drive signal Sdr.

[0058] The drive circuit 150 in FIG. 5 includes a transistor 151 connected between a power supply node 161 and a gate 15, and a transistor 152 connected between the gate 15 and a power supply node 162. The power supply node 161 supplies an on-voltage VH (VH>Vth), which is a positive voltage for charging the gate 15. The power supply node 162 supplies an off-voltage VL for turning off the semiconductor device 10. In this embodiment, the off-voltage VL is a negative voltage relative to the source, but a voltage Vss (FIG. 1) having the same potential as the source can also be used. That is, the power supply node 162 corresponds to an example of a "first voltage terminal," and the power supply node 161 corresponds to an example of a "second voltage terminal." The off-voltage VL and the on-voltage VH correspond to a "first voltage" and a "second voltage," respectively.

[0059] The gates of the transistors 151 and 152 are commonly connected and receive the drive signal Sdr from the drive adjustment unit 110. During the period when the drive signal Sdr is "1", the transistor 151 is turned on, while the transistor 152 is turned off, and the gate 15 is connected to the power supply node 161 that supplies the on-voltage VH. This charges the gate 15.

[0060] On the other hand, during the period when the drive signal Sdr="0", the transistor 152 is turned on, while the transistor 151 is turned off, and the gate 15 is connected to the power supply node 162 that supplies the off-voltage VL. Therefore, it can be understood that the gate 15 is temporarily discharged during the voltage drop period 210.

[0061] Next, voltage and current waveforms of semiconductor device 10 that has been normally turned on by driving device 100 according to the first embodiment will be described with reference to FIG.

[0062] During the period from time ts to time t1 when the voltage drop period 210 starts, the drive signal Sdr is set to "1" in accordance with the drive control signal Ssw. Therefore, from time ts to t1, the waveforms of the gate voltage Vg, drain voltage Vds, and drain current Id are the same as those in FIG. 2. As a result, in FIG. 6 as well, when a turn-on command is issued at time ts similar to that in FIG. 2, the gate voltage Vg exceeds the threshold voltage Vth at time ta similar to that in FIG. 2, and is maintained constant from time tb to tc (mirror period 200) similar to that in FIG. 2, before rising toward the on-voltage VH.

[0063] In response to this change in gate voltage Vg, drain voltage Vds starts to decrease and drain current Id starts to increase from time ta, just as in Figure 2. Then, at time tc when mirror period 200 ends, Vds drops to 0. Therefore, the loss generated up to this point is the same as in Figure 2.

[0064] 6, in a voltage drop period 210 provided after the mirror period 200, the drive signal Sdr is set to "0", so the drive circuit 150 discharges the gate 15 by turning on the transistor 152. As a result, the gate voltage Vg drops during the period from time t1 to t2.

[0065] After time t2, the drive signal Sdr is set to "1" again, and the drive circuit 150 charges the gate 15 by turning on the transistor 151. As a result, the gate voltage Vg rises again toward the on-voltage VH.

[0066] Here, the voltage drop period 210 is set to have a short duration so that the gate voltage Vg does not drop below the mirror voltage Vp during the voltage drop period 210. As a result, the gate voltage Vg does not drop below the mirror voltage Vp and the semiconductor device 10 does not transition to a turn-off operation.

[0067] 6, the waveforms of the drain current Id and the drain voltage Vds are the same as those in FIG. 2 during the voltage drop period 210 (times t1 to t2) and after the voltage drop period 210 (time t2 and thereafter).

[0068] In this way, the behavior of the drain voltage Vds and the drain current Id of the semiconductor device 10 that has been normally turned on by the driving device 100 according to the first embodiment is the same as in the general case (FIG. 2) in which the driving signal Sdr is maintained at "1" without providing the voltage drop period 210. As a result, it can be seen that even if the voltage drop period 210 is provided, the loss generated during normal turn-on does not increase.

[0069] Fig. 7 shows an operational waveform diagram of an abnormality in the semiconductor device 10 that has been turned on by the driving device 100 according to the first embodiment. That is, Fig. 7 shows voltage and current waveforms in a case where an overcurrent occurs due to the formation of a short circuit path in response to the turning on of the semiconductor device 10 that begins at time ts, similar to Fig. 3 .

[0070] 7, the drive signal Sdr is set to "1" from time ts to t1, then set to "0" from time t1 to t2, and then set to "1" from time t2 onwards, as in Fig. 6. This provides a voltage drop period 210 similar to that in Fig. 6 when the semiconductor element 10 is turned on. That is, the drive device 100 according to the first embodiment sets the drive signal Sdr in common between normal operation (Fig. 6) and abnormal operation (Fig. 7).

[0071] During the period from time ts to t1 in FIG. 7, that is, the period from the start of turn-on until the start of the voltage drop period 210, the waveforms of the gate voltage Vg, drain voltage Vds, and drain current Id are the same as those in FIG.

[0072] However, in FIG. 7, by providing the voltage drop period 210, the gate voltage Vg drops during the period from time t1 to t2 due to the discharge of the gate 15 by the drive circuit 150. Note that during the abnormal state shown in FIG. 7, the mirror period 200 (FIGS. 2 and 6) that occurs during normal operation does not occur, and therefore the charge stored in the gate 15 at time t1 is less than that at time t1 during normal operation (FIGS. 2 and 6). Therefore, if a voltage drop period 210 of the same length is provided, the amount of drop in the gate voltage Vg during the voltage drop period 210 will be greater than that during normal operation. As a result, in the example of the operational waveforms shown in FIG. 8, unlike FIG. 6, the gate voltage Vg drops below the mirror voltage Vp during the voltage drop period 210.

[0073] During the voltage drop period 210, the behavior of the drain voltage Vds and the drain current Id changes from that shown in FIG. 3 in response to the drop in the gate voltage Vg described above. In particular, it can be seen that the drain current Id drops in accordance with the characteristic relationship shown in FIG. 4. As a result, an increase in generated loss is significantly suppressed during the voltage drop period 210. Furthermore, as the drain current Id drops, the drain voltage Vds momentarily increases due to the generation of a surge voltage caused by parasitic inductance (typically, parasitic inductance of wiring) in the current path including the semiconductor element 10.

[0074] 3 and 7, when semiconductor device 10 is turned on by driving device 100 according to embodiment 1, voltage drop period 210 is provided, which makes it possible to extend the time required for the generated loss to exceed the destructive energy of semiconductor device 10. This reduces the possibility that semiconductor device 10 will be destroyed before the above-described protection circuit can operate effectively.

[0075] In this way, according to the driving device 100 of the first embodiment, by providing the voltage drop period 210 at a timing corresponding to the time after the mirror period 200 has elapsed in the turn-on operation of the semiconductor element 10, it is possible to control the switching of the semiconductor element so as to suppress the influence on switching loss during normal operation and reduce the possibility of damage during an overcurrent abnormality.

[0076] As can be understood from the above explanation, extending the voltage drop period 210 increases the effect of reducing losses that occur during abnormal conditions. On the other hand, the upper limit of the time length of the voltage drop period 210 is limited to a value that prevents the gate voltage Vg from dropping to the mirror voltage Vp during normal operation. Furthermore, while the start timing of the voltage drop period 210 during turn-on operation must be after the mirror period 200 ends, it is desirable to set it so that it is not too late in order to suppress an increase in the drain current Id during abnormal conditions.

[0077] However, because the behavior at turn-on differs depending on the characteristics of the semiconductor element 10, it is expected that the optimal values ​​for the start timing and end timing (i.e., start timing and duration) of the voltage drop period 210 will differ depending on the characteristics of the semiconductor element 10. For this reason, it is preferable to determine in advance the above-mentioned optimal values ​​suited to the characteristics of the semiconductor element 10 through actual device testing or simulation using the semiconductor element 10 that is the target of switching control by the driving device 100. By setting the durations Ta and Tb pre-stored in the memory 135 in correspondence with the previously determined optimal values, it becomes possible to appropriately set at least one of the start timing and duration of the voltage drop period 210 in order to achieve the effects of the first embodiment described above.

[0078] A variation of the first embodiment. FIG. 8 shows an operational waveform diagram when an abnormality occurs in a semiconductor element turned on by a driving device according to a modification of the first embodiment.

[0079] As can be seen from a comparison between FIG. 8 and FIG. 7, the modification of the first embodiment differs from the first embodiment in that the voltage drop period 210 is configured to include a plurality of divided drop periods 211 and 212.

[0080] In the example of FIG. 8, the start timing and end timing of the divided fall period 211 are determined by the time lengths Ta1 and Tb1 that have elapsed since the turn-on start time (time ts). Similarly, the start timing and end timing of the divided fall period 212 that is provided after the divided fall period 211 are determined by the time lengths Ta2 and Tb2 that have elapsed since the turn-on start time (time ts) (Ta1 <Tb1<Ta2<Tb2)。

[0081] As a result, the drop period including the divided drop periods 211 and 212 is provided between time t1 and time t2#, which is after time t2, as in Figures 6 and 7. In this way, by configuring the voltage drop period 210 with multiple divided drop periods 211 and 212, the drop period of the drain current Id and the generation period of the surge voltage are also divided. As a result, the change (increase) in the drain voltage Vds during the voltage drop period 210 can be suppressed.

[0082] In the modification of the first embodiment, too, the voltage drop period 210 must be arranged so that the gate voltage Vg does not drop to the mirror voltage Vp under normal conditions after the mirror period 200 (FIGS. 2 and 6) ends. As a result, although not shown, the waveforms of the drain voltage Vds and the drain current Id when the semiconductor device 10 is normally turned on in accordance with the drive signal Sdr shown in FIG. 8 can be made similar to those in FIG. 6 (first embodiment).

[0083] A driving device according to a modification of the first embodiment can be realized, for example, by modifying the configuration shown in Fig. 5 as follows. First, the above-mentioned time lengths Ta1, Tb1, Ta2, and Tb2 are stored in advance in the memory 135, and the delay circuit 130 operates to input a total of four pulses to the insertion pulse generation unit 140 as the time lengths Ta1, Tb1, Ta2, and Tb2 elapse from time ts. Furthermore, the insertion pulse generation unit 140 operates to generate, in accordance with the four pulses, an off-pulse signal Pof that is set to "0" corresponding to the timing of the divided fall periods 211 and 212 in Fig. 8 and is set to "1" during other periods, thereby allowing the signal synthesis unit 145 to generate the driving signal Sdr shown in Fig. 8.

[0084] Although the example in which the voltage drop period 210 is composed of two divided drop periods 211 and 212 has been described in FIG. 8, the number of divisions can be three or more.

[0085] As described above, according to the driving device of the modified example of the first embodiment, in addition to the effects described in the first embodiment, it is possible to suppress the surge voltage during the voltage drop period 210 during the turn-on operation in the event of an abnormality that causes an overcurrent.

[0086] Embodiment 2 As can be understood from the explanations of the first embodiment and its modifications, in the drive device according to this embodiment, it is important to set the start timing and duration of the voltage drop period 210. In the second embodiment, a technique will be described in which the voltage drop period 210 is variably adjusted using information about the operating state of the semiconductor element 10 (at least one of the gate voltage Vg, gate current, drain voltage Vds, drain current Id, and temperature Tj).

[0087] FIG. 9 is a block diagram illustrating an example of the configuration of a driving device 101 according to the second embodiment.

[0088] 9, drive device 101 according to embodiment 2 differs from drive device 100 according to embodiment 1 (FIG. 5) in that drive adjustment unit 111 is provided instead of drive adjustment unit 110. Drive adjustment unit 111 differs from drive adjustment unit 110 in that external interface circuit 170 is added.

[0089] A detection value by a detector 18 provided in the semiconductor element 10 is input to the external interface circuit 170. The detector 18 detects at least one of the gate voltage Vg, gate current, drain voltage Vds, drain current Id, and temperature Tj, which are the information amount ST relating to the operating state of the semiconductor element 10. The functions of the edge detection unit 120, insertion pulse generation unit 140, and signal synthesis unit 145 in the drive adjustment unit 110 are the same as those in the first embodiment, and therefore detailed description thereof will not be repeated.

[0090] In the driving device 101 according to the second embodiment, the driving adjustment unit 110 includes a delay circuit 131 instead of the delay circuit 130 (FIG. 5) in the first embodiment. The delay circuit 131 acquires the value of the information amount ST via the external interface circuit 170. Furthermore, the delay circuit 131 has a function of variably adjusting at least one of the start timing and the duration of the voltage drop period 210 according to the information amount ST. For example, the delay circuit 131 is configured to generate the first pulse P1 and the second pulse P2 in such a manner that at least one of the time lengths Ta and Tb that define the voltage drop period 210 is corrected according to the information amount ST.

[0091] The insertion pulse generating unit 140 generates the off-pulse signal Pof using the first pulse P1 and the second pulse P2 from the delay circuit 131, and thus the driving device 101 can variably adjust at least one of the start timing and the duration of the voltage drop period 210 provided in the driving signal Sdr according to the amount of information ST.

[0092] The switching operation of the semiconductor element 10 varies depending on the characteristic variations of the semiconductor element 10 and the operating environment, such as temperature. Therefore, when the start timing and end timing of the voltage drop period 210 are fixed, it is necessary to set the timings including a margin that takes into account the above-mentioned characteristic variations and changes in the switching operation of the semiconductor element 10 due to the operating environment.

[0093] Therefore, in the second embodiment, the amount of information relating to the operating state of the semiconductor element 10 is fed back to the driving device 101 via the external interface circuit 170, and at least one of the start timing and end timing of the voltage drop period 210 is variably adjusted in response to the changes in the switching operation described above, thereby realizing optimal switching operation.

[0094] Next, specific examples of variable adjustment of the voltage drop period 210 in relation to the amount of information ST will be described one by one. As a first example, the drain voltage Vds of the semiconductor element 10 can be used as the information amount ST.

[0095] FIG. 10 shows a typical drain voltage-drain current characteristic diagram of the semiconductor device 10.

[0096] As shown in FIG. 10, the semiconductor element 10 has different drain voltage-drain current characteristics depending on the gate voltage Vg (Vg1 to Vg5 in FIG. 10), but at any gate voltage Vg, the larger the drain voltage Vds, the larger the drain current Id.

[0097] 11 shows an operational waveform diagram for explaining variable adjustment of the drop period when the drain voltage Vds is set to the information content ST. In FIG. 11, the dotted line indicates the effect on the switching operation of the semiconductor device 10 when the drain voltage Vds increases before the start of the mirror period 200.

[0098] 11, the higher the drain voltage Vds, the faster the change in drain current Id, and therefore the occurrence timing of the mirror period 200 becomes earlier and shorter. As a result, the higher the drain voltage Vds, the higher the gate voltage Vg at time t1 corresponding to the pre-stored time length Ta.

[0099] Therefore, by correcting the durations Ta and Tb of the voltage drop period 210 so that the start timing is advanced (the duration Ta is shortened) and / or the duration is lengthened (Tb-Ta is lengthened) as the drain voltage Vds increases, it is possible to optimize at least one of the start timing and duration of the voltage drop period 210 in accordance with the actual switching operation of the semiconductor element 10. This enhances the effect of extending the time required for the loss generated by the semiconductor element 10 to exceed the destructive energy of the semiconductor element 10 in the event of an abnormality in which an overcurrent occurs, and further reduces the possibility of the semiconductor element 10 being destroyed.

[0100] Fig. 12 shows a first flowchart illustrating the control process for variably adjusting the decrease period in driving device 101 according to embodiment 2. Apart from the process according to the flowchart shown in Fig. 12, driving device 101 can periodically acquire the detected value by detector 18, i.e., the amount of information relating to the operating state of the semiconductor element, via external interface circuit 170.

[0101] 12, the driving device 101 detects a transition of the driving control signal Ssw from "0" to "1", i.e., a turn-on command to the semiconductor element 10, in step (hereinafter simply referred to as "S") 110. The processing in S110 is equivalent to the function of the edge detection unit 120.

[0102] When the drive device 101 detects a turn-on command (YES in S110), it executes the processes of S120 and S130. On the other hand, even if the turn-on operation is completed once and the process returns to "START," the processes from S120 onward are not executed until a turn-on command is detected (NO in S110).

[0103] In S120, the driving device 101 determines the value of the information amount ST used for variably adjusting the voltage drop period 210 from the information amount ST acquired at a constant cycle. For example, when the drain voltage Vds before the start of the mirror period 200 described in Fig. 11 is used as the information amount ST, the value of the information amount ST used for adjustment can be determined by extracting a detection value acquired at a predetermined timing before time ts (before the turn-on operation) or between times ts and tb (after the start of turn-on and before the start of the mirror period 200).

[0104] The driving device 101 adjusts at least one of the time length Ta that defines the time t1 (the start timing of the voltage drop period 210) and the time length Tb that defines the time t2 (the end timing of the voltage drop period 210) based on the value of the information amount ST (here, the drain voltage Vds) determined in S120. For example, when the above-mentioned drain voltage Vds is used as the information amount ST, at least one of the time lengths Ta and Tb can be adjusted so that the higher the drain voltage Vds, the earlier the start timing of the voltage drop period 210 and / or the longer the time length, and conversely, the lower the drain voltage Vds, the later the start timing of the voltage drop period 210 and / or the shorter the time length.

[0105] Typically, the process of S130 can be realized by storing in advance in memory 135 a lookup table or a function formula for determining optimal values ​​of time lengths Ta and Tb relative to information content ST (drain voltage Vds). Note that the above-mentioned optimal values ​​can be determined in advance by testing an actual device or simulating the switching operation of semiconductor device 10 while varying information content ST (drain voltage Vds). Alternatively, if memory 135 is configured with the above-mentioned analog circuit, the analog circuit can be provided with a variable mechanism for switching circuit constant values ​​or the number of inverter stages relative to information content ST (drain voltage Vds).

[0106] In this way, by executing the processes of S120 and S130 for each turn-on command of the semiconductor element 10, at least one of the start timing and duration of the voltage drop period 210 can be appropriately variably adjusted by feedback of information regarding the operating state of the semiconductor element 10 (here, the drain voltage Vds).

[0107] As a second example, it is also possible to feed back the drain current Id of the semiconductor element 10 as the amount of information ST.

[0108] Fig. 13 shows an operational waveform diagram for explaining variable adjustment of the decrease period when the drain current Id is set to the information content ST. In Fig. 13, the influence on the switching operation of the semiconductor element 10 when the drain current Id becomes small after turning on is shown by a dotted line.

[0109] 13, when the drain current Id is small, the mirror voltage Vp drops during the mirror period 200. As a result, the timing at which the mirror period 200 occurs becomes earlier, and the amount of drop in the gate voltage Vg allowed during the voltage drop period 210 increases.

[0110] Therefore, by correcting the time lengths Ta and Tb of the voltage drop period 210 so that the start timing is advanced (the time length Ta is shortened) and / or the period length is lengthened (the difference Tb-Ta is lengthened) as the drain current Id is smaller, it is possible to optimize at least one of the start timing and the time length of the voltage drop period 210 to suit the actual switching operation of the semiconductor element 10.

[0111] When the drain current Id of the semiconductor element 10 is used as the amount of information ST, the control process applied in the flowchart of Fig. 12 can also be applied. In this case, in S120, the driving device 101 extracts the drain current Id from the previous turn-on operation of the semiconductor element 10 (after time tb) and can determine the amount of information ST to be used for variably adjusting the voltage drop period 210.

[0112] Alternatively, in S120, it is also possible to predict the drain current Id using the current value of a load (not shown) before the current turn-on operation, thereby determining the amount of information ST used for variable adjustment of the voltage drop period 210. In this case, it is necessary to arrange the detector 18 corresponding to the load (not shown).

[0113] In this way, the position and duration of the voltage drop period 210 can be appropriately adjusted by feedback of the drain current Id of the semiconductor device 10 as well.

[0114] As a third example, it is also possible to feed back the temperature (element temperature) Tj of the semiconductor element 10 as the amount of information ST.

[0115] FIG. 14 shows a graph illustrating the temperature dependency of the relationship between the gate voltage Vg and the drain current Id when a short-circuit current flows through the semiconductor element 10 shown in FIG.

[0116] 14, when the element temperature Tj of the semiconductor element 10 increases, the threshold voltage Vth of the semiconductor element 10 decreases. As a result, the characteristic line of gate voltage Vg vs. drain current Id (short circuit) shifts to the left in the figure. That is, the drain current Id increases for the same gate voltage Vg.

[0117] Fig. 15 shows an operational waveform diagram for explaining variable adjustment of the decrease period when the element temperature Tj is the information amount ST. In Fig. 15, the influence of an increase in the element temperature Tj on the switching operation of the semiconductor element 10 is shown by a dotted line.

[0118] 15, as the element temperature Tj rises, the threshold voltage Vth of the semiconductor element 10 decreases. Furthermore, since the mirror voltage Vp also changes in conjunction with the threshold voltage Vth, the mirror voltage Vp also decreases as the element temperature rises.

[0119] 15 (the timing when Vg=Vth), time tb (the start timing of the mirror period 200), and time tc (the end timing of the mirror period 200) become earlier as the element temperature Tj rises. As a result, it can be understood that as the element temperature Tj rises, the timing when the mirror period 200 occurs becomes earlier and the amount of decrease in gate voltage Vg allowed in the voltage drop period 210 becomes larger.

[0120] Therefore, when the element temperature Tj rises, the start timing of the voltage drop period 210 can be advanced (the time length Ta can be shortened) and / or the period length can be lengthened (Tb-Ta can be lengthened) by correcting the time lengths Ta and Tb. This makes it possible to optimize at least one of the start timing and the time length of the voltage drop period 210 to suit the actual switching operation of the semiconductor element 10.

[0121] When the element temperature Tj of the semiconductor element 10 is used as the amount of information ST, the control process applied in the flowchart of Fig. 12 can also be applied. In this case, in S120, the driving device 101 can extract the element temperature Tj at the time of a turn-on command to the semiconductor element 10 (time ts) and determine the amount of information ST to be used for variably adjusting the voltage drop period 210.

[0122] In this way, at least one of the start timing and duration of the voltage drop period 210 can be appropriately variably adjusted by feedback of the element temperature Tj of the semiconductor element 10 as well.

[0123] As a fourth example, it is also possible to adjust the voltage drop period 210 by feeding back the gate voltage Vg of the semiconductor element 10 as the amount of information ST.

[0124] FIG. 16 shows an operational waveform diagram for explaining variable adjustment of the drop period when the gate voltage Vg is set to the information amount ST.

[0125] By feeding back the gate voltage Vg as the information content ST, it is possible to directly detect the mirror voltage Vp. Furthermore, by detecting the gate voltage Vg for a certain period, it is also possible to detect the start timing (time tb) and end timing (time tc) of the mirror period 200. This makes it possible to appropriately set the start timing of the voltage drop period 210 in accordance with the detection of the end timing of the mirror period 200.

[0126] Furthermore, by feedback of the gate voltage Vg during the voltage drop period 210, it is possible to reliably prevent the gate voltage Vg from dropping to the mirror voltage Vp, and then terminate the voltage drop period 210.

[0127] Fig. 17 shows a second flowchart illustrating the control process for variably adjusting the decrease period in the driving device 101 according to embodiment 2. Fig. 17 shows the control process when the gate voltage Vg is fed back as the information amount ST as described above.

[0128] 17, the driving device 101 detects the transition of the driving control signal Ssw from "0" to "1", that is, the turn-on command to the semiconductor element 10, in S210 similar to S110 in FIG.

[0129] When the drive device 101 detects a turn-on command (YES in S210), it executes the processes of S220 and S230. In S220, the drive device 101 periodically acquires the detection value from the detector 18 to read the gate voltage Vg, and in S230, it determines the start timing of the voltage reduction period 210 by monitoring the transition of the read gate voltage Vg. For example, the start timing (time t1) of the voltage reduction period 210 can be determined from a preset optimal value of the length of time (time tc to t1) from the end of the mirror period 200 to the start of the voltage reduction period 210 and the start timing (time tc) of the mirror period 200 detected from the transition of the gate voltage Vg. At the start timing of the voltage reduction period 210, the drive device 101 changes the drive signal Sdr from “1” to “0.”

[0130] The processes of S220 and S230 are repeatedly executed until the voltage reduction period 210 starts (NO determination in S240). When the voltage reduction period 210 starts (YES determination in S240), the driving device 101 executes the processes of S240 to S280 to determine the end timing of the voltage reduction period 210.

[0131] In S250, the driving device 101 reads the gate voltage Vg as in S220, and in S260, compares the gate voltage Vg read in S250 with the sum of the mirror voltage Vp and the margin value ε. The mirror voltage Vp can be obtained in advance from the transition of the gate voltage Vg monitored in S230 until the determination in S240 is YES.

[0132] Until the gate voltage Vg becomes equal to or lower than Vp+ε (NO in S260), the drive signal Sdr is maintained at "0" in S270, and the processes of S250 and S260 are repeatedly executed.

[0133] On the other hand, when the gate voltage Vg drops to Vp+ε or less (YES in S260), the driving device 101 changes the driving signal Sdr from “0” to “1” in S280, thereby ending the voltage drop period 210.

[0134] In this way, by setting the start and end timings of the voltage drop period 210 based on the transition of the gate voltage Vg of the semiconductor element 10 that is fed back, the start timing and duration of the voltage drop period 210 can be optimally variably adjusted.

[0135] As described above, the drive device according to the second embodiment allows for appropriate setting of at least one of the start timing and duration of the voltage drop period 210 in accordance with the actual switching operation, which changes depending on the operating environment, such as temperature and variations in the characteristics of the semiconductor element 10, by feedback of the amount of information relating to the operating state of the semiconductor element 10. This enhances the effect of extending the time required for the loss generated by the semiconductor element 10 in the event of an abnormality to exceed the destructive energy of the semiconductor element 10, as described in the first embodiment, and further reduces the possibility of the semiconductor element 10 being destroyed.

[0136] The amount of information ST to be fed back can be at least one of the gate voltage Vg, gate current, drain voltage Vds, drain current Id, and temperature Tj, and it is also possible to feed back a plurality of amounts of information ST. For example, by determining optimal values ​​of the time lengths Ta and Tb for a combination of a plurality of amounts of information ST in advance and storing them in memory 135, it becomes possible to variably adjust the voltage drop period 210 according to the control process shown in the flowchart of FIG.

[0137] Alternatively, the start timing of the voltage reduction period 210 may be determined by the control process of FIG. 12, while the end timing of the voltage reduction period 210 may be variably adjusted by a combination determined by the processes of S250 to S280 of FIG. 17.

[0138] Also in the second embodiment, as in the modified example of the first embodiment, the voltage drop period 210 can be configured by two or more divided drop periods. In this case, too, the start and end timings of each divided drop period can be adjusted by feedback of the amount of information relating to the operating state of the semiconductor element 10.

[0139] Embodiment 3 In embodiment 3, switching control during a turn-off operation will be described. When a semiconductor element is turned off in the event of an abnormality such as an overcurrent caused by a load short circuit, there is a concern that the semiconductor element may be destroyed by an excessive surge voltage.

[0140] Fig. 18 shows a typical operational waveform diagram of a turn-on operation when a semiconductor element is abnormal. Note that the example of Fig. 18 also shows the operational waveform when a semiconductor element 10 (in an ON state) included in a short-circuit path is turned off, which is the case in which the surge voltage is the largest.

[0141] 18, before time te, semiconductor device 10 is in an on-state with conduction between the main electrodes (drain and source), but when a short-circuit current such as that described above flows, the drain current Id before the turn-off operation is a finite value depending on the gate voltage Vg (i.e., on-voltage VH) in accordance with the characteristic relationship shown in Fig. 4. Also, with regard to the drain voltage Vds, while the turn-off operation normally begins with Vds = 0, when a short-circuit current flows, the turn-off operation starts from Vds = (Vdd - Vss).

[0142] At time te, in response to the drive control signal Ssw changing from "1" to "0", the drive device 100 starts discharging the gate 15. That is, the turn-off operation starts from time te. For example, during the period when Ssw = "0", the gate 15 is connected to a power supply node that supplies an off-voltage VL (here, a negative voltage). As a result, the gate voltage starts to decrease from time te. Then, at time tf, the gate voltage Vg drops to the threshold voltage Vth, and after time tf, Vg < Vth.

[0143] In the short-circuit state shown in FIG. 18, similar to the turn-on operation described in FIG. 3, no mirror period in which the gate voltage Vg is maintained at a constant value occurs. On the other hand, although not shown in the figure, during a normal turn-off operation, similar to the turn-on operation shown in FIG. 2, the gate voltage Vg decreases from the on-voltage VH to the off-voltage VL with the occurrence of a mirror period. Even during the turn-off operation, the gate voltage Vg during the mirror period is maintained at the same mirror voltage Vp as during the turn-on operation.

[0144] After time te, the drain current Id decreases as the gate voltage Vg decreases. Then, after time tf when Vg < Vth, the drain current Id becomes 0 (Id = 0), and the semiconductor element 10 is in an off state.

[0145] At this time, a surge voltage proportional to the rate of decrease of the drain current Id (dId / dt) is superimposed on the drain voltage Vds. If the drain voltage Vds exceeds the breakdown voltage due to the influence of the surge voltage, the semiconductor element 10 will be damaged. Therefore, in order to reduce the possibility of damage to the semiconductor element 10 during abnormal conditions, in the turn-off operation from the short-circuit state, at least the drain voltage Vds with the superimposed surge voltage must be suppressed below the breakdown voltage.

[0146] To suppress surge voltage, a slower switching speed, i.e., a slower gate voltage drop, is advantageous in order to reduce the rate at which the drain current Id drops. However, as with the turn-on operation, slowing down the switching speed of the semiconductor element 10 increases the loss generated during normal turn-off operation. Thus, even during the turn-off operation, increasing the switching speed of the semiconductor element 10 reduces the loss generated during normal operation, but increases the possibility of damage to the semiconductor element 10 in the event of an abnormality accompanied by the generation of an overcurrent. In the third embodiment, switching control during turn-off to improve this trade-off is described.

[0147] Fig. 19 shows a block diagram for explaining a configuration example of the driving device 102 according to the embodiment 3. Fig. 20 shows an operational waveform diagram of a turn-on operation in an abnormal state (short-circuit state) of a semiconductor element that is on / off controlled by the driving device 102 according to the embodiment 3.

[0148] Referring to FIG. 19, the drive device 102 includes a drive adjustment unit 112 and a drive circuit 150.

[0149] 20 and 18, the driving device 102 according to the third embodiment drives the semiconductor device 10 so that, at the time of turn-off when the drive control signal Ssw transitions from "1" to "0," the drive control signal Ssw is maintained at "0" while a voltage rise period 410 is provided in which the drive signal Sdr is set to "1." As shown in FIG. 20, during the voltage rise period 410, the semiconductor device 10 is driven so that the gate voltage Vg begins to rise.

[0150] 19, the drive adjuster 112 generates the drive signal Sdr having the above-mentioned voltage rise period 410 (FIG. 20) based on the drive control signal Ssw. The drive adjuster 112 has an edge detector 122, a delay circuit 132, a memory 135, an insertion pulse generator 142, and a signal combiner 146. The functions of each element of the drive adjuster 112 may be realized by a dedicated electronic circuit (hardware) or by program processing (software).

[0151] The memory 135 is configured to store the time lengths Tc and Td that respectively define the start and end timings of the voltage rise period 410 in Fig. 20. That is, the relationship Td>Tc holds between Tc and Td. The memory 135 can be configured to store the time lengths Tc and Td in common with the time lengths that define the start and end timings of the voltage drop period 210 during the turn-on operation in the first embodiment and its modifications.

[0152] When the drive control signal Ssw changes from "1" to "0" at time te, the edge detection unit 122 detects a turn-off command and generates a one-shot pulse. That is, time te corresponds to the turn-off start timing. The one-shot pulse from the edge detection unit 122 is input to the delay circuit 132. Furthermore, the edge detection unit 122 transmits the drive control signal Ssw to the signal synthesis unit 146.

[0153] The delay circuit 132 generates a third pulse P3 by delaying the one-shot pulse from the edge detection unit 120 by Tc, and a fourth pulse P4 by delaying the one-shot pulse from the edge detection unit 120 by Td, and inputs them to the insertion pulse generation unit 142.

[0154] The insertion pulse generation unit 142 can use the third pulse P3 and the fourth pulse P4 to detect the start timing and end timing of the voltage rise period 410. For example, during a turn-off operation, the insertion pulse generation unit 142 generates an on-pulse signal Pon that is set to "1" from the time the third pulse P3 is received until the time the fourth pulse P4 is received, and is set to "0" during other periods.

[0155] The signal synthesizing unit 146 generates the drive signal Sdr by performing a logical OR operation on the drive control signal Ssw and the on-pulse signal Pon from the insertion pulse generating unit 142. As a result, as shown in Fig. 20, during the period in which the drive control signal Ssw is set to "0," the drive signal Sdr is set to "1" from time t3 to time t4, and is set to "0" during the other periods. This provides a voltage rise period 410 for the drive signal Sdr. The drive circuit 150 has a configuration similar to that described in the first embodiment (Fig. 5), and discharges the gate 15 during the period in which the drive signal Sdr is "0," while charging the gate 15 during the period in which the drive signal Sdr is "1."

[0156] The duration of the voltage rise period 410, i.e., (Td-Tc), is set so that there is a period during which the gate voltage Vg starts to rise. Note that time t3 corresponds to the timing when time Tc has elapsed since time te when the turn-off operation is started, and time t4 corresponds to the timing when time Td has elapsed since time te.

[0157] As can be seen from a comparison between Fig. 20 and Fig. 18, the gate voltage Vg temporarily starts to rise during the voltage rise period 410 from time t3 to t4. As described above, the drain current Id in a short-circuit state depends on the gate voltage Vg, and therefore the rate at which the drain current Id decreases is slowed by the rise in the gate voltage Vg during the voltage rise period 410. As a result, the surge voltage decreases, and the drain voltage Vds starts to decrease temporarily during the rise period in Fig. 18.

[0158] As a result, it is possible to suppress the maximum value of the drain voltage Vds, which reduces the possibility that the drain voltage Vds superimposed with a surge voltage will exceed the withstand voltage during a turn-off operation from a short-circuit state, thereby damaging the semiconductor element 10.

[0159] 18 and 20, the voltage rise period 410 must be set during the period in which the surge voltage is rising, i.e., during the period in which the drain current Id is decreasing (the period until it decreases to 0), and is preferably set at a relatively early timing during the turn-off operation. Therefore, unlike the voltage fall period 210 during the turn-on operation, the voltage rise period 410 during the turn-off operation is expected to be set at a timing starting from time te earlier than the mirror period 200 during normal turn-off operation.

[0160] 20, by providing a voltage rise period 410, the timing at which the gate voltage Vg falls to the threshold voltage Vth is time tf′, which is delayed from time tf, which is the same as in FIG. 18. The delay time from time tf to time tf′, i.e., the increase in the time required for the turn-off operation to be completed, depends on the length of the voltage rise period 410.

[0161] This raises concerns that the delay time may increase losses during turn-off, including during normal turn-off. However, the duration of the voltage rise period 410 can be set as short as possible within a range in which the increase in the drain voltage Vds can be temporarily stopped by the increase in the gate voltage Vg. Therefore, by minimizing the delay time, it is possible to suppress the increase in losses caused by applying the voltage rise period 410. At least, it can be understood that the increase in losses, which comes at the expense of the surge voltage suppression effect, is significantly suppressed compared to when the switching speed is reduced throughout the entire turn-off operation to slow down the rate at which the drain current Id decreases, i.e., when the discharge rate of the gate 15 by the drive circuit 150 is reduced.

[0162] As described above, according to the driving device 102 of the third embodiment, by providing a short-pulse voltage rise period 410 in the turn-off operation of the semiconductor element 10, it is possible to suppress an increase in the loss generated in normal times, while reducing the possibility of damage to the semiconductor element 10 due to the suppression of the surge voltage in an abnormal time accompanied by the generation of an overcurrent. As a result, even in the turn-off operation, it is possible to control the switching of the semiconductor element so as to reduce the possibility of damage in the event of an abnormal overcurrent, while suppressing the effect on switching loss in normal times.

[0163] The behavior of the turn-off operation of the semiconductor element 10 also differs depending on the characteristics of the semiconductor element 10. For this reason, it is preferable to determine in advance the optimal values ​​for the position and duration (i.e., start timing and end timing) of the voltage rise period 410 through actual device testing or simulation using the semiconductor element 10 that is the target of switching control by the driving device 102. By setting the durations Tb and Tc pre-stored in the memory 135 in accordance with the pre-determined optimal values, it becomes possible to provide the voltage rise period 410 at an appropriate position and duration in order to achieve the effects of the third embodiment described above.

[0164] In the third embodiment, the division setting of the voltage drop period 210 in the modification of the first embodiment can be similarly applied to the voltage rise period 410. That is, the voltage rise period 410 can also be divided into any number of periods.

[0165] Embodiment 4 In the fourth embodiment, a technique for variably setting the voltage rise period 410 using information about the operating state of the semiconductor element 10 (at least one of the gate voltage Vg, gate current, drain voltage Vds, drain current Id, and element temperature Tj) similar to that in the second embodiment will be described.

[0166] FIG. 21 is a block diagram illustrating an example of the configuration of a driving device 103 according to the fourth embodiment.

[0167] 21, drive device 103 according to embodiment 4 differs from drive device 102 according to embodiment 3 (FIG. 19) in that drive adjustment unit 113 is provided instead of drive adjustment unit 112. Drive adjustment unit 113 differs from drive adjustment unit 112 in that external interface circuit 170 is added.

[0168] 9, at least one detected value (detector 18) of the gate voltage Vg, the gate current, the drain voltage Vds, the drain current Id, and the temperature Tj, which are information ST relating to the operating state of the semiconductor device 10, is input to the external interface circuit 170. The functions of the edge detection unit 122, the insertion pulse generation unit 142, and the signal synthesis unit 146 in the drive adjustment unit 112 are the same as those in the third embodiment, and therefore detailed description thereof will not be repeated.

[0169] In the driving device 103 according to the fourth embodiment, the drive adjustment unit 112 includes a delay circuit 133 instead of the delay circuit 132 (FIG. 5) in the third embodiment. The delay circuit 133 acquires the value of the information amount ST via the external interface circuit 170. Furthermore, the delay circuit 133 has a function of variably adjusting at least one of the start timing and duration of the voltage rise period 410 according to the information amount ST. For example, the delay circuit 133 is configured to generate the third pulse P3 and the fourth pulse P4 in such a manner that at least one of the durations Tc and Td that define the voltage rise period 410 is corrected according to the information amount ST.

[0170] The insertion pulse generating unit 142 generates an on-pulse signal Pon using the third pulse P3 and the fourth pulse P4 from the delay circuit 133, and thus in the driving device 103, at least one of the start timing and the duration of the voltage rise period 410 provided during the turn-off operation can be variably adjusted according to the amount of information ST, similar to the voltage drop period 210 during the turn-on operation (embodiment 2).

[0171] In the semiconductor device 10, the higher the drain voltage Vds before the start of turn-off (before time te), the longer the time length from time te to tf' in Fig. 20, and the longer the time required for the turn-off operation. Similarly, with respect to the drain current Id, the larger the drain current Id before the start of turn-off (before time te), the longer the time required for the turn-off operation of the semiconductor device 10 (the time length from time te to tf').

[0172] Therefore, when the drain voltage Vds and drain current Id before the start of turn-off (before time te) are taken as the information amount ST, the higher the drain voltage Vds or the larger the drain current Id, the earlier the start timing of the voltage rise period 410 can be set and / or the longer the duration of the voltage rise period 410 can be adjusted by adjusting at least one of the time lengths Tc and Td.

[0173] 4 and other figures, there is a correlation between the gate voltage Vg and the drain current Id in a short-circuited state, so the gate voltage Vg before the start of turn-off (before time te) can also be used as the information amount ST. As shown in Fig. 4, the higher the gate voltage Vg, the larger the drain current Id. Therefore, the higher the gate voltage Vg at the start of turn-off (time te), the earlier the start timing of the voltage rise period 410 can be set and / or the length of the voltage rise period 410 can be adjusted so as to lengthen the period.

[0174] As described in the second embodiment, as the element temperature Tj increases, the threshold voltage Vth of the semiconductor element 10 decreases. Therefore, the lower the element temperature Tj, the longer the time required for the turn-off operation of the semiconductor element 10 (the time length from time te to time tf' in FIG. 20). Therefore, the lower the element temperature Tj at the start of turn-off (time te), the earlier the start timing of the voltage rise period 410 can be set and / or the longer the duration of the voltage rise period 410 can be adjusted by adjusting at least one of the time lengths Tc and Td.

[0175] Fig. 22 shows a flowchart illustrating the control process for variably adjusting the rise period based on the amount of information about the operating state of the semiconductor element in the driving device according to embodiment 4. Note that, apart from the process according to the flowchart shown in Fig. 22, driving device 101 can periodically acquire the value detected by detector 18, i.e., the amount of information about the operating state of the semiconductor element, via external interface circuit 170.

[0176] 22, in S150, the driving device 103 detects a transition of the driving control signal Ssw from “1” to “0”, that is, a turn-off command to the semiconductor element 10. The processing in S150 is equivalent to the function of the edge detection unit 122.

[0177] When the drive device 103 detects a turn-off command (YES in S150), it executes the processes of S160 and S170. On the other hand, even if the turn-off operation is completed once and the process returns to "START," the processes from S160 onward are not executed until a turn-off command is detected (NO in S150).

[0178] In S160, the driving device 103 extracts the value of the information amount ST used for variable adjustment of the voltage rise period 410 from the information amount ST acquired at a constant cycle. For example, as described above, the value of the information amount ST used for adjustment can be determined by extracting a detection value acquired at a predetermined timing included in the start timing (time te) of the turn-off command or before the start of turn-off.

[0179] In S170, the driving device 103 adjusts at least one of the time length Ta that defines the time t3 (the start timing of the voltage rise period 410) and the time length Tb that defines the time t4 (the end timing of the voltage rise period 410) based on the value of the information amount ST determined in S160.

[0180] The process of S170 can be executed in the same manner as S130 in the second embodiment (FIG. 12). That is, typically, this can be realized by storing in advance in memory 135 a lookup table or a function formula for determining optimal values ​​of the time lengths Tc and Td for the amount of information ST. The optimal values ​​of the time lengths Tc and Td in the turn-off operation can also be determined in advance by testing an actual device or simulating the switching operation of semiconductor device 10 while changing each amount of information ST.

[0181] In S170, it is also possible to adjust at least one of the durations Tc and Td by feedback of a plurality of amounts of information ST. In this case, it is necessary to determine in advance the optimum values ​​of the durations Tc and Td for the combination of a plurality of amounts of information ST.

[0182] In this way, by executing the processes of S160 and S170 for each turn-off command of the semiconductor element 10, at least one of the start timing and duration of the voltage rise period 410 can be appropriately variably adjusted by feedback of information regarding the operating state of the semiconductor element 10 (at least one of the gate voltage Vg, gate current, drain voltage Vds, drain current Id, and element temperature Tj).

[0183] As a result, the drive device according to the fourth embodiment can appropriately set at least one of the start timing and duration of the voltage rise period 410 in accordance with the actual switching operation that changes depending on the operating environment, such as the temperature and the characteristic variations of the semiconductor element 10, by feeding back the amount of information related to the operating state of the semiconductor element 10. This increases the effect of suppressing the surge voltage, further reducing the possibility of the semiconductor element 10 being destroyed.

[0184] Here, unlike the turn-on operation, the turn-off operation can distinguish between the start of a normal turn-off operation and an abnormal turn-off operation due to an overcurrent at the time of detecting the turn-off command based on the amount of information ST of the semiconductor device 10 before the start of the turn-off operation (on state). Also, as mentioned above, the voltage rise period 410 is not necessarily positioned after the end of the mirror period 200, so there is a concern that it may have some effect on the switching loss (generated loss) during normal operation.

[0185] FIG. 23 shows a flowchart illustrating a control process for selecting the placement of the voltage rise period during the turn-off operation by the driving device 103 according to the fourth embodiment.

[0186] 23, the driving device 103 detects a transition of the driving control signal Ssw from "1" to "0", i.e., a turn-off command to the semiconductor element 10, in S250, which is similar to S160 in Fig. 22. As described above, the driving device 103 periodically acquires information about the operating state of the semiconductor element 10 via the external interface circuit 170, even during the ON state period of the semiconductor element 10, separate from the processing according to the flowchart shown in Fig. 23.

[0187] When the drive device 103 detects a turn-off command (YES in S250), it executes the processes of S260 and S270. In S260, the drive device 103 extracts information ST, which is used to detect and determine an overcurrent state in S270, from the detection value of the detector 18 read while the semiconductor device 10 is in the on state. For example, in S260, the drive device 103 extracts instantaneous values, or average values, maximum values, etc. over a certain period of currents or voltages such as the drain current Id and the drain voltage Vds at or before the time (time te) when the turn-off command is detected.

[0188] In S270, the driving device 103 compares the amount of information ST extracted in S170 with a predetermined judgment value to determine whether the semiconductor device 10 is in an overcurrent state before being turned off. Typically, the overcurrent state can be detected when the drain current Id is larger than the judgment value.

[0189] When an overcurrent state is detected (YES in S270), the drive device 103 performs S280 to include a voltage increase period 410 in the turn-off operation. In S280, the voltage increase period 410 can be fixed using predetermined time lengths Tc and Td, as in the third embodiment. Alternatively, in S280, by further executing S160 and S170 of FIG. 22, it is possible to variably set the time lengths Tc and Td by feedback of the information content ST (at least one of the gate voltage Vg, gate current, drain voltage Vds, drain current Id, and element temperature Tj).

[0190] On the other hand, when an overcurrent state is not detected (NO in S270), the drive device 103 executes a turn-off operation by disabling the voltage rise period 410 in S290. In this case, in Fig. 20, the drive signal Sdr is maintained at "0" after time te until the next turn-on command is generated.

[0191] In the driving device 103 according to the fourth embodiment, by applying the control shown in Fig. 23, it is possible to suppress surge voltages during abnormal turn-off operations when an overcurrent state occurs, without increasing losses during normal turn-off operations when no overcurrent state occurs. In particular, the start timing and duration of the voltage rise period 410 can be set specifically to suppress surge voltages during abnormal operations, without considering increases in steady-state losses during normal operations, which is expected to enhance the surge voltage suppression effect. This further reduces the possibility of semiconductor device 10 being destroyed.

[0192] In the fourth embodiment, the voltage rise period 410 can also be divided into any number of periods, which is expected to further improve the effect of suppressing surge voltages in the event of an abnormality.

[0193] In the driving devices 100 to 103 described in the first to fourth embodiments, as described with reference to Figs. 5 and 19, the voltage applied to the gate 15 during the voltage drop period 210 is common to the off-voltage VL of the semiconductor element 10, and the voltage applied to the gate 15 during the voltage rise period 410 is common to the on-voltage VH of the semiconductor element 10. This makes it possible to provide the voltage drop period 210 and / or the voltage rise period 410 without increasing the number of voltage level stages applied to the gate 15 by the driving devices 100 to 103. As a result, it is possible to avoid a complicated circuit configuration.

[0194] Conversely, even if voltages different from the on-voltage VH and the off-voltage VL are applied to the gate 15 during the voltage drop period 210 and the voltage rise period 410, respectively, it is possible to obtain the same effect as that described in this embodiment as long as the gate voltage Vg drops during the voltage drop period 210 and / or the gate voltage Vg rises during the voltage rise period 410. However, if the number of voltage level stages is increased in this way, there is a concern that the configuration of the driving devices 100 to 103 including the driving circuit 150 will become complicated.

[0195] As described above, in the driving devices 101 to 103 described in the first to fourth embodiments, the functions of the drive adjustment units 110 to 113 can be configured by either hardware or software. In particular, when all of the functions of the drive adjustment units 110 to 113 are realized by software, the drive adjustment units can be configured by using part of the functions of the control circuit 20 shown in FIG.

[0196] In this case, the drive signal Sdr including an off pulse corresponding to the voltage drop period 210 and / or an on pulse corresponding to the voltage rise period 410 can be directly input from the control circuit 20 to the drive circuit 150 that forms the drive device 100. Even in this case, the drive signal Sdr and the drive control signal Ssw described in this embodiment can be identified by comparing the number of times the signal level changes with the actual number of times the semiconductor element 10 is turned on and off.

[0197] Note that if all of the drive adjusters 110 to 113 are implemented by software, it becomes easier to adjust the start timing and duration of the voltage drop period 210 and / or the voltage rise period 410. In this case, with regard to hardware, the drive circuit 150 can be designed specifically for the function of quickly turning the semiconductor element 10 on and off, eliminating the need for fine adjustments such as gate resistance adjustment, and reducing the design burden. In other words, after simplifying the hardware design, it is possible to control the switching of the semiconductor element by software adjustments so as to achieve both reduced switching loss during normal operation and reduced risk of damage during an overcurrent abnormality.

[0198] It is also possible to control the switching of the semiconductor element 10 by combining the driving device 100 or 101 according to the first or second embodiment with the driving device 103 or 104 according to the third or fourth embodiment so as to set both the voltage drop period 210 in the turn-on operation and the voltage rise period 410 in the turn-off operation. For example, such switching control can be realized by selectively transmitting the driving signal Sdr from the driving adjustment unit 110 or 111 of the driving device 100 or 101 and the driving signal Sdr from the driving adjustment unit 112 or 113 of the driving device 102 or 103 to the driving circuit 150 using a selector or the like that operates in response to the driving control signal Ssw.

[0199] Embodiment 5 In the fifth embodiment, a configuration example of a power conversion device to which the semiconductor element driving device described in the first to fourth embodiments is applied will be described.

[0200] FIG. 24 is a block diagram showing a configuration of a power conversion system to which a power conversion device according to the fifth embodiment is applied.

[0201] Referring to Fig. 24, the power conversion system includes a power supply 190, a power conversion device 250, and a load 300. The power supply 190 is a DC power supply and supplies DC power to the power conversion device 250. The power supply 190 can be configured from various elements, such as a DC system, a solar cell, or a storage battery. Alternatively, the power supply 190 may be configured from a rectifier circuit or an AC / DC converter connected to an AC system. Furthermore, the power supply 190 can also be configured from a DC / DC converter that converts DC power output from a DC system into predetermined power.

[0202] The load 300 is typically a three-phase motor driven by AC power supplied from the power conversion device 250. The load 300 is not limited to a specific application, but may be a motor mounted on various types of electrical equipment. For example, a motor for a hybrid vehicle, an electric vehicle, a railroad car, an elevator, or an air conditioning device may be used as the load 300.

[0203] The power conversion device 250 is, for example, a three-phase inverter connected between the power supply 190 and the load 300 , converts DC power supplied from the power supply 190 into AC power, and supplies the AC power to the load 300 .

[0204] The power conversion device 250 includes a main conversion circuit 251 that converts DC power into AC power and outputs the AC power, and a control circuit 255 that outputs a control signal 256 to the main conversion circuit 251 for controlling the main conversion circuit 251 .

[0205] The main conversion circuit 251 includes at least one semiconductor element 10 and a driving device 100X arranged corresponding to each semiconductor element 10. The driving device 100X comprehensively refers to the driving devices 101 to 103 described in this embodiment and combinations thereof.

[0206] The control signal 256 from the control circuit 255 includes a drive control signal Ssw for controlling the on / off of the semiconductor elements 10. Each semiconductor element 10 is turned on / off in accordance with the respective drive control signal Ssw, whereby the main conversion circuit 251 converts the DC power supplied from the power supply 190 into AC power and supplies it to the load 300.

[0207] There are various specific circuit configurations for the main conversion circuit 251, but for example, the main conversion circuit 251 can be a two-level three-phase full-bridge circuit composed of six semiconductor elements 10 and six freewheeling diodes connected in anti-parallel to the semiconductor elements 10. The six semiconductor elements 10 are connected in series in groups of two semiconductor elements 10 to form upper and lower arms, and each upper and lower arm constitutes one phase (U phase, V phase, W phase) of the full-bridge circuit. The output terminals of each upper and lower arm, i.e., the three output terminals of the main conversion circuit 251, are connected to a load 300.

[0208] The control circuit 255 controls the on / off of the semiconductor elements 10 of the main conversion circuit 251 so that the desired power is supplied to the load 300. Specifically, the control circuit 255 calculates the time (on time) that each semiconductor element 10 of the main conversion circuit 251 should be in the on state based on the power to be supplied to the load 300. For example, the main conversion circuit 251 can be controlled in accordance with PWM control that modulates the on time of each semiconductor element 10 in accordance with the voltage to be output.

[0209] At each point in time, the control circuit 255 sets the drive control signal Ssw of the semiconductor element 10 that should be in the ON state to "1", while setting the drive control signal Ssw of the semiconductor element 10 that should be in the OFF state to "0".

[0210] The drive device 100X controls the gate voltage of the corresponding semiconductor element 10 in accordance with the drive control signal Ssw from the control circuit 255. This makes it possible to control the switching of each semiconductor element 10 so as to reduce the possibility of damage in the event of an overcurrent abnormality, while suppressing the effect on switching loss in each semiconductor element 10 during normal operation. This also makes it possible for the power conversion device 250 to achieve high efficiency in power conversion due to low switching loss, and to reduce the possibility of damage in the event of a short circuit in the load 300, etc.

[0211] The driving device 100X may be built into a semiconductor module (not shown) in which the semiconductor element 10 is built, or may be connected to the semiconductor module from the outside.

[0212] Furthermore, in this embodiment, a two-level three-phase inverter has been described as an example of the power conversion device 250, but the drive device 100 described in this embodiment can be applied to various other power conversion devices. For example, the power conversion device 250 may be a three-level or multi-level power conversion device, and when the load 300 is a single-phase AC load, the power conversion device 250 can be configured as a single-phase inverter. Furthermore, when the load 300 is a DC load, the power conversion device 250 can be configured as a DC / DC converter or an AC / DC converter.

[0213] In this way, for any power conversion device that performs power conversion by controlling the on / off of a semiconductor element, the semiconductor element 10 can be turned on and off by the driving device 100X according to any of the first to fourth embodiments or a combination thereof.

[0214] In the fifth embodiment as well, all of the functions of the drive adjustment units 110 to 113 of the drive device 100X can be realized by software. In this case, the control signal 256 from the control circuit 255 can be configured to include a drive signal Sdr that includes an off-pulse corresponding to the voltage drop period 210 and / or an on-pulse corresponding to the voltage rise period 410. In this case as well, the drive signal Sdr and the drive control signal Ssw can be distinguished by comparing the number of times the signal level changes with the actual number of times the semiconductor element 10 is turned on and off.

[0215] Furthermore, the power conversion device according to this embodiment is not limited to the case where the load described above is an electric motor, but can also be used, for example, as a power supply device for an electric discharge machine, a laser processing machine, an induction heating cooker, or a contactless power supply system, and can also be used as a power conditioner for a solar power generation system, a power storage system, etc.

[0216] The embodiments disclosed herein should be considered to be illustrative in all respects and not restrictive. The technical scope of the present disclosure is defined by the claims, not the above description, and is intended to include all modifications within the meaning and scope of the claims. [Explanation of symbols]

[0217] 10 semiconductor element, 11 drain, 12 source, 15 gate, 18 detector, 20, 255 control circuit, 100, 100X, 101, 102, 103 drive device, 110, 111, 112, 113 drive adjustment unit, 120, 122 edge detection unit, 130, 131, 132, 133 delay circuit, 135 memory, 140, 142 insertion pulse generation unit, 145, 146 signal synthesis unit, 150 drive circuit, 151, 152 transistor, 161, 162 power supply node, 170 external interface circuit, 190 power supply, 200 mirror period, 210 voltage drop period, 211, 212 division drop period, 250 power conversion device, 251 main conversion circuit, 256 control signal, 300 load, 410 voltage rise period, Id Drain current, P1 to P4 pulses, Pof off-pulse signal, Pon on-pulse signal, Sdr drive signal, Ssw drive control signal, Tj element temperature, VH on-voltage, VL off-voltage, Vds drain voltage (drain-source voltage), Vg gate voltage (gate-source voltage), Vp mirror voltage, Vth threshold voltage.

Claims

1. A method for driving a semiconductor element that is turned on and off in accordance with a drive control signal, comprising: Initiating a turn-on operation to charge a gate of the semiconductor element in an off state in response to a turn-on command in which the drive control signal transitions from a first level to a second level; Initiating a turn-off operation of discharging the gate of the semiconductor element in an ON state in response to a turn-off command in which the drive control signal transitions from the second level to the first level; and providing a voltage drop period within a period in which the drive control signal is maintained at the second level after the start of the turn-on operation, The method for driving a semiconductor element, wherein the voltage drop period is set so that the gate voltage is temporarily dropped by discharging the gate after the mirror period ends.

2. a voltage rise period within a period in which the drive control signal is maintained at the first level after the start of the turn-off operation; 2. The method for driving a semiconductor device according to claim 1, wherein the voltage rise period is set so that the voltage of the gate temporarily rises by charging the gate before the start of the mirror period during a period in which the current of the semiconductor device is decreasing.

3. The step of placing the voltage drop period includes:

3. The method for driving a semiconductor element according to claim 1, further comprising the step of variably adjusting at least one of a start timing and a duration of the voltage drop period arranged in the turn-on operation in accordance with an amount of information on an operating state of the semiconductor element.

4. The step of placing the voltage rise period includes:

3. The method of driving a semiconductor device according to claim 2, further comprising the step of variably adjusting at least one of the start timing and duration of the voltage rise period arranged in the turn-off operation in accordance with an amount of information on the operating state of the semiconductor device.

5. 5. The method of driving a semiconductor element according to claim 3, wherein the amount of information on the operating state includes at least one of a voltage between main electrodes of the semiconductor element, a current between main electrodes, a gate voltage, and an element temperature.

6. 4. The method for driving a semiconductor element according to claim 1, wherein the voltage drop period is divided into a plurality of periods.

7. 5. The method of driving a semiconductor element according to claim 2, wherein the voltage rise period is divided into a plurality of periods.

8. In response to the turn-off command, detecting an overcurrent state of the semiconductor element based on a current or a voltage of the semiconductor element in an on-state before the turn-off command; 8. The method for driving a semiconductor element according to claim 2, further comprising the step of: in the turn-off operation corresponding to the turn-off command, providing the voltage rise period when the overcurrent state is detected, and not providing the voltage rise period when the overcurrent state is not detected.

9. 7. The method for driving a semiconductor element according to claim 1, wherein a common first voltage is applied to the gate during the voltage drop period and during the gate discharge period in the turn-off operation.

10. 9. The method for driving a semiconductor element according to claim 2, wherein a common second voltage is applied to the gate during the voltage rise period and during the charging period of the gate in the turn-on operation.

11. A drive device for a semiconductor element that is turned on and off in accordance with a drive control signal, a drive adjusting unit that generates drive signals for controlling a turn-on operation of charging the gate of the semiconductor element in an OFF state and a turn-off operation of discharging the gate of the semiconductor element in an ON state in response to a turn-on command in which the drive control signal transitions from a first level to a second level and a turn-off command in which the drive control signal transitions from the second level to the first level; a drive circuit that charges or discharges the gate in accordance with the drive signal; The drive adjustment unit generating the drive signal so as to arrange a voltage drop period provided within a period during which the drive control signal is maintained at the second level after the start of the turn-on operation; The drive device for a semiconductor element, wherein the voltage drop period is set so that the gate voltage is temporarily dropped by discharging the gate after the mirror period ends.

12. The drive adjustment unit 12. The semiconductor element driver of claim 11, wherein the drive signal is generated so as to include, in addition to the voltage drop period, a voltage rise period that is provided within a period during which the drive control signal is maintained at the first level after the start of the turn-off operation.

13. an interface circuit to which a detected value of an amount of information on an operating state of the semiconductor element is inputted from a detector provided in the semiconductor element; 13. The semiconductor element drive device according to claim 11, wherein the drive adjustment unit variably adjusts at least one of a start timing and a duration of the voltage drop period arranged in the turn-on operation, using the value of the amount of information input to the interface circuit.

14. an interface circuit to which a detected value of an amount of information on an operating state of the semiconductor element by a detector provided in the semiconductor element is input; 13. The semiconductor element drive device according to claim 12, wherein the drive adjustment unit varies at least one of the start timing and the duration of the voltage rise period arranged in the turn-off operation using the value of the amount of information input to the interface circuit.

15. 15. The semiconductor element driving device according to claim 13, wherein the amount of information on the operating state includes at least one of a voltage between main electrodes of the semiconductor element, a current between main electrodes, a gate voltage, and an element temperature.

16. 14. The semiconductor element driving device according to claim 11, wherein the drive adjusting section divides the voltage drop period into a plurality of periods.

17. 15. The semiconductor element driving device according to claim 12, wherein the drive adjusting section divides the voltage rise period into a plurality of periods.

18. 18. The semiconductor element driving device of claim 12, wherein the drive adjustment unit detects an overcurrent state of the semiconductor element based on the current or voltage of the semiconductor element in an on-state prior to the turn-off command in response to the turn-off command, and in the turn-off operation corresponding to the turn-off command, the drive adjustment unit arranges the voltage rise period when the overcurrent state is detected, but does not arrange the voltage rise period when the overcurrent state is not detected.

19. the drive circuit electrically connects the gate to a first voltage terminal when the drive signal is at the first level, and electrically connects the gate to a second voltage terminal when the drive signal is at the second level; A semiconductor element driving device described in any one of claims 11 to 13 and 16, wherein the drive adjustment unit sets the drive signal to the first level during the voltage drop period during a period when the drive control signal is at the second level, while setting the drive signal to the second level during a period other than the voltage drop period.

20. the drive circuit electrically connects the gate to a first voltage terminal when the drive signal is at the first level, and electrically connects the gate to a second voltage terminal when the drive signal is at the second level; 19. The semiconductor element driving device according to claim 12, wherein the drive adjustment unit sets the drive signal to the second level during the voltage rise period while setting the drive signal to the first level during periods other than the voltage rise period during which the drive control signal is at the first level.

21. a main conversion circuit including at least one of the semiconductor devices, which converts input power and outputs the converted power; a control circuit that outputs a control signal to the main conversion circuit to control the main conversion circuit; the control signals include the drive control signals for each of the semiconductor elements; the main conversion circuit further includes a drive device according to any one of claims 11 to 20, arranged corresponding to each of the semiconductor elements; The drive device controls the on / off of each of the semiconductor elements in accordance with the drive control signal.

Images