Planar light-emitting transistor emitting light from a surface light source, its manufacturing method and applications

Abstract

The present invention discloses a planar light-emitting transistor device emitting light from a surface light source and its manufacturing method and application. By inserting a charge buffer layer between the semiconductor charge transport layer and the light-emitting unit, the manufactured planar light-emitting transistor can realize a stable surface light source emission, effectively overcoming the drawback of the linear or stripe-shaped emitted light of the conventional planar light-emitting transistor. The planar light-emitting transistor device emitting light from the surface light source has a high integration degree, can realize a stable surface light source emission, effectively improves the aperture ratio of the transistor device, has good gate electrode adjustment ability, high loop stability and arbitrary adjustment, is easy to be miniaturized, can be mass-produced, and has good compatibility with flexible wearable devices, which plays an important role in promoting the application of the light-emitting transistor device in the field of light-emitting displays.

Description

[Technical Field]

[0001] This application claims priority to two prior applications: patent application number 202111288584.3, entitled "Planar light-emitting field-effect transistor for emission from a surface light source, its manufacturing method and application," filed by the applicant with the State Intellectual Property Office of the People's Republic of China on November 2, 2021; and patent application number 202111460089.6, entitled "Planar light-emitting field-effect transistor for emission from a surface light source, its manufacturing method and application," filed by the applicant with the State Intellectual Property Office of the People's Republic of China on December 1, 2021. Both of these prior applications are incorporated herein by reference in their entireties.

[0002] The present invention relates to the field of electroluminescent devices, and more particularly to a planar light-emitting transistor emitting light from a surface light source, and its manufacturing method and application. [Background technology]

[0003] The display industry has become a pillar of the information technology industry. Light-emitting transistors are a type of highly integrated electroluminescent device that combines the current amplification function of organic transistors and the electroluminescence function of organic light-emitting diodes into a single device. They have unique advantages such as high integration and simple manufacturing processes, and are considered to be an important device building block for the next generation of revolutionary display technology that will realize miniaturization, flexibility, and high definition.

[0004] Currently, light-emitting transistors are typically divided into planar and vertical structures. Vertical light-emitting transistors have short channels, making it relatively easy to achieve low-voltage operation and surface light emission. However, their operating mechanism requires the use of porous source electrodes, which are difficult to fabricate, affecting device stability and uniformity. Planar light-emitting transistor processes are relatively compatible with conventional industrial processes, resulting in relatively stable devices. However, electrons and holes generally recombine at the channel and electrode sides, resulting in linear light emission, making them unsuitable for display applications.

[0005] Achieving good device processability and stability of the light-emitting transistor through rational design of the device structure, and realizing stable emission of a surface light source, are technical problems to be solved in this technical field. Summary of the Invention

[0006] The present invention provides a surface light source planar light emitting transistor, which includes a source electrode, a drain electrode, and a charge buffer layer disposed under the source electrode or the drain electrode.

[0007] According to an embodiment of the present invention, the surface light source planar light emitting transistor further comprises a semiconductor charge transport layer.

[0008] Preferably, the semiconductor charge transport layer is disposed below the source electrode. In one embodiment of the present invention, the charge buffer layer is disposed above the semiconductor charge transport layer.

[0009] According to an embodiment of the present invention, the transistor further includes a light-emitting unit, and preferably the light-emitting unit is disposed below the drain electrode.

[0010] In one embodiment of the present invention, the charge buffer layer is disposed below the light-emitting unit, hi another embodiment of the present invention, the charge buffer layer is disposed below the source electrode and the light-emitting unit.

[0011] According to an embodiment of the present invention, the charge buffer layer may be disposed between the drain electrode (or source electrode) and the semiconductor charge transport layer, or between the semiconductor charge transport layer and the light-emitting unit.

[0012] According to an embodiment of the present invention, the light-emitting surface (including the light-emitting unit) of the transistor is U-shaped, and the source electrode is located at the opening side of the U-shape.

[0013] According to one embodiment of the present invention, the drain electrode, the light-emitting unit and the charge buffer layer have a U-shaped planar shape, and the source electrode is disposed at the opening of the U-shape.

[0014] According to another embodiment of the present invention, the planar shape of the drain electrode and the light-emitting unit is U-shaped, the source electrode is disposed at the opening side of the U-shape, and preferably the charge buffer layer is disposed below the source electrode.

[0015] Preferably, the surface light source planar light emitting transistor is A support substrate; a gate electrode disposed on a surface of the support substrate; a dielectric layer disposed over the gate electrode; a semiconductor charge transport layer disposed on the dielectric layer; a source electrode and a charge buffer layer disposed over the semiconductor charge transport layer, preferably on different sides of the charge transport layer; The light-emitting element includes a light-emitting unit and a drain electrode disposed in this order on the charge buffer layer.

[0016] Preferably, the surface light source planar light emitting transistor is A support substrate; a gate electrode disposed on a surface of the support substrate; a dielectric layer disposed over the gate electrode; a semiconductor charge transport layer disposed on the dielectric layer; a charge buffer layer disposed on the semiconductor charge transport layer; a source electrode and a light-emitting unit disposed in sequence on the charge buffer layer, preferably on different sides of the charge buffer layer; and a drain electrode disposed on the light-emitting unit.

[0017] It should be noted that when an element such as a layer, film, crystal, region, or substrate is described as being located "on top of another element" / "under another element" or "between two elements," it may be located directly above / below the other element, or there may be one or more intervening layers.

[0018] According to an embodiment of the present invention, the source electrode and the drain electrode are arranged non-planarly, i.e., have a height difference. For example, both the source electrode and the charge buffer layer are located on the semiconductor charge transport layer, and there is optionally a gap or no gap between them, and they are optionally the same or different thicknesses, and the charge buffer layer optionally covers the source electrode or they are independent of each other, the drain electrode is located on the charge buffer layer (the drain electrode may completely or partially cover the charge buffer layer), forming a conductive channel between the drain electrode and the source electrode, and optionally a light-emitting unit is located between the drain electrode and the charge buffer layer, and the light-emitting unit may completely or partially cover the charge buffer layer and / or the source electrode. For example, both the source electrode and the light-emitting unit are disposed on a charge buffer layer, the drain electrode is disposed on the light-emitting unit, forming a conductive channel between the drain electrode and the source electrode, optionally the thicknesses of the source electrode and the light-emitting unit are the same or different, optionally there is or there is not a gap between the light-emitting unit and the source electrode, optionally the light-emitting unit covers the source electrode or both are independent from each other, the light-emitting portion is the entire effective area of ​​the source electrode or the drain electrode, and the gate voltage can adjust the light-emitting brightness.

[0019] According to an embodiment of the present invention, the charge buffer layer and the source electrode may be disposed on different sides of the semiconductor charge transport layer. The inventors have proposed the introduction and location of the charge buffer layer for the first time, and the thickness and area of ​​the charge buffer layer and other layers can be adjusted by those skilled in the art according to actual needs.

[0020] According to an embodiment of the present invention, the material of the semiconductor charge transport layer has good electrical properties, and preferably the mobility of the semiconductor charge transport layer is less than 0.1 cm 2 V -1 s -1 For example, the semiconductor charge transport layer comprises an organic semiconductor material and / or an inorganic semiconductor material, for example, the organic semiconductor material is selected from a small molecule material and / or a polymer material.

[0021] Preferably, the organic semiconductor material is 2,7-dioctyl[1]benzothieno[3,2-b]benzothiophene (C8-BTBT), 2,6-diphenylanthracene (DPA), 2,6-dinaphthylanthracene (dNaAnt), 2,6-di(p-n-hexylbenzene)anthracene (C6-DPA), 2,6-di(p-octylhexylbenzene)anthracene (C8-DPA), 2,6-di(p-decylbenzene)anthracene (C 10 The polymers include, but are not limited to, one or more selected from the group consisting of poly(2,5-(2-octyldodecyl)-3,6-diketopyrrolopyrrole-alt-5,5-(2,5-di(thiophen-2-yl)thieno[3,2-b]thiophene)] (DPP-DTT), poly(3-hexylthiophene) (P3HT), 9,9-di-n-octylfluorene-benzothiadiazole copolymer (F8BT), and poly[2,5-(2-octyldodecyl)-3,6-diketopyrrolopyrrole-alt-5,5-(2,5-di(thiophen-2-yl)thieno[3,2-b]thiophene)] (DPP-DTT), and more preferably C8-BTBT.

[0022] Preferably, the inorganic semiconductor material includes, but is not limited to, one or more selected from the group consisting of carbon nanotubes (CNTs), zinc tin oxide (ZTO), gallium nitride (GaN), silicon carbide (SiC), and zinc selenide (ZnSe).

[0023] According to an embodiment of the present invention, the material of the charge buffer layer has suitable electrical properties, such as one or more materials selected from low-mobility organic materials, metal materials, pnp junctions, etc. Preferably, the low mobility means that the mobility is 2 to 5 orders of magnitude smaller than that of the semiconductor charge transport layer. For example, the charge buffer layer is a layer formed from one or more low-mobility organic materials, such as 4,4'-cyclohexyldi[N,N-di(4-methylphenyl)aniline] (TAPC), N,N'-diphenyl-N,N'-(1-naphthyl)-1,1'-biphenyl-4,4'-diamine (NPB), and polyvinylcarbazole (PVK), more preferably a layer formed from TAPC. For example, the work function of the metal material may be matched to the highest occupied molecular orbital (HOMO) energy level of the light-emitting unit and may be defined in the range of 4.5 eV to 6 eV. Preferably, the charge buffer layer is a layer formed from one or more metal materials such as Au, Ni, Pt, etc., and may be, for example, an ultrathin layer with a thickness of 0.5 to 10 nm, for example, 1 nm, 2 nm, or 3 nm. For example, the charge buffer layer is a layer formed from one or more pnp junctions such as C60-pentacene-C60, C70-tetracene-C70, and C60-tetracene-C70.

[0024] According to an embodiment of the present invention, when the material of the charge buffer layer is a low-mobility organic material or a pnp junction, the thickness of the charge buffer layer is 20 to 80 nm, for example, 30 nm, 40 nm, or 50 nm.

[0025] According to an embodiment of the present invention, the light-emitting unit includes an emitting layer and an electron transport layer, a hole transport layer, an electron injection layer, and / or a hole injection layer whose energy level is matched to that of the emitting layer.

[0026] Furthermore, the light-emitting layer may be a layer formed from a light-emitting material having a light-emitting mechanism known in the art. For example, the light-emitting material may include, but is not limited to, one or more materials selected from fluorescent materials, phosphorescent materials, and thermally activated delayed fluorescent materials.

[0027] Preferably, the fluorescent material is one or more selected from aluminum octahydroxyquinoline (Alq3), 5,6,11,12-tetraphenyltetracene (ie, rubrene), and 4,4'-bis[4-(diphenylamino)styryl]biphenyl (BDAVBi).

[0028] Preferably, the phosphorescent material is one or more selected from tris(2-phenylpyridine)iridium (Ir(ppy)), di(2-phenylpyridine-C2,N)iridium acetylacetonate (Ir(ppy)2(acac)), and iridium(III) tris[N,N'-diphenylbenzimidazol-2-ylidene-C2,C2'] (Ir(dpbic)3).

[0029] Preferably, the thermally activated delayed fluorescent material is one or two selected from 9,9'-(5-(4,6-diphenyl-1,3,5-triazin-2-yl)-1,3-phenylene)bis(9H-carbazole) (DCzTRZ), (N-phenoxazine)phenyl]thiosulfone (PXZ-DPS), and 10-(4-(4,6-diphenyl-1,3,5-triazol-2-yl)phenyl)-9,9-dimethyl-9,10-dihydroacridine (DMAC-TRZ).

[0030] Furthermore, the spectrum of the light emitted from the light emitting unit is 390 nm to 780 nm.

[0031] For example, the light-emitting layer in the above-mentioned light-emitting unit may be a single light-emitting material or a guest-doped host material. In the present invention, "doping" refers to a material in any layer that has different physical properties from the material occupying the largest weight percent of the corresponding layer, added to the material occupying the largest weight percent in an amount of 30% or less. The host material and dopant material in any layer are distinguishable from each other.

[0032] According to an embodiment of the present invention, the single emitting material is preferably Alq3, DPA, or dNaAnt, and the guest doping material in the guest doped host material may be one or more kinds, and the host material may be a single substance or a mixture. The guest doping material is preferably 1,4-bis(10-phenylanthracen-9-yl)benzene (BD-1), BDAVBi, perylene, bisdimethyl-dihydroacridine phenylthiosulfone (DMAC-DPS), di[2-(5-cyano-4,6 iridium(III) bis[(2,3,4-difluorophenyl)pyridine-C2,N]picolinate (FCNirPic), iridium(III) bis[(2,3,4-difluorophenyl)pyridine-N,C2']picolinate (Ir(tfpd)2pic), bis[2,4-dimethyl-6-(4-methyl-2-quinolinyl-κN)phenyl-κC](2,2,6,6-tetramethyl-3,5-heptanedione-κO3 (Ir(mphmq)2tmd), 4,4'-bis[4-(di-p-tolylamino)styryl]biphenyl (DPAVBi), 9,9'-(5-(4,6-difluorophenyl)pyridine-C2,N)picolinate (Ir(tfpd)2pic), bis[2,4-dimethyl-6-(4-methyl-2-quinolinyl-κN)phenyl-κC](2,2,6,6-tetramethyl-3,5-heptanedione-κO3) ... (phenyl-1,3,5-triazin-2-yl)-1,3-benzene)bis(9H-carbazole) (DCzTrz), 5,5-dibromo-4,4-bis(tetradecyl)-2,2-bithiophene (fac-Ir(dpbic)3), tris(2-phenylpyridine)iridium (Ir(ppy)3), tris[2-(p-tolyl)pyridine]iridium(III) (Ir(mppy)3), di(2-phenylpyridine-C2,N)iridium(III) acetylacetonate (Ir(ppy)2(acac)), bis(2-(naphth-2-yl)pyridine )(acetylacetone)iridium(III) (Ir(npy)2acac), tris[2-(3-methyl-2-pyridyl)phenyl]iridium (Ir(3mppy)3), bis(2-(3,5-dimethylphenyl)quinoline-C2,N')(acetylacetone)iridium(III) (Ir(dmpq)2acac), bis(2-(2'-benzothienyl)-pyridine-N,C3')iridium(acetylacetone) (Ir(btp)2(acac)), 4-(dicyanomethylene)-2-methyl-6-[2-(2,3,6,7-tetrahydro-1H,

[0023] The host material is preferably one or more of: 5H-benzo[ij]quinolizin-9-yl)vinyl]-4H-pyran (DCM2), 5,6,11,12-tetraphenyltetracene (i.e., Rubrene), tris(2-(3,5-dimethylphenyl)quinoline-C2,N')iridium(III) (Ir(dmpq)3), 2,8-ditert-butyl-5,11-bis(4-tert-butylphenyl)-6,12-diphenyltetracene (TBRb). or Alq3, 4,4'-bis(N-carbazole)-1,1'-biphenyl (CBP), 4,4'-bis(2,2-diphenyl-ethylene-1-yl)-4,4'-dimethylphenyl (p-DMDPVBi), 4,4'-di(2,2-distyryl)-1,1'-biphenyl (DPVBi), 2-tert-butyl-9,10-di(2-naphthyl)anthracene (TBADN), diphenyl[4-(triphenylsilyl)phenyl]phosphine oxide (TSPO 1), 3-(3-(9H-carbazol-9-yl)phenyl)benzofuran[2,3-b]pyridine (PCz-BFP), 2,4,6-tris[3-(diphenylphosphineoxy)phenyl]-1,3,5-triazole (PO-T2T), 2,4,6-tris(3-(carbazol-9-yl)phenyl)-1,3,5-triazine (TCPZ), 4,4'-bis(triphenylsilyl)-1,1'-biphenyl (BSB), 2,7-bis[9,9-di(4- [4-methylphenyl]-9,9-di(4-methylphenyl)fluoren-2-yl]-9,9-di(4-methylphenyl)fluorene (TDAF), 3',3'',3'''-(1,3,5-triazine-2,4,6-triyl)tris(([1,1'-biphenyl]-3-nitrile)) (CN-T2T), 10-(4-(4,6-diphenyl-1,3,5-triazol-2-yl)phenyl)-9,9-dimethyl-9,10-dihydroacridine (DMAC-TRZ),

[0033] Preferably, the light-emitting unit is a green light-emitting unit 10% Ir(ppy)3:CBP / 3TPYMB, a red light-emitting unit 5% Ir(mphmq)2tmd:CBP / Tmpypb, or a blue light-emitting unit 10% BD-1:CBP / B3pypb, e.g., 20 nm 10% Ir(ppy)3:CBP / 40 nm 3TPYMB, 20 nm 5% Ir(mphmq)2tmd:CBP / 40 nm Tmpypb, or 20 nm 10% BD-1:CBP / 40 nm B3pypb.

[0034] In one embodiment, the light-emitting unit is a white light-emitting unit, such as 2% Rubrene:DMAC-TRZ / 3TPYMB, or such as 30 nm 2% Rubrene:DMAC-TRZ / 40 nm 3TPYMB.

[0035] According to an embodiment of the present invention, the semiconductor charge transport layer, charge buffer layer, and light-emitting unit can be obtained by a processing method useful for charge transport and visible light emission known in the art, including, but not limited to, vacuum thermal evaporation, physical vapor transport, solution shearing, solution epitaxy, spin coating, and inkjet printing. It should be understood by those skilled in the art that the specific method to be used can be specifically selected depending on the physical properties (e.g., solubility, melting point, boiling point, etc.) of the semiconductor material actually used.

[0036] For example, a method for producing an active layer including the semiconductor charge transport layer, the charge buffer layer, and the light-emitting unit may include the following steps: Method 1: depositing a thin film of the small molecule material on the dielectric layer and the electrode by vacuum deposition in a deposition chamber to obtain an active layer; Method 2: spin-coating a solution of an active layer material onto the dielectric layer and the electrode by spin-coating to obtain an active layer; Method 3: Preparation and growth of single crystal thin film of the small molecule material by solution epitaxial growth method: dissolving the small molecule material in a solvent that is incompatible with water, slowly dripping the obtained homogeneous mixed solution onto the water surface, spreading the mixed solution on the water surface, and volatilizing the solvent therein to obtain the single crystal thin film, inserting a support substrate with a dielectric layer into water, and transferring the single crystal thin film onto the surface of the dielectric layer to obtain an active layer; Method 4: preparing a single crystal thin film of the small molecule material by solution shearing method: dissolving the small molecule material in an organic solvent, dropping the resulting homogeneous mixed solution onto a support substrate having a dielectric layer, and then gradually shearing and stretching the dropped solution to form an active layer; The method may be any one of the methods selected from the above.

[0037] Charges are injected from one electrode (e.g., a source electrode) of the semiconductor charge transport layer, and are transported to the other end in an extremely thin conductive channel formed under the application of a gate voltage. Through the action of the charge buffer layer, a relatively uniform current is injected below the other electrode (e.g., a drain electrode), where they recombine with electrons injected from the drain electrode, forming a uniform surface light source that is then emitted.

[0038] According to an embodiment of the present invention, the thickness of each of the semiconductor charge transport layer, charge buffer layer, and light-emitting unit is on the order of nanometers to submicrons, and for example, the thickness of each layer may be independently 5 to 500 nm, for example, 10 to 100 nm.

[0039] According to an embodiment of the present invention, the number of light-emitting components (referring to charge buffer layers and light-emitting units) is at least one, for example, two, three, or more. When the number of light-emitting components is two, three, or more, the charge buffer layers and light-emitting units therein are optionally the same or different. Each light-emitting component is connected by a charge generation layer (CGL).

[0040] According to an embodiment of the present invention, the source electrode, drain electrode, and gate electrode of the surface light source planar light-emitting transistor may be transparent or non-transparent, and may be made of, independently of one another, metals such as magnesium, calcium, sodium, potassium, titanium, indium, yttrium, lithium, gadolinium, aluminum, silver, tin, nickel, gold, molybdenum, iron, and lead, alloys of the above metals, multilayer materials such as LiF / Al, LiO / Al, or LiF / Al / Ag, and ITO, IZO, MoO x The semiconductor material may be, but is not limited to, one or more selected from the group consisting of metal oxides such as silicon dioxide, silicon dioxide, and highly doped silicon. It should be understood by those skilled in the art that the type of metal specifically selected can be adjusted depending on the energy level of the semiconductor material.

[0041] According to an embodiment of the present invention, the source electrode, the drain electrode, and the gate electrode are fabricated by a method known in the art, such as at least one of a vacuum thermal evaporation method, an inkjet printing method, and an electron beam deposition method.

[0042] According to an embodiment of the present invention, the type of the dielectric layer is not particularly limited and may be an inorganic material dielectric layer and / or an organic material dielectric layer. Illustratively, the dielectric layer may be an inorganic material dielectric layer, for example, a dielectric layer formed from an inorganic oxide (Al2O3, SiO2), and / or an organic material dielectric layer, for example, a dielectric layer formed from polymethyl methacrylate (PMMA).

[0043] According to an embodiment of the present invention, the dielectric layer can be manufactured by a method known in the art, such as at least one of a thermal growth method, a physical vapor deposition method, and a spin coating method.

[0044] According to an embodiment of the present invention, the thickness of the dielectric layer is not particularly limited. For example, the thickness of the dielectric layer is 10 to 800 nm. Those skilled in the art can adjust the thickness of the dielectric layer according to actual needs.

[0045] According to an embodiment of the present invention, the support substrate is a rigid substrate (such as a silicon dioxide wafer, glass or quartz) or a flexible substrate (such as PC, PMMA, PDMS).

[0046] According to an embodiment of the present invention, the surface light source planar light emitting transistor can use a top-emitting or bottom-emitting device structure.

[0047] According to an embodiment of the present invention, the surface light source planar light emitting transistor can emit a surface light that matches the color of the light emitting unit under the application of a voltage.

[0048] The present invention further provides a method for manufacturing a planar light-emitting transistor emitted from the above-mentioned surface light source, which includes a step of installing a charge buffer layer under the drain electrode or the source electrode, wherein the drain electrode, the source electrode and the charge buffer layer all have the above-mentioned meanings.

[0049] According to an embodiment of the present invention, the manufacturing method includes the step of providing a charge buffer layer between the drain electrode (or source electrode) and the semiconductor charge transport layer, or providing a charge buffer layer between the semiconductor charge transport layer and the light-emitting unit; The drain electrode, source electrode, semiconductor charge transport layer, light-emitting unit and charge buffer layer all have the same meanings as above.

[0050] Preferably, the structure comprising the semiconductor charge transport layer, the charge buffer layer and the light-emitting unit is referred to as an active layer, and the active layer is produced by the method described above.

[0051] The transistor device according to the present invention and low temperature manufacturing processes, such as solution processing processes (inkjet printing, electrogas atomization, roll-to-roll, etc.) have very good compatibility.

[0052] The present invention further provides an application of the planar light-emitting transistor emitted from the above surface light source in a wearable device.

[0053] The present invention further provides applications of the planar light emitting transistor emitted from the surface light source in fields such as illumination display, optical communication or new optoelectronic integration, etc. For example, another related application field of the above is laser, etc.

[0054] The present invention further provides an application of the planar light emitting transistor emitted from the above surface light source in the field of illumination such as white light illumination.

[0055] The planar light-emitting transistor emitted from the surface light source may be a transistor including one light-emitting component, or may be a series transistor including at least two light-emitting components. Beneficial effects of the present invention: Most conventional planar light-emitting transistors emit linear or band-like light, failing to provide a good surface light source. To overcome the drawbacks of conventional light-emitting transistors, the present invention proposes a light-emitting transistor with a charge buffer layer. The present inventors have found that by inserting a charge buffer layer under the source or drain electrode, between the drain electrode (or source electrode) and the semiconductor charge transport layer, or between the charge transport layer and the light-emitting unit, the current density can be redistributed in the transistor, and the fabricated planar light-emitting transistor can achieve stable surface light source emission and provide uniform RGB region emission. At the same time, the gate electrode has good tunability (on / off ratio 10 6 ), has high loop stability and arbitrary adjustability, and has a high aperture ratio that can be adjusted according to actual needs, for example, from 10% or more in the conventional technology to 94% or more. Due to the flexible characteristics of organic semiconductors, they can be integrated with wearable devices, which is more advantageous for expanding the functions and application scenarios of wearable surface light source light-emitting devices.

[0056] 1. The planar light emitting transistor device according to the present invention can realize a planar light source emission that is not affected by the gate voltage, which is useful for the application of the device in the display field.

[0057] 2. The planar light-emitting transistor device of the present invention can realize the construction of an electroluminescent device with a high aperture ratio and can be well compatible with flexible and wearable devices, which plays an important role in promoting the development of light-emitting transistor devices.

[0058] 3. By developing a light-emitting transistor device that emits light from an area light source based on organic semiconductors, the present invention maximizes the advantages of organic semiconductor material systems, which are abundant, lightweight, inexpensive, and easy to process, and provides an efficient solution for the controllable fabrication of large areas and arrays of light-emitting transistor devices.

[0059] The "aperture ratio" refers to the percentage of the area of ​​the light-emitting surface that occupies the sum of the areas of the light-emitting surface and the aperture. By adjusting the area occupancy ratio of the light-emitting surface, a range of aperture ratios (e.g., aperture ratios of 10%, 15%, 20%, 30%, 40%, 50%, 60%, 70%, 80%, 82%, 85%, 88%, 90%, and 94%) can be obtained. [Brief explanation of the drawings]

[0060] [Figure 1-1] 1 is a structural schematic diagram of a light-emitting transistor device emitted from a surface light source manufactured in Examples 1 to 4. FIG. [Figure 1-2] 1 is a structural schematic diagram of a light-emitting transistor device emitted from a surface light source manufactured in Example 5. FIG. [Figure 2-1] 1A to 1C are optical microscope photographs of the surface light source emission of the planar light-emitting transistor devices of the primary colors red, green, and blue fabricated in Examples 1, 2, and 3, respectively. [Figure 2-2]1A shows a typical transition curve, FIG. 1B shows an output curve, FIG. 1C shows an emission spectrum of the green planar light-emitting transistor device fabricated in Example 1. FIG. [Figure 3] 10 shows an optical photograph of a device and an optical photograph of light emission of a planar light-emitting transistor in Example 4, which emits light from a surface light source with a high aperture ratio. [Figure 4] 10 shows a typical transition curve and emission spectrum of a planar light-emitting transistor emitted from a surface light source with a high aperture ratio in Example 4. [Figure 5] 10 is a structural schematic diagram of a planar light-emitting series transistor emitted from a surface light source including three light-emitting components in Example 8. FIG. [Figure 6] 10 shows a structural schematic diagram (left) and an optical photograph (right, scale 0.2 mm) of a light-emitting transistor device emitting light from a surface light source manufactured in Example 9. [Figure 7] 10 shows a relationship curve (left) of source-drain current-luminance-gate voltage for the device of Example 9, and a relationship graph (right) of external quantum efficiency (EQE) and luminance. [Figure 8] 10 shows luminescence photographs of the device of Example 9 at gate voltages of −5 V, −6 V, and −20 V. DETAILED DESCRIPTION OF THE INVENTION

[0061] The present invention will be further described below with reference to specific examples. Note that these examples are merely for the purpose of illustrating the present invention and do not limit the scope of the claims of the present invention. Furthermore, after reading the contents disclosed in the present invention, those skilled in the art may make various changes and modifications to the present invention, and it should be understood that equivalent forms thereof are also included in the scope of the claims limited by the present invention.

[0062] Unless otherwise specified, the experimental methods used in the following examples are all conventional methods, and the reagents, materials, etc. used in the following examples are all commercially available unless otherwise specified.

[0063] Example 1 Planar light-emitting transistor device emitting from an area light source based on a CBP:Ir(ppy)3 green light-emitting unit 1) Si / SiO2 wafer cleaning and aqueous layer modification: Before use, silicon wafers with SiO2 oxide layers were first cleaned with a 1:2 volume ratio of hydrogen peroxide and concentrated sulfuric acid (heated in an electric furnace and boiled for 15 minutes). They were then ultrasonically treated with deionized water, acetone, and isopropanol, each for approximately 10 minutes, and then rapidly dried with nitrogen gas. The surface energy levels were modified in an O2plasma plasma cleaner for 5 minutes to remove residual organic solvents. The wafers were then dried in a dry box at 90°C for 90 minutes. Finally, a drop of octadecyltrichlorosilane (OTS) was placed in a capillary tube and placed in the center of a Petri dish containing the silicon wafer. The Petri dish was then heated in a dry box at 120°C for 120 minutes, then allowed to cool naturally.

[0064] 2) Preparation of the organic charge transport layer (i.e., semiconductor charge transport layer) C8-BTBT A patterned metal mask plate was fixed to the substrate, and 50 nm of C8-BTBT was thermally evaporated onto the Si / SiO2 wafer modified in step 1 using a vacuum evaporator. After the evaporation was completed, the wafer was immediately annealed at a temperature of 45°C for 20 minutes.

[0065] 3) Fabrication of the source electrode The mask plate was replaced and fixed to the substrate, and a 2 nm MoO film was deposited on one side of the organic charge transport layer using a vacuum deposition machine. x and 40 nm of Au was thermally evaporated.

[0066] 4) Preparation of charge buffer layer and light-emitting unit: The mask plate was replaced and fixed to the substrate, and a charge buffer layer of 40 nm TAPC and a light-emitting unit of 20 nm 10% Ir(ppy)3:CBP / 40 nm 3TPYMB were sequentially deposited on the other side of the organic charge transport layer using a vacuum deposition machine.

[0067] 5) Fabrication of the drain electrode: The mask plate was replaced and fixed to the substrate, and a vacuum deposition machine was used to deposit 0.5 nm LiF / 1 nm Al / 35 nm Ag as the drain electrode on the light-emitting unit in this order. The device fabrication was completed, and the device structure is shown in Figure 1.

[0068] 6) Performance testing and characterization of light-emitting transistors: In a nitrogen gas atmosphere in a glove box, a probe was used to apply voltages to the source, drain, and gate electrodes. The gate electrode was heavily doped silicon, and the source electrode was grounded. The voltage between the source and drain electrodes was -70 V. The voltage between the gate and source electrodes was varied from 20 V to -70 V with a step width of -2 V. In a dark environment, a photomultiplier tube was used to measure the photocurrent of the device in 0.5 V steps, and the current-photocurrent-voltage relationship curve was obtained. The device spectrum was measured using a spectrometer, and emission photographs were collected using a CCD.

[0069] Example 2 Planar light-emitting transistor device emitting from an area light source based on CBP:Ir(mphmq)2tmd red light-emitting units 1) Si / SiO2 wafer cleaning and aqueous layer modification: Before use, silicon wafers with SiO2 oxide layers were first cleaned with a 1:2 volume ratio of hydrogen peroxide and concentrated sulfuric acid (heated in an electric furnace and boiled for 15 minutes). They were then ultrasonically treated with deionized water, acetone, and isopropanol, each for approximately 10 minutes, and then rapidly dried with nitrogen gas. The surface energy levels were modified in an O2plasma plasma cleaner for 5 minutes to remove residual organic solvents. The wafers were then dried in a dry box at 90°C for 90 minutes. Finally, a drop of octadecyltrichlorosilane (OTS) was placed in a capillary tube and placed in the center of a Petri dish containing the silicon wafer. The Petri dish was then heated in a dry box at 120°C for 120 minutes, then allowed to cool naturally.

[0070] 2) Preparation of the organic charge transport layer (i.e., semiconductor charge transport layer) C8-BTBT A patterned metal mask plate was fixed to the substrate, and 50 nm of C8-BTBT was thermally evaporated onto the Si / SiO2 wafer modified in step 1 using a vacuum evaporator. After the evaporation was completed, the wafer was immediately annealed at a temperature of 45°C for 20 minutes.

[0071] 3) Fabrication of the source electrode The mask plate was replaced and fixed to the substrate, and a 2 nm MoO film was deposited on one side of the organic charge transport layer using a vacuum deposition machine. x and 40 nm of Au was thermally evaporated.

[0072] 4) Preparation of charge buffer layer and light-emitting unit The mask plate was replaced and fixed to the substrate, and a charge buffer layer of 40 nm TAPC and a light-emitting unit of 20 nm 5% Ir(mphmq)2tmd:CBP / 40 nm Tmpypb were sequentially deposited on the other side of the organic charge transport layer using a vacuum deposition machine.

[0073] 5) Fabrication of the drain electrode The mask plate was replaced and fixed to the substrate, and a vacuum deposition machine was used to deposit 0.5 nm LiF / 1 nm Al / 35 nm Ag as the drain electrode on the light-emitting unit in this order. The device fabrication was completed, and the device structure is shown in Figure 1.

[0074] 6) Performance testing and characterization of light-emitting transistors: In a nitrogen gas atmosphere in a glove box, a probe was used to apply voltages to the source, drain, and gate electrodes. The gate electrode was heavily doped silicon, and the source electrode was grounded. The voltage between the source and drain electrodes was -70 V. The voltage between the gate and source electrodes was varied from 20 V to -70 V with a step width of -2 V. In a dark environment, a photomultiplier tube was used to measure the photocurrent of the device in 0.5 V steps, and the current-photocurrent-voltage relationship curve was obtained. The device spectrum was measured using a spectrometer, and emission photographs were collected using a CCD.

[0075] Example 3 Planar Light-Emitting Transistor Device Emitted from an Area Light Source Based on CBP:BD-1 Blue Light-Emitting Unit 1) Si / SiO2 wafer cleaning and aqueous layer modification: Before use, silicon wafers with SiO2 oxide layers were first cleaned with a 1:2 volume ratio of hydrogen peroxide and concentrated sulfuric acid (heated in an electric furnace and boiled for 15 minutes). They were then ultrasonically treated with deionized water, acetone, and isopropanol, each for approximately 10 minutes, and then rapidly dried with nitrogen gas. The surface energy levels were modified in an O2plasma plasma cleaner for 5 minutes to remove residual organic solvents. The wafers were then dried in a dry box at 90°C for 90 minutes. Finally, a drop of octadecyltrichlorosilane (OTS) was placed in a capillary tube and placed in the center of a Petri dish containing the silicon wafer. The Petri dish was then heated in a dry box at 120°C for 120 minutes, then allowed to cool naturally.

[0076] 2) Preparation of the organic charge transport layer (i.e., semiconductor charge transport layer) C8-BTBT A patterned metal mask plate was fixed to the substrate, and 50 nm of C8-BTBT was thermally evaporated onto the Si / SiO2 wafer modified in step 1 using a vacuum evaporator. After the evaporation was completed, the wafer was immediately annealed at a temperature of 45°C for 20 minutes.

[0077] 3) Fabrication of the source electrode The mask plate was replaced and fixed to the substrate, and a 2 nm MoO film was deposited on one side of the organic charge transport layer using a vacuum deposition machine. x and 40 nm of Au was thermally evaporated.

[0078] 4) Preparation of charge buffer layer and light-emitting unit: The mask plate was replaced and fixed to the substrate, and a charge buffer layer of 40 nm TAPC and a light-emitting unit of 20 nm 10% BD-1:CBP / 40 nm B3pypb were sequentially deposited on the other side of the organic charge transport layer by a vacuum deposition machine.

[0079] 5) Fabrication of the drain electrode: The mask plate was replaced and fixed to the substrate, and a vacuum deposition machine was used to deposit 0.5 nm LiF / 1 nm Al / 35 nm Ag as the drain electrode on the light-emitting unit in this order. The device fabrication was completed, and the device structure is shown in Figure 1.

[0080] 6) Performance testing and characterization of light-emitting transistors: In a nitrogen gas atmosphere in a glove box, a probe was used to apply voltages to the source, drain, and gate electrodes. The gate electrode was heavily doped silicon, and the source electrode was grounded. The voltage between the source and drain electrodes was -70 V. The voltage between the gate and source electrodes was varied from 20 V to -70 V with a step width of -2 V. In a dark environment, a photomultiplier tube was used to measure the photocurrent of the device in 0.5 V steps, and the current-photocurrent-voltage relationship curve was obtained. The device spectrum was measured using a spectrometer, and emission photographs were collected using a CCD.

[0081] Figure 2-1 shows optical microscope photographs of the surface light source emission under dark field for the red, green, and blue planar light-emitting field-effect transistor devices fabricated in Examples 1, 2, and 3, respectively. The emission colors from left to right are red, green, and blue, respectively, and all of them achieved surface light source emission. Figure 2-2 shows the typical transition curve, output curve, and emission spectrum of the green planar light-emitting field-effect transistor device fabricated in Example 1, which demonstrates the good gate voltage control characteristics of the transistor device (on / off ratio 10 6 ) and luminescence performance.

[0082] Example 4 High aperture ratio planar light-emitting transistor device emitting from a surface light source based on a CBP:Ir(ppy)3 green light-emitting unit 1) Si / SiO2 wafer cleaning and aqueous layer modification: Before use, silicon wafers with SiO2 oxide layers were first cleaned with a 1:2 volume ratio of hydrogen peroxide and concentrated sulfuric acid (heated in an electric furnace and boiled for 15 minutes). They were then ultrasonically treated with deionized water, acetone, and isopropanol, each for approximately 10 minutes, and then rapidly dried with nitrogen gas. The surface energy levels were modified in an O2plasma plasma cleaner for 5 minutes to remove residual organic solvents. The wafers were then dried in a dry box at 90°C for 90 minutes. Finally, a drop of octadecyltrichlorosilane (OTS) was placed in a capillary tube and placed in the center of a Petri dish containing the silicon wafer. The Petri dish was then heated in a dry box at 120°C for 120 minutes, then allowed to cool naturally.

[0083] 2) Preparation of organic charge transport layer C8-BTBT A patterned metal mask plate was fixed to the substrate, and 50 nm of C8-BTBT was thermally evaporated onto the Si / SiO2 wafer modified in step 1 using a vacuum evaporator. After the evaporation was completed, the wafer was immediately annealed at a temperature of 45°C for 20 minutes.

[0084] 3) Fabrication of the source electrode The mask plate was replaced and fixed to the substrate, and a 2 nm MoO film was deposited on one side of the organic charge transport layer using a vacuum deposition machine. x and 40 nm of Au was thermally evaporated.

[0085] 4) Preparation of charge buffer layer and light-emitting unit: The mask plate was replaced and fixed to the substrate, and a charge buffer layer of 40 nm TAPC and a light-emitting unit of 20 nm 10% Ir(ppy)3:CBP / 40 nm 3TPYMB were sequentially deposited on the other side of the organic charge transport layer using a vacuum deposition machine.

[0086] 5) Fabrication of the drain electrode: The mask plate was replaced and fixed to the substrate, and 0.5 nm LiF / 1 nm Al / 35 nm Ag were sequentially deposited on the light-emitting unit as the drain electrode using a vacuum evaporator. The device fabrication was completed, and the device structure is shown in Figure 1. The optical photograph (left) and optical photograph (right) of the resulting device are shown in Figure 3.

[0087] 6) Performance testing and characterization of light-emitting transistors: In a nitrogen gas glovebox, a probe was used to apply voltages to the source, drain, and gate electrodes. The gate electrode was heavily doped silicon, the source electrode was grounded, and the voltage between the source and drain electrodes was -70 V. The voltage between the gate and source electrodes was varied from 20 V to -70 V with a step width of -2 V. In a dark environment, a photomultiplier tube was used to measure the photocurrent and the current-photocurrent-voltage relationship. A spectrometer was used to measure the device spectrum, and a CCD was used to collect bright-field and dark-field emission photographs of the device. The test results, shown in Figure 4, indicate that increasing the light-emitting area can improve the aperture ratio (approximately 90%) while still achieving relatively good surface light source effect and emission brightness. This demonstrates that planar light-emitting transistors emitting from such surface light sources can be used to construct high-aperture devices.

[0088] Example 5 Referring to the transistor fabrication process of Example 4, the difference from Example 4 is that in this example, a semiconductor charge transport layer is first deposited on the modified Si / SiO2 wafer, followed by deposition of a charge buffer layer. After that, a source electrode and a light-emitting unit, each located on one side of the charge buffer layer, are deposited on the charge buffer layer, and finally a drain electrode is deposited on the light-emitting unit. The specific structure is shown in Figures 1-2. Tests have shown that the transistor device obtained in this example also has good gate voltage adjustment characteristics, light-emitting performance, a large aperture ratio (aperture ratio reaching at least 80%), and stability.

[0089] Examples 6-7 The transistors of Examples 6 and 7 were fabricated by replacing the TAPC in Example 4 with an ultrathin metal material Au as the charge buffer layer, or by replacing the TAPC in Example 4 with C60-pentacene-C60 as the charge buffer layer. These transistors had the same or similar performance as Example 4, i.e., they were planar light-emitting transistors that could emit light from a surface light source, and had good gate voltage adjustment characteristics, light-emitting performance, and stability.

[0090] Example 8 5, the device of this example included a source electrode, an organic charge transport layer C8-BTBT, a charge buffer layer TAPC, a blue light-emitting unit BD-1:CBP / TmPTPB, a second light-emitting unit TAPC, a green light-emitting unit Ir(ppy)3:CBP / 3TPYMB, a charge buffer layer TAPC, and a red light-emitting unit Ir(mphmq)2tmd:CBP / Tmpypb, and a drain electrode LiF / Al / Ag. The light-emitting components were connected by a CGL layer.

[0091] Example 9 Planar light-emitting field-effect transistor device emitting from an area light source based on DMAC-TRZ:Rubrene white light-emitting units 1) Glass / Indium Tin Oxide (ITO) Wafer Cleaning and Dielectric Layer Fabrication: Before use, the glass sheet with the ITO layer was ultrasonically treated with deionized water, acetone, and isopropanol, respectively, for approximately 10 minutes, and then quickly dried with nitrogen gas. The surface energy level was modified in an O2plasma plasma cleaner for 5 minutes to remove any remaining organic solvents on the surface.

[0092] PVA powder (average M w ≒205,000 g mol -1) was dissolved in deionized water (58 mg mL-1), and the solution was stirred at 800 rpm for 6 h. Glutaraldehyde (GA, 50 wt%) was then added to the solution (volume ratio 1:80). The prepared PVA solution was spin-coated onto a glass / ITO substrate (4200 rpm × 45 s) to obtain a 350 nm-thick thin film. The thin film was then annealed in air at 100 °C for 90 min. A layer of perfluororesin CYTOP (CTL-809M, M-type) (approximately 10 nm thick) was then spin-coated onto the PVA layer and annealed at 100 °C for 30 min.

[0093] 2) Preparation of organic charge transport layer C8-BTBT A patterned metal mask plate was fixed to the substrate, and 50 nm of C8-BTBT was thermally evaporated onto the glass / ITO / dielectric layer using a vacuum evaporator.

[0094] 3) Fabrication of the source electrode The mask plate was replaced and fixed to the substrate, and a 2 nm MoO was deposited on the glass / ITO / dielectric layer / C8-BTBT using a vacuum deposition machine. x and 40 nm of Au was thermally evaporated.

[0095] 4) Preparation of charge buffer layer and light-emitting unit: The mask plate was replaced and fixed to the substrate, and a vacuum deposition machine was used to form a glass / ITO / dielectric layer / C8-BTBT / MoO x On the / Au, a 40 nm TAPC charge buffer layer and a light-emitting unit 30 nm 2% Rubrene:DMAC-TRZ / 40 nm 3TPYMB were deposited.

[0096] 5) Fabrication of the drain electrode: The mask plate was replaced and fixed to the substrate, and a vacuum deposition machine was used to form a glass / ITO / dielectric layer / C8-BTBT / MoO x The drain electrode was then deposited on the Au / TAPC / 2% Rubrene:DMAC-TRZ / 40 nm 3TPYMB, followed by 2 nm LiF and 120 nm Al. The device fabrication was completed, and the device structure schematic (left) and optical photograph (right) are shown in Figure 6.

[0097] 6) Performance testing and characterization of light-emitting field-effect transistors: In a nitrogen gas atmosphere in a glovebox, a probe was used to apply voltages to the source, drain, and gate electrodes, respectively. The gate electrode was made of ITO, and the source electrode was grounded. The voltage between the source and drain electrodes was -20 V. The voltage between the gate and source electrodes was varied from 0 V to -20 V with a step width of -1 V. The device photocurrent was measured using a photomultiplier tube in a dark environment in 0.5 V steps. The current-photocurrent-voltage relationship curve was measured, and the relationship between the external quantum efficiency (EQE) and luminance was calculated. As shown in Figure 7, the device achieved a maximum luminance of 1121 nits, with a high maximum EQE of 6.9%. Photographs of the device were taken using a mobile phone camera. Photographs of the device at gate voltages of -5 V, -6 V, and -20 V are shown in Figure 8. They demonstrate uniform white light emission, which is significant for the application of light-emitting transistors in lighting applications.

[0098] Although the embodiments of the present invention have been described above, the present invention is not limited to the above embodiments. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention are intended to be included within the scope of the claims of the present invention.

Claims

1. A surface light source planar light emitting transistor, comprising a source electrode, a drain electrode, a charge buffer layer, a semiconductor charge transport layer, and a light-emitting unit; the semiconductor charge transport layer is disposed below the source electrode; The light-emitting unit is disposed under the drain electrode; the charge buffer layer is disposed between the drain electrode and the semiconductor charge transport layer, or between the source electrode and the semiconductor charge transport layer, or between the semiconductor charge transport layer and the light-emitting unit; the charge buffer layer is a layer formed from one or more of low-mobility organic materials 4,4'-cyclohexyldi[N,N-di(4-methylphenyl)aniline] (TAPC), N,N'-diphenyl-N,N'-(1-naphthyl)-1,1'-biphenyl-4,4'-diamine (NPB) and PVK; alternatively, the charge buffer layer is a layer formed from one or more of metal materials Au, Ni and Pt; or alternatively, the charge buffer layer is a layer formed from one or more of C60-pentacene-C60, C70-tetracene-C70 and C60-tetracene-C70 among pnp junctions; A surface light source planar light emitting transistor characterized by:

2. The surface light source planar light-emitting transistor is A support substrate; a gate electrode disposed on a surface of the support substrate; a dielectric layer disposed over the gate electrode; a semiconductor charge transport layer disposed on the dielectric layer; a source electrode and a charge buffer layer disposed on the semiconductor charge transport layer and disposed on different sides of the semiconductor charge transport layer; a light-emitting unit and a drain electrode disposed in sequence on the charge buffer layer; or The surface light source planar light emitting transistor is A support substrate; a gate electrode disposed on a surface of the support substrate; a dielectric layer disposed over the gate electrode; a semiconductor charge transport layer disposed on the dielectric layer; a charge buffer layer disposed on the semiconductor charge transport layer; a source electrode and a light-emitting unit disposed on the charge buffer layer in order, the source electrode and the light-emitting unit being disposed on different sides of the charge buffer layer; a drain electrode disposed on the light-emitting unit; The source electrode and the drain electrode are arranged in a non-planar manner, and the light-emitting part is the entire effective area of ​​the source electrode or the drain electrode, and the gate voltage is used to adjust the light-emitting brightness.

2. The surface light source flat light emitting transistor according to claim 1.

3. The mobility of the semiconductor charge transport layer is 0.1 cm 2 V -1 s -1 That's all, the semiconducting charge transport layer comprises an organic semiconductor material and / or an inorganic semiconductor material; The organic semiconductor material is 2,7-dioctyl[1]benzothieno[3,2-b]benzothiophene (C 8 -BTBT), 2,6-diphenylanthracene (DPA), 2,6-dinaphthylanthracene (dNaAnt), 2,6-di(pn-hexylbenzene)anthracene (C 6 -DPA), 2,6-di(p-octylhexylbenzene)anthracene (C 8 -DPA), 2,6-di(p-decylbenzene)anthracene (C 10 -DPA), poly(3-hexylthiophene) (P3HT), 9,9-di-n-octylfluorene-benzothiadiazole copolymer (F8BT), poly[2,5-(2-octyldodecyl)-3,6-diketopyrrolopyrrole-alt-5,5-(2,5-di(thiophen-2-yl)thieno[3,2-b]thiophene)] (DPP-DTT), The inorganic semiconductor material includes one or more selected from the group consisting of carbon nanotubes (CNTs), zinc tin oxide (ZTO), gallium nitride (GaN), silicon carbide (SiC), and zinc selenide (ZnSe); 2. The surface light source flat light emitting transistor according to claim 1.

4. The charge buffer layer is a layer formed from 4,4'-cyclohexyldi[N,N-di(4-methylphenyl)aniline] (TAPC), or the charge buffer layer is a layer formed from Au, or the charge buffer layer is a layer formed from C60-pentacene-C60.

2. The surface light source flat light emitting transistor according to claim 1.

5. the light-emitting unit includes an emitting layer and an electron transport layer, a hole transport layer, an electron injection layer, and / or a hole injection layer whose energy level is matched to that of the emitting layer; Furthermore, the light-emitting layer is a layer formed from a light-emitting material, and the light-emitting material includes one or more materials selected from a fluorescent material, a phosphorescent material, and a thermally activated delayed fluorescent material; The fluorescent material is aluminum octahydroxyquinoline (Alq 3 ), 5,6,11,12-tetraphenyltetracene, and 4,4'-bis[4-(diphenylamino)styryl]biphenyl (BDAVBi), The phosphorescent material is tris(2-phenylpyridine)iridium (Ir(ppy) 3 ), di(2-phenylpyridine-C2,N)iridium acetylacetonate (Ir(ppy) 2 (acac)) and iridium(III) tris[N,N'-diphenylbenzimidazol-2-ylidene-C2,C2'] (Ir(dpbic) 3 ) one or more selected from the thermally activated delayed fluorescent material is one or two selected from 9,9'-(5-(4,6-diphenyl-1,3,5-triazin-2-yl)-1,3-phenylene)bis(9H-carbazole) (DCzTRZ), (N-phenoxazine)phenyl]thiosulfone (PXZ-DPS), and 10-(4-(4,6-diphenyl-1,3,5-triazol-2-yl)phenyl)-9,9-dimethyl-9,10-dihydroacridine (DMAC-TRZ); 2. The surface light source flat light emitting transistor according to claim 1.

6. the spectrum of light emitted from the light-emitting unit is between 390 nm and 780 nm; The light-emitting layer in the light-emitting unit is formed from a single light-emitting material or a guest-doped host material; The single luminescent material is Alq 3 , DPA, dNaAnt, and the guest doping materials in the guest-doped host material are 1,4-bis(10-phenylanthracen-9-yl)benzene (BD-1), BDAVBi, perylene, bisdimethyl-dihydroacridine phenylthiosulfone (DMAC-DPS), di[2-(5-cyano-4,6-difluorophenyl)pyridine-C2,N)]picolinatoiridium (FCNirPic), iridium(III) bis[(2,3,4-difluorophenyl)-pyridine-N,C2′]picolinate (Ir(tfpd) 2 pic), bis[2,4-dimethyl-6-(4-methyl-2-quinolinyl-κN)phenyl-κC](2,2,6,6-tetramethyl-3,5-heptanedione-κO 3 (Ir(mphmq) 2 tmd), 4,4'-bis[4-(di-p-tolylamino)styryl]biphenyl (DPAVBi), 9,9'-(5-(4,6-diphenyl-1,3,5-triazin-2-yl)-1,3-benzene)bis(9H-carbazole) (DCzTrz), 5,5-dibromo-4,4-bis(tetradecyl)-2,2-bithiophene (fac-Ir(dpbic) 3 ), tris(2-phenylpyridine)iridium (Ir(ppy) 3 ), tris[2-(p-tolyl)pyridine]iridium(III) (Ir(mppy) 3 ), di(2-phenylpyridine-C2,N)iridium(III) acetylacetonate (Ir(ppy) 2 (acac)), bis(2-(naphth-2-yl)pyridine)(acetylacetone)iridium(III) (Ir(npy) 2 acac), tris[2-(3-methyl-2-pyridyl)phenyl]iridium (Ir(3mppy) 3 ), bis(2-(3,5-dimethylphenyl)quinoline-C2,N')(acetylacetone)iridium(III) (Ir(dmpq) 2 acac), bis(2-(2'-benzothienyl)-pyridine-N,C3')iridium(acetylacetone) (Ir(btp) 2 (acac)), 4-(dicyanomethylene)-2-methyl-6-[2-(2,3,6,7-tetrahydro-1H,5H-benzo[ij]quinolizin-9-yl)vinyl]-4H-pyran (DCM2), 5,6,11,12-tetraphenyltetracene, tris(2-(3,5-dimethylphenyl)quinoline-C2,N')iridium(III) (Ir(dmpq) 3 ), 2,8-ditert-butyl-5,11-bis(4-tert-butylphenyl)-6,12-diphenyltetracene (TBRb), 10-(4-(4,6-diphenyl-1,3,5-triazol-2-yl)phenyl)-9,9-dimethyl-9,10-dihydroacridine (DMAC-TRZ), The host material is Alq 3 , 4,4'-bis(N-carbazole)-1,1'-biphenyl (CBP), 4,4'-bis(2,2-diphenyl-ethylene-1-yl)-4,4'-dimethylphenyl (p-DMDPVBi), 4,4'-di(2,2-distyryl)-1,1'-biphenyl (DPVBi), 2-tert-butyl-9,10-di(2-naphthyl)anthracene (TBADN), diphenyl[4-(triphenylsilyl)phenyl]phosphine oxide (TSPO1), 3-(3-(9H-carbazol-9-yl)phenyl)benzofuran[2,3-b]pyridine (PCz-BFP), 2,4,6-tris[3-(diphenylphosphineoxy)phenyl]-1,3,5-triazole (PO-T2T ... one or more of the following substances: tris(3-(carbazol-9-yl)phenyl)-1,3,5-triazine (TCPZ), 4,4'-bis(triphenylsilyl)-1,1'-biphenyl (BSB), 2,7-bis[9,9-di(4-methylphenyl)-fluoren-2-yl]-9,9-di(4-methylphenyl)fluorene (TDAF), 3',3'',3'''-(1,3,5-triazine-2,4,6-triyl)tris(([1,1'-biphenyl]-3-nitrile)) (CN-T2T); 2. The surface light source flat light emitting transistor according to claim 1.

7. the thickness of the semiconductor charge transport layer, the charge buffer layer, and the light-emitting unit is on the order of nanometers to submicrons; 2. The surface light source flat light emitting transistor according to claim 1.

8. The surface light source planar light emitting transistor emits a surface light that matches the color of the light emitting unit under voltage application, and / or uses a top-emitting or bottom-emitting device structure; 8. The surface light source flat light emitting transistor according to claim 7.

9. A method for manufacturing the surface light source flat light-emitting transistor according to any one of claims 1 to 8, comprising: A charge buffer layer is provided between the drain electrode and the semiconductor charge transport layer, or providing a charge buffer layer between the source electrode and the semiconductor charge transport layer, or providing a charge buffer layer between the semiconductor charge transport layer and the light-emitting unit; A method characterized by:

10. The surface light source planar light-emitting transistor according to any one of claims 1 to 8 in the fields of wearable devices, lighting, lighting displays, and lasers, How to use.

11. The surface light source planar light-emitting transistor according to claim 10, wherein the lighting field is a white light lighting field. How to use.

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